2 * i.MX drm driver - Television Encoder (TVEv2)
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/component.h>
19 #include <linux/module.h>
20 #include <linux/i2c.h>
21 #include <linux/regmap.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/spinlock.h>
24 #include <linux/videodev2.h>
26 #include <drm/drm_atomic_helper.h>
27 #include <drm/drm_fb_helper.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <video/imx-ipu-v3.h>
33 #define TVE_COM_CONF_REG 0x00
34 #define TVE_TVDAC0_CONT_REG 0x28
35 #define TVE_TVDAC1_CONT_REG 0x2c
36 #define TVE_TVDAC2_CONT_REG 0x30
37 #define TVE_CD_CONT_REG 0x34
38 #define TVE_INT_CONT_REG 0x64
39 #define TVE_STAT_REG 0x68
40 #define TVE_TST_MODE_REG 0x6c
41 #define TVE_MV_CONT_REG 0xdc
43 /* TVE_COM_CONF_REG */
44 #define TVE_SYNC_CH_2_EN BIT(22)
45 #define TVE_SYNC_CH_1_EN BIT(21)
46 #define TVE_SYNC_CH_0_EN BIT(20)
47 #define TVE_TV_OUT_MODE_MASK (0x7 << 12)
48 #define TVE_TV_OUT_DISABLE (0x0 << 12)
49 #define TVE_TV_OUT_CVBS_0 (0x1 << 12)
50 #define TVE_TV_OUT_CVBS_2 (0x2 << 12)
51 #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
52 #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
53 #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
54 #define TVE_TV_OUT_YPBPR (0x6 << 12)
55 #define TVE_TV_OUT_RGB (0x7 << 12)
56 #define TVE_TV_STAND_MASK (0xf << 8)
57 #define TVE_TV_STAND_HD_1080P30 (0xc << 8)
58 #define TVE_P2I_CONV_EN BIT(7)
59 #define TVE_INP_VIDEO_FORM BIT(6)
60 #define TVE_INP_YCBCR_422 (0x0 << 6)
61 #define TVE_INP_YCBCR_444 (0x1 << 6)
62 #define TVE_DATA_SOURCE_MASK (0x3 << 4)
63 #define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
64 #define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
65 #define TVE_DATA_SOURCE_EXT (0x2 << 4)
66 #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
67 #define TVE_IPU_CLK_EN_OFS 3
68 #define TVE_IPU_CLK_EN BIT(3)
69 #define TVE_DAC_SAMP_RATE_OFS 1
70 #define TVE_DAC_SAMP_RATE_WIDTH 2
71 #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
72 #define TVE_DAC_FULL_RATE (0x0 << 1)
73 #define TVE_DAC_DIV2_RATE (0x1 << 1)
74 #define TVE_DAC_DIV4_RATE (0x2 << 1)
77 /* TVE_TVDACx_CONT_REG */
78 #define TVE_TVDAC_GAIN_MASK (0x3f << 0)
81 #define TVE_CD_CH_2_SM_EN BIT(22)
82 #define TVE_CD_CH_1_SM_EN BIT(21)
83 #define TVE_CD_CH_0_SM_EN BIT(20)
84 #define TVE_CD_CH_2_LM_EN BIT(18)
85 #define TVE_CD_CH_1_LM_EN BIT(17)
86 #define TVE_CD_CH_0_LM_EN BIT(16)
87 #define TVE_CD_CH_2_REF_LVL BIT(10)
88 #define TVE_CD_CH_1_REF_LVL BIT(9)
89 #define TVE_CD_CH_0_REF_LVL BIT(8)
90 #define TVE_CD_EN BIT(0)
92 /* TVE_INT_CONT_REG */
93 #define TVE_FRAME_END_IEN BIT(13)
94 #define TVE_CD_MON_END_IEN BIT(2)
95 #define TVE_CD_SM_IEN BIT(1)
96 #define TVE_CD_LM_IEN BIT(0)
98 /* TVE_TST_MODE_REG */
99 #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
101 #define IMX_TVE_DAC_VOLTAGE 2750000
109 struct drm_connector connector;
110 struct drm_encoder encoder;
112 spinlock_t lock; /* register lock */
118 struct regmap *regmap;
119 struct regulator *dac_reg;
120 struct i2c_adapter *ddc;
122 struct clk *di_sel_clk;
123 struct clk_hw clk_hw_di;
127 static inline struct imx_tve *con_to_tve(struct drm_connector *c)
129 return container_of(c, struct imx_tve, connector);
132 static inline struct imx_tve *enc_to_tve(struct drm_encoder *e)
134 return container_of(e, struct imx_tve, encoder);
137 static void tve_lock(void *__tve)
138 __acquires(&tve->lock)
140 struct imx_tve *tve = __tve;
142 spin_lock(&tve->lock);
145 static void tve_unlock(void *__tve)
146 __releases(&tve->lock)
148 struct imx_tve *tve = __tve;
150 spin_unlock(&tve->lock);
153 static void tve_enable(struct imx_tve *tve)
159 clk_prepare_enable(tve->clk);
160 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
164 /* clear interrupt status register */
165 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
167 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
168 if (tve->mode == TVE_MODE_VGA)
169 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
171 regmap_write(tve->regmap, TVE_INT_CONT_REG,
177 static void tve_disable(struct imx_tve *tve)
182 tve->enabled = false;
183 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
185 clk_disable_unprepare(tve->clk);
189 static int tve_setup_tvout(struct imx_tve *tve)
194 static int tve_setup_vga(struct imx_tve *tve)
200 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
201 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
202 TVE_TVDAC_GAIN_MASK, 0x0a);
206 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
207 TVE_TVDAC_GAIN_MASK, 0x0a);
211 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
212 TVE_TVDAC_GAIN_MASK, 0x0a);
216 /* set configuration register */
217 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
218 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
219 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
220 val |= TVE_TV_STAND_HD_1080P30 | 0;
221 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
222 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
223 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
227 /* set test mode (as documented) */
228 return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
229 TVE_TVDAC_TEST_MODE_MASK, 1);
232 static enum drm_connector_status imx_tve_connector_detect(
233 struct drm_connector *connector, bool force)
235 return connector_status_connected;
238 static int imx_tve_connector_get_modes(struct drm_connector *connector)
240 struct imx_tve *tve = con_to_tve(connector);
247 edid = drm_get_edid(connector, tve->ddc);
249 drm_mode_connector_update_edid_property(connector, edid);
250 ret = drm_add_edid_modes(connector, edid);
257 static int imx_tve_connector_mode_valid(struct drm_connector *connector,
258 struct drm_display_mode *mode)
260 struct imx_tve *tve = con_to_tve(connector);
263 /* pixel clock with 2x oversampling */
264 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
265 if (rate == mode->clock)
268 /* pixel clock without oversampling */
269 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
270 if (rate == mode->clock)
273 dev_warn(tve->dev, "ignoring mode %dx%d\n",
274 mode->hdisplay, mode->vdisplay);
279 static struct drm_encoder *imx_tve_connector_best_encoder(
280 struct drm_connector *connector)
282 struct imx_tve *tve = con_to_tve(connector);
284 return &tve->encoder;
287 static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
288 struct drm_display_mode *orig_mode,
289 struct drm_display_mode *mode)
291 struct imx_tve *tve = enc_to_tve(encoder);
292 unsigned long rounded_rate;
299 * we should try 4k * mode->clock first,
300 * and enable 4x oversampling for lower resolutions
302 rate = 2000UL * mode->clock;
303 clk_set_rate(tve->clk, rate);
304 rounded_rate = clk_get_rate(tve->clk);
305 if (rounded_rate >= rate)
307 clk_set_rate(tve->di_clk, rounded_rate / div);
309 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
311 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
315 regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
316 TVE_IPU_CLK_EN, TVE_IPU_CLK_EN);
318 if (tve->mode == TVE_MODE_VGA)
319 ret = tve_setup_vga(tve);
321 ret = tve_setup_tvout(tve);
323 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
326 static void imx_tve_encoder_enable(struct drm_encoder *encoder)
328 struct imx_tve *tve = enc_to_tve(encoder);
333 static void imx_tve_encoder_disable(struct drm_encoder *encoder)
335 struct imx_tve *tve = enc_to_tve(encoder);
340 static int imx_tve_atomic_check(struct drm_encoder *encoder,
341 struct drm_crtc_state *crtc_state,
342 struct drm_connector_state *conn_state)
344 struct imx_crtc_state *imx_crtc_state = to_imx_crtc_state(crtc_state);
345 struct imx_tve *tve = enc_to_tve(encoder);
347 imx_crtc_state->bus_format = MEDIA_BUS_FMT_GBR888_1X24;
348 imx_crtc_state->di_hsync_pin = tve->di_hsync_pin;
349 imx_crtc_state->di_vsync_pin = tve->di_vsync_pin;
354 static const struct drm_connector_funcs imx_tve_connector_funcs = {
355 .dpms = drm_atomic_helper_connector_dpms,
356 .fill_modes = drm_helper_probe_single_connector_modes,
357 .detect = imx_tve_connector_detect,
358 .destroy = imx_drm_connector_destroy,
359 .reset = drm_atomic_helper_connector_reset,
360 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
361 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
364 static const struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
365 .get_modes = imx_tve_connector_get_modes,
366 .best_encoder = imx_tve_connector_best_encoder,
367 .mode_valid = imx_tve_connector_mode_valid,
370 static const struct drm_encoder_funcs imx_tve_encoder_funcs = {
371 .destroy = imx_drm_encoder_destroy,
374 static const struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
375 .mode_set = imx_tve_encoder_mode_set,
376 .enable = imx_tve_encoder_enable,
377 .disable = imx_tve_encoder_disable,
378 .atomic_check = imx_tve_atomic_check,
381 static irqreturn_t imx_tve_irq_handler(int irq, void *data)
383 struct imx_tve *tve = data;
386 regmap_read(tve->regmap, TVE_STAT_REG, &val);
388 /* clear interrupt status register */
389 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
394 static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
395 unsigned long parent_rate)
397 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
401 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
405 switch (val & TVE_DAC_SAMP_RATE_MASK) {
406 case TVE_DAC_DIV4_RATE:
407 return parent_rate / 4;
408 case TVE_DAC_DIV2_RATE:
409 return parent_rate / 2;
410 case TVE_DAC_FULL_RATE:
418 static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
419 unsigned long *prate)
431 static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
432 unsigned long parent_rate)
434 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
439 div = parent_rate / rate;
441 val = TVE_DAC_DIV4_RATE;
443 val = TVE_DAC_DIV2_RATE;
445 val = TVE_DAC_FULL_RATE;
447 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
448 TVE_DAC_SAMP_RATE_MASK, val);
451 dev_err(tve->dev, "failed to set divider: %d\n", ret);
458 static struct clk_ops clk_tve_di_ops = {
459 .round_rate = clk_tve_di_round_rate,
460 .set_rate = clk_tve_di_set_rate,
461 .recalc_rate = clk_tve_di_recalc_rate,
464 static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
466 const char *tve_di_parent[1];
467 struct clk_init_data init = {
469 .ops = &clk_tve_di_ops,
474 tve_di_parent[0] = __clk_get_name(tve->clk);
475 init.parent_names = (const char **)&tve_di_parent;
477 tve->clk_hw_di.init = &init;
478 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
479 if (IS_ERR(tve->di_clk)) {
480 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
481 PTR_ERR(tve->di_clk));
482 return PTR_ERR(tve->di_clk);
488 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
493 encoder_type = tve->mode == TVE_MODE_VGA ?
494 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
496 ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
500 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
501 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
504 drm_connector_helper_add(&tve->connector,
505 &imx_tve_connector_helper_funcs);
506 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
507 DRM_MODE_CONNECTOR_VGA);
509 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
514 static void imx_tve_disable_regulator(void *data)
516 struct imx_tve *tve = data;
518 regulator_disable(tve->dac_reg);
521 static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
523 return (reg % 4 == 0) && (reg <= 0xdc);
526 static struct regmap_config tve_regmap_config = {
531 .readable_reg = imx_tve_readable_reg,
534 .unlock = tve_unlock,
536 .max_register = 0xdc,
539 static const char * const imx_tve_modes[] = {
540 [TVE_MODE_TVOUT] = "tvout",
541 [TVE_MODE_VGA] = "vga",
544 static const int of_get_tve_mode(struct device_node *np)
549 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
553 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
554 if (!strcasecmp(bm, imx_tve_modes[i]))
560 static int imx_tve_bind(struct device *dev, struct device *master, void *data)
562 struct platform_device *pdev = to_platform_device(dev);
563 struct drm_device *drm = data;
564 struct device_node *np = dev->of_node;
565 struct device_node *ddc_node;
567 struct resource *res;
573 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
578 spin_lock_init(&tve->lock);
580 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
582 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
583 of_node_put(ddc_node);
586 tve->mode = of_get_tve_mode(np);
587 if (tve->mode != TVE_MODE_VGA) {
588 dev_err(dev, "only VGA mode supported, currently\n");
592 if (tve->mode == TVE_MODE_VGA) {
593 ret = of_property_read_u32(np, "fsl,hsync-pin",
597 dev_err(dev, "failed to get hsync pin\n");
601 ret = of_property_read_u32(np, "fsl,vsync-pin",
605 dev_err(dev, "failed to get vsync pin\n");
610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
611 base = devm_ioremap_resource(dev, res);
613 return PTR_ERR(base);
615 tve_regmap_config.lock_arg = tve;
616 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
618 if (IS_ERR(tve->regmap)) {
619 dev_err(dev, "failed to init regmap: %ld\n",
620 PTR_ERR(tve->regmap));
621 return PTR_ERR(tve->regmap);
624 irq = platform_get_irq(pdev, 0);
626 dev_err(dev, "failed to get irq\n");
630 ret = devm_request_threaded_irq(dev, irq, NULL,
631 imx_tve_irq_handler, IRQF_ONESHOT,
634 dev_err(dev, "failed to request irq: %d\n", ret);
638 tve->dac_reg = devm_regulator_get(dev, "dac");
639 if (!IS_ERR(tve->dac_reg)) {
640 if (regulator_get_voltage(tve->dac_reg) != IMX_TVE_DAC_VOLTAGE)
641 dev_warn(dev, "dac voltage is not %d uV\n", IMX_TVE_DAC_VOLTAGE);
642 ret = regulator_enable(tve->dac_reg);
645 ret = devm_add_action_or_reset(dev, imx_tve_disable_regulator, tve);
650 tve->clk = devm_clk_get(dev, "tve");
651 if (IS_ERR(tve->clk)) {
652 dev_err(dev, "failed to get high speed tve clock: %ld\n",
654 return PTR_ERR(tve->clk);
657 /* this is the IPU DI clock input selector, can be parented to tve_di */
658 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
659 if (IS_ERR(tve->di_sel_clk)) {
660 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
661 PTR_ERR(tve->di_sel_clk));
662 return PTR_ERR(tve->di_sel_clk);
665 ret = tve_clk_init(tve, base);
669 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
671 dev_err(dev, "failed to read configuration register: %d\n",
675 if (val != 0x00100000) {
676 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
680 /* disable cable detection for VGA mode */
681 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
685 ret = imx_tve_register(drm, tve);
689 dev_set_drvdata(dev, tve);
694 static const struct component_ops imx_tve_ops = {
695 .bind = imx_tve_bind,
698 static int imx_tve_probe(struct platform_device *pdev)
700 return component_add(&pdev->dev, &imx_tve_ops);
703 static int imx_tve_remove(struct platform_device *pdev)
705 component_del(&pdev->dev, &imx_tve_ops);
709 static const struct of_device_id imx_tve_dt_ids[] = {
710 { .compatible = "fsl,imx53-tve", },
713 MODULE_DEVICE_TABLE(of, imx_tve_dt_ids);
715 static struct platform_driver imx_tve_driver = {
716 .probe = imx_tve_probe,
717 .remove = imx_tve_remove,
719 .of_match_table = imx_tve_dt_ids,
724 module_platform_driver(imx_tve_driver);
726 MODULE_DESCRIPTION("i.MX Television Encoder driver");
727 MODULE_AUTHOR("Philipp Zabel, Pengutronix");
728 MODULE_LICENSE("GPL");
729 MODULE_ALIAS("platform:imx-tve");