2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "intel_drv.h"
26 #include "i915_vgpu.h"
28 #include <linux/pm_runtime.h>
30 #define FORCEWAKE_ACK_TIMEOUT_MS 50
32 #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
33 #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
35 #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
36 #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
38 #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
39 #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
41 #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
42 #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
44 #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
46 static const char * const forcewake_domain_names[] = {
53 intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id)
55 BUILD_BUG_ON(ARRAY_SIZE(forcewake_domain_names) != FW_DOMAIN_ID_COUNT);
57 if (id >= 0 && id < FW_DOMAIN_ID_COUNT)
58 return forcewake_domain_names[id];
66 assert_device_not_suspended(struct drm_i915_private *dev_priv)
68 WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
69 "Device suspended\n");
73 fw_domain_reset(const struct intel_uncore_forcewake_domain *d)
75 WARN_ON(d->reg_set == 0);
76 __raw_i915_write32(d->i915, d->reg_set, d->val_reset);
80 fw_domain_arm_timer(struct intel_uncore_forcewake_domain *d)
82 mod_timer_pinned(&d->timer, jiffies + 1);
86 fw_domain_wait_ack_clear(const struct intel_uncore_forcewake_domain *d)
88 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
89 FORCEWAKE_KERNEL) == 0,
90 FORCEWAKE_ACK_TIMEOUT_MS))
91 DRM_ERROR("%s: timed out waiting for forcewake ack to clear.\n",
92 intel_uncore_forcewake_domain_to_str(d->id));
96 fw_domain_get(const struct intel_uncore_forcewake_domain *d)
98 __raw_i915_write32(d->i915, d->reg_set, d->val_set);
102 fw_domain_wait_ack(const struct intel_uncore_forcewake_domain *d)
104 if (wait_for_atomic((__raw_i915_read32(d->i915, d->reg_ack) &
106 FORCEWAKE_ACK_TIMEOUT_MS))
107 DRM_ERROR("%s: timed out waiting for forcewake ack request.\n",
108 intel_uncore_forcewake_domain_to_str(d->id));
112 fw_domain_put(const struct intel_uncore_forcewake_domain *d)
114 __raw_i915_write32(d->i915, d->reg_set, d->val_clear);
118 fw_domain_posting_read(const struct intel_uncore_forcewake_domain *d)
120 /* something from same cacheline, but not from the set register */
122 __raw_posting_read(d->i915, d->reg_post);
126 fw_domains_get(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
128 struct intel_uncore_forcewake_domain *d;
129 enum forcewake_domain_id id;
131 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
132 fw_domain_wait_ack_clear(d);
134 fw_domain_wait_ack(d);
139 fw_domains_put(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
141 struct intel_uncore_forcewake_domain *d;
142 enum forcewake_domain_id id;
144 for_each_fw_domain_mask(d, fw_domains, dev_priv, id) {
146 fw_domain_posting_read(d);
151 fw_domains_posting_read(struct drm_i915_private *dev_priv)
153 struct intel_uncore_forcewake_domain *d;
154 enum forcewake_domain_id id;
156 /* No need to do for all, just do for first found */
157 for_each_fw_domain(d, dev_priv, id) {
158 fw_domain_posting_read(d);
164 fw_domains_reset(struct drm_i915_private *dev_priv, enum forcewake_domains fw_domains)
166 struct intel_uncore_forcewake_domain *d;
167 enum forcewake_domain_id id;
169 if (dev_priv->uncore.fw_domains == 0)
172 for_each_fw_domain_mask(d, fw_domains, dev_priv, id)
175 fw_domains_posting_read(dev_priv);
178 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
180 /* w/a for a sporadic read returning 0 by waiting for the GT
183 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
184 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
185 DRM_ERROR("GT thread status wait timed out\n");
188 static void fw_domains_get_with_thread_status(struct drm_i915_private *dev_priv,
189 enum forcewake_domains fw_domains)
191 fw_domains_get(dev_priv, fw_domains);
193 /* WaRsForcewakeWaitTC0:snb,ivb,hsw,bdw,vlv */
194 __gen6_gt_wait_for_thread_c0(dev_priv);
197 static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
201 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
202 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
203 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
206 static void fw_domains_put_with_fifo(struct drm_i915_private *dev_priv,
207 enum forcewake_domains fw_domains)
209 fw_domains_put(dev_priv, fw_domains);
210 gen6_gt_check_fifodbg(dev_priv);
213 static inline u32 fifo_free_entries(struct drm_i915_private *dev_priv)
215 u32 count = __raw_i915_read32(dev_priv, GTFIFOCTL);
217 return count & GT_FIFO_FREE_ENTRIES_MASK;
220 static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
224 /* On VLV, FIFO will be shared by both SW and HW.
225 * So, we need to read the FREE_ENTRIES everytime */
226 if (IS_VALLEYVIEW(dev_priv->dev))
227 dev_priv->uncore.fifo_count = fifo_free_entries(dev_priv);
229 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
231 u32 fifo = fifo_free_entries(dev_priv);
233 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
235 fifo = fifo_free_entries(dev_priv);
237 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
239 dev_priv->uncore.fifo_count = fifo;
241 dev_priv->uncore.fifo_count--;
246 static void intel_uncore_fw_release_timer(unsigned long arg)
248 struct intel_uncore_forcewake_domain *domain = (void *)arg;
249 unsigned long irqflags;
251 assert_device_not_suspended(domain->i915);
253 spin_lock_irqsave(&domain->i915->uncore.lock, irqflags);
254 if (WARN_ON(domain->wake_count == 0))
255 domain->wake_count++;
257 if (--domain->wake_count == 0)
258 domain->i915->uncore.funcs.force_wake_put(domain->i915,
261 spin_unlock_irqrestore(&domain->i915->uncore.lock, irqflags);
264 void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
266 struct drm_i915_private *dev_priv = dev->dev_private;
267 unsigned long irqflags;
268 struct intel_uncore_forcewake_domain *domain;
269 int retry_count = 100;
270 enum forcewake_domain_id id;
271 enum forcewake_domains fw = 0, active_domains;
273 /* Hold uncore.lock across reset to prevent any register access
274 * with forcewake not set correctly. Wait until all pending
275 * timers are run before holding.
280 for_each_fw_domain(domain, dev_priv, id) {
281 if (del_timer_sync(&domain->timer) == 0)
284 intel_uncore_fw_release_timer((unsigned long)domain);
287 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
289 for_each_fw_domain(domain, dev_priv, id) {
290 if (timer_pending(&domain->timer))
291 active_domains |= (1 << id);
294 if (active_domains == 0)
297 if (--retry_count == 0) {
298 DRM_ERROR("Timed out waiting for forcewake timers to finish\n");
302 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
306 WARN_ON(active_domains);
308 for_each_fw_domain(domain, dev_priv, id)
309 if (domain->wake_count)
313 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw);
315 fw_domains_reset(dev_priv, FORCEWAKE_ALL);
317 if (restore) { /* If reset with a user forcewake, try to restore */
319 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
321 if (IS_GEN6(dev) || IS_GEN7(dev))
322 dev_priv->uncore.fifo_count =
323 fifo_free_entries(dev_priv);
327 assert_forcewakes_inactive(dev_priv);
329 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
332 static void intel_uncore_ellc_detect(struct drm_device *dev)
334 struct drm_i915_private *dev_priv = dev->dev_private;
336 if ((IS_HASWELL(dev) || IS_BROADWELL(dev) ||
337 INTEL_INFO(dev)->gen >= 9) &&
338 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) & EDRAM_ENABLED)) {
339 /* The docs do not explain exactly how the calculation can be
340 * made. It is somewhat guessable, but for now, it's always
342 * NB: We can't write IDICR yet because we do not have gt funcs
344 dev_priv->ellc_size = 128;
345 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
349 static void __intel_uncore_early_sanitize(struct drm_device *dev,
350 bool restore_forcewake)
352 struct drm_i915_private *dev_priv = dev->dev_private;
354 if (HAS_FPGA_DBG_UNCLAIMED(dev))
355 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
357 /* clear out old GT FIFO errors */
358 if (IS_GEN6(dev) || IS_GEN7(dev))
359 __raw_i915_write32(dev_priv, GTFIFODBG,
360 __raw_i915_read32(dev_priv, GTFIFODBG));
362 /* WaDisableShadowRegForCpd:chv */
363 if (IS_CHERRYVIEW(dev)) {
364 __raw_i915_write32(dev_priv, GTFIFOCTL,
365 __raw_i915_read32(dev_priv, GTFIFOCTL) |
366 GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL |
367 GT_FIFO_CTL_RC6_POLICY_STALL);
370 intel_uncore_forcewake_reset(dev, restore_forcewake);
373 void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
375 __intel_uncore_early_sanitize(dev, restore_forcewake);
376 i915_check_and_clear_faults(dev);
379 void intel_uncore_sanitize(struct drm_device *dev)
381 /* BIOS often leaves RC6 enabled, but disable it for hw init */
382 intel_disable_gt_powersave(dev);
385 static void __intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
386 enum forcewake_domains fw_domains)
388 struct intel_uncore_forcewake_domain *domain;
389 enum forcewake_domain_id id;
391 if (!dev_priv->uncore.funcs.force_wake_get)
394 fw_domains &= dev_priv->uncore.fw_domains;
396 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
397 if (domain->wake_count++)
398 fw_domains &= ~(1 << id);
402 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
406 * intel_uncore_forcewake_get - grab forcewake domain references
407 * @dev_priv: i915 device instance
408 * @fw_domains: forcewake domains to get reference on
410 * This function can be used get GT's forcewake domain references.
411 * Normal register access will handle the forcewake domains automatically.
412 * However if some sequence requires the GT to not power down a particular
413 * forcewake domains this function should be called at the beginning of the
414 * sequence. And subsequently the reference should be dropped by symmetric
415 * call to intel_unforce_forcewake_put(). Usually caller wants all the domains
416 * to be kept awake so the @fw_domains would be then FORCEWAKE_ALL.
418 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
419 enum forcewake_domains fw_domains)
421 unsigned long irqflags;
423 if (!dev_priv->uncore.funcs.force_wake_get)
426 WARN_ON(dev_priv->pm.suspended);
428 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
429 __intel_uncore_forcewake_get(dev_priv, fw_domains);
430 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
434 * intel_uncore_forcewake_get__locked - grab forcewake domain references
435 * @dev_priv: i915 device instance
436 * @fw_domains: forcewake domains to get reference on
438 * See intel_uncore_forcewake_get(). This variant places the onus
439 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
441 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
442 enum forcewake_domains fw_domains)
444 assert_spin_locked(&dev_priv->uncore.lock);
446 if (!dev_priv->uncore.funcs.force_wake_get)
449 __intel_uncore_forcewake_get(dev_priv, fw_domains);
452 static void __intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
453 enum forcewake_domains fw_domains)
455 struct intel_uncore_forcewake_domain *domain;
456 enum forcewake_domain_id id;
458 if (!dev_priv->uncore.funcs.force_wake_put)
461 fw_domains &= dev_priv->uncore.fw_domains;
463 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
464 if (WARN_ON(domain->wake_count == 0))
467 if (--domain->wake_count)
470 domain->wake_count++;
471 fw_domain_arm_timer(domain);
476 * intel_uncore_forcewake_put - release a forcewake domain reference
477 * @dev_priv: i915 device instance
478 * @fw_domains: forcewake domains to put references
480 * This function drops the device-level forcewakes for specified
481 * domains obtained by intel_uncore_forcewake_get().
483 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
484 enum forcewake_domains fw_domains)
486 unsigned long irqflags;
488 if (!dev_priv->uncore.funcs.force_wake_put)
491 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
492 __intel_uncore_forcewake_put(dev_priv, fw_domains);
493 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
497 * intel_uncore_forcewake_put__locked - grab forcewake domain references
498 * @dev_priv: i915 device instance
499 * @fw_domains: forcewake domains to get reference on
501 * See intel_uncore_forcewake_put(). This variant places the onus
502 * on the caller to explicitly handle the dev_priv->uncore.lock spinlock.
504 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
505 enum forcewake_domains fw_domains)
507 assert_spin_locked(&dev_priv->uncore.lock);
509 if (!dev_priv->uncore.funcs.force_wake_put)
512 __intel_uncore_forcewake_put(dev_priv, fw_domains);
515 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv)
517 struct intel_uncore_forcewake_domain *domain;
518 enum forcewake_domain_id id;
520 if (!dev_priv->uncore.funcs.force_wake_get)
523 for_each_fw_domain(domain, dev_priv, id)
524 WARN_ON(domain->wake_count);
527 /* We give fast paths for the really cool registers */
528 #define NEEDS_FORCE_WAKE(reg) \
529 ((reg) < 0x40000 && (reg) != FORCEWAKE)
531 #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
533 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
534 (REG_RANGE((reg), 0x2000, 0x4000) || \
535 REG_RANGE((reg), 0x5000, 0x8000) || \
536 REG_RANGE((reg), 0xB000, 0x12000) || \
537 REG_RANGE((reg), 0x2E000, 0x30000))
539 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
540 (REG_RANGE((reg), 0x12000, 0x14000) || \
541 REG_RANGE((reg), 0x22000, 0x24000) || \
542 REG_RANGE((reg), 0x30000, 0x40000))
544 #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
545 (REG_RANGE((reg), 0x2000, 0x4000) || \
546 REG_RANGE((reg), 0x5200, 0x8000) || \
547 REG_RANGE((reg), 0x8300, 0x8500) || \
548 REG_RANGE((reg), 0xB000, 0xB480) || \
549 REG_RANGE((reg), 0xE000, 0xE800))
551 #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
552 (REG_RANGE((reg), 0x8800, 0x8900) || \
553 REG_RANGE((reg), 0xD000, 0xD800) || \
554 REG_RANGE((reg), 0x12000, 0x14000) || \
555 REG_RANGE((reg), 0x1A000, 0x1C000) || \
556 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
557 REG_RANGE((reg), 0x30000, 0x38000))
559 #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
560 (REG_RANGE((reg), 0x4000, 0x5000) || \
561 REG_RANGE((reg), 0x8000, 0x8300) || \
562 REG_RANGE((reg), 0x8500, 0x8600) || \
563 REG_RANGE((reg), 0x9000, 0xB000) || \
564 REG_RANGE((reg), 0xF000, 0x10000))
566 #define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
567 REG_RANGE((reg), 0xB00, 0x2000)
569 #define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
570 (REG_RANGE((reg), 0x2000, 0x2700) || \
571 REG_RANGE((reg), 0x3000, 0x4000) || \
572 REG_RANGE((reg), 0x5200, 0x8000) || \
573 REG_RANGE((reg), 0x8140, 0x8160) || \
574 REG_RANGE((reg), 0x8300, 0x8500) || \
575 REG_RANGE((reg), 0x8C00, 0x8D00) || \
576 REG_RANGE((reg), 0xB000, 0xB480) || \
577 REG_RANGE((reg), 0xE000, 0xE900) || \
578 REG_RANGE((reg), 0x24400, 0x24800))
580 #define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
581 (REG_RANGE((reg), 0x8130, 0x8140) || \
582 REG_RANGE((reg), 0x8800, 0x8A00) || \
583 REG_RANGE((reg), 0xD000, 0xD800) || \
584 REG_RANGE((reg), 0x12000, 0x14000) || \
585 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
586 REG_RANGE((reg), 0x30000, 0x40000))
588 #define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
589 REG_RANGE((reg), 0x9400, 0x9800)
591 #define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
593 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
594 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
595 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
596 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
599 ilk_dummy_write(struct drm_i915_private *dev_priv)
601 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
602 * the chip from rc6 before touching it for real. MI_MODE is masked,
603 * hence harmless to write 0 into. */
604 __raw_i915_write32(dev_priv, MI_MODE, 0);
608 hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
611 const char *op = read ? "reading" : "writing to";
612 const char *when = before ? "before" : "after";
614 if (!i915.mmio_debug)
617 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
618 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
620 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
621 i915.mmio_debug--; /* Only report the first N failures */
626 hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
628 static bool mmio_debug_once = true;
630 if (i915.mmio_debug || !mmio_debug_once)
633 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
634 DRM_DEBUG("Unclaimed register detected, "
635 "enabling oneshot unclaimed register reporting. "
636 "Please use i915.mmio_debug=N for more information.\n");
637 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
638 i915.mmio_debug = mmio_debug_once;
639 mmio_debug_once = false;
643 #define GEN2_READ_HEADER(x) \
645 assert_device_not_suspended(dev_priv);
647 #define GEN2_READ_FOOTER \
648 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
651 #define __gen2_read(x) \
653 gen2_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
654 GEN2_READ_HEADER(x); \
655 val = __raw_i915_read##x(dev_priv, reg); \
659 #define __gen5_read(x) \
661 gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
662 GEN2_READ_HEADER(x); \
663 ilk_dummy_write(dev_priv); \
664 val = __raw_i915_read##x(dev_priv, reg); \
680 #undef GEN2_READ_FOOTER
681 #undef GEN2_READ_HEADER
683 #define GEN6_READ_HEADER(x) \
684 unsigned long irqflags; \
686 assert_device_not_suspended(dev_priv); \
687 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
689 #define GEN6_READ_FOOTER \
690 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
691 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
694 static inline void __force_wake_get(struct drm_i915_private *dev_priv,
695 enum forcewake_domains fw_domains)
697 struct intel_uncore_forcewake_domain *domain;
698 enum forcewake_domain_id id;
700 if (WARN_ON(!fw_domains))
703 /* Ideally GCC would be constant-fold and eliminate this loop */
704 for_each_fw_domain_mask(domain, fw_domains, dev_priv, id) {
705 if (domain->wake_count) {
706 fw_domains &= ~(1 << id);
710 domain->wake_count++;
711 fw_domain_arm_timer(domain);
715 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_domains);
718 #define __vgpu_read(x) \
720 vgpu_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
721 GEN6_READ_HEADER(x); \
722 val = __raw_i915_read##x(dev_priv, reg); \
726 #define __gen6_read(x) \
728 gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
729 GEN6_READ_HEADER(x); \
730 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
731 if (NEEDS_FORCE_WAKE(reg)) \
732 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
733 val = __raw_i915_read##x(dev_priv, reg); \
734 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
738 #define __vlv_read(x) \
740 vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
741 GEN6_READ_HEADER(x); \
742 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) \
743 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
744 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) \
745 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
746 val = __raw_i915_read##x(dev_priv, reg); \
750 #define __chv_read(x) \
752 chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
753 GEN6_READ_HEADER(x); \
754 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
755 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
756 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
757 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
758 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
759 __force_wake_get(dev_priv, \
760 FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
761 val = __raw_i915_read##x(dev_priv, reg); \
765 #define SKL_NEEDS_FORCE_WAKE(reg) \
766 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
768 #define __gen9_read(x) \
770 gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
771 enum forcewake_domains fw_engine; \
772 GEN6_READ_HEADER(x); \
773 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
774 if (!SKL_NEEDS_FORCE_WAKE(reg)) \
776 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
777 fw_engine = FORCEWAKE_RENDER; \
778 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
779 fw_engine = FORCEWAKE_MEDIA; \
780 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
781 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
783 fw_engine = FORCEWAKE_BLITTER; \
785 __force_wake_get(dev_priv, fw_engine); \
786 val = __raw_i915_read##x(dev_priv, reg); \
787 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
817 #undef GEN6_READ_FOOTER
818 #undef GEN6_READ_HEADER
820 #define GEN2_WRITE_HEADER \
821 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
822 assert_device_not_suspended(dev_priv); \
824 #define GEN2_WRITE_FOOTER
826 #define __gen2_write(x) \
828 gen2_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
830 __raw_i915_write##x(dev_priv, reg, val); \
834 #define __gen5_write(x) \
836 gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
838 ilk_dummy_write(dev_priv); \
839 __raw_i915_write##x(dev_priv, reg, val); \
855 #undef GEN2_WRITE_FOOTER
856 #undef GEN2_WRITE_HEADER
858 #define GEN6_WRITE_HEADER \
859 unsigned long irqflags; \
860 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
861 assert_device_not_suspended(dev_priv); \
862 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
864 #define GEN6_WRITE_FOOTER \
865 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
867 #define __gen6_write(x) \
869 gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
870 u32 __fifo_ret = 0; \
872 if (NEEDS_FORCE_WAKE(reg)) { \
873 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
875 __raw_i915_write##x(dev_priv, reg, val); \
876 if (unlikely(__fifo_ret)) { \
877 gen6_gt_check_fifodbg(dev_priv); \
882 #define __hsw_write(x) \
884 hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
885 u32 __fifo_ret = 0; \
887 if (NEEDS_FORCE_WAKE(reg)) { \
888 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
890 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
891 __raw_i915_write##x(dev_priv, reg, val); \
892 if (unlikely(__fifo_ret)) { \
893 gen6_gt_check_fifodbg(dev_priv); \
895 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
896 hsw_unclaimed_reg_detect(dev_priv); \
900 #define __vgpu_write(x) \
901 static void vgpu_write##x(struct drm_i915_private *dev_priv, \
902 off_t reg, u##x val, bool trace) { \
904 __raw_i915_write##x(dev_priv, reg, val); \
908 static const u32 gen8_shadowed_regs[] = {
912 RING_TAIL(RENDER_RING_BASE),
913 RING_TAIL(GEN6_BSD_RING_BASE),
914 RING_TAIL(VEBOX_RING_BASE),
915 RING_TAIL(BLT_RING_BASE),
916 /* TODO: Other registers are not yet used */
919 static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
922 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
923 if (reg == gen8_shadowed_regs[i])
929 #define __gen8_write(x) \
931 gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
933 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
934 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) \
935 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
936 __raw_i915_write##x(dev_priv, reg, val); \
937 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
938 hsw_unclaimed_reg_detect(dev_priv); \
942 #define __chv_write(x) \
944 chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
945 bool shadowed = is_gen8_shadowed(dev_priv, reg); \
948 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) \
949 __force_wake_get(dev_priv, FORCEWAKE_RENDER); \
950 else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) \
951 __force_wake_get(dev_priv, FORCEWAKE_MEDIA); \
952 else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) \
953 __force_wake_get(dev_priv, FORCEWAKE_RENDER | FORCEWAKE_MEDIA); \
955 __raw_i915_write##x(dev_priv, reg, val); \
959 static const u32 gen9_shadowed_regs[] = {
960 RING_TAIL(RENDER_RING_BASE),
961 RING_TAIL(GEN6_BSD_RING_BASE),
962 RING_TAIL(VEBOX_RING_BASE),
963 RING_TAIL(BLT_RING_BASE),
964 FORCEWAKE_BLITTER_GEN9,
965 FORCEWAKE_RENDER_GEN9,
966 FORCEWAKE_MEDIA_GEN9,
969 /* TODO: Other registers are not yet used */
972 static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
975 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
976 if (reg == gen9_shadowed_regs[i])
982 #define __gen9_write(x) \
984 gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
986 enum forcewake_domains fw_engine; \
988 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
989 if (!SKL_NEEDS_FORCE_WAKE(reg) || \
990 is_gen9_shadowed(dev_priv, reg)) \
992 else if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) \
993 fw_engine = FORCEWAKE_RENDER; \
994 else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) \
995 fw_engine = FORCEWAKE_MEDIA; \
996 else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) \
997 fw_engine = FORCEWAKE_RENDER | FORCEWAKE_MEDIA; \
999 fw_engine = FORCEWAKE_BLITTER; \
1001 __force_wake_get(dev_priv, fw_engine); \
1002 __raw_i915_write##x(dev_priv, reg, val); \
1003 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
1004 hsw_unclaimed_reg_detect(dev_priv); \
1005 GEN6_WRITE_FOOTER; \
1039 #undef GEN6_WRITE_FOOTER
1040 #undef GEN6_WRITE_HEADER
1042 #define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1044 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1045 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1046 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1047 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1050 #define ASSIGN_READ_MMIO_VFUNCS(x) \
1052 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1053 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1054 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1055 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1059 static void fw_domain_init(struct drm_i915_private *dev_priv,
1060 enum forcewake_domain_id domain_id,
1061 u32 reg_set, u32 reg_ack)
1063 struct intel_uncore_forcewake_domain *d;
1065 if (WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT))
1068 d = &dev_priv->uncore.fw_domain[domain_id];
1070 WARN_ON(d->wake_count);
1073 d->reg_set = reg_set;
1074 d->reg_ack = reg_ack;
1076 if (IS_GEN6(dev_priv)) {
1078 d->val_set = FORCEWAKE_KERNEL;
1081 /* WaRsClearFWBitsAtReset:bdw,skl */
1082 d->val_reset = _MASKED_BIT_DISABLE(0xffff);
1083 d->val_set = _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL);
1084 d->val_clear = _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL);
1087 if (IS_VALLEYVIEW(dev_priv))
1088 d->reg_post = FORCEWAKE_ACK_VLV;
1089 else if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv) || IS_GEN8(dev_priv))
1090 d->reg_post = ECOBUS;
1097 setup_timer(&d->timer, intel_uncore_fw_release_timer, (unsigned long)d);
1099 dev_priv->uncore.fw_domains |= (1 << domain_id);
1104 static void intel_uncore_fw_domains_init(struct drm_device *dev)
1106 struct drm_i915_private *dev_priv = dev->dev_private;
1108 if (INTEL_INFO(dev_priv->dev)->gen <= 5)
1112 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1113 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1114 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1115 FORCEWAKE_RENDER_GEN9,
1116 FORCEWAKE_ACK_RENDER_GEN9);
1117 fw_domain_init(dev_priv, FW_DOMAIN_ID_BLITTER,
1118 FORCEWAKE_BLITTER_GEN9,
1119 FORCEWAKE_ACK_BLITTER_GEN9);
1120 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1121 FORCEWAKE_MEDIA_GEN9, FORCEWAKE_ACK_MEDIA_GEN9);
1122 } else if (IS_VALLEYVIEW(dev)) {
1123 dev_priv->uncore.funcs.force_wake_get = fw_domains_get;
1124 if (!IS_CHERRYVIEW(dev))
1125 dev_priv->uncore.funcs.force_wake_put =
1126 fw_domains_put_with_fifo;
1128 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1129 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1130 FORCEWAKE_VLV, FORCEWAKE_ACK_VLV);
1131 fw_domain_init(dev_priv, FW_DOMAIN_ID_MEDIA,
1132 FORCEWAKE_MEDIA_VLV, FORCEWAKE_ACK_MEDIA_VLV);
1133 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1134 dev_priv->uncore.funcs.force_wake_get =
1135 fw_domains_get_with_thread_status;
1136 if (IS_HASWELL(dev))
1137 dev_priv->uncore.funcs.force_wake_put =
1138 fw_domains_put_with_fifo;
1140 dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
1141 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1142 FORCEWAKE_MT, FORCEWAKE_ACK_HSW);
1143 } else if (IS_IVYBRIDGE(dev)) {
1146 /* IVB configs may use multi-threaded forcewake */
1148 /* A small trick here - if the bios hasn't configured
1149 * MT forcewake, and if the device is in RC6, then
1150 * force_wake_mt_get will not wake the device and the
1151 * ECOBUS read will return zero. Which will be
1152 * (correctly) interpreted by the test below as MT
1153 * forcewake being disabled.
1155 dev_priv->uncore.funcs.force_wake_get =
1156 fw_domains_get_with_thread_status;
1157 dev_priv->uncore.funcs.force_wake_put =
1158 fw_domains_put_with_fifo;
1160 /* We need to init first for ECOBUS access and then
1161 * determine later if we want to reinit, in case of MT access is
1162 * not working. In this stage we don't know which flavour this
1163 * ivb is, so it is better to reset also the gen6 fw registers
1164 * before the ecobus check.
1167 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
1168 __raw_posting_read(dev_priv, ECOBUS);
1170 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1171 FORCEWAKE_MT, FORCEWAKE_MT_ACK);
1173 mutex_lock(&dev->struct_mutex);
1174 fw_domains_get_with_thread_status(dev_priv, FORCEWAKE_ALL);
1175 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
1176 fw_domains_put_with_fifo(dev_priv, FORCEWAKE_ALL);
1177 mutex_unlock(&dev->struct_mutex);
1179 if (!(ecobus & FORCEWAKE_MT_ENABLE)) {
1180 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1181 DRM_INFO("when using vblank-synced partial screen updates.\n");
1182 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1183 FORCEWAKE, FORCEWAKE_ACK);
1185 } else if (IS_GEN6(dev)) {
1186 dev_priv->uncore.funcs.force_wake_get =
1187 fw_domains_get_with_thread_status;
1188 dev_priv->uncore.funcs.force_wake_put =
1189 fw_domains_put_with_fifo;
1190 fw_domain_init(dev_priv, FW_DOMAIN_ID_RENDER,
1191 FORCEWAKE, FORCEWAKE_ACK);
1194 /* All future platforms are expected to require complex power gating */
1195 WARN_ON(dev_priv->uncore.fw_domains == 0);
1198 void intel_uncore_init(struct drm_device *dev)
1200 struct drm_i915_private *dev_priv = dev->dev_private;
1202 i915_check_vgpu(dev);
1204 intel_uncore_ellc_detect(dev);
1205 intel_uncore_fw_domains_init(dev);
1206 __intel_uncore_early_sanitize(dev, false);
1208 switch (INTEL_INFO(dev)->gen) {
1211 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1212 ASSIGN_READ_MMIO_VFUNCS(gen9);
1215 if (IS_CHERRYVIEW(dev)) {
1216 ASSIGN_WRITE_MMIO_VFUNCS(chv);
1217 ASSIGN_READ_MMIO_VFUNCS(chv);
1220 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1221 ASSIGN_READ_MMIO_VFUNCS(gen6);
1226 if (IS_HASWELL(dev)) {
1227 ASSIGN_WRITE_MMIO_VFUNCS(hsw);
1229 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
1232 if (IS_VALLEYVIEW(dev)) {
1233 ASSIGN_READ_MMIO_VFUNCS(vlv);
1235 ASSIGN_READ_MMIO_VFUNCS(gen6);
1239 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1240 ASSIGN_READ_MMIO_VFUNCS(gen5);
1245 ASSIGN_WRITE_MMIO_VFUNCS(gen2);
1246 ASSIGN_READ_MMIO_VFUNCS(gen2);
1250 if (intel_vgpu_active(dev)) {
1251 ASSIGN_WRITE_MMIO_VFUNCS(vgpu);
1252 ASSIGN_READ_MMIO_VFUNCS(vgpu);
1255 i915_check_and_clear_faults(dev);
1257 #undef ASSIGN_WRITE_MMIO_VFUNCS
1258 #undef ASSIGN_READ_MMIO_VFUNCS
1260 void intel_uncore_fini(struct drm_device *dev)
1262 /* Paranoia: make sure we have disabled everything before we exit. */
1263 intel_uncore_sanitize(dev);
1264 intel_uncore_forcewake_reset(dev, false);
1267 #define GEN_RANGE(l, h) GENMASK(h, l)
1269 static const struct register_whitelist {
1272 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1273 uint32_t gen_bitmask;
1275 { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
1278 int i915_reg_read_ioctl(struct drm_device *dev,
1279 void *data, struct drm_file *file)
1281 struct drm_i915_private *dev_priv = dev->dev_private;
1282 struct drm_i915_reg_read *reg = data;
1283 struct register_whitelist const *entry = whitelist;
1288 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1289 if (entry->offset == (reg->offset & -entry->size) &&
1290 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1294 if (i == ARRAY_SIZE(whitelist))
1297 /* We use the low bits to encode extra flags as the register should
1298 * be naturally aligned (and those that are not so aligned merely
1299 * limit the available flags for that register).
1301 offset = entry->offset;
1303 size |= reg->offset ^ offset;
1305 intel_runtime_pm_get(dev_priv);
1309 reg->val = I915_READ64_2x32(offset, offset+4);
1312 reg->val = I915_READ64(offset);
1315 reg->val = I915_READ(offset);
1318 reg->val = I915_READ16(offset);
1321 reg->val = I915_READ8(offset);
1329 intel_runtime_pm_put(dev_priv);
1333 int i915_get_reset_stats_ioctl(struct drm_device *dev,
1334 void *data, struct drm_file *file)
1336 struct drm_i915_private *dev_priv = dev->dev_private;
1337 struct drm_i915_reset_stats *args = data;
1338 struct i915_ctx_hang_stats *hs;
1339 struct intel_context *ctx;
1342 if (args->flags || args->pad)
1345 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
1348 ret = mutex_lock_interruptible(&dev->struct_mutex);
1352 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1354 mutex_unlock(&dev->struct_mutex);
1355 return PTR_ERR(ctx);
1357 hs = &ctx->hang_stats;
1359 if (capable(CAP_SYS_ADMIN))
1360 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1362 args->reset_count = 0;
1364 args->batch_active = hs->batch_active;
1365 args->batch_pending = hs->batch_pending;
1367 mutex_unlock(&dev->struct_mutex);
1372 static int i915_reset_complete(struct drm_device *dev)
1375 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1376 return (gdrst & GRDOM_RESET_STATUS) == 0;
1379 static int i915_do_reset(struct drm_device *dev)
1381 /* assert reset for at least 20 usec */
1382 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1384 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1386 return wait_for(i915_reset_complete(dev), 500);
1389 static int g4x_reset_complete(struct drm_device *dev)
1392 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
1393 return (gdrst & GRDOM_RESET_ENABLE) == 0;
1396 static int g33_do_reset(struct drm_device *dev)
1398 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1399 return wait_for(g4x_reset_complete(dev), 500);
1402 static int g4x_do_reset(struct drm_device *dev)
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1407 pci_write_config_byte(dev->pdev, I915_GDRST,
1408 GRDOM_RENDER | GRDOM_RESET_ENABLE);
1409 ret = wait_for(g4x_reset_complete(dev), 500);
1413 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1414 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1415 POSTING_READ(VDECCLK_GATE_D);
1417 pci_write_config_byte(dev->pdev, I915_GDRST,
1418 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1419 ret = wait_for(g4x_reset_complete(dev), 500);
1423 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1424 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1425 POSTING_READ(VDECCLK_GATE_D);
1427 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
1432 static int ironlake_do_reset(struct drm_device *dev)
1434 struct drm_i915_private *dev_priv = dev->dev_private;
1437 I915_WRITE(ILK_GDSR,
1438 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
1439 ret = wait_for((I915_READ(ILK_GDSR) &
1440 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1444 I915_WRITE(ILK_GDSR,
1445 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
1446 ret = wait_for((I915_READ(ILK_GDSR) &
1447 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1451 I915_WRITE(ILK_GDSR, 0);
1456 static int gen6_do_reset(struct drm_device *dev)
1458 struct drm_i915_private *dev_priv = dev->dev_private;
1461 /* Reset the chip */
1463 /* GEN6_GDRST is not in the gt power well, no need to check
1464 * for fifo space for the write or forcewake the chip for
1467 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1469 /* Spin waiting for the device to ack the reset request */
1470 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1472 intel_uncore_forcewake_reset(dev, true);
1477 static int wait_for_register(struct drm_i915_private *dev_priv,
1481 const unsigned long timeout_ms)
1483 return wait_for((I915_READ(reg) & mask) == value, timeout_ms);
1486 static int gen8_do_reset(struct drm_device *dev)
1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 struct intel_engine_cs *engine;
1492 for_each_ring(engine, dev_priv, i) {
1493 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1494 _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
1496 if (wait_for_register(dev_priv,
1497 RING_RESET_CTL(engine->mmio_base),
1498 RESET_CTL_READY_TO_RESET,
1499 RESET_CTL_READY_TO_RESET,
1501 DRM_ERROR("%s: reset request timeout\n", engine->name);
1506 return gen6_do_reset(dev);
1509 for_each_ring(engine, dev_priv, i)
1510 I915_WRITE(RING_RESET_CTL(engine->mmio_base),
1511 _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
1516 static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
1521 if (INTEL_INFO(dev)->gen >= 8)
1522 return gen8_do_reset;
1523 else if (INTEL_INFO(dev)->gen >= 6)
1524 return gen6_do_reset;
1525 else if (IS_GEN5(dev))
1526 return ironlake_do_reset;
1527 else if (IS_G4X(dev))
1528 return g4x_do_reset;
1529 else if (IS_G33(dev))
1530 return g33_do_reset;
1531 else if (INTEL_INFO(dev)->gen >= 3)
1532 return i915_do_reset;
1537 int intel_gpu_reset(struct drm_device *dev)
1539 struct drm_i915_private *dev_priv = to_i915(dev);
1540 int (*reset)(struct drm_device *);
1543 reset = intel_get_gpu_reset(dev);
1547 /* If the power well sleeps during the reset, the reset
1548 * request may be dropped and never completes (causing -EIO).
1550 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1552 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1557 bool intel_has_gpu_reset(struct drm_device *dev)
1559 return intel_get_gpu_reset(dev) != NULL;
1562 void intel_uncore_check_errors(struct drm_device *dev)
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1566 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1567 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1568 DRM_ERROR("Unclaimed register before interrupt\n");
1569 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);