2 * Copyright © 2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
26 * New plane/sprite handling.
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
33 #include <drm/drm_atomic_helper.h>
34 #include <drm/drm_crtc.h>
35 #include <drm/drm_fourcc.h>
36 #include <drm/drm_rect.h>
37 #include <drm/drm_atomic.h>
38 #include <drm/drm_plane_helper.h>
39 #include "intel_drv.h"
40 #include "intel_frontbuffer.h"
41 #include <drm/i915_drm.h>
45 format_is_yuv(uint32_t format)
58 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
62 if (!adjusted_mode->crtc_htotal)
65 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
66 1000 * adjusted_mode->crtc_htotal);
69 #define VBLANK_EVASION_TIME_US 100
72 * intel_pipe_update_start() - start update of a set of display registers
73 * @crtc: the crtc of which the registers are going to be updated
74 * @start_vbl_count: vblank counter return pointer used for error checking
76 * Mark the start of an update to pipe registers that should be updated
77 * atomically regarding vblank. If the next vblank will happens within
78 * the next 100 us, this function waits until the vblank passes.
80 * After a successful call to this function, interrupts will be disabled
81 * until a subsequent call to intel_pipe_update_end(). That is done to
82 * avoid random delays. The value written to @start_vbl_count should be
83 * supplied to intel_pipe_update_end() for error checking.
85 void intel_pipe_update_start(struct intel_crtc *crtc)
87 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
88 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
89 long timeout = msecs_to_jiffies_timeout(1);
90 int scanline, min, max, vblank_start;
91 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
92 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
93 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI);
96 vblank_start = adjusted_mode->crtc_vblank_start;
97 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
98 vblank_start = DIV_ROUND_UP(vblank_start, 2);
100 /* FIXME needs to be calibrated sensibly */
101 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
102 VBLANK_EVASION_TIME_US);
103 max = vblank_start - 1;
107 if (min <= 0 || max <= 0)
110 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
113 crtc->debug.min_vbl = min;
114 crtc->debug.max_vbl = max;
115 trace_i915_pipe_update_start(crtc);
119 * prepare_to_wait() has a memory barrier, which guarantees
120 * other CPUs can see the task state update by the time we
123 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
125 scanline = intel_get_crtc_scanline(crtc);
126 if (scanline < min || scanline > max)
130 DRM_ERROR("Potential atomic update failure on pipe %c\n",
131 pipe_name(crtc->pipe));
137 timeout = schedule_timeout(timeout);
142 finish_wait(wq, &wait);
144 drm_crtc_vblank_put(&crtc->base);
147 * On VLV/CHV DSI the scanline counter would appear to
148 * increment approx. 1/3 of a scanline before start of vblank.
149 * The registers still get latched at start of vblank however.
150 * This means we must not write any registers on the first
151 * line of vblank (since not the whole line is actually in
152 * vblank). And unfortunately we can't use the interrupt to
153 * wait here since it will fire too soon. We could use the
154 * frame start interrupt instead since it will fire after the
155 * critical scanline, but that would require more changes
156 * in the interrupt code. So for now we'll just do the nasty
157 * thing and poll for the bad scanline to pass us by.
159 * FIXME figure out if BXT+ DSI suffers from this as well
161 while (need_vlv_dsi_wa && scanline == vblank_start)
162 scanline = intel_get_crtc_scanline(crtc);
164 crtc->debug.scanline_start = scanline;
165 crtc->debug.start_vbl_time = ktime_get();
166 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
168 trace_i915_pipe_update_vblank_evaded(crtc);
172 * intel_pipe_update_end() - end update of a set of display registers
173 * @crtc: the crtc of which the registers were updated
174 * @start_vbl_count: start vblank counter (used for error checking)
176 * Mark the end of an update started with intel_pipe_update_start(). This
177 * re-enables interrupts and verifies the update was actually completed
178 * before a vblank using the value of @start_vbl_count.
180 void intel_pipe_update_end(struct intel_crtc *crtc)
182 enum pipe pipe = crtc->pipe;
183 int scanline_end = intel_get_crtc_scanline(crtc);
184 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
185 ktime_t end_vbl_time = ktime_get();
186 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
188 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
190 /* We're still in the vblank-evade critical section, this can't race.
191 * Would be slightly nice to just grab the vblank count and arm the
192 * event outside of the critical section - the spinlock might spin for a
194 if (crtc->base.state->event) {
195 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
197 spin_lock(&crtc->base.dev->event_lock);
198 drm_crtc_arm_vblank_event(&crtc->base, crtc->base.state->event);
199 spin_unlock(&crtc->base.dev->event_lock);
201 crtc->base.state->event = NULL;
206 if (intel_vgpu_active(dev_priv))
209 if (crtc->debug.start_vbl_count &&
210 crtc->debug.start_vbl_count != end_vbl_count) {
211 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
212 pipe_name(pipe), crtc->debug.start_vbl_count,
214 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
215 crtc->debug.min_vbl, crtc->debug.max_vbl,
216 crtc->debug.scanline_start, scanline_end);
218 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
219 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
220 VBLANK_EVASION_TIME_US)
221 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
223 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
224 VBLANK_EVASION_TIME_US);
229 skl_update_plane(struct intel_plane *plane,
230 const struct intel_crtc_state *crtc_state,
231 const struct intel_plane_state *plane_state)
233 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
234 const struct drm_framebuffer *fb = plane_state->base.fb;
235 enum plane_id plane_id = plane->id;
236 enum pipe pipe = plane->pipe;
237 u32 plane_ctl = plane_state->ctl;
238 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
239 u32 surf_addr = plane_state->main.offset;
240 unsigned int rotation = plane_state->base.rotation;
241 u32 stride = skl_plane_stride(fb, 0, rotation);
242 u32 aux_stride = skl_plane_stride(fb, 1, rotation);
243 int crtc_x = plane_state->base.dst.x1;
244 int crtc_y = plane_state->base.dst.y1;
245 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
246 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
247 uint32_t x = plane_state->main.x;
248 uint32_t y = plane_state->main.y;
249 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
250 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
251 unsigned long irqflags;
253 /* Sizes are 0 based */
259 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
261 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
262 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
263 PLANE_COLOR_PIPE_GAMMA_ENABLE |
264 PLANE_COLOR_PIPE_CSC_ENABLE |
265 PLANE_COLOR_PLANE_GAMMA_DISABLE);
269 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
270 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
271 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
274 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
275 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
276 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
277 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
278 (plane_state->aux.offset - surf_addr) | aux_stride);
279 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
280 (plane_state->aux.y << 16) | plane_state->aux.x);
282 /* program plane scaler */
283 if (plane_state->scaler_id >= 0) {
284 int scaler_id = plane_state->scaler_id;
285 const struct intel_scaler *scaler;
287 scaler = &crtc_state->scaler_state.scalers[scaler_id];
289 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
290 PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
291 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
292 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
293 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
294 ((crtc_w + 1) << 16)|(crtc_h + 1));
296 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
298 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
301 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
302 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
303 intel_plane_ggtt_offset(plane_state) + surf_addr);
304 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
306 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
310 skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
312 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
313 enum plane_id plane_id = plane->id;
314 enum pipe pipe = plane->pipe;
315 unsigned long irqflags;
317 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
319 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
321 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
322 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
324 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
328 skl_plane_get_hw_state(struct intel_plane *plane)
330 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
331 enum intel_display_power_domain power_domain;
332 enum plane_id plane_id = plane->id;
333 enum pipe pipe = plane->pipe;
336 power_domain = POWER_DOMAIN_PIPE(pipe);
337 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
340 ret = I915_READ(PLANE_CTL(pipe, plane_id)) & PLANE_CTL_ENABLE;
342 intel_display_power_put(dev_priv, power_domain);
348 chv_update_csc(const struct intel_plane_state *plane_state)
350 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
351 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
352 const struct drm_framebuffer *fb = plane_state->base.fb;
353 enum plane_id plane_id = plane->id;
355 /* Seems RGB data bypasses the CSC always */
356 if (!format_is_yuv(fb->format->format))
360 * BT.601 full range YCbCr -> full range RGB
362 * |r| | 5743 4096 0| |cr|
363 * |g| = |-2925 4096 -1410| x |y |
364 * |b| | 0 4096 7258| |cb|
366 * Cb and Cr apparently come in as signed already,
367 * and we get full range data in on account of CLRC0/1
369 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
370 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
371 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
373 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4096) | SPCSC_C0(5743));
374 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-2925) | SPCSC_C0(0));
375 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1410) | SPCSC_C0(4096));
376 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4096) | SPCSC_C0(0));
377 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(7258));
379 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0));
380 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
381 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512));
383 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
384 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
385 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
392 vlv_update_clrc(const struct intel_plane_state *plane_state)
394 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
395 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
396 const struct drm_framebuffer *fb = plane_state->base.fb;
397 enum pipe pipe = plane->pipe;
398 enum plane_id plane_id = plane->id;
399 int contrast, brightness, sh_scale, sh_sin, sh_cos;
401 if (format_is_yuv(fb->format->format)) {
403 * Expand limited range to full range:
404 * Contrast is applied first and is used to expand Y range.
405 * Brightness is applied second and is used to remove the
406 * offset from Y. Saturation/hue is used to expand CbCr range.
408 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16);
409 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16);
410 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128);
411 sh_sin = SIN_0 * sh_scale;
412 sh_cos = COS_0 * sh_scale;
414 /* Pass-through everything. */
418 sh_sin = SIN_0 * sh_scale;
419 sh_cos = COS_0 * sh_scale;
422 /* FIXME these register are single buffered :( */
423 I915_WRITE_FW(SPCLRC0(pipe, plane_id),
424 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness));
425 I915_WRITE_FW(SPCLRC1(pipe, plane_id),
426 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos));
429 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
430 const struct intel_plane_state *plane_state)
432 const struct drm_framebuffer *fb = plane_state->base.fb;
433 unsigned int rotation = plane_state->base.rotation;
434 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
437 sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
439 switch (fb->format->format) {
440 case DRM_FORMAT_YUYV:
441 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
443 case DRM_FORMAT_YVYU:
444 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
446 case DRM_FORMAT_UYVY:
447 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
449 case DRM_FORMAT_VYUY:
450 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
452 case DRM_FORMAT_RGB565:
453 sprctl |= SP_FORMAT_BGR565;
455 case DRM_FORMAT_XRGB8888:
456 sprctl |= SP_FORMAT_BGRX8888;
458 case DRM_FORMAT_ARGB8888:
459 sprctl |= SP_FORMAT_BGRA8888;
461 case DRM_FORMAT_XBGR2101010:
462 sprctl |= SP_FORMAT_RGBX1010102;
464 case DRM_FORMAT_ABGR2101010:
465 sprctl |= SP_FORMAT_RGBA1010102;
467 case DRM_FORMAT_XBGR8888:
468 sprctl |= SP_FORMAT_RGBX8888;
470 case DRM_FORMAT_ABGR8888:
471 sprctl |= SP_FORMAT_RGBA8888;
474 MISSING_CASE(fb->format->format);
478 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
481 if (rotation & DRM_MODE_ROTATE_180)
482 sprctl |= SP_ROTATE_180;
484 if (rotation & DRM_MODE_REFLECT_X)
487 if (key->flags & I915_SET_COLORKEY_SOURCE)
488 sprctl |= SP_SOURCE_KEY;
494 vlv_update_plane(struct intel_plane *plane,
495 const struct intel_crtc_state *crtc_state,
496 const struct intel_plane_state *plane_state)
498 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
499 const struct drm_framebuffer *fb = plane_state->base.fb;
500 enum pipe pipe = plane->pipe;
501 enum plane_id plane_id = plane->id;
502 u32 sprctl = plane_state->ctl;
503 u32 sprsurf_offset = plane_state->main.offset;
505 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
506 int crtc_x = plane_state->base.dst.x1;
507 int crtc_y = plane_state->base.dst.y1;
508 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
509 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
510 uint32_t x = plane_state->main.x;
511 uint32_t y = plane_state->main.y;
512 unsigned long irqflags;
514 /* Sizes are 0 based */
518 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
520 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
522 vlv_update_clrc(plane_state);
524 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
525 chv_update_csc(plane_state);
528 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
529 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
530 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
532 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
533 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
535 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
536 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
538 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
540 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
542 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
543 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
544 I915_WRITE_FW(SPSURF(pipe, plane_id),
545 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
546 POSTING_READ_FW(SPSURF(pipe, plane_id));
548 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
552 vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
554 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
555 enum pipe pipe = plane->pipe;
556 enum plane_id plane_id = plane->id;
557 unsigned long irqflags;
559 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
561 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
563 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
564 POSTING_READ_FW(SPSURF(pipe, plane_id));
566 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
570 vlv_plane_get_hw_state(struct intel_plane *plane)
572 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
573 enum intel_display_power_domain power_domain;
574 enum plane_id plane_id = plane->id;
575 enum pipe pipe = plane->pipe;
578 power_domain = POWER_DOMAIN_PIPE(pipe);
579 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
582 ret = I915_READ(SPCNTR(pipe, plane_id)) & SP_ENABLE;
584 intel_display_power_put(dev_priv, power_domain);
589 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
590 const struct intel_plane_state *plane_state)
592 struct drm_i915_private *dev_priv =
593 to_i915(plane_state->base.plane->dev);
594 const struct drm_framebuffer *fb = plane_state->base.fb;
595 unsigned int rotation = plane_state->base.rotation;
596 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
599 sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
601 if (IS_IVYBRIDGE(dev_priv))
602 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
604 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
605 sprctl |= SPRITE_PIPE_CSC_ENABLE;
607 switch (fb->format->format) {
608 case DRM_FORMAT_XBGR8888:
609 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
611 case DRM_FORMAT_XRGB8888:
612 sprctl |= SPRITE_FORMAT_RGBX888;
614 case DRM_FORMAT_YUYV:
615 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
617 case DRM_FORMAT_YVYU:
618 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
620 case DRM_FORMAT_UYVY:
621 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
623 case DRM_FORMAT_VYUY:
624 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
627 MISSING_CASE(fb->format->format);
631 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
632 sprctl |= SPRITE_TILED;
634 if (rotation & DRM_MODE_ROTATE_180)
635 sprctl |= SPRITE_ROTATE_180;
637 if (key->flags & I915_SET_COLORKEY_DESTINATION)
638 sprctl |= SPRITE_DEST_KEY;
639 else if (key->flags & I915_SET_COLORKEY_SOURCE)
640 sprctl |= SPRITE_SOURCE_KEY;
646 ivb_update_plane(struct intel_plane *plane,
647 const struct intel_crtc_state *crtc_state,
648 const struct intel_plane_state *plane_state)
650 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
651 const struct drm_framebuffer *fb = plane_state->base.fb;
652 enum pipe pipe = plane->pipe;
653 u32 sprctl = plane_state->ctl, sprscale = 0;
654 u32 sprsurf_offset = plane_state->main.offset;
656 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
657 int crtc_x = plane_state->base.dst.x1;
658 int crtc_y = plane_state->base.dst.y1;
659 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
660 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
661 uint32_t x = plane_state->main.x;
662 uint32_t y = plane_state->main.y;
663 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
664 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
665 unsigned long irqflags;
667 /* Sizes are 0 based */
673 if (crtc_w != src_w || crtc_h != src_h)
674 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
676 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
678 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
681 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
682 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
683 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
686 I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
687 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
689 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
691 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
692 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
693 else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
694 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
696 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
698 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
699 if (plane->can_scale)
700 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
701 I915_WRITE_FW(SPRCTL(pipe), sprctl);
702 I915_WRITE_FW(SPRSURF(pipe),
703 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
704 POSTING_READ_FW(SPRSURF(pipe));
706 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
710 ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
712 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
713 enum pipe pipe = plane->pipe;
714 unsigned long irqflags;
716 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
718 I915_WRITE_FW(SPRCTL(pipe), 0);
719 /* Can't leave the scaler enabled... */
720 if (plane->can_scale)
721 I915_WRITE_FW(SPRSCALE(pipe), 0);
723 I915_WRITE_FW(SPRSURF(pipe), 0);
724 POSTING_READ_FW(SPRSURF(pipe));
726 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
730 ivb_plane_get_hw_state(struct intel_plane *plane)
732 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
733 enum intel_display_power_domain power_domain;
734 enum pipe pipe = plane->pipe;
737 power_domain = POWER_DOMAIN_PIPE(pipe);
738 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
741 ret = I915_READ(SPRCTL(pipe)) & SPRITE_ENABLE;
743 intel_display_power_put(dev_priv, power_domain);
748 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
749 const struct intel_plane_state *plane_state)
751 struct drm_i915_private *dev_priv =
752 to_i915(plane_state->base.plane->dev);
753 const struct drm_framebuffer *fb = plane_state->base.fb;
754 unsigned int rotation = plane_state->base.rotation;
755 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
758 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
760 if (IS_GEN6(dev_priv))
761 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
763 switch (fb->format->format) {
764 case DRM_FORMAT_XBGR8888:
765 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
767 case DRM_FORMAT_XRGB8888:
768 dvscntr |= DVS_FORMAT_RGBX888;
770 case DRM_FORMAT_YUYV:
771 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
773 case DRM_FORMAT_YVYU:
774 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
776 case DRM_FORMAT_UYVY:
777 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
779 case DRM_FORMAT_VYUY:
780 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
783 MISSING_CASE(fb->format->format);
787 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
788 dvscntr |= DVS_TILED;
790 if (rotation & DRM_MODE_ROTATE_180)
791 dvscntr |= DVS_ROTATE_180;
793 if (key->flags & I915_SET_COLORKEY_DESTINATION)
794 dvscntr |= DVS_DEST_KEY;
795 else if (key->flags & I915_SET_COLORKEY_SOURCE)
796 dvscntr |= DVS_SOURCE_KEY;
802 g4x_update_plane(struct intel_plane *plane,
803 const struct intel_crtc_state *crtc_state,
804 const struct intel_plane_state *plane_state)
806 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
807 const struct drm_framebuffer *fb = plane_state->base.fb;
808 enum pipe pipe = plane->pipe;
809 u32 dvscntr = plane_state->ctl, dvsscale = 0;
810 u32 dvssurf_offset = plane_state->main.offset;
812 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
813 int crtc_x = plane_state->base.dst.x1;
814 int crtc_y = plane_state->base.dst.y1;
815 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
816 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
817 uint32_t x = plane_state->main.x;
818 uint32_t y = plane_state->main.y;
819 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
820 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
821 unsigned long irqflags;
823 /* Sizes are 0 based */
829 if (crtc_w != src_w || crtc_h != src_h)
830 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
832 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
834 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
837 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
838 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
839 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
842 I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
843 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
845 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
846 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
848 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
850 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
851 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
852 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
853 I915_WRITE_FW(DVSSURF(pipe),
854 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
855 POSTING_READ_FW(DVSSURF(pipe));
857 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
861 g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
863 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
864 enum pipe pipe = plane->pipe;
865 unsigned long irqflags;
867 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
869 I915_WRITE_FW(DVSCNTR(pipe), 0);
870 /* Disable the scaler */
871 I915_WRITE_FW(DVSSCALE(pipe), 0);
873 I915_WRITE_FW(DVSSURF(pipe), 0);
874 POSTING_READ_FW(DVSSURF(pipe));
876 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
880 g4x_plane_get_hw_state(struct intel_plane *plane)
882 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
883 enum intel_display_power_domain power_domain;
884 enum pipe pipe = plane->pipe;
887 power_domain = POWER_DOMAIN_PIPE(pipe);
888 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
891 ret = I915_READ(DVSCNTR(pipe)) & DVS_ENABLE;
893 intel_display_power_put(dev_priv, power_domain);
899 intel_check_sprite_plane(struct intel_plane *plane,
900 struct intel_crtc_state *crtc_state,
901 struct intel_plane_state *state)
903 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
904 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
905 struct drm_framebuffer *fb = state->base.fb;
907 unsigned int crtc_w, crtc_h;
908 uint32_t src_x, src_y, src_w, src_h;
909 struct drm_rect *src = &state->base.src;
910 struct drm_rect *dst = &state->base.dst;
911 const struct drm_rect *clip = &state->clip;
913 int max_scale, min_scale;
917 *src = drm_plane_state_src(&state->base);
918 *dst = drm_plane_state_dest(&state->base);
921 state->base.visible = false;
925 /* Don't modify another pipe's plane */
926 if (plane->pipe != crtc->pipe) {
927 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
931 /* FIXME check all gen limits */
932 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
933 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
937 /* setup can_scale, min_scale, max_scale */
938 if (INTEL_GEN(dev_priv) >= 9) {
939 /* use scaler when colorkey is not required */
940 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
943 max_scale = skl_max_scale(crtc, crtc_state);
946 min_scale = DRM_PLANE_HELPER_NO_SCALING;
947 max_scale = DRM_PLANE_HELPER_NO_SCALING;
950 can_scale = plane->can_scale;
951 max_scale = plane->max_downscale << 16;
952 min_scale = plane->can_scale ? 1 : (1 << 16);
956 * FIXME the following code does a bunch of fuzzy adjustments to the
957 * coordinates and sizes. We probably need some way to decide whether
958 * more strict checking should be done instead.
960 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
961 state->base.rotation);
963 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
966 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
969 state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
973 crtc_w = drm_rect_width(dst);
974 crtc_h = drm_rect_height(dst);
976 if (state->base.visible) {
977 /* check again in case clipping clamped the results */
978 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
980 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
981 drm_rect_debug_print("src: ", src, true);
982 drm_rect_debug_print("dst: ", dst, false);
987 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
989 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
990 drm_rect_debug_print("src: ", src, true);
991 drm_rect_debug_print("dst: ", dst, false);
996 /* Make the source viewport size an exact multiple of the scaling factors. */
997 drm_rect_adjust_size(src,
998 drm_rect_width(dst) * hscale - drm_rect_width(src),
999 drm_rect_height(dst) * vscale - drm_rect_height(src));
1001 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
1002 state->base.rotation);
1004 /* sanity check to make sure the src viewport wasn't enlarged */
1005 WARN_ON(src->x1 < (int) state->base.src_x ||
1006 src->y1 < (int) state->base.src_y ||
1007 src->x2 > (int) state->base.src_x + state->base.src_w ||
1008 src->y2 > (int) state->base.src_y + state->base.src_h);
1011 * Hardware doesn't handle subpixel coordinates.
1012 * Adjust to (macro)pixel boundary, but be careful not to
1013 * increase the source viewport size, because that could
1014 * push the downscaling factor out of bounds.
1016 src_x = src->x1 >> 16;
1017 src_w = drm_rect_width(src) >> 16;
1018 src_y = src->y1 >> 16;
1019 src_h = drm_rect_height(src) >> 16;
1021 if (format_is_yuv(fb->format->format)) {
1026 * Must keep src and dst the
1027 * same if we can't scale.
1033 state->base.visible = false;
1037 /* Check size restrictions when scaling */
1038 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
1039 unsigned int width_bytes;
1040 int cpp = fb->format->cpp[0];
1042 WARN_ON(!can_scale);
1044 /* FIXME interlacing min height is 6 */
1046 if (crtc_w < 3 || crtc_h < 3)
1047 state->base.visible = false;
1049 if (src_w < 3 || src_h < 3)
1050 state->base.visible = false;
1052 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
1054 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
1055 width_bytes > 4096 || fb->pitches[0] > 4096)) {
1056 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1061 if (state->base.visible) {
1062 src->x1 = src_x << 16;
1063 src->x2 = (src_x + src_w) << 16;
1064 src->y1 = src_y << 16;
1065 src->y2 = (src_y + src_h) << 16;
1069 dst->x2 = crtc_x + crtc_w;
1071 dst->y2 = crtc_y + crtc_h;
1073 if (INTEL_GEN(dev_priv) >= 9) {
1074 ret = skl_check_plane_surface(state);
1078 state->ctl = skl_plane_ctl(crtc_state, state);
1079 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1080 ret = i9xx_check_plane_surface(state);
1084 state->ctl = vlv_sprite_ctl(crtc_state, state);
1085 } else if (INTEL_GEN(dev_priv) >= 7) {
1086 ret = i9xx_check_plane_surface(state);
1090 state->ctl = ivb_sprite_ctl(crtc_state, state);
1092 ret = i9xx_check_plane_surface(state);
1096 state->ctl = g4x_sprite_ctl(crtc_state, state);
1102 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1103 struct drm_file *file_priv)
1105 struct drm_i915_private *dev_priv = to_i915(dev);
1106 struct drm_intel_sprite_colorkey *set = data;
1107 struct drm_plane *plane;
1108 struct drm_plane_state *plane_state;
1109 struct drm_atomic_state *state;
1110 struct drm_modeset_acquire_ctx ctx;
1113 /* Make sure we don't try to enable both src & dest simultaneously */
1114 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1117 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1118 set->flags & I915_SET_COLORKEY_DESTINATION)
1121 plane = drm_plane_find(dev, set->plane_id);
1122 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1125 drm_modeset_acquire_init(&ctx, 0);
1127 state = drm_atomic_state_alloc(plane->dev);
1132 state->acquire_ctx = &ctx;
1135 plane_state = drm_atomic_get_plane_state(state, plane);
1136 ret = PTR_ERR_OR_ZERO(plane_state);
1138 to_intel_plane_state(plane_state)->ckey = *set;
1139 ret = drm_atomic_commit(state);
1142 if (ret != -EDEADLK)
1145 drm_atomic_state_clear(state);
1146 drm_modeset_backoff(&ctx);
1149 drm_atomic_state_put(state);
1151 drm_modeset_drop_locks(&ctx);
1152 drm_modeset_acquire_fini(&ctx);
1156 static const uint32_t g4x_plane_formats[] = {
1157 DRM_FORMAT_XRGB8888,
1164 static const uint64_t i9xx_plane_format_modifiers[] = {
1165 I915_FORMAT_MOD_X_TILED,
1166 DRM_FORMAT_MOD_LINEAR,
1167 DRM_FORMAT_MOD_INVALID
1170 static const uint32_t snb_plane_formats[] = {
1171 DRM_FORMAT_XBGR8888,
1172 DRM_FORMAT_XRGB8888,
1179 static const uint32_t vlv_plane_formats[] = {
1181 DRM_FORMAT_ABGR8888,
1182 DRM_FORMAT_ARGB8888,
1183 DRM_FORMAT_XBGR8888,
1184 DRM_FORMAT_XRGB8888,
1185 DRM_FORMAT_XBGR2101010,
1186 DRM_FORMAT_ABGR2101010,
1193 static uint32_t skl_plane_formats[] = {
1195 DRM_FORMAT_ABGR8888,
1196 DRM_FORMAT_ARGB8888,
1197 DRM_FORMAT_XBGR8888,
1198 DRM_FORMAT_XRGB8888,
1205 static const uint64_t skl_plane_format_modifiers[] = {
1206 I915_FORMAT_MOD_X_TILED,
1207 DRM_FORMAT_MOD_LINEAR,
1208 DRM_FORMAT_MOD_INVALID
1211 static bool g4x_sprite_plane_format_mod_supported(struct drm_plane *plane,
1216 case DRM_FORMAT_XBGR8888:
1217 case DRM_FORMAT_XRGB8888:
1218 case DRM_FORMAT_YUYV:
1219 case DRM_FORMAT_YVYU:
1220 case DRM_FORMAT_UYVY:
1221 case DRM_FORMAT_VYUY:
1222 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1223 modifier == I915_FORMAT_MOD_X_TILED)
1231 static bool vlv_sprite_plane_format_mod_supported(struct drm_plane *plane,
1236 case DRM_FORMAT_YUYV:
1237 case DRM_FORMAT_YVYU:
1238 case DRM_FORMAT_UYVY:
1239 case DRM_FORMAT_VYUY:
1240 case DRM_FORMAT_RGB565:
1241 case DRM_FORMAT_XRGB8888:
1242 case DRM_FORMAT_ARGB8888:
1243 case DRM_FORMAT_XBGR2101010:
1244 case DRM_FORMAT_ABGR2101010:
1245 case DRM_FORMAT_XBGR8888:
1246 case DRM_FORMAT_ABGR8888:
1247 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1248 modifier == I915_FORMAT_MOD_X_TILED)
1256 static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane,
1260 /* This is the same as primary plane since SKL has universal planes */
1262 case DRM_FORMAT_XRGB8888:
1263 case DRM_FORMAT_XBGR8888:
1264 case DRM_FORMAT_ARGB8888:
1265 case DRM_FORMAT_ABGR8888:
1266 case DRM_FORMAT_RGB565:
1267 case DRM_FORMAT_XRGB2101010:
1268 case DRM_FORMAT_XBGR2101010:
1269 case DRM_FORMAT_YUYV:
1270 case DRM_FORMAT_YVYU:
1271 case DRM_FORMAT_UYVY:
1272 case DRM_FORMAT_VYUY:
1273 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1277 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1278 modifier == I915_FORMAT_MOD_X_TILED ||
1279 modifier == I915_FORMAT_MOD_Y_TILED)
1287 static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1291 struct drm_i915_private *dev_priv = to_i915(plane->dev);
1293 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1296 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1297 modifier != DRM_FORMAT_MOD_LINEAR)
1300 if (INTEL_GEN(dev_priv) >= 9)
1301 return skl_sprite_plane_format_mod_supported(plane, format, modifier);
1302 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1303 return vlv_sprite_plane_format_mod_supported(plane, format, modifier);
1305 return g4x_sprite_plane_format_mod_supported(plane, format, modifier);
1310 static const struct drm_plane_funcs intel_sprite_plane_funcs = {
1311 .update_plane = drm_atomic_helper_update_plane,
1312 .disable_plane = drm_atomic_helper_disable_plane,
1313 .destroy = intel_plane_destroy,
1314 .atomic_get_property = intel_plane_atomic_get_property,
1315 .atomic_set_property = intel_plane_atomic_set_property,
1316 .atomic_duplicate_state = intel_plane_duplicate_state,
1317 .atomic_destroy_state = intel_plane_destroy_state,
1318 .format_mod_supported = intel_sprite_plane_format_mod_supported,
1321 struct intel_plane *
1322 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, int plane)
1325 struct intel_plane *intel_plane = NULL;
1326 struct intel_plane_state *state = NULL;
1327 unsigned long possible_crtcs;
1328 const uint32_t *plane_formats;
1329 const uint64_t *modifiers;
1330 unsigned int supported_rotations;
1331 int num_plane_formats;
1334 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
1340 state = intel_create_plane_state(&intel_plane->base);
1345 intel_plane->base.state = &state->base;
1347 if (INTEL_GEN(dev_priv) >= 10) {
1348 intel_plane->can_scale = true;
1349 state->scaler_id = -1;
1351 intel_plane->update_plane = skl_update_plane;
1352 intel_plane->disable_plane = skl_disable_plane;
1353 intel_plane->get_hw_state = skl_plane_get_hw_state;
1355 plane_formats = skl_plane_formats;
1356 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1357 modifiers = skl_plane_format_modifiers;
1358 } else if (INTEL_GEN(dev_priv) >= 9) {
1359 intel_plane->can_scale = true;
1360 state->scaler_id = -1;
1362 intel_plane->update_plane = skl_update_plane;
1363 intel_plane->disable_plane = skl_disable_plane;
1364 intel_plane->get_hw_state = skl_plane_get_hw_state;
1366 plane_formats = skl_plane_formats;
1367 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1368 modifiers = skl_plane_format_modifiers;
1369 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1370 intel_plane->can_scale = false;
1371 intel_plane->max_downscale = 1;
1373 intel_plane->update_plane = vlv_update_plane;
1374 intel_plane->disable_plane = vlv_disable_plane;
1375 intel_plane->get_hw_state = vlv_plane_get_hw_state;
1377 plane_formats = vlv_plane_formats;
1378 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1379 modifiers = i9xx_plane_format_modifiers;
1380 } else if (INTEL_GEN(dev_priv) >= 7) {
1381 if (IS_IVYBRIDGE(dev_priv)) {
1382 intel_plane->can_scale = true;
1383 intel_plane->max_downscale = 2;
1385 intel_plane->can_scale = false;
1386 intel_plane->max_downscale = 1;
1389 intel_plane->update_plane = ivb_update_plane;
1390 intel_plane->disable_plane = ivb_disable_plane;
1391 intel_plane->get_hw_state = ivb_plane_get_hw_state;
1393 plane_formats = snb_plane_formats;
1394 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1395 modifiers = i9xx_plane_format_modifiers;
1397 intel_plane->can_scale = true;
1398 intel_plane->max_downscale = 16;
1400 intel_plane->update_plane = g4x_update_plane;
1401 intel_plane->disable_plane = g4x_disable_plane;
1402 intel_plane->get_hw_state = g4x_plane_get_hw_state;
1404 modifiers = i9xx_plane_format_modifiers;
1405 if (IS_GEN6(dev_priv)) {
1406 plane_formats = snb_plane_formats;
1407 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1409 plane_formats = g4x_plane_formats;
1410 num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
1414 if (INTEL_GEN(dev_priv) >= 9) {
1415 supported_rotations =
1416 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1417 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
1418 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1419 supported_rotations =
1420 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1423 supported_rotations =
1424 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1427 intel_plane->pipe = pipe;
1428 intel_plane->plane = plane;
1429 intel_plane->id = PLANE_SPRITE0 + plane;
1430 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
1431 intel_plane->check_plane = intel_check_sprite_plane;
1433 possible_crtcs = (1 << pipe);
1435 if (INTEL_GEN(dev_priv) >= 9)
1436 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1437 possible_crtcs, &intel_sprite_plane_funcs,
1438 plane_formats, num_plane_formats,
1440 DRM_PLANE_TYPE_OVERLAY,
1441 "plane %d%c", plane + 2, pipe_name(pipe));
1443 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
1444 possible_crtcs, &intel_sprite_plane_funcs,
1445 plane_formats, num_plane_formats,
1447 DRM_PLANE_TYPE_OVERLAY,
1448 "sprite %c", sprite_name(pipe, plane));
1452 drm_plane_create_rotation_property(&intel_plane->base,
1454 supported_rotations);
1456 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1464 return ERR_PTR(ret);