drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *    Daniel Vetter <daniel.vetter@ffwll.ch>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 static struct i915_power_well *
  69 lookup_power_well(struct drm_i915_private *dev_priv, int power_well_id);
  70
  71 const char *
  72 intel_display_power_domain_str(enum intel_display_power_domain domain)
  73 {
  74         switch (domain) {
  75         case POWER_DOMAIN_PIPE_A:
  76                 return "PIPE_A";
  77         case POWER_DOMAIN_PIPE_B:
  78                 return "PIPE_B";
  79         case POWER_DOMAIN_PIPE_C:
  80                 return "PIPE_C";
  81         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  82                 return "PIPE_A_PANEL_FITTER";
  83         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  84                 return "PIPE_B_PANEL_FITTER";
  85         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  86                 return "PIPE_C_PANEL_FITTER";
  87         case POWER_DOMAIN_TRANSCODER_A:
  88                 return "TRANSCODER_A";
  89         case POWER_DOMAIN_TRANSCODER_B:
  90                 return "TRANSCODER_B";
  91         case POWER_DOMAIN_TRANSCODER_C:
  92                 return "TRANSCODER_C";
  93         case POWER_DOMAIN_TRANSCODER_EDP:
  94                 return "TRANSCODER_EDP";
  95         case POWER_DOMAIN_TRANSCODER_DSI_A:
  96                 return "TRANSCODER_DSI_A";
  97         case POWER_DOMAIN_TRANSCODER_DSI_C:
  98                 return "TRANSCODER_DSI_C";
  99         case POWER_DOMAIN_PORT_DDI_A_LANES:
 100                 return "PORT_DDI_A_LANES";
 101         case POWER_DOMAIN_PORT_DDI_B_LANES:
 102                 return "PORT_DDI_B_LANES";
 103         case POWER_DOMAIN_PORT_DDI_C_LANES:
 104                 return "PORT_DDI_C_LANES";
 105         case POWER_DOMAIN_PORT_DDI_D_LANES:
 106                 return "PORT_DDI_D_LANES";
 107         case POWER_DOMAIN_PORT_DDI_E_LANES:
 108                 return "PORT_DDI_E_LANES";
 109         case POWER_DOMAIN_PORT_DSI:
 110                 return "PORT_DSI";
 111         case POWER_DOMAIN_PORT_CRT:
 112                 return "PORT_CRT";
 113         case POWER_DOMAIN_PORT_OTHER:
 114                 return "PORT_OTHER";
 115         case POWER_DOMAIN_VGA:
 116                 return "VGA";
 117         case POWER_DOMAIN_AUDIO:
 118                 return "AUDIO";
 119         case POWER_DOMAIN_PLLS:
 120                 return "PLLS";
 121         case POWER_DOMAIN_AUX_A:
 122                 return "AUX_A";
 123         case POWER_DOMAIN_AUX_B:
 124                 return "AUX_B";
 125         case POWER_DOMAIN_AUX_C:
 126                 return "AUX_C";
 127         case POWER_DOMAIN_AUX_D:
 128                 return "AUX_D";
 129         case POWER_DOMAIN_GMBUS:
 130                 return "GMBUS";
 131         case POWER_DOMAIN_INIT:
 132                 return "INIT";
 133         case POWER_DOMAIN_MODESET:
 134                 return "MODESET";
 135         default:
 136                 MISSING_CASE(domain);
 137                 return "?";
 138         }
 139 }
 140
 141 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 142                                     struct i915_power_well *power_well)
 143 {
 144         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 145         power_well->ops->enable(dev_priv, power_well);
 146         power_well->hw_enabled = true;
 147 }
 148
 149 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 150                                      struct i915_power_well *power_well)
 151 {
 152         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 153         power_well->hw_enabled = false;
 154         power_well->ops->disable(dev_priv, power_well);
 155 }
 156
 157 static void intel_power_well_get(struct drm_i915_private *dev_priv,
 158                                  struct i915_power_well *power_well)
 159 {
 160         if (!power_well->count++)
 161                 intel_power_well_enable(dev_priv, power_well);
 162 }
 163
 164 static void intel_power_well_put(struct drm_i915_private *dev_priv,
 165                                  struct i915_power_well *power_well)
 166 {
 167         WARN(!power_well->count, "Use count on power well %s is already zero",
 168              power_well->name);
 169
 170         if (!--power_well->count)
 171                 intel_power_well_disable(dev_priv, power_well);
 172 }
 173
 174 /*
 175  * We should only use the power well if we explicitly asked the hardware to
 176  * enable it, so check if it's enabled and also check if we've requested it to
 177  * be enabled.
 178  */
 179 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 180                                    struct i915_power_well *power_well)
 181 {
 182         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 183                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 184 }
 185
 186 /**
 187  * __intel_display_power_is_enabled - unlocked check for a power domain
 188  * @dev_priv: i915 device instance
 189  * @domain: power domain to check
 190  *
 191  * This is the unlocked version of intel_display_power_is_enabled() and should
 192  * only be used from error capture and recovery code where deadlocks are
 193  * possible.
 194  *
 195  * Returns:
 196  * True when the power domain is enabled, false otherwise.
 197  */
 198 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 199                                       enum intel_display_power_domain domain)
 200 {
 201         struct i915_power_domains *power_domains;
 202         struct i915_power_well *power_well;
 203         bool is_enabled;
 204         int i;
 205
 206         if (dev_priv->pm.suspended)
 207                 return false;
 208
 209         power_domains = &dev_priv->power_domains;
 210
 211         is_enabled = true;
 212
 213         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 214                 if (power_well->always_on)
 215                         continue;
 216
 217                 if (!power_well->hw_enabled) {
 218                         is_enabled = false;
 219                         break;
 220                 }
 221         }
 222
 223         return is_enabled;
 224 }
 225
 226 /**
 227  * intel_display_power_is_enabled - check for a power domain
 228  * @dev_priv: i915 device instance
 229  * @domain: power domain to check
 230  *
 231  * This function can be used to check the hw power domain state. It is mostly
 232  * used in hardware state readout functions. Everywhere else code should rely
 233  * upon explicit power domain reference counting to ensure that the hardware
 234  * block is powered up before accessing it.
 235  *
 236  * Callers must hold the relevant modesetting locks to ensure that concurrent
 237  * threads can't disable the power well while the caller tries to read a few
 238  * registers.
 239  *
 240  * Returns:
 241  * True when the power domain is enabled, false otherwise.
 242  */
 243 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 244                                     enum intel_display_power_domain domain)
 245 {
 246         struct i915_power_domains *power_domains;
 247         bool ret;
 248
 249         power_domains = &dev_priv->power_domains;
 250
 251         mutex_lock(&power_domains->lock);
 252         ret = __intel_display_power_is_enabled(dev_priv, domain);
 253         mutex_unlock(&power_domains->lock);
 254
 255         return ret;
 256 }
 257
 258 /**
 259  * intel_display_set_init_power - set the initial power domain state
 260  * @dev_priv: i915 device instance
 261  * @enable: whether to enable or disable the initial power domain state
 262  *
 263  * For simplicity our driver load/unload and system suspend/resume code assumes
 264  * that all power domains are always enabled. This functions controls the state
 265  * of this little hack. While the initial power domain state is enabled runtime
 266  * pm is effectively disabled.
 267  */
 268 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 269                                   bool enable)
 270 {
 271         if (dev_priv->power_domains.init_power_on == enable)
 272                 return;
 273
 274         if (enable)
 275                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 276         else
 277                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 278
 279         dev_priv->power_domains.init_power_on = enable;
 280 }
 281
 282 /*
 283  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 284  * when not needed anymore. We have 4 registers that can request the power well
 285  * to be enabled, and it will only be disabled if none of the registers is
 286  * requesting it to be enabled.
 287  */
 288 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 289 {
 290         struct pci_dev *pdev = dev_priv->drm.pdev;
 291         struct drm_device *dev = &dev_priv->drm;
 292
 293         /*
 294          * After we re-enable the power well, if we touch VGA register 0x3d5
 295          * we'll get unclaimed register interrupts. This stops after we write
 296          * anything to the VGA MSR register. The vgacon module uses this
 297          * register all the time, so if we unbind our driver and, as a
 298          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 299          * console_unlock(). So make here we touch the VGA MSR register, making
 300          * sure vgacon can keep working normally without triggering interrupts
 301          * and error messages.
 302          */
 303         vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
 304         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 305         vga_put(pdev, VGA_RSRC_LEGACY_IO);
 306
 307         if (IS_BROADWELL(dev))
 308                 gen8_irq_power_well_post_enable(dev_priv,
 309                                                 1 << PIPE_C | 1 << PIPE_B);
 310 }
 311
 312 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 313 {
 314         if (IS_BROADWELL(dev_priv))
 315                 gen8_irq_power_well_pre_disable(dev_priv,
 316                                                 1 << PIPE_C | 1 << PIPE_B);
 317 }
 318
 319 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 320                                        struct i915_power_well *power_well)
 321 {
 322         struct pci_dev *pdev = dev_priv->drm.pdev;
 323
 324         /*
 325          * After we re-enable the power well, if we touch VGA register 0x3d5
 326          * we'll get unclaimed register interrupts. This stops after we write
 327          * anything to the VGA MSR register. The vgacon module uses this
 328          * register all the time, so if we unbind our driver and, as a
 329          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 330          * console_unlock(). So make here we touch the VGA MSR register, making
 331          * sure vgacon can keep working normally without triggering interrupts
 332          * and error messages.
 333          */
 334         if (power_well->data == SKL_DISP_PW_2) {
 335                 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
 336                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 337                 vga_put(pdev, VGA_RSRC_LEGACY_IO);
 338
 339                 gen8_irq_power_well_post_enable(dev_priv,
 340                                                 1 << PIPE_C | 1 << PIPE_B);
 341         }
 342 }
 343
 344 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 345                                        struct i915_power_well *power_well)
 346 {
 347         if (power_well->data == SKL_DISP_PW_2)
 348                 gen8_irq_power_well_pre_disable(dev_priv,
 349                                                 1 << PIPE_C | 1 << PIPE_B);
 350 }
 351
 352 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 353                                struct i915_power_well *power_well, bool enable)
 354 {
 355         bool is_enabled, enable_requested;
 356         uint32_t tmp;
 357
 358         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 359         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 360         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 361
 362         if (enable) {
 363                 if (!enable_requested)
 364                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 365                                    HSW_PWR_WELL_ENABLE_REQUEST);
 366
 367                 if (!is_enabled) {
 368                         DRM_DEBUG_KMS("Enabling power well\n");
 369                         if (intel_wait_for_register(dev_priv,
 370                                                     HSW_PWR_WELL_DRIVER,
 371                                                     HSW_PWR_WELL_STATE_ENABLED,
 372                                                     HSW_PWR_WELL_STATE_ENABLED,
 373                                                     20))
 374                                 DRM_ERROR("Timeout enabling power well\n");
 375                         hsw_power_well_post_enable(dev_priv);
 376                 }
 377
 378         } else {
 379                 if (enable_requested) {
 380                         hsw_power_well_pre_disable(dev_priv);
 381                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 382                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 383                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 384                 }
 385         }
 386 }
 387
 388 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 389         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 390         BIT(POWER_DOMAIN_PIPE_B) |                      \
 391         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 392         BIT(POWER_DOMAIN_PIPE_C) |                      \
 393         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 394         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 395         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 396         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 397         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 398         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 399         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 400         BIT(POWER_DOMAIN_AUX_B) |                       \
 401         BIT(POWER_DOMAIN_AUX_C) |                       \
 402         BIT(POWER_DOMAIN_AUX_D) |                       \
 403         BIT(POWER_DOMAIN_AUDIO) |                       \
 404         BIT(POWER_DOMAIN_VGA) |                         \
 405         BIT(POWER_DOMAIN_INIT))
 406 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 407         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 408         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 409         BIT(POWER_DOMAIN_INIT))
 410 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 411         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 412         BIT(POWER_DOMAIN_INIT))
 413 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 414         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 415         BIT(POWER_DOMAIN_INIT))
 416 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 417         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 418         BIT(POWER_DOMAIN_INIT))
 419 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 420         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 421         BIT(POWER_DOMAIN_MODESET) |                     \
 422         BIT(POWER_DOMAIN_AUX_A) |                       \
 423         BIT(POWER_DOMAIN_INIT))
 424
 425 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 426         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 427         BIT(POWER_DOMAIN_PIPE_B) |                      \
 428         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 429         BIT(POWER_DOMAIN_PIPE_C) |                      \
 430         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 431         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 432         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 433         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 434         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 435         BIT(POWER_DOMAIN_AUX_B) |                       \
 436         BIT(POWER_DOMAIN_AUX_C) |                       \
 437         BIT(POWER_DOMAIN_AUDIO) |                       \
 438         BIT(POWER_DOMAIN_VGA) |                         \
 439         BIT(POWER_DOMAIN_GMBUS) |                       \
 440         BIT(POWER_DOMAIN_INIT))
 441 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 442         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 443         BIT(POWER_DOMAIN_MODESET) |                     \
 444         BIT(POWER_DOMAIN_AUX_A) |                       \
 445         BIT(POWER_DOMAIN_INIT))
 446 #define BXT_DPIO_CMN_A_POWER_DOMAINS (                  \
 447         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 448         BIT(POWER_DOMAIN_AUX_A) |                       \
 449         BIT(POWER_DOMAIN_INIT))
 450 #define BXT_DPIO_CMN_BC_POWER_DOMAINS (                 \
 451         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 452         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 453         BIT(POWER_DOMAIN_AUX_B) |                       \
 454         BIT(POWER_DOMAIN_AUX_C) |                       \
 455         BIT(POWER_DOMAIN_INIT))
 456
 457 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 458 {
 459         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 460                   "DC9 already programmed to be enabled.\n");
 461         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 462                   "DC5 still not disabled to enable DC9.\n");
 463         WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 464         WARN_ONCE(intel_irqs_enabled(dev_priv),
 465                   "Interrupts not disabled yet.\n");
 466
 467          /*
 468           * TODO: check for the following to verify the conditions to enter DC9
 469           * state are satisfied:
 470           * 1] Check relevant display engine registers to verify if mode set
 471           * disable sequence was followed.
 472           * 2] Check if display uninitialize sequence is initialized.
 473           */
 474 }
 475
 476 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 477 {
 478         WARN_ONCE(intel_irqs_enabled(dev_priv),
 479                   "Interrupts not disabled yet.\n");
 480         WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 481                   "DC5 still not disabled.\n");
 482
 483          /*
 484           * TODO: check for the following to verify DC9 state was indeed
 485           * entered before programming to disable it:
 486           * 1] Check relevant display engine registers to verify if mode
 487           *  set disable sequence was followed.
 488           * 2] Check if display uninitialize sequence is initialized.
 489           */
 490 }
 491
 492 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 493                                 u32 state)
 494 {
 495         int rewrites = 0;
 496         int rereads = 0;
 497         u32 v;
 498
 499         I915_WRITE(DC_STATE_EN, state);
 500
 501         /* It has been observed that disabling the dc6 state sometimes
 502          * doesn't stick and dmc keeps returning old value. Make sure
 503          * the write really sticks enough times and also force rewrite until
 504          * we are confident that state is exactly what we want.
 505          */
 506         do  {
 507                 v = I915_READ(DC_STATE_EN);
 508
 509                 if (v != state) {
 510                         I915_WRITE(DC_STATE_EN, state);
 511                         rewrites++;
 512                         rereads = 0;
 513                 } else if (rereads++ > 5) {
 514                         break;
 515                 }
 516
 517         } while (rewrites < 100);
 518
 519         if (v != state)
 520                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 521                           state, v);
 522
 523         /* Most of the times we need one retry, avoid spam */
 524         if (rewrites > 1)
 525                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 526                               state, rewrites);
 527 }
 528
 529 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 530 {
 531         u32 mask;
 532
 533         mask = DC_STATE_EN_UPTO_DC5;
 534         if (IS_BROXTON(dev_priv))
 535                 mask |= DC_STATE_EN_DC9;
 536         else
 537                 mask |= DC_STATE_EN_UPTO_DC6;
 538
 539         return mask;
 540 }
 541
 542 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
 543 {
 544         u32 val;
 545
 546         val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
 547
 548         DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
 549                       dev_priv->csr.dc_state, val);
 550         dev_priv->csr.dc_state = val;
 551 }
 552
 553 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 554 {
 555         uint32_t val;
 556         uint32_t mask;
 557
 558         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 559                 state &= dev_priv->csr.allowed_dc_mask;
 560
 561         val = I915_READ(DC_STATE_EN);
 562         mask = gen9_dc_mask(dev_priv);
 563         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 564                       val & mask, state);
 565
 566         /* Check if DMC is ignoring our DC state requests */
 567         if ((val & mask) != dev_priv->csr.dc_state)
 568                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 569                           dev_priv->csr.dc_state, val & mask);
 570
 571         val &= ~mask;
 572         val |= state;
 573
 574         gen9_write_dc_state(dev_priv, val);
 575
 576         dev_priv->csr.dc_state = val & mask;
 577 }
 578
 579 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 580 {
 581         assert_can_enable_dc9(dev_priv);
 582
 583         DRM_DEBUG_KMS("Enabling DC9\n");
 584
 585         intel_power_sequencer_reset(dev_priv);
 586         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 587 }
 588
 589 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 590 {
 591         assert_can_disable_dc9(dev_priv);
 592
 593         DRM_DEBUG_KMS("Disabling DC9\n");
 594
 595         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 596
 597         intel_pps_unlock_regs_wa(dev_priv);
 598 }
 599
 600 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 601 {
 602         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 603                   "CSR program storage start is NULL\n");
 604         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 605         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 606 }
 607
 608 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 609 {
 610         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 611                                         SKL_DISP_PW_2);
 612
 613         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 614
 615         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 616                   "DC5 already programmed to be enabled.\n");
 617         assert_rpm_wakelock_held(dev_priv);
 618
 619         assert_csr_loaded(dev_priv);
 620 }
 621
 622 void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 623 {
 624         assert_can_enable_dc5(dev_priv);
 625
 626         DRM_DEBUG_KMS("Enabling DC5\n");
 627
 628         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 629 }
 630
 631 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 632 {
 633         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 634                   "Backlight is not disabled.\n");
 635         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 636                   "DC6 already programmed to be enabled.\n");
 637
 638         assert_csr_loaded(dev_priv);
 639 }
 640
 641 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 642 {
 643         assert_can_enable_dc6(dev_priv);
 644
 645         DRM_DEBUG_KMS("Enabling DC6\n");
 646
 647         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 648
 649 }
 650
 651 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 652 {
 653         DRM_DEBUG_KMS("Disabling DC6\n");
 654
 655         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 656 }
 657
 658 static void
 659 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 660                                   struct i915_power_well *power_well)
 661 {
 662         enum skl_disp_power_wells power_well_id = power_well->data;
 663         u32 val;
 664         u32 mask;
 665
 666         mask = SKL_POWER_WELL_REQ(power_well_id);
 667
 668         val = I915_READ(HSW_PWR_WELL_KVMR);
 669         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 670                       power_well->name))
 671                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 672
 673         val = I915_READ(HSW_PWR_WELL_BIOS);
 674         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 675
 676         if (!(val & mask))
 677                 return;
 678
 679         /*
 680          * DMC is known to force on the request bits for power well 1 on SKL
 681          * and BXT and the misc IO power well on SKL but we don't expect any
 682          * other request bits to be set, so WARN for those.
 683          */
 684         if (power_well_id == SKL_DISP_PW_1 ||
 685             ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
 686              power_well_id == SKL_DISP_PW_MISC_IO))
 687                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 688                                  "by DMC\n", power_well->name);
 689         else
 690                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 691                           power_well->name);
 692
 693         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 694         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 695 }
 696
 697 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 698                         struct i915_power_well *power_well, bool enable)
 699 {
 700         uint32_t tmp, fuse_status;
 701         uint32_t req_mask, state_mask;
 702         bool is_enabled, enable_requested, check_fuse_status = false;
 703
 704         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 705         fuse_status = I915_READ(SKL_FUSE_STATUS);
 706
 707         switch (power_well->data) {
 708         case SKL_DISP_PW_1:
 709                 if (intel_wait_for_register(dev_priv,
 710                                             SKL_FUSE_STATUS,
 711                                             SKL_FUSE_PG0_DIST_STATUS,
 712                                             SKL_FUSE_PG0_DIST_STATUS,
 713                                             1)) {
 714                         DRM_ERROR("PG0 not enabled\n");
 715                         return;
 716                 }
 717                 break;
 718         case SKL_DISP_PW_2:
 719                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 720                         DRM_ERROR("PG1 in disabled state\n");
 721                         return;
 722                 }
 723                 break;
 724         case SKL_DISP_PW_DDI_A_E:
 725         case SKL_DISP_PW_DDI_B:
 726         case SKL_DISP_PW_DDI_C:
 727         case SKL_DISP_PW_DDI_D:
 728         case SKL_DISP_PW_MISC_IO:
 729                 break;
 730         default:
 731                 WARN(1, "Unknown power well %lu\n", power_well->data);
 732                 return;
 733         }
 734
 735         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 736         enable_requested = tmp & req_mask;
 737         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 738         is_enabled = tmp & state_mask;
 739
 740         if (!enable && enable_requested)
 741                 skl_power_well_pre_disable(dev_priv, power_well);
 742
 743         if (enable) {
 744                 if (!enable_requested) {
 745                         WARN((tmp & state_mask) &&
 746                                 !I915_READ(HSW_PWR_WELL_BIOS),
 747                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 748                                 when request is to disable!\n");
 749                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 750                 }
 751
 752                 if (!is_enabled) {
 753                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 754                         check_fuse_status = true;
 755                 }
 756         } else {
 757                 if (enable_requested) {
 758                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 759                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 760                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 761                 }
 762
 763                 if (IS_GEN9(dev_priv))
 764                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 765         }
 766
 767         if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
 768                      1))
 769                 DRM_ERROR("%s %s timeout\n",
 770                           power_well->name, enable ? "enable" : "disable");
 771
 772         if (check_fuse_status) {
 773                 if (power_well->data == SKL_DISP_PW_1) {
 774                         if (intel_wait_for_register(dev_priv,
 775                                                     SKL_FUSE_STATUS,
 776                                                     SKL_FUSE_PG1_DIST_STATUS,
 777                                                     SKL_FUSE_PG1_DIST_STATUS,
 778                                                     1))
 779                                 DRM_ERROR("PG1 distributing status timeout\n");
 780                 } else if (power_well->data == SKL_DISP_PW_2) {
 781                         if (intel_wait_for_register(dev_priv,
 782                                                     SKL_FUSE_STATUS,
 783                                                     SKL_FUSE_PG2_DIST_STATUS,
 784                                                     SKL_FUSE_PG2_DIST_STATUS,
 785                                                     1))
 786                                 DRM_ERROR("PG2 distributing status timeout\n");
 787                 }
 788         }
 789
 790         if (enable && !is_enabled)
 791                 skl_power_well_post_enable(dev_priv, power_well);
 792 }
 793
 794 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 795                                    struct i915_power_well *power_well)
 796 {
 797         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 798
 799         /*
 800          * We're taking over the BIOS, so clear any requests made by it since
 801          * the driver is in charge now.
 802          */
 803         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 804                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 805 }
 806
 807 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 808                                   struct i915_power_well *power_well)
 809 {
 810         hsw_set_power_well(dev_priv, power_well, true);
 811 }
 812
 813 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 814                                    struct i915_power_well *power_well)
 815 {
 816         hsw_set_power_well(dev_priv, power_well, false);
 817 }
 818
 819 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 820                                         struct i915_power_well *power_well)
 821 {
 822         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 823                 SKL_POWER_WELL_STATE(power_well->data);
 824
 825         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 826 }
 827
 828 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 829                                 struct i915_power_well *power_well)
 830 {
 831         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 832
 833         /* Clear any request made by BIOS as driver is taking over */
 834         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 835 }
 836
 837 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 838                                 struct i915_power_well *power_well)
 839 {
 840         skl_set_power_well(dev_priv, power_well, true);
 841 }
 842
 843 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 844                                 struct i915_power_well *power_well)
 845 {
 846         skl_set_power_well(dev_priv, power_well, false);
 847 }
 848
 849 static enum dpio_phy bxt_power_well_to_phy(struct i915_power_well *power_well)
 850 {
 851         enum skl_disp_power_wells power_well_id = power_well->data;
 852
 853         return power_well_id == BXT_DPIO_CMN_A ? DPIO_PHY1 : DPIO_PHY0;
 854 }
 855
 856 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
 857                                            struct i915_power_well *power_well)
 858 {
 859         enum skl_disp_power_wells power_well_id = power_well->data;
 860         struct i915_power_well *cmn_a_well = NULL;
 861
 862         if (power_well_id == BXT_DPIO_CMN_BC) {
 863                 /*
 864                  * We need to copy the GRC calibration value from the eDP PHY,
 865                  * so make sure it's powered up.
 866                  */
 867                 cmn_a_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 868                 intel_power_well_get(dev_priv, cmn_a_well);
 869         }
 870
 871         bxt_ddi_phy_init(dev_priv, bxt_power_well_to_phy(power_well));
 872
 873         if (cmn_a_well)
 874                 intel_power_well_put(dev_priv, cmn_a_well);
 875 }
 876
 877 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
 878                                             struct i915_power_well *power_well)
 879 {
 880         bxt_ddi_phy_uninit(dev_priv, bxt_power_well_to_phy(power_well));
 881 }
 882
 883 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
 884                                             struct i915_power_well *power_well)
 885 {
 886         return bxt_ddi_phy_is_enabled(dev_priv,
 887                                       bxt_power_well_to_phy(power_well));
 888 }
 889
 890 static void bxt_dpio_cmn_power_well_sync_hw(struct drm_i915_private *dev_priv,
 891                                             struct i915_power_well *power_well)
 892 {
 893         if (power_well->count > 0)
 894                 bxt_dpio_cmn_power_well_enable(dev_priv, power_well);
 895         else
 896                 bxt_dpio_cmn_power_well_disable(dev_priv, power_well);
 897 }
 898
 899
 900 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
 901 {
 902         struct i915_power_well *power_well;
 903
 904         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
 905         if (power_well->count > 0)
 906                 bxt_ddi_phy_verify_state(dev_priv,
 907                                          bxt_power_well_to_phy(power_well));
 908
 909         power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC);
 910         if (power_well->count > 0)
 911                 bxt_ddi_phy_verify_state(dev_priv,
 912                                          bxt_power_well_to_phy(power_well));
 913 }
 914
 915 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 916                                            struct i915_power_well *power_well)
 917 {
 918         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 919 }
 920
 921 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
 922 {
 923         u32 tmp = I915_READ(DBUF_CTL);
 924
 925         WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
 926              (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
 927              "Unexpected DBuf power power state (0x%08x)\n", tmp);
 928 }
 929
 930 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 931                                           struct i915_power_well *power_well)
 932 {
 933         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 934
 935         WARN_ON(dev_priv->cdclk_freq !=
 936                 dev_priv->display.get_display_clock_speed(&dev_priv->drm));
 937
 938         gen9_assert_dbuf_enabled(dev_priv);
 939
 940         if (IS_BROXTON(dev_priv))
 941                 bxt_verify_ddi_phy_power_wells(dev_priv);
 942 }
 943
 944 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 945                                            struct i915_power_well *power_well)
 946 {
 947         if (!dev_priv->csr.dmc_payload)
 948                 return;
 949
 950         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 951                 skl_enable_dc6(dev_priv);
 952         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 953                 gen9_enable_dc5(dev_priv);
 954 }
 955
 956 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 957                                            struct i915_power_well *power_well)
 958 {
 959         if (power_well->count > 0)
 960                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 961         else
 962                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 963 }
 964
 965 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 966                                            struct i915_power_well *power_well)
 967 {
 968 }
 969
 970 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 971                                              struct i915_power_well *power_well)
 972 {
 973         return true;
 974 }
 975
 976 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 977                                struct i915_power_well *power_well, bool enable)
 978 {
 979         enum punit_power_well power_well_id = power_well->data;
 980         u32 mask;
 981         u32 state;
 982         u32 ctrl;
 983
 984         mask = PUNIT_PWRGT_MASK(power_well_id);
 985         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 986                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 987
 988         mutex_lock(&dev_priv->rps.hw_lock);
 989
 990 #define COND \
 991         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 992
 993         if (COND)
 994                 goto out;
 995
 996         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 997         ctrl &= ~mask;
 998         ctrl |= state;
 999         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
1000
1001         if (wait_for(COND, 100))
1002                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1003                           state,
1004                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
1005
1006 #undef COND
1007
1008 out:
1009         mutex_unlock(&dev_priv->rps.hw_lock);
1010 }
1011
1012 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
1013                                    struct i915_power_well *power_well)
1014 {
1015         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
1016 }
1017
1018 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
1019                                   struct i915_power_well *power_well)
1020 {
1021         vlv_set_power_well(dev_priv, power_well, true);
1022 }
1023
1024 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
1025                                    struct i915_power_well *power_well)
1026 {
1027         vlv_set_power_well(dev_priv, power_well, false);
1028 }
1029
1030 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
1031                                    struct i915_power_well *power_well)
1032 {
1033         int power_well_id = power_well->data;
1034         bool enabled = false;
1035         u32 mask;
1036         u32 state;
1037         u32 ctrl;
1038
1039         mask = PUNIT_PWRGT_MASK(power_well_id);
1040         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
1041
1042         mutex_lock(&dev_priv->rps.hw_lock);
1043
1044         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
1045         /*
1046          * We only ever set the power-on and power-gate states, anything
1047          * else is unexpected.
1048          */
1049         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
1050                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
1051         if (state == ctrl)
1052                 enabled = true;
1053
1054         /*
1055          * A transient state at this point would mean some unexpected party
1056          * is poking at the power controls too.
1057          */
1058         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
1059         WARN_ON(ctrl != state);
1060
1061         mutex_unlock(&dev_priv->rps.hw_lock);
1062
1063         return enabled;
1064 }
1065
1066 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
1067 {
1068         u32 val;
1069
1070         /*
1071          * On driver load, a pipe may be active and driving a DSI display.
1072          * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
1073          * (and never recovering) in this case. intel_dsi_post_disable() will
1074          * clear it when we turn off the display.
1075          */
1076         val = I915_READ(DSPCLK_GATE_D);
1077         val &= DPOUNIT_CLOCK_GATE_DISABLE;
1078         val |= VRHUNIT_CLOCK_GATE_DISABLE;
1079         I915_WRITE(DSPCLK_GATE_D, val);
1080
1081         /*
1082          * Disable trickle feed and enable pnd deadline calculation
1083          */
1084         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
1085         I915_WRITE(CBR1_VLV, 0);
1086
1087         WARN_ON(dev_priv->rawclk_freq == 0);
1088
1089         I915_WRITE(RAWCLK_FREQ_VLV,
1090                    DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000));
1091 }
1092
1093 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
1094 {
1095         struct intel_encoder *encoder;
1096         enum pipe pipe;
1097
1098         /*
1099          * Enable the CRI clock source so we can get at the
1100          * display and the reference clock for VGA
1101          * hotplug / manual detection. Supposedly DSI also
1102          * needs the ref clock up and running.
1103          *
1104          * CHV DPLL B/C have some issues if VGA mode is enabled.
1105          */
1106         for_each_pipe(&dev_priv->drm, pipe) {
1107                 u32 val = I915_READ(DPLL(pipe));
1108
1109                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1110                 if (pipe != PIPE_A)
1111                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1112
1113                 I915_WRITE(DPLL(pipe), val);
1114         }
1115
1116         vlv_init_display_clock_gating(dev_priv);
1117
1118         spin_lock_irq(&dev_priv->irq_lock);
1119         valleyview_enable_display_irqs(dev_priv);
1120         spin_unlock_irq(&dev_priv->irq_lock);
1121
1122         /*
1123          * During driver initialization/resume we can avoid restoring the
1124          * part of the HW/SW state that will be inited anyway explicitly.
1125          */
1126         if (dev_priv->power_domains.initializing)
1127                 return;
1128
1129         intel_hpd_init(dev_priv);
1130
1131         /* Re-enable the ADPA, if we have one */
1132         for_each_intel_encoder(&dev_priv->drm, encoder) {
1133                 if (encoder->type == INTEL_OUTPUT_ANALOG)
1134                         intel_crt_reset(&encoder->base);
1135         }
1136
1137         i915_redisable_vga_power_on(&dev_priv->drm);
1138
1139         intel_pps_unlock_regs_wa(dev_priv);
1140 }
1141
1142 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
1143 {
1144         spin_lock_irq(&dev_priv->irq_lock);
1145         valleyview_disable_display_irqs(dev_priv);
1146         spin_unlock_irq(&dev_priv->irq_lock);
1147
1148         /* make sure we're done processing display irqs */
1149         synchronize_irq(dev_priv->drm.irq);
1150
1151         intel_power_sequencer_reset(dev_priv);
1152
1153         /* Prevent us from re-enabling polling on accident in late suspend */
1154         if (!dev_priv->drm.dev->power.is_suspended)
1155                 intel_hpd_poll_init(dev_priv);
1156 }
1157
1158 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1159                                           struct i915_power_well *power_well)
1160 {
1161         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1162
1163         vlv_set_power_well(dev_priv, power_well, true);
1164
1165         vlv_display_power_well_init(dev_priv);
1166 }
1167
1168 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1169                                            struct i915_power_well *power_well)
1170 {
1171         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1172
1173         vlv_display_power_well_deinit(dev_priv);
1174
1175         vlv_set_power_well(dev_priv, power_well, false);
1176 }
1177
1178 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1179                                            struct i915_power_well *power_well)
1180 {
1181         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1182
1183         /* since ref/cri clock was enabled */
1184         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1185
1186         vlv_set_power_well(dev_priv, power_well, true);
1187
1188         /*
1189          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1190          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1191          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1192          *   b. The other bits such as sfr settings / modesel may all
1193          *      be set to 0.
1194          *
1195          * This should only be done on init and resume from S3 with
1196          * both PLLs disabled, or we risk losing DPIO and PLL
1197          * synchronization.
1198          */
1199         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1200 }
1201
1202 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1203                                             struct i915_power_well *power_well)
1204 {
1205         enum pipe pipe;
1206
1207         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1208
1209         for_each_pipe(dev_priv, pipe)
1210                 assert_pll_disabled(dev_priv, pipe);
1211
1212         /* Assert common reset */
1213         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1214
1215         vlv_set_power_well(dev_priv, power_well, false);
1216 }
1217
1218 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1219
1220 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1221                                                  int power_well_id)
1222 {
1223         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1224         int i;
1225
1226         for (i = 0; i < power_domains->power_well_count; i++) {
1227                 struct i915_power_well *power_well;
1228
1229                 power_well = &power_domains->power_wells[i];
1230                 if (power_well->data == power_well_id)
1231                         return power_well;
1232         }
1233
1234         return NULL;
1235 }
1236
1237 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1238
1239 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1240 {
1241         struct i915_power_well *cmn_bc =
1242                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1243         struct i915_power_well *cmn_d =
1244                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1245         u32 phy_control = dev_priv->chv_phy_control;
1246         u32 phy_status = 0;
1247         u32 phy_status_mask = 0xffffffff;
1248
1249         /*
1250          * The BIOS can leave the PHY is some weird state
1251          * where it doesn't fully power down some parts.
1252          * Disable the asserts until the PHY has been fully
1253          * reset (ie. the power well has been disabled at
1254          * least once).
1255          */
1256         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1257                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1258                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1259                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1260                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1261                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1262                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1263
1264         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1265                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1266                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1267                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1268
1269         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1270                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1271
1272                 /* this assumes override is only used to enable lanes */
1273                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1274                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1275
1276                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1277                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1278
1279                 /* CL1 is on whenever anything is on in either channel */
1280                 if (BITS_SET(phy_control,
1281                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1282                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1283                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1284
1285                 /*
1286                  * The DPLLB check accounts for the pipe B + port A usage
1287                  * with CL2 powered up but all the lanes in the second channel
1288                  * powered down.
1289                  */
1290                 if (BITS_SET(phy_control,
1291                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1292                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1293                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1294
1295                 if (BITS_SET(phy_control,
1296                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1297                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1298                 if (BITS_SET(phy_control,
1299                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1300                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1301
1302                 if (BITS_SET(phy_control,
1303                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1304                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1305                 if (BITS_SET(phy_control,
1306                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1307                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1308         }
1309
1310         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1311                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1312
1313                 /* this assumes override is only used to enable lanes */
1314                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1315                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1316
1317                 if (BITS_SET(phy_control,
1318                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1319                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1320
1321                 if (BITS_SET(phy_control,
1322                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1323                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1324                 if (BITS_SET(phy_control,
1325                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1326                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1327         }
1328
1329         phy_status &= phy_status_mask;
1330
1331         /*
1332          * The PHY may be busy with some initial calibration and whatnot,
1333          * so the power state can take a while to actually change.
1334          */
1335         if (intel_wait_for_register(dev_priv,
1336                                     DISPLAY_PHY_STATUS,
1337                                     phy_status_mask,
1338                                     phy_status,
1339                                     10))
1340                 DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1341                           I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
1342                            phy_status, dev_priv->chv_phy_control);
1343 }
1344
1345 #undef BITS_SET
1346
1347 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1348                                            struct i915_power_well *power_well)
1349 {
1350         enum dpio_phy phy;
1351         enum pipe pipe;
1352         uint32_t tmp;
1353
1354         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1355                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1356
1357         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1358                 pipe = PIPE_A;
1359                 phy = DPIO_PHY0;
1360         } else {
1361                 pipe = PIPE_C;
1362                 phy = DPIO_PHY1;
1363         }
1364
1365         /* since ref/cri clock was enabled */
1366         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1367         vlv_set_power_well(dev_priv, power_well, true);
1368
1369         /* Poll for phypwrgood signal */
1370         if (intel_wait_for_register(dev_priv,
1371                                     DISPLAY_PHY_STATUS,
1372                                     PHY_POWERGOOD(phy),
1373                                     PHY_POWERGOOD(phy),
1374                                     1))
1375                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1376
1377         mutex_lock(&dev_priv->sb_lock);
1378
1379         /* Enable dynamic power down */
1380         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1381         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1382                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1383         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1384
1385         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1386                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1387                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1388                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1389         } else {
1390                 /*
1391                  * Force the non-existing CL2 off. BXT does this
1392                  * too, so maybe it saves some power even though
1393                  * CL2 doesn't exist?
1394                  */
1395                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1396                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1397                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1398         }
1399
1400         mutex_unlock(&dev_priv->sb_lock);
1401
1402         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1403         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1404
1405         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1406                       phy, dev_priv->chv_phy_control);
1407
1408         assert_chv_phy_status(dev_priv);
1409 }
1410
1411 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1412                                             struct i915_power_well *power_well)
1413 {
1414         enum dpio_phy phy;
1415
1416         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1417                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1418
1419         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1420                 phy = DPIO_PHY0;
1421                 assert_pll_disabled(dev_priv, PIPE_A);
1422                 assert_pll_disabled(dev_priv, PIPE_B);
1423         } else {
1424                 phy = DPIO_PHY1;
1425                 assert_pll_disabled(dev_priv, PIPE_C);
1426         }
1427
1428         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1429         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1430
1431         vlv_set_power_well(dev_priv, power_well, false);
1432
1433         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1434                       phy, dev_priv->chv_phy_control);
1435
1436         /* PHY is fully reset now, so we can enable the PHY state asserts */
1437         dev_priv->chv_phy_assert[phy] = true;
1438
1439         assert_chv_phy_status(dev_priv);
1440 }
1441
1442 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1443                                      enum dpio_channel ch, bool override, unsigned int mask)
1444 {
1445         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1446         u32 reg, val, expected, actual;
1447
1448         /*
1449          * The BIOS can leave the PHY is some weird state
1450          * where it doesn't fully power down some parts.
1451          * Disable the asserts until the PHY has been fully
1452          * reset (ie. the power well has been disabled at
1453          * least once).
1454          */
1455         if (!dev_priv->chv_phy_assert[phy])
1456                 return;
1457
1458         if (ch == DPIO_CH0)
1459                 reg = _CHV_CMN_DW0_CH0;
1460         else
1461                 reg = _CHV_CMN_DW6_CH1;
1462
1463         mutex_lock(&dev_priv->sb_lock);
1464         val = vlv_dpio_read(dev_priv, pipe, reg);
1465         mutex_unlock(&dev_priv->sb_lock);
1466
1467         /*
1468          * This assumes !override is only used when the port is disabled.
1469          * All lanes should power down even without the override when
1470          * the port is disabled.
1471          */
1472         if (!override || mask == 0xf) {
1473                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1474                 /*
1475                  * If CH1 common lane is not active anymore
1476                  * (eg. for pipe B DPLL) the entire channel will
1477                  * shut down, which causes the common lane registers
1478                  * to read as 0. That means we can't actually check
1479                  * the lane power down status bits, but as the entire
1480                  * register reads as 0 it's a good indication that the
1481                  * channel is indeed entirely powered down.
1482                  */
1483                 if (ch == DPIO_CH1 && val == 0)
1484                         expected = 0;
1485         } else if (mask != 0x0) {
1486                 expected = DPIO_ANYDL_POWERDOWN;
1487         } else {
1488                 expected = 0;
1489         }
1490
1491         if (ch == DPIO_CH0)
1492                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1493         else
1494                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1495         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1496
1497         WARN(actual != expected,
1498              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1499              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1500              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1501              reg, val);
1502 }
1503
1504 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1505                           enum dpio_channel ch, bool override)
1506 {
1507         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1508         bool was_override;
1509
1510         mutex_lock(&power_domains->lock);
1511
1512         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1513
1514         if (override == was_override)
1515                 goto out;
1516
1517         if (override)
1518                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1519         else
1520                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1521
1522         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1523
1524         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1525                       phy, ch, dev_priv->chv_phy_control);
1526
1527         assert_chv_phy_status(dev_priv);
1528
1529 out:
1530         mutex_unlock(&power_domains->lock);
1531
1532         return was_override;
1533 }
1534
1535 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1536                              bool override, unsigned int mask)
1537 {
1538         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1539         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1540         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1541         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1542
1543         mutex_lock(&power_domains->lock);
1544
1545         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1546         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1547
1548         if (override)
1549                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1550         else
1551                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1552
1553         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1554
1555         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1556                       phy, ch, mask, dev_priv->chv_phy_control);
1557
1558         assert_chv_phy_status(dev_priv);
1559
1560         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1561
1562         mutex_unlock(&power_domains->lock);
1563 }
1564
1565 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1566                                         struct i915_power_well *power_well)
1567 {
1568         enum pipe pipe = power_well->data;
1569         bool enabled;
1570         u32 state, ctrl;
1571
1572         mutex_lock(&dev_priv->rps.hw_lock);
1573
1574         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1575         /*
1576          * We only ever set the power-on and power-gate states, anything
1577          * else is unexpected.
1578          */
1579         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1580         enabled = state == DP_SSS_PWR_ON(pipe);
1581
1582         /*
1583          * A transient state at this point would mean some unexpected party
1584          * is poking at the power controls too.
1585          */
1586         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1587         WARN_ON(ctrl << 16 != state);
1588
1589         mutex_unlock(&dev_priv->rps.hw_lock);
1590
1591         return enabled;
1592 }
1593
1594 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1595                                     struct i915_power_well *power_well,
1596                                     bool enable)
1597 {
1598         enum pipe pipe = power_well->data;
1599         u32 state;
1600         u32 ctrl;
1601
1602         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1603
1604         mutex_lock(&dev_priv->rps.hw_lock);
1605
1606 #define COND \
1607         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1608
1609         if (COND)
1610                 goto out;
1611
1612         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1613         ctrl &= ~DP_SSC_MASK(pipe);
1614         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1615         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1616
1617         if (wait_for(COND, 100))
1618                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1619                           state,
1620                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1621
1622 #undef COND
1623
1624 out:
1625         mutex_unlock(&dev_priv->rps.hw_lock);
1626 }
1627
1628 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1629                                         struct i915_power_well *power_well)
1630 {
1631         WARN_ON_ONCE(power_well->data != PIPE_A);
1632
1633         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1634 }
1635
1636 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1637                                        struct i915_power_well *power_well)
1638 {
1639         WARN_ON_ONCE(power_well->data != PIPE_A);
1640
1641         chv_set_pipe_power_well(dev_priv, power_well, true);
1642
1643         vlv_display_power_well_init(dev_priv);
1644 }
1645
1646 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1647                                         struct i915_power_well *power_well)
1648 {
1649         WARN_ON_ONCE(power_well->data != PIPE_A);
1650
1651         vlv_display_power_well_deinit(dev_priv);
1652
1653         chv_set_pipe_power_well(dev_priv, power_well, false);
1654 }
1655
1656 static void
1657 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1658                                  enum intel_display_power_domain domain)
1659 {
1660         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1661         struct i915_power_well *power_well;
1662         int i;
1663
1664         for_each_power_well(i, power_well, BIT(domain), power_domains)
1665                 intel_power_well_get(dev_priv, power_well);
1666
1667         power_domains->domain_use_count[domain]++;
1668 }
1669
1670 /**
1671  * intel_display_power_get - grab a power domain reference
1672  * @dev_priv: i915 device instance
1673  * @domain: power domain to reference
1674  *
1675  * This function grabs a power domain reference for @domain and ensures that the
1676  * power domain and all its parents are powered up. Therefore users should only
1677  * grab a reference to the innermost power domain they need.
1678  *
1679  * Any power domain reference obtained by this function must have a symmetric
1680  * call to intel_display_power_put() to release the reference again.
1681  */
1682 void intel_display_power_get(struct drm_i915_private *dev_priv,
1683                              enum intel_display_power_domain domain)
1684 {
1685         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1686
1687         intel_runtime_pm_get(dev_priv);
1688
1689         mutex_lock(&power_domains->lock);
1690
1691         __intel_display_power_get_domain(dev_priv, domain);
1692
1693         mutex_unlock(&power_domains->lock);
1694 }
1695
1696 /**
1697  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1698  * @dev_priv: i915 device instance
1699  * @domain: power domain to reference
1700  *
1701  * This function grabs a power domain reference for @domain and ensures that the
1702  * power domain and all its parents are powered up. Therefore users should only
1703  * grab a reference to the innermost power domain they need.
1704  *
1705  * Any power domain reference obtained by this function must have a symmetric
1706  * call to intel_display_power_put() to release the reference again.
1707  */
1708 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1709                                         enum intel_display_power_domain domain)
1710 {
1711         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1712         bool is_enabled;
1713
1714         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1715                 return false;
1716
1717         mutex_lock(&power_domains->lock);
1718
1719         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1720                 __intel_display_power_get_domain(dev_priv, domain);
1721                 is_enabled = true;
1722         } else {
1723                 is_enabled = false;
1724         }
1725
1726         mutex_unlock(&power_domains->lock);
1727
1728         if (!is_enabled)
1729                 intel_runtime_pm_put(dev_priv);
1730
1731         return is_enabled;
1732 }
1733
1734 /**
1735  * intel_display_power_put - release a power domain reference
1736  * @dev_priv: i915 device instance
1737  * @domain: power domain to reference
1738  *
1739  * This function drops the power domain reference obtained by
1740  * intel_display_power_get() and might power down the corresponding hardware
1741  * block right away if this is the last reference.
1742  */
1743 void intel_display_power_put(struct drm_i915_private *dev_priv,
1744                              enum intel_display_power_domain domain)
1745 {
1746         struct i915_power_domains *power_domains;
1747         struct i915_power_well *power_well;
1748         int i;
1749
1750         power_domains = &dev_priv->power_domains;
1751
1752         mutex_lock(&power_domains->lock);
1753
1754         WARN(!power_domains->domain_use_count[domain],
1755              "Use count on domain %s is already zero\n",
1756              intel_display_power_domain_str(domain));
1757         power_domains->domain_use_count[domain]--;
1758
1759         for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
1760                 intel_power_well_put(dev_priv, power_well);
1761
1762         mutex_unlock(&power_domains->lock);
1763
1764         intel_runtime_pm_put(dev_priv);
1765 }
1766
1767 #define HSW_DISPLAY_POWER_DOMAINS (                     \
1768         BIT(POWER_DOMAIN_PIPE_B) |                      \
1769         BIT(POWER_DOMAIN_PIPE_C) |                      \
1770         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
1771         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1772         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1773         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1774         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1775         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1776         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1777         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1778         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1779         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1780         BIT(POWER_DOMAIN_VGA) |                         \
1781         BIT(POWER_DOMAIN_AUDIO) |                       \
1782         BIT(POWER_DOMAIN_INIT))
1783
1784 #define BDW_DISPLAY_POWER_DOMAINS (                     \
1785         BIT(POWER_DOMAIN_PIPE_B) |                      \
1786         BIT(POWER_DOMAIN_PIPE_C) |                      \
1787         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
1788         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
1789         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
1790         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
1791         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
1792         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1793         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1794         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1795         BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */        \
1796         BIT(POWER_DOMAIN_VGA) |                         \
1797         BIT(POWER_DOMAIN_AUDIO) |                       \
1798         BIT(POWER_DOMAIN_INIT))
1799
1800 #define VLV_DISPLAY_POWER_DOMAINS (             \
1801         BIT(POWER_DOMAIN_PIPE_A) |              \
1802         BIT(POWER_DOMAIN_PIPE_B) |              \
1803         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1804         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1805         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1806         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1807         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1808         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1809         BIT(POWER_DOMAIN_PORT_DSI) |            \
1810         BIT(POWER_DOMAIN_PORT_CRT) |            \
1811         BIT(POWER_DOMAIN_VGA) |                 \
1812         BIT(POWER_DOMAIN_AUDIO) |               \
1813         BIT(POWER_DOMAIN_AUX_B) |               \
1814         BIT(POWER_DOMAIN_AUX_C) |               \
1815         BIT(POWER_DOMAIN_GMBUS) |               \
1816         BIT(POWER_DOMAIN_INIT))
1817
1818 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1819         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1820         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1821         BIT(POWER_DOMAIN_PORT_CRT) |            \
1822         BIT(POWER_DOMAIN_AUX_B) |               \
1823         BIT(POWER_DOMAIN_AUX_C) |               \
1824         BIT(POWER_DOMAIN_INIT))
1825
1826 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1827         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1828         BIT(POWER_DOMAIN_AUX_B) |               \
1829         BIT(POWER_DOMAIN_INIT))
1830
1831 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1832         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1833         BIT(POWER_DOMAIN_AUX_B) |               \
1834         BIT(POWER_DOMAIN_INIT))
1835
1836 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1837         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1838         BIT(POWER_DOMAIN_AUX_C) |               \
1839         BIT(POWER_DOMAIN_INIT))
1840
1841 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1842         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1843         BIT(POWER_DOMAIN_AUX_C) |               \
1844         BIT(POWER_DOMAIN_INIT))
1845
1846 #define CHV_DISPLAY_POWER_DOMAINS (             \
1847         BIT(POWER_DOMAIN_PIPE_A) |              \
1848         BIT(POWER_DOMAIN_PIPE_B) |              \
1849         BIT(POWER_DOMAIN_PIPE_C) |              \
1850         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
1851         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
1852         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
1853         BIT(POWER_DOMAIN_TRANSCODER_A) |        \
1854         BIT(POWER_DOMAIN_TRANSCODER_B) |        \
1855         BIT(POWER_DOMAIN_TRANSCODER_C) |        \
1856         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1857         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1858         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1859         BIT(POWER_DOMAIN_PORT_DSI) |            \
1860         BIT(POWER_DOMAIN_VGA) |                 \
1861         BIT(POWER_DOMAIN_AUDIO) |               \
1862         BIT(POWER_DOMAIN_AUX_B) |               \
1863         BIT(POWER_DOMAIN_AUX_C) |               \
1864         BIT(POWER_DOMAIN_AUX_D) |               \
1865         BIT(POWER_DOMAIN_GMBUS) |               \
1866         BIT(POWER_DOMAIN_INIT))
1867
1868 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1869         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1870         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1871         BIT(POWER_DOMAIN_AUX_B) |               \
1872         BIT(POWER_DOMAIN_AUX_C) |               \
1873         BIT(POWER_DOMAIN_INIT))
1874
1875 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1876         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1877         BIT(POWER_DOMAIN_AUX_D) |               \
1878         BIT(POWER_DOMAIN_INIT))
1879
1880 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1881         .sync_hw = i9xx_always_on_power_well_noop,
1882         .enable = i9xx_always_on_power_well_noop,
1883         .disable = i9xx_always_on_power_well_noop,
1884         .is_enabled = i9xx_always_on_power_well_enabled,
1885 };
1886
1887 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1888         .sync_hw = chv_pipe_power_well_sync_hw,
1889         .enable = chv_pipe_power_well_enable,
1890         .disable = chv_pipe_power_well_disable,
1891         .is_enabled = chv_pipe_power_well_enabled,
1892 };
1893
1894 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1895         .sync_hw = vlv_power_well_sync_hw,
1896         .enable = chv_dpio_cmn_power_well_enable,
1897         .disable = chv_dpio_cmn_power_well_disable,
1898         .is_enabled = vlv_power_well_enabled,
1899 };
1900
1901 static struct i915_power_well i9xx_always_on_power_well[] = {
1902         {
1903                 .name = "always-on",
1904                 .always_on = 1,
1905                 .domains = POWER_DOMAIN_MASK,
1906                 .ops = &i9xx_always_on_power_well_ops,
1907         },
1908 };
1909
1910 static const struct i915_power_well_ops hsw_power_well_ops = {
1911         .sync_hw = hsw_power_well_sync_hw,
1912         .enable = hsw_power_well_enable,
1913         .disable = hsw_power_well_disable,
1914         .is_enabled = hsw_power_well_enabled,
1915 };
1916
1917 static const struct i915_power_well_ops skl_power_well_ops = {
1918         .sync_hw = skl_power_well_sync_hw,
1919         .enable = skl_power_well_enable,
1920         .disable = skl_power_well_disable,
1921         .is_enabled = skl_power_well_enabled,
1922 };
1923
1924 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1925         .sync_hw = gen9_dc_off_power_well_sync_hw,
1926         .enable = gen9_dc_off_power_well_enable,
1927         .disable = gen9_dc_off_power_well_disable,
1928         .is_enabled = gen9_dc_off_power_well_enabled,
1929 };
1930
1931 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
1932         .sync_hw = bxt_dpio_cmn_power_well_sync_hw,
1933         .enable = bxt_dpio_cmn_power_well_enable,
1934         .disable = bxt_dpio_cmn_power_well_disable,
1935         .is_enabled = bxt_dpio_cmn_power_well_enabled,
1936 };
1937
1938 static struct i915_power_well hsw_power_wells[] = {
1939         {
1940                 .name = "always-on",
1941                 .always_on = 1,
1942                 .domains = POWER_DOMAIN_MASK,
1943                 .ops = &i9xx_always_on_power_well_ops,
1944         },
1945         {
1946                 .name = "display",
1947                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1948                 .ops = &hsw_power_well_ops,
1949         },
1950 };
1951
1952 static struct i915_power_well bdw_power_wells[] = {
1953         {
1954                 .name = "always-on",
1955                 .always_on = 1,
1956                 .domains = POWER_DOMAIN_MASK,
1957                 .ops = &i9xx_always_on_power_well_ops,
1958         },
1959         {
1960                 .name = "display",
1961                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1962                 .ops = &hsw_power_well_ops,
1963         },
1964 };
1965
1966 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1967         .sync_hw = vlv_power_well_sync_hw,
1968         .enable = vlv_display_power_well_enable,
1969         .disable = vlv_display_power_well_disable,
1970         .is_enabled = vlv_power_well_enabled,
1971 };
1972
1973 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1974         .sync_hw = vlv_power_well_sync_hw,
1975         .enable = vlv_dpio_cmn_power_well_enable,
1976         .disable = vlv_dpio_cmn_power_well_disable,
1977         .is_enabled = vlv_power_well_enabled,
1978 };
1979
1980 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1981         .sync_hw = vlv_power_well_sync_hw,
1982         .enable = vlv_power_well_enable,
1983         .disable = vlv_power_well_disable,
1984         .is_enabled = vlv_power_well_enabled,
1985 };
1986
1987 static struct i915_power_well vlv_power_wells[] = {
1988         {
1989                 .name = "always-on",
1990                 .always_on = 1,
1991                 .domains = POWER_DOMAIN_MASK,
1992                 .ops = &i9xx_always_on_power_well_ops,
1993                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1994         },
1995         {
1996                 .name = "display",
1997                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1998                 .data = PUNIT_POWER_WELL_DISP2D,
1999                 .ops = &vlv_display_power_well_ops,
2000         },
2001         {
2002                 .name = "dpio-tx-b-01",
2003                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2004                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2005                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2006                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2007                 .ops = &vlv_dpio_power_well_ops,
2008                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
2009         },
2010         {
2011                 .name = "dpio-tx-b-23",
2012                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2013                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2014                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2015                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2016                 .ops = &vlv_dpio_power_well_ops,
2017                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
2018         },
2019         {
2020                 .name = "dpio-tx-c-01",
2021                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2022                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2023                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2024                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2025                 .ops = &vlv_dpio_power_well_ops,
2026                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
2027         },
2028         {
2029                 .name = "dpio-tx-c-23",
2030                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
2031                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
2032                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
2033                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
2034                 .ops = &vlv_dpio_power_well_ops,
2035                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
2036         },
2037         {
2038                 .name = "dpio-common",
2039                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
2040                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2041                 .ops = &vlv_dpio_cmn_power_well_ops,
2042         },
2043 };
2044
2045 static struct i915_power_well chv_power_wells[] = {
2046         {
2047                 .name = "always-on",
2048                 .always_on = 1,
2049                 .domains = POWER_DOMAIN_MASK,
2050                 .ops = &i9xx_always_on_power_well_ops,
2051         },
2052         {
2053                 .name = "display",
2054                 /*
2055                  * Pipe A power well is the new disp2d well. Pipe B and C
2056                  * power wells don't actually exist. Pipe A power well is
2057                  * required for any pipe to work.
2058                  */
2059                 .domains = CHV_DISPLAY_POWER_DOMAINS,
2060                 .data = PIPE_A,
2061                 .ops = &chv_pipe_power_well_ops,
2062         },
2063         {
2064                 .name = "dpio-common-bc",
2065                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
2066                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
2067                 .ops = &chv_dpio_cmn_power_well_ops,
2068         },
2069         {
2070                 .name = "dpio-common-d",
2071                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
2072                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
2073                 .ops = &chv_dpio_cmn_power_well_ops,
2074         },
2075 };
2076
2077 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
2078                                     int power_well_id)
2079 {
2080         struct i915_power_well *power_well;
2081         bool ret;
2082
2083         power_well = lookup_power_well(dev_priv, power_well_id);
2084         ret = power_well->ops->is_enabled(dev_priv, power_well);
2085
2086         return ret;
2087 }
2088
2089 static struct i915_power_well skl_power_wells[] = {
2090         {
2091                 .name = "always-on",
2092                 .always_on = 1,
2093                 .domains = POWER_DOMAIN_MASK,
2094                 .ops = &i9xx_always_on_power_well_ops,
2095                 .data = SKL_DISP_PW_ALWAYS_ON,
2096         },
2097         {
2098                 .name = "power well 1",
2099                 /* Handled by the DMC firmware */
2100                 .domains = 0,
2101                 .ops = &skl_power_well_ops,
2102                 .data = SKL_DISP_PW_1,
2103         },
2104         {
2105                 .name = "MISC IO power well",
2106                 /* Handled by the DMC firmware */
2107                 .domains = 0,
2108                 .ops = &skl_power_well_ops,
2109                 .data = SKL_DISP_PW_MISC_IO,
2110         },
2111         {
2112                 .name = "DC off",
2113                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
2114                 .ops = &gen9_dc_off_power_well_ops,
2115                 .data = SKL_DISP_PW_DC_OFF,
2116         },
2117         {
2118                 .name = "power well 2",
2119                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2120                 .ops = &skl_power_well_ops,
2121                 .data = SKL_DISP_PW_2,
2122         },
2123         {
2124                 .name = "DDI A/E power well",
2125                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
2126                 .ops = &skl_power_well_ops,
2127                 .data = SKL_DISP_PW_DDI_A_E,
2128         },
2129         {
2130                 .name = "DDI B power well",
2131                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
2132                 .ops = &skl_power_well_ops,
2133                 .data = SKL_DISP_PW_DDI_B,
2134         },
2135         {
2136                 .name = "DDI C power well",
2137                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
2138                 .ops = &skl_power_well_ops,
2139                 .data = SKL_DISP_PW_DDI_C,
2140         },
2141         {
2142                 .name = "DDI D power well",
2143                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
2144                 .ops = &skl_power_well_ops,
2145                 .data = SKL_DISP_PW_DDI_D,
2146         },
2147 };
2148
2149 static struct i915_power_well bxt_power_wells[] = {
2150         {
2151                 .name = "always-on",
2152                 .always_on = 1,
2153                 .domains = POWER_DOMAIN_MASK,
2154                 .ops = &i9xx_always_on_power_well_ops,
2155         },
2156         {
2157                 .name = "power well 1",
2158                 .domains = 0,
2159                 .ops = &skl_power_well_ops,
2160                 .data = SKL_DISP_PW_1,
2161         },
2162         {
2163                 .name = "DC off",
2164                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
2165                 .ops = &gen9_dc_off_power_well_ops,
2166                 .data = SKL_DISP_PW_DC_OFF,
2167         },
2168         {
2169                 .name = "power well 2",
2170                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
2171                 .ops = &skl_power_well_ops,
2172                 .data = SKL_DISP_PW_2,
2173         },
2174         {
2175                 .name = "dpio-common-a",
2176                 .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
2177                 .ops = &bxt_dpio_cmn_power_well_ops,
2178                 .data = BXT_DPIO_CMN_A,
2179         },
2180         {
2181                 .name = "dpio-common-bc",
2182                 .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
2183                 .ops = &bxt_dpio_cmn_power_well_ops,
2184                 .data = BXT_DPIO_CMN_BC,
2185         },
2186 };
2187
2188 static int
2189 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2190                                    int disable_power_well)
2191 {
2192         if (disable_power_well >= 0)
2193                 return !!disable_power_well;
2194
2195         return 1;
2196 }
2197
2198 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2199                                     int enable_dc)
2200 {
2201         uint32_t mask;
2202         int requested_dc;
2203         int max_dc;
2204
2205         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2206                 max_dc = 2;
2207                 mask = 0;
2208         } else if (IS_BROXTON(dev_priv)) {
2209                 max_dc = 1;
2210                 /*
2211                  * DC9 has a separate HW flow from the rest of the DC states,
2212                  * not depending on the DMC firmware. It's needed by system
2213                  * suspend/resume, so allow it unconditionally.
2214                  */
2215                 mask = DC_STATE_EN_DC9;
2216         } else {
2217                 max_dc = 0;
2218                 mask = 0;
2219         }
2220
2221         if (!i915.disable_power_well)
2222                 max_dc = 0;
2223
2224         if (enable_dc >= 0 && enable_dc <= max_dc) {
2225                 requested_dc = enable_dc;
2226         } else if (enable_dc == -1) {
2227                 requested_dc = max_dc;
2228         } else if (enable_dc > max_dc && enable_dc <= 2) {
2229                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2230                               enable_dc, max_dc);
2231                 requested_dc = max_dc;
2232         } else {
2233                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2234                 requested_dc = max_dc;
2235         }
2236
2237         if (requested_dc > 1)
2238                 mask |= DC_STATE_EN_UPTO_DC6;
2239         if (requested_dc > 0)
2240                 mask |= DC_STATE_EN_UPTO_DC5;
2241
2242         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2243
2244         return mask;
2245 }
2246
2247 #define set_power_wells(power_domains, __power_wells) ({                \
2248         (power_domains)->power_wells = (__power_wells);                 \
2249         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2250 })
2251
2252 /**
2253  * intel_power_domains_init - initializes the power domain structures
2254  * @dev_priv: i915 device instance
2255  *
2256  * Initializes the power domain structures for @dev_priv depending upon the
2257  * supported platform.
2258  */
2259 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2260 {
2261         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2262
2263         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2264                                                      i915.disable_power_well);
2265         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2266                                                             i915.enable_dc);
2267
2268         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2269
2270         mutex_init(&power_domains->lock);
2271
2272         /*
2273          * The enabling order will be from lower to higher indexed wells,
2274          * the disabling order is reversed.
2275          */
2276         if (IS_HASWELL(dev_priv)) {
2277                 set_power_wells(power_domains, hsw_power_wells);
2278         } else if (IS_BROADWELL(dev_priv)) {
2279                 set_power_wells(power_domains, bdw_power_wells);
2280         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2281                 set_power_wells(power_domains, skl_power_wells);
2282         } else if (IS_BROXTON(dev_priv)) {
2283                 set_power_wells(power_domains, bxt_power_wells);
2284         } else if (IS_CHERRYVIEW(dev_priv)) {
2285                 set_power_wells(power_domains, chv_power_wells);
2286         } else if (IS_VALLEYVIEW(dev_priv)) {
2287                 set_power_wells(power_domains, vlv_power_wells);
2288         } else {
2289                 set_power_wells(power_domains, i9xx_always_on_power_well);
2290         }
2291
2292         return 0;
2293 }
2294
2295 /**
2296  * intel_power_domains_fini - finalizes the power domain structures
2297  * @dev_priv: i915 device instance
2298  *
2299  * Finalizes the power domain structures for @dev_priv depending upon the
2300  * supported platform. This function also disables runtime pm and ensures that
2301  * the device stays powered up so that the driver can be reloaded.
2302  */
2303 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2304 {
2305         struct device *kdev = &dev_priv->drm.pdev->dev;
2306
2307         /*
2308          * The i915.ko module is still not prepared to be loaded when
2309          * the power well is not enabled, so just enable it in case
2310          * we're going to unload/reload.
2311          * The following also reacquires the RPM reference the core passed
2312          * to the driver during loading, which is dropped in
2313          * intel_runtime_pm_enable(). We have to hand back the control of the
2314          * device to the core with this reference held.
2315          */
2316         intel_display_set_init_power(dev_priv, true);
2317
2318         /* Remove the refcount we took to keep power well support disabled. */
2319         if (!i915.disable_power_well)
2320                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2321
2322         /*
2323          * Remove the refcount we took in intel_runtime_pm_enable() in case
2324          * the platform doesn't support runtime PM.
2325          */
2326         if (!HAS_RUNTIME_PM(dev_priv))
2327                 pm_runtime_put(kdev);
2328 }
2329
2330 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2331 {
2332         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2333         struct i915_power_well *power_well;
2334         int i;
2335
2336         mutex_lock(&power_domains->lock);
2337         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2338                 power_well->ops->sync_hw(dev_priv, power_well);
2339                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2340                                                                      power_well);
2341         }
2342         mutex_unlock(&power_domains->lock);
2343 }
2344
2345 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv)
2346 {
2347         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
2348         POSTING_READ(DBUF_CTL);
2349
2350         udelay(10);
2351
2352         if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
2353                 DRM_ERROR("DBuf power enable timeout\n");
2354 }
2355
2356 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
2357 {
2358         I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
2359         POSTING_READ(DBUF_CTL);
2360
2361         udelay(10);
2362
2363         if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
2364                 DRM_ERROR("DBuf power disable timeout!\n");
2365 }
2366
2367 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2368                                    bool resume)
2369 {
2370         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2371         struct i915_power_well *well;
2372         uint32_t val;
2373
2374         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2375
2376         /* enable PCH reset handshake */
2377         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2378         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2379
2380         /* enable PG1 and Misc I/O */
2381         mutex_lock(&power_domains->lock);
2382
2383         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2384         intel_power_well_enable(dev_priv, well);
2385
2386         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2387         intel_power_well_enable(dev_priv, well);
2388
2389         mutex_unlock(&power_domains->lock);
2390
2391         skl_init_cdclk(dev_priv);
2392
2393         gen9_dbuf_enable(dev_priv);
2394
2395         if (resume && dev_priv->csr.dmc_payload)
2396                 intel_csr_load_program(dev_priv);
2397 }
2398
2399 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2400 {
2401         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2402         struct i915_power_well *well;
2403
2404         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2405
2406         gen9_dbuf_disable(dev_priv);
2407
2408         skl_uninit_cdclk(dev_priv);
2409
2410         /* The spec doesn't call for removing the reset handshake flag */
2411         /* disable PG1 and Misc I/O */
2412
2413         mutex_lock(&power_domains->lock);
2414
2415         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2416         intel_power_well_disable(dev_priv, well);
2417
2418         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2419         intel_power_well_disable(dev_priv, well);
2420
2421         mutex_unlock(&power_domains->lock);
2422 }
2423
2424 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2425                            bool resume)
2426 {
2427         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2428         struct i915_power_well *well;
2429         uint32_t val;
2430
2431         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2432
2433         /*
2434          * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2435          * or else the reset will hang because there is no PCH to respond.
2436          * Move the handshake programming to initialization sequence.
2437          * Previously was left up to BIOS.
2438          */
2439         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2440         val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2441         I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2442
2443         /* Enable PG1 */
2444         mutex_lock(&power_domains->lock);
2445
2446         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2447         intel_power_well_enable(dev_priv, well);
2448
2449         mutex_unlock(&power_domains->lock);
2450
2451         bxt_init_cdclk(dev_priv);
2452
2453         gen9_dbuf_enable(dev_priv);
2454
2455         if (resume && dev_priv->csr.dmc_payload)
2456                 intel_csr_load_program(dev_priv);
2457 }
2458
2459 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2460 {
2461         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2462         struct i915_power_well *well;
2463
2464         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2465
2466         gen9_dbuf_disable(dev_priv);
2467
2468         bxt_uninit_cdclk(dev_priv);
2469
2470         /* The spec doesn't call for removing the reset handshake flag */
2471
2472         /* Disable PG1 */
2473         mutex_lock(&power_domains->lock);
2474
2475         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2476         intel_power_well_disable(dev_priv, well);
2477
2478         mutex_unlock(&power_domains->lock);
2479 }
2480
2481 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2482 {
2483         struct i915_power_well *cmn_bc =
2484                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2485         struct i915_power_well *cmn_d =
2486                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2487
2488         /*
2489          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2490          * workaround never ever read DISPLAY_PHY_CONTROL, and
2491          * instead maintain a shadow copy ourselves. Use the actual
2492          * power well state and lane status to reconstruct the
2493          * expected initial value.
2494          */
2495         dev_priv->chv_phy_control =
2496                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2497                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2498                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2499                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2500                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2501
2502         /*
2503          * If all lanes are disabled we leave the override disabled
2504          * with all power down bits cleared to match the state we
2505          * would use after disabling the port. Otherwise enable the
2506          * override and set the lane powerdown bits accding to the
2507          * current lane status.
2508          */
2509         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2510                 uint32_t status = I915_READ(DPLL(PIPE_A));
2511                 unsigned int mask;
2512
2513                 mask = status & DPLL_PORTB_READY_MASK;
2514                 if (mask == 0xf)
2515                         mask = 0x0;
2516                 else
2517                         dev_priv->chv_phy_control |=
2518                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2519
2520                 dev_priv->chv_phy_control |=
2521                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2522
2523                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2524                 if (mask == 0xf)
2525                         mask = 0x0;
2526                 else
2527                         dev_priv->chv_phy_control |=
2528                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2529
2530                 dev_priv->chv_phy_control |=
2531                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2532
2533                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2534
2535                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2536         } else {
2537                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2538         }
2539
2540         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2541                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2542                 unsigned int mask;
2543
2544                 mask = status & DPLL_PORTD_READY_MASK;
2545
2546                 if (mask == 0xf)
2547                         mask = 0x0;
2548                 else
2549                         dev_priv->chv_phy_control |=
2550                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2551
2552                 dev_priv->chv_phy_control |=
2553                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2554
2555                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2556
2557                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2558         } else {
2559                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2560         }
2561
2562         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2563
2564         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2565                       dev_priv->chv_phy_control);
2566 }
2567
2568 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2569 {
2570         struct i915_power_well *cmn =
2571                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2572         struct i915_power_well *disp2d =
2573                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2574
2575         /* If the display might be already active skip this */
2576         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2577             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2578             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2579                 return;
2580
2581         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2582
2583         /* cmnlane needs DPLL registers */
2584         disp2d->ops->enable(dev_priv, disp2d);
2585
2586         /*
2587          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2588          * Need to assert and de-assert PHY SB reset by gating the
2589          * common lane power, then un-gating it.
2590          * Simply ungating isn't enough to reset the PHY enough to get
2591          * ports and lanes running.
2592          */
2593         cmn->ops->disable(dev_priv, cmn);
2594 }
2595
2596 /**
2597  * intel_power_domains_init_hw - initialize hardware power domain state
2598  * @dev_priv: i915 device instance
2599  * @resume: Called from resume code paths or not
2600  *
2601  * This function initializes the hardware power domain state and enables all
2602  * power domains using intel_display_set_init_power().
2603  */
2604 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2605 {
2606         struct drm_device *dev = &dev_priv->drm;
2607         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2608
2609         power_domains->initializing = true;
2610
2611         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2612                 skl_display_core_init(dev_priv, resume);
2613         } else if (IS_BROXTON(dev)) {
2614                 bxt_display_core_init(dev_priv, resume);
2615         } else if (IS_CHERRYVIEW(dev)) {
2616                 mutex_lock(&power_domains->lock);
2617                 chv_phy_control_init(dev_priv);
2618                 mutex_unlock(&power_domains->lock);
2619         } else if (IS_VALLEYVIEW(dev)) {
2620                 mutex_lock(&power_domains->lock);
2621                 vlv_cmnlane_wa(dev_priv);
2622                 mutex_unlock(&power_domains->lock);
2623         }
2624
2625         /* For now, we need the power well to be always enabled. */
2626         intel_display_set_init_power(dev_priv, true);
2627         /* Disable power support if the user asked so. */
2628         if (!i915.disable_power_well)
2629                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2630         intel_power_domains_sync_hw(dev_priv);
2631         power_domains->initializing = false;
2632 }
2633
2634 /**
2635  * intel_power_domains_suspend - suspend power domain state
2636  * @dev_priv: i915 device instance
2637  *
2638  * This function prepares the hardware power domain state before entering
2639  * system suspend. It must be paired with intel_power_domains_init_hw().
2640  */
2641 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2642 {
2643         /*
2644          * Even if power well support was disabled we still want to disable
2645          * power wells while we are system suspended.
2646          */
2647         if (!i915.disable_power_well)
2648                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2649
2650         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2651                 skl_display_core_uninit(dev_priv);
2652         else if (IS_BROXTON(dev_priv))
2653                 bxt_display_core_uninit(dev_priv);
2654 }
2655
2656 /**
2657  * intel_runtime_pm_get - grab a runtime pm reference
2658  * @dev_priv: i915 device instance
2659  *
2660  * This function grabs a device-level runtime pm reference (mostly used for GEM
2661  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2662  *
2663  * Any runtime pm reference obtained by this function must have a symmetric
2664  * call to intel_runtime_pm_put() to release the reference again.
2665  */
2666 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2667 {
2668         struct pci_dev *pdev = dev_priv->drm.pdev;
2669         struct device *kdev = &pdev->dev;
2670
2671         pm_runtime_get_sync(kdev);
2672
2673         atomic_inc(&dev_priv->pm.wakeref_count);
2674         assert_rpm_wakelock_held(dev_priv);
2675 }
2676
2677 /**
2678  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2679  * @dev_priv: i915 device instance
2680  *
2681  * This function grabs a device-level runtime pm reference if the device is
2682  * already in use and ensures that it is powered up.
2683  *
2684  * Any runtime pm reference obtained by this function must have a symmetric
2685  * call to intel_runtime_pm_put() to release the reference again.
2686  */
2687 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2688 {
2689         struct pci_dev *pdev = dev_priv->drm.pdev;
2690         struct device *kdev = &pdev->dev;
2691
2692         if (IS_ENABLED(CONFIG_PM)) {
2693                 int ret = pm_runtime_get_if_in_use(kdev);
2694
2695                 /*
2696                  * In cases runtime PM is disabled by the RPM core and we get
2697                  * an -EINVAL return value we are not supposed to call this
2698                  * function, since the power state is undefined. This applies
2699                  * atm to the late/early system suspend/resume handlers.
2700                  */
2701                 WARN_ON_ONCE(ret < 0);
2702                 if (ret <= 0)
2703                         return false;
2704         }
2705
2706         atomic_inc(&dev_priv->pm.wakeref_count);
2707         assert_rpm_wakelock_held(dev_priv);
2708
2709         return true;
2710 }
2711
2712 /**
2713  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2714  * @dev_priv: i915 device instance
2715  *
2716  * This function grabs a device-level runtime pm reference (mostly used for GEM
2717  * code to ensure the GTT or GT is on).
2718  *
2719  * It will _not_ power up the device but instead only check that it's powered
2720  * on.  Therefore it is only valid to call this functions from contexts where
2721  * the device is known to be powered up and where trying to power it up would
2722  * result in hilarity and deadlocks. That pretty much means only the system
2723  * suspend/resume code where this is used to grab runtime pm references for
2724  * delayed setup down in work items.
2725  *
2726  * Any runtime pm reference obtained by this function must have a symmetric
2727  * call to intel_runtime_pm_put() to release the reference again.
2728  */
2729 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2730 {
2731         struct pci_dev *pdev = dev_priv->drm.pdev;
2732         struct device *kdev = &pdev->dev;
2733
2734         assert_rpm_wakelock_held(dev_priv);
2735         pm_runtime_get_noresume(kdev);
2736
2737         atomic_inc(&dev_priv->pm.wakeref_count);
2738 }
2739
2740 /**
2741  * intel_runtime_pm_put - release a runtime pm reference
2742  * @dev_priv: i915 device instance
2743  *
2744  * This function drops the device-level runtime pm reference obtained by
2745  * intel_runtime_pm_get() and might power down the corresponding
2746  * hardware block right away if this is the last reference.
2747  */
2748 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2749 {
2750         struct pci_dev *pdev = dev_priv->drm.pdev;
2751         struct device *kdev = &pdev->dev;
2752
2753         assert_rpm_wakelock_held(dev_priv);
2754         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2755                 atomic_inc(&dev_priv->pm.atomic_seq);
2756
2757         pm_runtime_mark_last_busy(kdev);
2758         pm_runtime_put_autosuspend(kdev);
2759 }
2760
2761 /**
2762  * intel_runtime_pm_enable - enable runtime pm
2763  * @dev_priv: i915 device instance
2764  *
2765  * This function enables runtime pm at the end of the driver load sequence.
2766  *
2767  * Note that this function does currently not enable runtime pm for the
2768  * subordinate display power domains. That is only done on the first modeset
2769  * using intel_display_set_init_power().
2770  */
2771 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2772 {
2773         struct pci_dev *pdev = dev_priv->drm.pdev;
2774         struct drm_device *dev = &dev_priv->drm;
2775         struct device *kdev = &pdev->dev;
2776
2777         pm_runtime_set_autosuspend_delay(kdev, 10000); /* 10s */
2778         pm_runtime_mark_last_busy(kdev);
2779
2780         /*
2781          * Take a permanent reference to disable the RPM functionality and drop
2782          * it only when unloading the driver. Use the low level get/put helpers,
2783          * so the driver's own RPM reference tracking asserts also work on
2784          * platforms without RPM support.
2785          */
2786         if (!HAS_RUNTIME_PM(dev)) {
2787                 pm_runtime_dont_use_autosuspend(kdev);
2788                 pm_runtime_get_sync(kdev);
2789         } else {
2790                 pm_runtime_use_autosuspend(kdev);
2791         }
2792
2793         /*
2794          * The core calls the driver load handler with an RPM reference held.
2795          * We drop that here and will reacquire it during unloading in
2796          * intel_power_domains_fini().
2797          */
2798         pm_runtime_put_autosuspend(kdev);
2799 }