drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <linux/log2.h>
  31
  32 #include <drm/drmP.h>
  33 #include <drm/i915_drm.h>
  34
  35 #include "i915_drv.h"
  36 #include "i915_gem_render_state.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39 #include "intel_workarounds.h"
  40
  41 /* Rough estimate of the typical request size, performing a flush,
  42  * set-context and then emitting the batch.
  43  */
  44 #define LEGACY_REQUEST_SIZE 200
  45
  46 static unsigned int __intel_ring_space(unsigned int head,
  47                                        unsigned int tail,
  48                                        unsigned int size)
  49 {
  50         /*
  51          * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
  52          * same cacheline, the Head Pointer must not be greater than the Tail
  53          * Pointer."
  54          */
  55         GEM_BUG_ON(!is_power_of_2(size));
  56         return (head - tail - CACHELINE_BYTES) & (size - 1);
  57 }
  58
  59 unsigned int intel_ring_update_space(struct intel_ring *ring)
  60 {
  61         unsigned int space;
  62
  63         space = __intel_ring_space(ring->head, ring->emit, ring->size);
  64
  65         ring->space = space;
  66         return space;
  67 }
  68
  69 static int
  70 gen2_render_ring_flush(struct i915_request *rq, u32 mode)
  71 {
  72         u32 cmd, *cs;
  73
  74         cmd = MI_FLUSH;
  75
  76         if (mode & EMIT_INVALIDATE)
  77                 cmd |= MI_READ_FLUSH;
  78
  79         cs = intel_ring_begin(rq, 2);
  80         if (IS_ERR(cs))
  81                 return PTR_ERR(cs);
  82
  83         *cs++ = cmd;
  84         *cs++ = MI_NOOP;
  85         intel_ring_advance(rq, cs);
  86
  87         return 0;
  88 }
  89
  90 static int
  91 gen4_render_ring_flush(struct i915_request *rq, u32 mode)
  92 {
  93         u32 cmd, *cs;
  94         int i;
  95
  96         /*
  97          * read/write caches:
  98          *
  99          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 100          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 101          * also flushed at 2d versus 3d pipeline switches.
 102          *
 103          * read-only caches:
 104          *
 105          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 106          * MI_READ_FLUSH is set, and is always flushed on 965.
 107          *
 108          * I915_GEM_DOMAIN_COMMAND may not exist?
 109          *
 110          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 111          * invalidated when MI_EXE_FLUSH is set.
 112          *
 113          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 114          * invalidated with every MI_FLUSH.
 115          *
 116          * TLBs:
 117          *
 118          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 119          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 120          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 121          * are flushed at any MI_FLUSH.
 122          */
 123
 124         cmd = MI_FLUSH;
 125         if (mode & EMIT_INVALIDATE) {
 126                 cmd |= MI_EXE_FLUSH;
 127                 if (IS_G4X(rq->i915) || IS_GEN5(rq->i915))
 128                         cmd |= MI_INVALIDATE_ISP;
 129         }
 130
 131         i = 2;
 132         if (mode & EMIT_INVALIDATE)
 133                 i += 20;
 134
 135         cs = intel_ring_begin(rq, i);
 136         if (IS_ERR(cs))
 137                 return PTR_ERR(cs);
 138
 139         *cs++ = cmd;
 140
 141         /*
 142          * A random delay to let the CS invalidate take effect? Without this
 143          * delay, the GPU relocation path fails as the CS does not see
 144          * the updated contents. Just as important, if we apply the flushes
 145          * to the EMIT_FLUSH branch (i.e. immediately after the relocation
 146          * write and before the invalidate on the next batch), the relocations
 147          * still fail. This implies that is a delay following invalidation
 148          * that is required to reset the caches as opposed to a delay to
 149          * ensure the memory is written.
 150          */
 151         if (mode & EMIT_INVALIDATE) {
 152                 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
 153                 *cs++ = i915_ggtt_offset(rq->engine->scratch) |
 154                         PIPE_CONTROL_GLOBAL_GTT;
 155                 *cs++ = 0;
 156                 *cs++ = 0;
 157
 158                 for (i = 0; i < 12; i++)
 159                         *cs++ = MI_FLUSH;
 160
 161                 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
 162                 *cs++ = i915_ggtt_offset(rq->engine->scratch) |
 163                         PIPE_CONTROL_GLOBAL_GTT;
 164                 *cs++ = 0;
 165                 *cs++ = 0;
 166         }
 167
 168         *cs++ = cmd;
 169
 170         intel_ring_advance(rq, cs);
 171
 172         return 0;
 173 }
 174
 175 /*
 176  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 177  * implementing two workarounds on gen6.  From section 1.4.7.1
 178  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 179  *
 180  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 181  * produced by non-pipelined state commands), software needs to first
 182  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 183  * 0.
 184  *
 185  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 186  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 187  *
 188  * And the workaround for these two requires this workaround first:
 189  *
 190  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 191  * BEFORE the pipe-control with a post-sync op and no write-cache
 192  * flushes.
 193  *
 194  * And this last workaround is tricky because of the requirements on
 195  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 196  * volume 2 part 1:
 197  *
 198  *     "1 of the following must also be set:
 199  *      - Render Target Cache Flush Enable ([12] of DW1)
 200  *      - Depth Cache Flush Enable ([0] of DW1)
 201  *      - Stall at Pixel Scoreboard ([1] of DW1)
 202  *      - Depth Stall ([13] of DW1)
 203  *      - Post-Sync Operation ([13] of DW1)
 204  *      - Notify Enable ([8] of DW1)"
 205  *
 206  * The cache flushes require the workaround flush that triggered this
 207  * one, so we can't use it.  Depth stall would trigger the same.
 208  * Post-sync nonzero is what triggered this second workaround, so we
 209  * can't use that one either.  Notify enable is IRQs, which aren't
 210  * really our business.  That leaves only stall at scoreboard.
 211  */
 212 static int
 213 intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
 214 {
 215         u32 scratch_addr =
 216                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 217         u32 *cs;
 218
 219         cs = intel_ring_begin(rq, 6);
 220         if (IS_ERR(cs))
 221                 return PTR_ERR(cs);
 222
 223         *cs++ = GFX_OP_PIPE_CONTROL(5);
 224         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 225         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 226         *cs++ = 0; /* low dword */
 227         *cs++ = 0; /* high dword */
 228         *cs++ = MI_NOOP;
 229         intel_ring_advance(rq, cs);
 230
 231         cs = intel_ring_begin(rq, 6);
 232         if (IS_ERR(cs))
 233                 return PTR_ERR(cs);
 234
 235         *cs++ = GFX_OP_PIPE_CONTROL(5);
 236         *cs++ = PIPE_CONTROL_QW_WRITE;
 237         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 238         *cs++ = 0;
 239         *cs++ = 0;
 240         *cs++ = MI_NOOP;
 241         intel_ring_advance(rq, cs);
 242
 243         return 0;
 244 }
 245
 246 static int
 247 gen6_render_ring_flush(struct i915_request *rq, u32 mode)
 248 {
 249         u32 scratch_addr =
 250                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 251         u32 *cs, flags = 0;
 252         int ret;
 253
 254         /* Force SNB workarounds for PIPE_CONTROL flushes */
 255         ret = intel_emit_post_sync_nonzero_flush(rq);
 256         if (ret)
 257                 return ret;
 258
 259         /* Just flush everything.  Experiments have shown that reducing the
 260          * number of bits based on the write domains has little performance
 261          * impact.
 262          */
 263         if (mode & EMIT_FLUSH) {
 264                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 265                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 266                 /*
 267                  * Ensure that any following seqno writes only happen
 268                  * when the render cache is indeed flushed.
 269                  */
 270                 flags |= PIPE_CONTROL_CS_STALL;
 271         }
 272         if (mode & EMIT_INVALIDATE) {
 273                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 274                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 275                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 276                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 277                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 278                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 279                 /*
 280                  * TLB invalidate requires a post-sync write.
 281                  */
 282                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 283         }
 284
 285         cs = intel_ring_begin(rq, 4);
 286         if (IS_ERR(cs))
 287                 return PTR_ERR(cs);
 288
 289         *cs++ = GFX_OP_PIPE_CONTROL(4);
 290         *cs++ = flags;
 291         *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
 292         *cs++ = 0;
 293         intel_ring_advance(rq, cs);
 294
 295         return 0;
 296 }
 297
 298 static int
 299 gen7_render_ring_cs_stall_wa(struct i915_request *rq)
 300 {
 301         u32 *cs;
 302
 303         cs = intel_ring_begin(rq, 4);
 304         if (IS_ERR(cs))
 305                 return PTR_ERR(cs);
 306
 307         *cs++ = GFX_OP_PIPE_CONTROL(4);
 308         *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
 309         *cs++ = 0;
 310         *cs++ = 0;
 311         intel_ring_advance(rq, cs);
 312
 313         return 0;
 314 }
 315
 316 static int
 317 gen7_render_ring_flush(struct i915_request *rq, u32 mode)
 318 {
 319         u32 scratch_addr =
 320                 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
 321         u32 *cs, flags = 0;
 322
 323         /*
 324          * Ensure that any following seqno writes only happen when the render
 325          * cache is indeed flushed.
 326          *
 327          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 328          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 329          * don't try to be clever and just set it unconditionally.
 330          */
 331         flags |= PIPE_CONTROL_CS_STALL;
 332
 333         /* Just flush everything.  Experiments have shown that reducing the
 334          * number of bits based on the write domains has little performance
 335          * impact.
 336          */
 337         if (mode & EMIT_FLUSH) {
 338                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 339                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 340                 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
 341                 flags |= PIPE_CONTROL_FLUSH_ENABLE;
 342         }
 343         if (mode & EMIT_INVALIDATE) {
 344                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 345                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 346                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 347                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 348                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 349                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 350                 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
 351                 /*
 352                  * TLB invalidate requires a post-sync write.
 353                  */
 354                 flags |= PIPE_CONTROL_QW_WRITE;
 355                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 356
 357                 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
 358
 359                 /* Workaround: we must issue a pipe_control with CS-stall bit
 360                  * set before a pipe_control command that has the state cache
 361                  * invalidate bit set. */
 362                 gen7_render_ring_cs_stall_wa(rq);
 363         }
 364
 365         cs = intel_ring_begin(rq, 4);
 366         if (IS_ERR(cs))
 367                 return PTR_ERR(cs);
 368
 369         *cs++ = GFX_OP_PIPE_CONTROL(4);
 370         *cs++ = flags;
 371         *cs++ = scratch_addr;
 372         *cs++ = 0;
 373         intel_ring_advance(rq, cs);
 374
 375         return 0;
 376 }
 377
 378 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
 379 {
 380         struct drm_i915_private *dev_priv = engine->i915;
 381         u32 addr;
 382
 383         addr = dev_priv->status_page_dmah->busaddr;
 384         if (INTEL_GEN(dev_priv) >= 4)
 385                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 386         I915_WRITE(HWS_PGA, addr);
 387 }
 388
 389 static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
 390 {
 391         struct drm_i915_private *dev_priv = engine->i915;
 392         i915_reg_t mmio;
 393
 394         /* The ring status page addresses are no longer next to the rest of
 395          * the ring registers as of gen7.
 396          */
 397         if (IS_GEN7(dev_priv)) {
 398                 switch (engine->id) {
 399                 /*
 400                  * No more rings exist on Gen7. Default case is only to shut up
 401                  * gcc switch check warning.
 402                  */
 403                 default:
 404                         GEM_BUG_ON(engine->id);
 405                 case RCS:
 406                         mmio = RENDER_HWS_PGA_GEN7;
 407                         break;
 408                 case BCS:
 409                         mmio = BLT_HWS_PGA_GEN7;
 410                         break;
 411                 case VCS:
 412                         mmio = BSD_HWS_PGA_GEN7;
 413                         break;
 414                 case VECS:
 415                         mmio = VEBOX_HWS_PGA_GEN7;
 416                         break;
 417                 }
 418         } else if (IS_GEN6(dev_priv)) {
 419                 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
 420         } else {
 421                 mmio = RING_HWS_PGA(engine->mmio_base);
 422         }
 423
 424         if (INTEL_GEN(dev_priv) >= 6) {
 425                 u32 mask = ~0u;
 426
 427                 /*
 428                  * Keep the render interrupt unmasked as this papers over
 429                  * lost interrupts following a reset.
 430                  */
 431                 if (engine->id == RCS)
 432                         mask &= ~BIT(0);
 433
 434                 I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);
 435         }
 436
 437         I915_WRITE(mmio, engine->status_page.ggtt_offset);
 438         POSTING_READ(mmio);
 439
 440         /* Flush the TLB for this page */
 441         if (IS_GEN(dev_priv, 6, 7)) {
 442                 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
 443
 444                 /* ring should be idle before issuing a sync flush*/
 445                 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
 446
 447                 I915_WRITE(reg,
 448                            _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
 449                                               INSTPM_SYNC_FLUSH));
 450                 if (intel_wait_for_register(dev_priv,
 451                                             reg, INSTPM_SYNC_FLUSH, 0,
 452                                             1000))
 453                         DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
 454                                   engine->name);
 455         }
 456 }
 457
 458 static bool stop_ring(struct intel_engine_cs *engine)
 459 {
 460         struct drm_i915_private *dev_priv = engine->i915;
 461
 462         if (INTEL_GEN(dev_priv) > 2) {
 463                 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
 464                 if (intel_wait_for_register(dev_priv,
 465                                             RING_MI_MODE(engine->mmio_base),
 466                                             MODE_IDLE,
 467                                             MODE_IDLE,
 468                                             1000)) {
 469                         DRM_ERROR("%s : timed out trying to stop ring\n",
 470                                   engine->name);
 471                         /* Sometimes we observe that the idle flag is not
 472                          * set even though the ring is empty. So double
 473                          * check before giving up.
 474                          */
 475                         if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
 476                                 return false;
 477                 }
 478         }
 479
 480         I915_WRITE_HEAD(engine, I915_READ_TAIL(engine));
 481
 482         I915_WRITE_HEAD(engine, 0);
 483         I915_WRITE_TAIL(engine, 0);
 484
 485         /* The ring must be empty before it is disabled */
 486         I915_WRITE_CTL(engine, 0);
 487
 488         return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
 489 }
 490
 491 static int init_ring_common(struct intel_engine_cs *engine)
 492 {
 493         struct drm_i915_private *dev_priv = engine->i915;
 494         struct intel_ring *ring = engine->buffer;
 495         int ret = 0;
 496
 497         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
 498
 499         if (!stop_ring(engine)) {
 500                 /* G45 ring initialization often fails to reset head to zero */
 501                 DRM_DEBUG_DRIVER("%s head not reset to zero "
 502                                 "ctl %08x head %08x tail %08x start %08x\n",
 503                                 engine->name,
 504                                 I915_READ_CTL(engine),
 505                                 I915_READ_HEAD(engine),
 506                                 I915_READ_TAIL(engine),
 507                                 I915_READ_START(engine));
 508
 509                 if (!stop_ring(engine)) {
 510                         DRM_ERROR("failed to set %s head to zero "
 511                                   "ctl %08x head %08x tail %08x start %08x\n",
 512                                   engine->name,
 513                                   I915_READ_CTL(engine),
 514                                   I915_READ_HEAD(engine),
 515                                   I915_READ_TAIL(engine),
 516                                   I915_READ_START(engine));
 517                         ret = -EIO;
 518                         goto out;
 519                 }
 520         }
 521
 522         if (HWS_NEEDS_PHYSICAL(dev_priv))
 523                 ring_setup_phys_status_page(engine);
 524         else
 525                 intel_ring_setup_status_page(engine);
 526
 527         intel_engine_reset_breadcrumbs(engine);
 528
 529         /* Enforce ordering by reading HEAD register back */
 530         I915_READ_HEAD(engine);
 531
 532         /* Initialize the ring. This must happen _after_ we've cleared the ring
 533          * registers with the above sequence (the readback of the HEAD registers
 534          * also enforces ordering), otherwise the hw might lose the new ring
 535          * register values. */
 536         I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
 537
 538         /* WaClearRingBufHeadRegAtInit:ctg,elk */
 539         if (I915_READ_HEAD(engine))
 540                 DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n",
 541                                  engine->name, I915_READ_HEAD(engine));
 542
 543         /* Check that the ring offsets point within the ring! */
 544         GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
 545         GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
 546
 547         intel_ring_update_space(ring);
 548         I915_WRITE_HEAD(engine, ring->head);
 549         I915_WRITE_TAIL(engine, ring->tail);
 550         (void)I915_READ_TAIL(engine);
 551
 552         I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
 553
 554         /* If the head is still not zero, the ring is dead */
 555         if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
 556                                     RING_VALID, RING_VALID,
 557                                     50)) {
 558                 DRM_ERROR("%s initialization failed "
 559                           "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
 560                           engine->name,
 561                           I915_READ_CTL(engine),
 562                           I915_READ_CTL(engine) & RING_VALID,
 563                           I915_READ_HEAD(engine), ring->head,
 564                           I915_READ_TAIL(engine), ring->tail,
 565                           I915_READ_START(engine),
 566                           i915_ggtt_offset(ring->vma));
 567                 ret = -EIO;
 568                 goto out;
 569         }
 570
 571         if (INTEL_GEN(dev_priv) > 2)
 572                 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
 573
 574 out:
 575         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
 576
 577         return ret;
 578 }
 579
 580 static struct i915_request *reset_prepare(struct intel_engine_cs *engine)
 581 {
 582         intel_engine_stop_cs(engine);
 583
 584         if (engine->irq_seqno_barrier)
 585                 engine->irq_seqno_barrier(engine);
 586
 587         return i915_gem_find_active_request(engine);
 588 }
 589
 590 static void skip_request(struct i915_request *rq)
 591 {
 592         void *vaddr = rq->ring->vaddr;
 593         u32 head;
 594
 595         head = rq->infix;
 596         if (rq->postfix < head) {
 597                 memset32(vaddr + head, MI_NOOP,
 598                          (rq->ring->size - head) / sizeof(u32));
 599                 head = 0;
 600         }
 601         memset32(vaddr + head, MI_NOOP, (rq->postfix - head) / sizeof(u32));
 602 }
 603
 604 static void reset_ring(struct intel_engine_cs *engine, struct i915_request *rq)
 605 {
 606         GEM_TRACE("%s seqno=%x\n", engine->name, rq ? rq->global_seqno : 0);
 607
 608         /*
 609          * Try to restore the logical GPU state to match the continuation
 610          * of the request queue. If we skip the context/PD restore, then
 611          * the next request may try to execute assuming that its context
 612          * is valid and loaded on the GPU and so may try to access invalid
 613          * memory, prompting repeated GPU hangs.
 614          *
 615          * If the request was guilty, we still restore the logical state
 616          * in case the next request requires it (e.g. the aliasing ppgtt),
 617          * but skip over the hung batch.
 618          *
 619          * If the request was innocent, we try to replay the request with
 620          * the restored context.
 621          */
 622         if (rq) {
 623                 /* If the rq hung, jump to its breadcrumb and skip the batch */
 624                 rq->ring->head = intel_ring_wrap(rq->ring, rq->head);
 625                 if (rq->fence.error == -EIO)
 626                         skip_request(rq);
 627         }
 628 }
 629
 630 static void reset_finish(struct intel_engine_cs *engine)
 631 {
 632 }
 633
 634 static int intel_rcs_ctx_init(struct i915_request *rq)
 635 {
 636         int ret;
 637
 638         ret = intel_ctx_workarounds_emit(rq);
 639         if (ret != 0)
 640                 return ret;
 641
 642         ret = i915_gem_render_state_emit(rq);
 643         if (ret)
 644                 return ret;
 645
 646         return 0;
 647 }
 648
 649 static int init_render_ring(struct intel_engine_cs *engine)
 650 {
 651         struct drm_i915_private *dev_priv = engine->i915;
 652         int ret = init_ring_common(engine);
 653         if (ret)
 654                 return ret;
 655
 656         intel_whitelist_workarounds_apply(engine);
 657
 658         /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
 659         if (IS_GEN(dev_priv, 4, 6))
 660                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 661
 662         /* We need to disable the AsyncFlip performance optimisations in order
 663          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 664          * programmed to '1' on all products.
 665          *
 666          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 667          */
 668         if (IS_GEN(dev_priv, 6, 7))
 669                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 670
 671         /* Required for the hardware to program scanline values for waiting */
 672         /* WaEnableFlushTlbInvalidationMode:snb */
 673         if (IS_GEN6(dev_priv))
 674                 I915_WRITE(GFX_MODE,
 675                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
 676
 677         /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
 678         if (IS_GEN7(dev_priv))
 679                 I915_WRITE(GFX_MODE_GEN7,
 680                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
 681                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 682
 683         if (IS_GEN6(dev_priv)) {
 684                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 685                  * "If this bit is set, STCunit will have LRA as replacement
 686                  *  policy. [...] This bit must be reset.  LRA replacement
 687                  *  policy is not supported."
 688                  */
 689                 I915_WRITE(CACHE_MODE_0,
 690                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 691         }
 692
 693         if (IS_GEN(dev_priv, 6, 7))
 694                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 695
 696         if (INTEL_GEN(dev_priv) >= 6)
 697                 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 698
 699         return 0;
 700 }
 701
 702 static u32 *gen6_signal(struct i915_request *rq, u32 *cs)
 703 {
 704         struct drm_i915_private *dev_priv = rq->i915;
 705         struct intel_engine_cs *engine;
 706         enum intel_engine_id id;
 707         int num_rings = 0;
 708
 709         for_each_engine(engine, dev_priv, id) {
 710                 i915_reg_t mbox_reg;
 711
 712                 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
 713                         continue;
 714
 715                 mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id];
 716                 if (i915_mmio_reg_valid(mbox_reg)) {
 717                         *cs++ = MI_LOAD_REGISTER_IMM(1);
 718                         *cs++ = i915_mmio_reg_offset(mbox_reg);
 719                         *cs++ = rq->global_seqno;
 720                         num_rings++;
 721                 }
 722         }
 723         if (num_rings & 1)
 724                 *cs++ = MI_NOOP;
 725
 726         return cs;
 727 }
 728
 729 static void cancel_requests(struct intel_engine_cs *engine)
 730 {
 731         struct i915_request *request;
 732         unsigned long flags;
 733
 734         spin_lock_irqsave(&engine->timeline.lock, flags);
 735
 736         /* Mark all submitted requests as skipped. */
 737         list_for_each_entry(request, &engine->timeline.requests, link) {
 738                 GEM_BUG_ON(!request->global_seqno);
 739                 if (!i915_request_completed(request))
 740                         dma_fence_set_error(&request->fence, -EIO);
 741         }
 742         /* Remaining _unready_ requests will be nop'ed when submitted */
 743
 744         spin_unlock_irqrestore(&engine->timeline.lock, flags);
 745 }
 746
 747 static void i9xx_submit_request(struct i915_request *request)
 748 {
 749         struct drm_i915_private *dev_priv = request->i915;
 750
 751         i915_request_submit(request);
 752
 753         I915_WRITE_TAIL(request->engine,
 754                         intel_ring_set_tail(request->ring, request->tail));
 755 }
 756
 757 static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 758 {
 759         *cs++ = MI_STORE_DWORD_INDEX;
 760         *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT;
 761         *cs++ = rq->global_seqno;
 762         *cs++ = MI_USER_INTERRUPT;
 763
 764         rq->tail = intel_ring_offset(rq, cs);
 765         assert_ring_tail_valid(rq->ring, rq->tail);
 766 }
 767
 768 static const int i9xx_emit_breadcrumb_sz = 4;
 769
 770 static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs)
 771 {
 772         return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs));
 773 }
 774
 775 static int
 776 gen6_ring_sync_to(struct i915_request *rq, struct i915_request *signal)
 777 {
 778         u32 dw1 = MI_SEMAPHORE_MBOX |
 779                   MI_SEMAPHORE_COMPARE |
 780                   MI_SEMAPHORE_REGISTER;
 781         u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id];
 782         u32 *cs;
 783
 784         WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
 785
 786         cs = intel_ring_begin(rq, 4);
 787         if (IS_ERR(cs))
 788                 return PTR_ERR(cs);
 789
 790         *cs++ = dw1 | wait_mbox;
 791         /* Throughout all of the GEM code, seqno passed implies our current
 792          * seqno is >= the last seqno executed. However for hardware the
 793          * comparison is strictly greater than.
 794          */
 795         *cs++ = signal->global_seqno - 1;
 796         *cs++ = 0;
 797         *cs++ = MI_NOOP;
 798         intel_ring_advance(rq, cs);
 799
 800         return 0;
 801 }
 802
 803 static void
 804 gen5_seqno_barrier(struct intel_engine_cs *engine)
 805 {
 806         /* MI_STORE are internally buffered by the GPU and not flushed
 807          * either by MI_FLUSH or SyncFlush or any other combination of
 808          * MI commands.
 809          *
 810          * "Only the submission of the store operation is guaranteed.
 811          * The write result will be complete (coherent) some time later
 812          * (this is practically a finite period but there is no guaranteed
 813          * latency)."
 814          *
 815          * Empirically, we observe that we need a delay of at least 75us to
 816          * be sure that the seqno write is visible by the CPU.
 817          */
 818         usleep_range(125, 250);
 819 }
 820
 821 static void
 822 gen6_seqno_barrier(struct intel_engine_cs *engine)
 823 {
 824         struct drm_i915_private *dev_priv = engine->i915;
 825
 826         /* Workaround to force correct ordering between irq and seqno writes on
 827          * ivb (and maybe also on snb) by reading from a CS register (like
 828          * ACTHD) before reading the status page.
 829          *
 830          * Note that this effectively stalls the read by the time it takes to
 831          * do a memory transaction, which more or less ensures that the write
 832          * from the GPU has sufficient time to invalidate the CPU cacheline.
 833          * Alternatively we could delay the interrupt from the CS ring to give
 834          * the write time to land, but that would incur a delay after every
 835          * batch i.e. much more frequent than a delay when waiting for the
 836          * interrupt (with the same net latency).
 837          *
 838          * Also note that to prevent whole machine hangs on gen7, we have to
 839          * take the spinlock to guard against concurrent cacheline access.
 840          */
 841         spin_lock_irq(&dev_priv->uncore.lock);
 842         POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
 843         spin_unlock_irq(&dev_priv->uncore.lock);
 844 }
 845
 846 static void
 847 gen5_irq_enable(struct intel_engine_cs *engine)
 848 {
 849         gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
 850 }
 851
 852 static void
 853 gen5_irq_disable(struct intel_engine_cs *engine)
 854 {
 855         gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
 856 }
 857
 858 static void
 859 i9xx_irq_enable(struct intel_engine_cs *engine)
 860 {
 861         struct drm_i915_private *dev_priv = engine->i915;
 862
 863         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 864         I915_WRITE(IMR, dev_priv->irq_mask);
 865         POSTING_READ_FW(RING_IMR(engine->mmio_base));
 866 }
 867
 868 static void
 869 i9xx_irq_disable(struct intel_engine_cs *engine)
 870 {
 871         struct drm_i915_private *dev_priv = engine->i915;
 872
 873         dev_priv->irq_mask |= engine->irq_enable_mask;
 874         I915_WRITE(IMR, dev_priv->irq_mask);
 875 }
 876
 877 static void
 878 i8xx_irq_enable(struct intel_engine_cs *engine)
 879 {
 880         struct drm_i915_private *dev_priv = engine->i915;
 881
 882         dev_priv->irq_mask &= ~engine->irq_enable_mask;
 883         I915_WRITE16(IMR, dev_priv->irq_mask);
 884         POSTING_READ16(RING_IMR(engine->mmio_base));
 885 }
 886
 887 static void
 888 i8xx_irq_disable(struct intel_engine_cs *engine)
 889 {
 890         struct drm_i915_private *dev_priv = engine->i915;
 891
 892         dev_priv->irq_mask |= engine->irq_enable_mask;
 893         I915_WRITE16(IMR, dev_priv->irq_mask);
 894 }
 895
 896 static int
 897 bsd_ring_flush(struct i915_request *rq, u32 mode)
 898 {
 899         u32 *cs;
 900
 901         cs = intel_ring_begin(rq, 2);
 902         if (IS_ERR(cs))
 903                 return PTR_ERR(cs);
 904
 905         *cs++ = MI_FLUSH;
 906         *cs++ = MI_NOOP;
 907         intel_ring_advance(rq, cs);
 908         return 0;
 909 }
 910
 911 static void
 912 gen6_irq_enable(struct intel_engine_cs *engine)
 913 {
 914         struct drm_i915_private *dev_priv = engine->i915;
 915
 916         I915_WRITE_IMR(engine,
 917                        ~(engine->irq_enable_mask |
 918                          engine->irq_keep_mask));
 919         gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
 920 }
 921
 922 static void
 923 gen6_irq_disable(struct intel_engine_cs *engine)
 924 {
 925         struct drm_i915_private *dev_priv = engine->i915;
 926
 927         I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
 928         gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
 929 }
 930
 931 static void
 932 hsw_vebox_irq_enable(struct intel_engine_cs *engine)
 933 {
 934         struct drm_i915_private *dev_priv = engine->i915;
 935
 936         I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
 937         gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
 938 }
 939
 940 static void
 941 hsw_vebox_irq_disable(struct intel_engine_cs *engine)
 942 {
 943         struct drm_i915_private *dev_priv = engine->i915;
 944
 945         I915_WRITE_IMR(engine, ~0);
 946         gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
 947 }
 948
 949 static int
 950 i965_emit_bb_start(struct i915_request *rq,
 951                    u64 offset, u32 length,
 952                    unsigned int dispatch_flags)
 953 {
 954         u32 *cs;
 955
 956         cs = intel_ring_begin(rq, 2);
 957         if (IS_ERR(cs))
 958                 return PTR_ERR(cs);
 959
 960         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
 961                 I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
 962         *cs++ = offset;
 963         intel_ring_advance(rq, cs);
 964
 965         return 0;
 966 }
 967
 968 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
 969 #define I830_BATCH_LIMIT (256*1024)
 970 #define I830_TLB_ENTRIES (2)
 971 #define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
 972 static int
 973 i830_emit_bb_start(struct i915_request *rq,
 974                    u64 offset, u32 len,
 975                    unsigned int dispatch_flags)
 976 {
 977         u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch);
 978
 979         cs = intel_ring_begin(rq, 6);
 980         if (IS_ERR(cs))
 981                 return PTR_ERR(cs);
 982
 983         /* Evict the invalid PTE TLBs */
 984         *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
 985         *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
 986         *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
 987         *cs++ = cs_offset;
 988         *cs++ = 0xdeadbeef;
 989         *cs++ = MI_NOOP;
 990         intel_ring_advance(rq, cs);
 991
 992         if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
 993                 if (len > I830_BATCH_LIMIT)
 994                         return -ENOSPC;
 995
 996                 cs = intel_ring_begin(rq, 6 + 2);
 997                 if (IS_ERR(cs))
 998                         return PTR_ERR(cs);
 999
1000                 /* Blit the batch (which has now all relocs applied) to the
1001                  * stable batch scratch bo area (so that the CS never
1002                  * stumbles over its tlb invalidation bug) ...
1003                  */
1004                 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
1005                 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
1006                 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
1007                 *cs++ = cs_offset;
1008                 *cs++ = 4096;
1009                 *cs++ = offset;
1010
1011                 *cs++ = MI_FLUSH;
1012                 *cs++ = MI_NOOP;
1013                 intel_ring_advance(rq, cs);
1014
1015                 /* ... and execute it. */
1016                 offset = cs_offset;
1017         }
1018
1019         cs = intel_ring_begin(rq, 2);
1020         if (IS_ERR(cs))
1021                 return PTR_ERR(cs);
1022
1023         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1024         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1025                 MI_BATCH_NON_SECURE);
1026         intel_ring_advance(rq, cs);
1027
1028         return 0;
1029 }
1030
1031 static int
1032 i915_emit_bb_start(struct i915_request *rq,
1033                    u64 offset, u32 len,
1034                    unsigned int dispatch_flags)
1035 {
1036         u32 *cs;
1037
1038         cs = intel_ring_begin(rq, 2);
1039         if (IS_ERR(cs))
1040                 return PTR_ERR(cs);
1041
1042         *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1043         *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1044                 MI_BATCH_NON_SECURE);
1045         intel_ring_advance(rq, cs);
1046
1047         return 0;
1048 }
1049
1050
1051
1052 int intel_ring_pin(struct intel_ring *ring,
1053                    struct drm_i915_private *i915,
1054                    unsigned int offset_bias)
1055 {
1056         enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1057         struct i915_vma *vma = ring->vma;
1058         unsigned int flags;
1059         void *addr;
1060         int ret;
1061
1062         GEM_BUG_ON(ring->vaddr);
1063
1064
1065         flags = PIN_GLOBAL;
1066         if (offset_bias)
1067                 flags |= PIN_OFFSET_BIAS | offset_bias;
1068         if (vma->obj->stolen)
1069                 flags |= PIN_MAPPABLE;
1070         else
1071                 flags |= PIN_HIGH;
1072
1073         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1074                 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
1075                         ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1076                 else
1077                         ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
1078                 if (unlikely(ret))
1079                         return ret;
1080         }
1081
1082         ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
1083         if (unlikely(ret))
1084                 return ret;
1085
1086         if (i915_vma_is_map_and_fenceable(vma))
1087                 addr = (void __force *)i915_vma_pin_iomap(vma);
1088         else
1089                 addr = i915_gem_object_pin_map(vma->obj, map);
1090         if (IS_ERR(addr))
1091                 goto err;
1092
1093         vma->obj->pin_global++;
1094
1095         ring->vaddr = addr;
1096         return 0;
1097
1098 err:
1099         i915_vma_unpin(vma);
1100         return PTR_ERR(addr);
1101 }
1102
1103 void intel_ring_reset(struct intel_ring *ring, u32 tail)
1104 {
1105         GEM_BUG_ON(!intel_ring_offset_valid(ring, tail));
1106
1107         ring->tail = tail;
1108         ring->head = tail;
1109         ring->emit = tail;
1110         intel_ring_update_space(ring);
1111 }
1112
1113 void intel_ring_unpin(struct intel_ring *ring)
1114 {
1115         GEM_BUG_ON(!ring->vma);
1116         GEM_BUG_ON(!ring->vaddr);
1117
1118         /* Discard any unused bytes beyond that submitted to hw. */
1119         intel_ring_reset(ring, ring->tail);
1120
1121         if (i915_vma_is_map_and_fenceable(ring->vma))
1122                 i915_vma_unpin_iomap(ring->vma);
1123         else
1124                 i915_gem_object_unpin_map(ring->vma->obj);
1125         ring->vaddr = NULL;
1126
1127         ring->vma->obj->pin_global--;
1128         i915_vma_unpin(ring->vma);
1129 }
1130
1131 static struct i915_vma *
1132 intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1133 {
1134         struct i915_address_space *vm = &dev_priv->ggtt.vm;
1135         struct drm_i915_gem_object *obj;
1136         struct i915_vma *vma;
1137
1138         obj = i915_gem_object_create_stolen(dev_priv, size);
1139         if (!obj)
1140                 obj = i915_gem_object_create_internal(dev_priv, size);
1141         if (IS_ERR(obj))
1142                 return ERR_CAST(obj);
1143
1144         /*
1145          * Mark ring buffers as read-only from GPU side (so no stray overwrites)
1146          * if supported by the platform's GGTT.
1147          */
1148         if (vm->has_read_only)
1149                 i915_gem_object_set_readonly(obj);
1150
1151         vma = i915_vma_instance(obj, vm, NULL);
1152         if (IS_ERR(vma))
1153                 goto err;
1154
1155         return vma;
1156
1157 err:
1158         i915_gem_object_put(obj);
1159         return vma;
1160 }
1161
1162 struct intel_ring *
1163 intel_engine_create_ring(struct intel_engine_cs *engine,
1164                          struct i915_timeline *timeline,
1165                          int size)
1166 {
1167         struct intel_ring *ring;
1168         struct i915_vma *vma;
1169
1170         GEM_BUG_ON(!is_power_of_2(size));
1171         GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1172         GEM_BUG_ON(timeline == &engine->timeline);
1173         lockdep_assert_held(&engine->i915->drm.struct_mutex);
1174
1175         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1176         if (!ring)
1177                 return ERR_PTR(-ENOMEM);
1178
1179         INIT_LIST_HEAD(&ring->request_list);
1180         ring->timeline = i915_timeline_get(timeline);
1181
1182         ring->size = size;
1183         /* Workaround an erratum on the i830 which causes a hang if
1184          * the TAIL pointer points to within the last 2 cachelines
1185          * of the buffer.
1186          */
1187         ring->effective_size = size;
1188         if (IS_I830(engine->i915) || IS_I845G(engine->i915))
1189                 ring->effective_size -= 2 * CACHELINE_BYTES;
1190
1191         intel_ring_update_space(ring);
1192
1193         vma = intel_ring_create_vma(engine->i915, size);
1194         if (IS_ERR(vma)) {
1195                 kfree(ring);
1196                 return ERR_CAST(vma);
1197         }
1198         ring->vma = vma;
1199
1200         return ring;
1201 }
1202
1203 void
1204 intel_ring_free(struct intel_ring *ring)
1205 {
1206         struct drm_i915_gem_object *obj = ring->vma->obj;
1207
1208         i915_vma_close(ring->vma);
1209         __i915_gem_object_release_unless_active(obj);
1210
1211         i915_timeline_put(ring->timeline);
1212         kfree(ring);
1213 }
1214
1215 static void intel_ring_context_destroy(struct intel_context *ce)
1216 {
1217         GEM_BUG_ON(ce->pin_count);
1218
1219         if (!ce->state)
1220                 return;
1221
1222         GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1223         i915_gem_object_put(ce->state->obj);
1224 }
1225
1226 static int __context_pin_ppgtt(struct i915_gem_context *ctx)
1227 {
1228         struct i915_hw_ppgtt *ppgtt;
1229         int err = 0;
1230
1231         ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
1232         if (ppgtt)
1233                 err = gen6_ppgtt_pin(ppgtt);
1234
1235         return err;
1236 }
1237
1238 static void __context_unpin_ppgtt(struct i915_gem_context *ctx)
1239 {
1240         struct i915_hw_ppgtt *ppgtt;
1241
1242         ppgtt = ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt;
1243         if (ppgtt)
1244                 gen6_ppgtt_unpin(ppgtt);
1245 }
1246
1247 static int __context_pin(struct intel_context *ce)
1248 {
1249         struct i915_vma *vma;
1250         int err;
1251
1252         vma = ce->state;
1253         if (!vma)
1254                 return 0;
1255
1256         /*
1257          * Clear this page out of any CPU caches for coherent swap-in/out.
1258          * We only want to do this on the first bind so that we do not stall
1259          * on an active context (which by nature is already on the GPU).
1260          */
1261         if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1262                 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1263                 if (err)
1264                         return err;
1265         }
1266
1267         err = i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT,
1268                            PIN_GLOBAL | PIN_HIGH);
1269         if (err)
1270                 return err;
1271
1272         /*
1273          * And mark is as a globally pinned object to let the shrinker know
1274          * it cannot reclaim the object until we release it.
1275          */
1276         vma->obj->pin_global++;
1277
1278         return 0;
1279 }
1280
1281 static void __context_unpin(struct intel_context *ce)
1282 {
1283         struct i915_vma *vma;
1284
1285         vma = ce->state;
1286         if (!vma)
1287                 return;
1288
1289         vma->obj->pin_global--;
1290         i915_vma_unpin(vma);
1291 }
1292
1293 static void intel_ring_context_unpin(struct intel_context *ce)
1294 {
1295         __context_unpin_ppgtt(ce->gem_context);
1296         __context_unpin(ce);
1297
1298         i915_gem_context_put(ce->gem_context);
1299 }
1300
1301 static struct i915_vma *
1302 alloc_context_vma(struct intel_engine_cs *engine)
1303 {
1304         struct drm_i915_private *i915 = engine->i915;
1305         struct drm_i915_gem_object *obj;
1306         struct i915_vma *vma;
1307         int err;
1308
1309         obj = i915_gem_object_create(i915, engine->context_size);
1310         if (IS_ERR(obj))
1311                 return ERR_CAST(obj);
1312
1313         if (engine->default_state) {
1314                 void *defaults, *vaddr;
1315
1316                 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1317                 if (IS_ERR(vaddr)) {
1318                         err = PTR_ERR(vaddr);
1319                         goto err_obj;
1320                 }
1321
1322                 defaults = i915_gem_object_pin_map(engine->default_state,
1323                                                    I915_MAP_WB);
1324                 if (IS_ERR(defaults)) {
1325                         err = PTR_ERR(defaults);
1326                         goto err_map;
1327                 }
1328
1329                 memcpy(vaddr, defaults, engine->context_size);
1330
1331                 i915_gem_object_unpin_map(engine->default_state);
1332                 i915_gem_object_unpin_map(obj);
1333         }
1334
1335         /*
1336          * Try to make the context utilize L3 as well as LLC.
1337          *
1338          * On VLV we don't have L3 controls in the PTEs so we
1339          * shouldn't touch the cache level, especially as that
1340          * would make the object snooped which might have a
1341          * negative performance impact.
1342          *
1343          * Snooping is required on non-llc platforms in execlist
1344          * mode, but since all GGTT accesses use PAT entry 0 we
1345          * get snooping anyway regardless of cache_level.
1346          *
1347          * This is only applicable for Ivy Bridge devices since
1348          * later platforms don't have L3 control bits in the PTE.
1349          */
1350         if (IS_IVYBRIDGE(i915)) {
1351                 /* Ignore any error, regard it as a simple optimisation */
1352                 i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
1353         }
1354
1355         vma = i915_vma_instance(obj, &i915->ggtt.vm, NULL);
1356         if (IS_ERR(vma)) {
1357                 err = PTR_ERR(vma);
1358                 goto err_obj;
1359         }
1360
1361         return vma;
1362
1363 err_map:
1364         i915_gem_object_unpin_map(obj);
1365 err_obj:
1366         i915_gem_object_put(obj);
1367         return ERR_PTR(err);
1368 }
1369
1370 static struct intel_context *
1371 __ring_context_pin(struct intel_engine_cs *engine,
1372                    struct i915_gem_context *ctx,
1373                    struct intel_context *ce)
1374 {
1375         int err;
1376
1377         if (!ce->state && engine->context_size) {
1378                 struct i915_vma *vma;
1379
1380                 vma = alloc_context_vma(engine);
1381                 if (IS_ERR(vma)) {
1382                         err = PTR_ERR(vma);
1383                         goto err;
1384                 }
1385
1386                 ce->state = vma;
1387         }
1388
1389         err = __context_pin(ce);
1390         if (err)
1391                 goto err;
1392
1393         err = __context_pin_ppgtt(ce->gem_context);
1394         if (err)
1395                 goto err_unpin;
1396
1397         i915_gem_context_get(ctx);
1398
1399         /* One ringbuffer to rule them all */
1400         GEM_BUG_ON(!engine->buffer);
1401         ce->ring = engine->buffer;
1402
1403         return ce;
1404
1405 err_unpin:
1406         __context_unpin(ce);
1407 err:
1408         ce->pin_count = 0;
1409         return ERR_PTR(err);
1410 }
1411
1412 static const struct intel_context_ops ring_context_ops = {
1413         .unpin = intel_ring_context_unpin,
1414         .destroy = intel_ring_context_destroy,
1415 };
1416
1417 static struct intel_context *
1418 intel_ring_context_pin(struct intel_engine_cs *engine,
1419                        struct i915_gem_context *ctx)
1420 {
1421         struct intel_context *ce = to_intel_context(ctx, engine);
1422
1423         lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1424
1425         if (likely(ce->pin_count++))
1426                 return ce;
1427         GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1428
1429         ce->ops = &ring_context_ops;
1430
1431         return __ring_context_pin(engine, ctx, ce);
1432 }
1433
1434 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1435 {
1436         struct i915_timeline *timeline;
1437         struct intel_ring *ring;
1438         unsigned int size;
1439         int err;
1440
1441         intel_engine_setup_common(engine);
1442
1443         timeline = i915_timeline_create(engine->i915, engine->name);
1444         if (IS_ERR(timeline)) {
1445                 err = PTR_ERR(timeline);
1446                 goto err;
1447         }
1448
1449         ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE);
1450         i915_timeline_put(timeline);
1451         if (IS_ERR(ring)) {
1452                 err = PTR_ERR(ring);
1453                 goto err;
1454         }
1455
1456         /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1457         err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
1458         if (err)
1459                 goto err_ring;
1460
1461         GEM_BUG_ON(engine->buffer);
1462         engine->buffer = ring;
1463
1464         size = PAGE_SIZE;
1465         if (HAS_BROKEN_CS_TLB(engine->i915))
1466                 size = I830_WA_SIZE;
1467         err = intel_engine_create_scratch(engine, size);
1468         if (err)
1469                 goto err_unpin;
1470
1471         err = intel_engine_init_common(engine);
1472         if (err)
1473                 goto err_scratch;
1474
1475         return 0;
1476
1477 err_scratch:
1478         intel_engine_cleanup_scratch(engine);
1479 err_unpin:
1480         intel_ring_unpin(ring);
1481 err_ring:
1482         intel_ring_free(ring);
1483 err:
1484         intel_engine_cleanup_common(engine);
1485         return err;
1486 }
1487
1488 void intel_engine_cleanup(struct intel_engine_cs *engine)
1489 {
1490         struct drm_i915_private *dev_priv = engine->i915;
1491
1492         WARN_ON(INTEL_GEN(dev_priv) > 2 &&
1493                 (I915_READ_MODE(engine) & MODE_IDLE) == 0);
1494
1495         intel_ring_unpin(engine->buffer);
1496         intel_ring_free(engine->buffer);
1497
1498         if (engine->cleanup)
1499                 engine->cleanup(engine);
1500
1501         intel_engine_cleanup_common(engine);
1502
1503         dev_priv->engine[engine->id] = NULL;
1504         kfree(engine);
1505 }
1506
1507 void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
1508 {
1509         struct intel_engine_cs *engine;
1510         enum intel_engine_id id;
1511
1512         /* Restart from the beginning of the rings for convenience */
1513         for_each_engine(engine, dev_priv, id)
1514                 intel_ring_reset(engine->buffer, 0);
1515 }
1516
1517 static int load_pd_dir(struct i915_request *rq,
1518                        const struct i915_hw_ppgtt *ppgtt)
1519 {
1520         const struct intel_engine_cs * const engine = rq->engine;
1521         u32 *cs;
1522
1523         cs = intel_ring_begin(rq, 6);
1524         if (IS_ERR(cs))
1525                 return PTR_ERR(cs);
1526
1527         *cs++ = MI_LOAD_REGISTER_IMM(1);
1528         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
1529         *cs++ = PP_DIR_DCLV_2G;
1530
1531         *cs++ = MI_LOAD_REGISTER_IMM(1);
1532         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1533         *cs++ = ppgtt->pd.base.ggtt_offset << 10;
1534
1535         intel_ring_advance(rq, cs);
1536
1537         return 0;
1538 }
1539
1540 static int flush_pd_dir(struct i915_request *rq)
1541 {
1542         const struct intel_engine_cs * const engine = rq->engine;
1543         u32 *cs;
1544
1545         cs = intel_ring_begin(rq, 4);
1546         if (IS_ERR(cs))
1547                 return PTR_ERR(cs);
1548
1549         /* Stall until the page table load is complete */
1550         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1551         *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1552         *cs++ = i915_ggtt_offset(engine->scratch);
1553         *cs++ = MI_NOOP;
1554
1555         intel_ring_advance(rq, cs);
1556         return 0;
1557 }
1558
1559 static inline int mi_set_context(struct i915_request *rq, u32 flags)
1560 {
1561         struct drm_i915_private *i915 = rq->i915;
1562         struct intel_engine_cs *engine = rq->engine;
1563         enum intel_engine_id id;
1564         const int num_rings =
1565                 /* Use an extended w/a on gen7 if signalling from other rings */
1566                 (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
1567                 INTEL_INFO(i915)->num_rings - 1 :
1568                 0;
1569         bool force_restore = false;
1570         int len;
1571         u32 *cs;
1572
1573         flags |= MI_MM_SPACE_GTT;
1574         if (IS_HASWELL(i915))
1575                 /* These flags are for resource streamer on HSW+ */
1576                 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
1577         else
1578                 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1579
1580         len = 4;
1581         if (IS_GEN7(i915))
1582                 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
1583         if (flags & MI_FORCE_RESTORE) {
1584                 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
1585                 flags &= ~MI_FORCE_RESTORE;
1586                 force_restore = true;
1587                 len += 2;
1588         }
1589
1590         cs = intel_ring_begin(rq, len);
1591         if (IS_ERR(cs))
1592                 return PTR_ERR(cs);
1593
1594         /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1595         if (IS_GEN7(i915)) {
1596                 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1597                 if (num_rings) {
1598                         struct intel_engine_cs *signaller;
1599
1600                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1601                         for_each_engine(signaller, i915, id) {
1602                                 if (signaller == engine)
1603                                         continue;
1604
1605                                 *cs++ = i915_mmio_reg_offset(
1606                                            RING_PSMI_CTL(signaller->mmio_base));
1607                                 *cs++ = _MASKED_BIT_ENABLE(
1608                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1609                         }
1610                 }
1611         }
1612
1613         if (force_restore) {
1614                 /*
1615                  * The HW doesn't handle being told to restore the current
1616                  * context very well. Quite often it likes goes to go off and
1617                  * sulk, especially when it is meant to be reloading PP_DIR.
1618                  * A very simple fix to force the reload is to simply switch
1619                  * away from the current context and back again.
1620                  *
1621                  * Note that the kernel_context will contain random state
1622                  * following the INHIBIT_RESTORE. We accept this since we
1623                  * never use the kernel_context state; it is merely a
1624                  * placeholder we use to flush other contexts.
1625                  */
1626                 *cs++ = MI_SET_CONTEXT;
1627                 *cs++ = i915_ggtt_offset(to_intel_context(i915->kernel_context,
1628                                                           engine)->state) |
1629                         MI_MM_SPACE_GTT |
1630                         MI_RESTORE_INHIBIT;
1631         }
1632
1633         *cs++ = MI_NOOP;
1634         *cs++ = MI_SET_CONTEXT;
1635         *cs++ = i915_ggtt_offset(rq->hw_context->state) | flags;
1636         /*
1637          * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
1638          * WaMiSetContext_Hang:snb,ivb,vlv
1639          */
1640         *cs++ = MI_NOOP;
1641
1642         if (IS_GEN7(i915)) {
1643                 if (num_rings) {
1644                         struct intel_engine_cs *signaller;
1645                         i915_reg_t last_reg = {}; /* keep gcc quiet */
1646
1647                         *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1648                         for_each_engine(signaller, i915, id) {
1649                                 if (signaller == engine)
1650                                         continue;
1651
1652                                 last_reg = RING_PSMI_CTL(signaller->mmio_base);
1653                                 *cs++ = i915_mmio_reg_offset(last_reg);
1654                                 *cs++ = _MASKED_BIT_DISABLE(
1655                                                 GEN6_PSMI_SLEEP_MSG_DISABLE);
1656                         }
1657
1658                         /* Insert a delay before the next switch! */
1659                         *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1660                         *cs++ = i915_mmio_reg_offset(last_reg);
1661                         *cs++ = i915_ggtt_offset(engine->scratch);
1662                         *cs++ = MI_NOOP;
1663                 }
1664                 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1665         }
1666
1667         intel_ring_advance(rq, cs);
1668
1669         return 0;
1670 }
1671
1672 static int remap_l3(struct i915_request *rq, int slice)
1673 {
1674         u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
1675         int i;
1676
1677         if (!remap_info)
1678                 return 0;
1679
1680         cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
1681         if (IS_ERR(cs))
1682                 return PTR_ERR(cs);
1683
1684         /*
1685          * Note: We do not worry about the concurrent register cacheline hang
1686          * here because no other code should access these registers other than
1687          * at initialization time.
1688          */
1689         *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
1690         for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
1691                 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
1692                 *cs++ = remap_info[i];
1693         }
1694         *cs++ = MI_NOOP;
1695         intel_ring_advance(rq, cs);
1696
1697         return 0;
1698 }
1699
1700 static int switch_context(struct i915_request *rq)
1701 {
1702         struct intel_engine_cs *engine = rq->engine;
1703         struct i915_gem_context *ctx = rq->gem_context;
1704         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
1705         unsigned int unwind_mm = 0;
1706         u32 hw_flags = 0;
1707         int ret, i;
1708
1709         lockdep_assert_held(&rq->i915->drm.struct_mutex);
1710         GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
1711
1712         if (ppgtt) {
1713                 ret = load_pd_dir(rq, ppgtt);
1714                 if (ret)
1715                         goto err;
1716
1717                 if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) {
1718                         unwind_mm = intel_engine_flag(engine);
1719                         ppgtt->pd_dirty_rings &= ~unwind_mm;
1720                         hw_flags = MI_FORCE_RESTORE;
1721                 }
1722         }
1723
1724         if (rq->hw_context->state) {
1725                 GEM_BUG_ON(engine->id != RCS);
1726
1727                 /*
1728                  * The kernel context(s) is treated as pure scratch and is not
1729                  * expected to retain any state (as we sacrifice it during
1730                  * suspend and on resume it may be corrupted). This is ok,
1731                  * as nothing actually executes using the kernel context; it
1732                  * is purely used for flushing user contexts.
1733                  */
1734                 if (i915_gem_context_is_kernel(ctx))
1735                         hw_flags = MI_RESTORE_INHIBIT;
1736
1737                 ret = mi_set_context(rq, hw_flags);
1738                 if (ret)
1739                         goto err_mm;
1740         }
1741
1742         if (ppgtt) {
1743                 ret = flush_pd_dir(rq);
1744                 if (ret)
1745                         goto err_mm;
1746         }
1747
1748         if (ctx->remap_slice) {
1749                 for (i = 0; i < MAX_L3_SLICES; i++) {
1750                         if (!(ctx->remap_slice & BIT(i)))
1751                                 continue;
1752
1753                         ret = remap_l3(rq, i);
1754                         if (ret)
1755                                 goto err_mm;
1756                 }
1757
1758                 ctx->remap_slice = 0;
1759         }
1760
1761         return 0;
1762
1763 err_mm:
1764         if (unwind_mm)
1765                 ppgtt->pd_dirty_rings |= unwind_mm;
1766 err:
1767         return ret;
1768 }
1769
1770 static int ring_request_alloc(struct i915_request *request)
1771 {
1772         int ret;
1773
1774         GEM_BUG_ON(!request->hw_context->pin_count);
1775
1776         /* Flush enough space to reduce the likelihood of waiting after
1777          * we start building the request - in which case we will just
1778          * have to repeat work.
1779          */
1780         request->reserved_space += LEGACY_REQUEST_SIZE;
1781
1782         ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1783         if (ret)
1784                 return ret;
1785
1786         ret = switch_context(request);
1787         if (ret)
1788                 return ret;
1789
1790         request->reserved_space -= LEGACY_REQUEST_SIZE;
1791         return 0;
1792 }
1793
1794 static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes)
1795 {
1796         struct i915_request *target;
1797         long timeout;
1798
1799         lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex);
1800
1801         if (intel_ring_update_space(ring) >= bytes)
1802                 return 0;
1803
1804         GEM_BUG_ON(list_empty(&ring->request_list));
1805         list_for_each_entry(target, &ring->request_list, ring_link) {
1806                 /* Would completion of this request free enough space? */
1807                 if (bytes <= __intel_ring_space(target->postfix,
1808                                                 ring->emit, ring->size))
1809                         break;
1810         }
1811
1812         if (WARN_ON(&target->ring_link == &ring->request_list))
1813                 return -ENOSPC;
1814
1815         timeout = i915_request_wait(target,
1816                                     I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
1817                                     MAX_SCHEDULE_TIMEOUT);
1818         if (timeout < 0)
1819                 return timeout;
1820
1821         i915_request_retire_upto(target);
1822
1823         intel_ring_update_space(ring);
1824         GEM_BUG_ON(ring->space < bytes);
1825         return 0;
1826 }
1827
1828 int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes)
1829 {
1830         GEM_BUG_ON(bytes > ring->effective_size);
1831         if (unlikely(bytes > ring->effective_size - ring->emit))
1832                 bytes += ring->size - ring->emit;
1833
1834         if (unlikely(bytes > ring->space)) {
1835                 int ret = wait_for_space(ring, bytes);
1836                 if (unlikely(ret))
1837                         return ret;
1838         }
1839
1840         GEM_BUG_ON(ring->space < bytes);
1841         return 0;
1842 }
1843
1844 u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)
1845 {
1846         struct intel_ring *ring = rq->ring;
1847         const unsigned int remain_usable = ring->effective_size - ring->emit;
1848         const unsigned int bytes = num_dwords * sizeof(u32);
1849         unsigned int need_wrap = 0;
1850         unsigned int total_bytes;
1851         u32 *cs;
1852
1853         /* Packets must be qword aligned. */
1854         GEM_BUG_ON(num_dwords & 1);
1855
1856         total_bytes = bytes + rq->reserved_space;
1857         GEM_BUG_ON(total_bytes > ring->effective_size);
1858
1859         if (unlikely(total_bytes > remain_usable)) {
1860                 const int remain_actual = ring->size - ring->emit;
1861
1862                 if (bytes > remain_usable) {
1863                         /*
1864                          * Not enough space for the basic request. So need to
1865                          * flush out the remainder and then wait for
1866                          * base + reserved.
1867                          */
1868                         total_bytes += remain_actual;
1869                         need_wrap = remain_actual | 1;
1870                 } else  {
1871                         /*
1872                          * The base request will fit but the reserved space
1873                          * falls off the end. So we don't need an immediate
1874                          * wrap and only need to effectively wait for the
1875                          * reserved size from the start of ringbuffer.
1876                          */
1877                         total_bytes = rq->reserved_space + remain_actual;
1878                 }
1879         }
1880
1881         if (unlikely(total_bytes > ring->space)) {
1882                 int ret;
1883
1884                 /*
1885                  * Space is reserved in the ringbuffer for finalising the
1886                  * request, as that cannot be allowed to fail. During request
1887                  * finalisation, reserved_space is set to 0 to stop the
1888                  * overallocation and the assumption is that then we never need
1889                  * to wait (which has the risk of failing with EINTR).
1890                  *
1891                  * See also i915_request_alloc() and i915_request_add().
1892                  */
1893                 GEM_BUG_ON(!rq->reserved_space);
1894
1895                 ret = wait_for_space(ring, total_bytes);
1896                 if (unlikely(ret))
1897                         return ERR_PTR(ret);
1898         }
1899
1900         if (unlikely(need_wrap)) {
1901                 need_wrap &= ~1;
1902                 GEM_BUG_ON(need_wrap > ring->space);
1903                 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
1904                 GEM_BUG_ON(!IS_ALIGNED(need_wrap, sizeof(u64)));
1905
1906                 /* Fill the tail with MI_NOOP */
1907                 memset64(ring->vaddr + ring->emit, 0, need_wrap / sizeof(u64));
1908                 ring->space -= need_wrap;
1909                 ring->emit = 0;
1910         }
1911
1912         GEM_BUG_ON(ring->emit > ring->size - bytes);
1913         GEM_BUG_ON(ring->space < bytes);
1914         cs = ring->vaddr + ring->emit;
1915         GEM_DEBUG_EXEC(memset32(cs, POISON_INUSE, bytes / sizeof(*cs)));
1916         ring->emit += bytes;
1917         ring->space -= bytes;
1918
1919         return cs;
1920 }
1921
1922 /* Align the ring tail to a cacheline boundary */
1923 int intel_ring_cacheline_align(struct i915_request *rq)
1924 {
1925         int num_dwords;
1926         void *cs;
1927
1928         num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);
1929         if (num_dwords == 0)
1930                 return 0;
1931
1932         num_dwords = CACHELINE_DWORDS - num_dwords;
1933         GEM_BUG_ON(num_dwords & 1);
1934
1935         cs = intel_ring_begin(rq, num_dwords);
1936         if (IS_ERR(cs))
1937                 return PTR_ERR(cs);
1938
1939         memset64(cs, (u64)MI_NOOP << 32 | MI_NOOP, num_dwords / 2);
1940         intel_ring_advance(rq, cs);
1941
1942         GEM_BUG_ON(rq->ring->emit & (CACHELINE_BYTES - 1));
1943         return 0;
1944 }
1945
1946 static void gen6_bsd_submit_request(struct i915_request *request)
1947 {
1948         struct drm_i915_private *dev_priv = request->i915;
1949
1950         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1951
1952        /* Every tail move must follow the sequence below */
1953
1954         /* Disable notification that the ring is IDLE. The GT
1955          * will then assume that it is busy and bring it out of rc6.
1956          */
1957         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1958                       _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1959
1960         /* Clear the context id. Here be magic! */
1961         I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
1962
1963         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1964         if (__intel_wait_for_register_fw(dev_priv,
1965                                          GEN6_BSD_SLEEP_PSMI_CONTROL,
1966                                          GEN6_BSD_SLEEP_INDICATOR,
1967                                          0,
1968                                          1000, 0, NULL))
1969                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1970
1971         /* Now that the ring is fully powered up, update the tail */
1972         i9xx_submit_request(request);
1973
1974         /* Let the ring send IDLE messages to the GT again,
1975          * and so let it sleep to conserve power when idle.
1976          */
1977         I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1978                       _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1979
1980         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1981 }
1982
1983 static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
1984 {
1985         u32 cmd, *cs;
1986
1987         cs = intel_ring_begin(rq, 4);
1988         if (IS_ERR(cs))
1989                 return PTR_ERR(cs);
1990
1991         cmd = MI_FLUSH_DW;
1992
1993         /* We always require a command barrier so that subsequent
1994          * commands, such as breadcrumb interrupts, are strictly ordered
1995          * wrt the contents of the write cache being flushed to memory
1996          * (and thus being coherent from the CPU).
1997          */
1998         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1999
2000         /*
2001          * Bspec vol 1c.5 - video engine command streamer:
2002          * "If ENABLED, all TLBs will be invalidated once the flush
2003          * operation is complete. This bit is only valid when the
2004          * Post-Sync Operation field is a value of 1h or 3h."
2005          */
2006         if (mode & EMIT_INVALIDATE)
2007                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
2008
2009         *cs++ = cmd;
2010         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2011         *cs++ = 0;
2012         *cs++ = MI_NOOP;
2013         intel_ring_advance(rq, cs);
2014         return 0;
2015 }
2016
2017 static int
2018 hsw_emit_bb_start(struct i915_request *rq,
2019                   u64 offset, u32 len,
2020                   unsigned int dispatch_flags)
2021 {
2022         u32 *cs;
2023
2024         cs = intel_ring_begin(rq, 2);
2025         if (IS_ERR(cs))
2026                 return PTR_ERR(cs);
2027
2028         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
2029                 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
2030                 (dispatch_flags & I915_DISPATCH_RS ?
2031                 MI_BATCH_RESOURCE_STREAMER : 0);
2032         /* bit0-7 is the length on GEN6+ */
2033         *cs++ = offset;
2034         intel_ring_advance(rq, cs);
2035
2036         return 0;
2037 }
2038
2039 static int
2040 gen6_emit_bb_start(struct i915_request *rq,
2041                    u64 offset, u32 len,
2042                    unsigned int dispatch_flags)
2043 {
2044         u32 *cs;
2045
2046         cs = intel_ring_begin(rq, 2);
2047         if (IS_ERR(cs))
2048                 return PTR_ERR(cs);
2049
2050         *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
2051                 0 : MI_BATCH_NON_SECURE_I965);
2052         /* bit0-7 is the length on GEN6+ */
2053         *cs++ = offset;
2054         intel_ring_advance(rq, cs);
2055
2056         return 0;
2057 }
2058
2059 /* Blitter support (SandyBridge+) */
2060
2061 static int gen6_ring_flush(struct i915_request *rq, u32 mode)
2062 {
2063         u32 cmd, *cs;
2064
2065         cs = intel_ring_begin(rq, 4);
2066         if (IS_ERR(cs))
2067                 return PTR_ERR(cs);
2068
2069         cmd = MI_FLUSH_DW;
2070
2071         /* We always require a command barrier so that subsequent
2072          * commands, such as breadcrumb interrupts, are strictly ordered
2073          * wrt the contents of the write cache being flushed to memory
2074          * (and thus being coherent from the CPU).
2075          */
2076         cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2077
2078         /*
2079          * Bspec vol 1c.3 - blitter engine command streamer:
2080          * "If ENABLED, all TLBs will be invalidated once the flush
2081          * operation is complete. This bit is only valid when the
2082          * Post-Sync Operation field is a value of 1h or 3h."
2083          */
2084         if (mode & EMIT_INVALIDATE)
2085                 cmd |= MI_INVALIDATE_TLB;
2086         *cs++ = cmd;
2087         *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2088         *cs++ = 0;
2089         *cs++ = MI_NOOP;
2090         intel_ring_advance(rq, cs);
2091
2092         return 0;
2093 }
2094
2095 static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
2096                                        struct intel_engine_cs *engine)
2097 {
2098         int i;
2099
2100         if (!HAS_LEGACY_SEMAPHORES(dev_priv))
2101                 return;
2102
2103         GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
2104         engine->semaphore.sync_to = gen6_ring_sync_to;
2105         engine->semaphore.signal = gen6_signal;
2106
2107         /*
2108          * The current semaphore is only applied on pre-gen8
2109          * platform.  And there is no VCS2 ring on the pre-gen8
2110          * platform. So the semaphore between RCS and VCS2 is
2111          * initialized as INVALID.
2112          */
2113         for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
2114                 static const struct {
2115                         u32 wait_mbox;
2116                         i915_reg_t mbox_reg;
2117                 } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
2118                         [RCS_HW] = {
2119                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RV,  .mbox_reg = GEN6_VRSYNC },
2120                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_RB,  .mbox_reg = GEN6_BRSYNC },
2121                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
2122                         },
2123                         [VCS_HW] = {
2124                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VR,  .mbox_reg = GEN6_RVSYNC },
2125                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VB,  .mbox_reg = GEN6_BVSYNC },
2126                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
2127                         },
2128                         [BCS_HW] = {
2129                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BR,  .mbox_reg = GEN6_RBSYNC },
2130                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_BV,  .mbox_reg = GEN6_VBSYNC },
2131                                 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
2132                         },
2133                         [VECS_HW] = {
2134                                 [RCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
2135                                 [VCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
2136                                 [BCS_HW] =  { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
2137                         },
2138                 };
2139                 u32 wait_mbox;
2140                 i915_reg_t mbox_reg;
2141
2142                 if (i == engine->hw_id) {
2143                         wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
2144                         mbox_reg = GEN6_NOSYNC;
2145                 } else {
2146                         wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
2147                         mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
2148                 }
2149
2150                 engine->semaphore.mbox.wait[i] = wait_mbox;
2151                 engine->semaphore.mbox.signal[i] = mbox_reg;
2152         }
2153 }
2154
2155 static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
2156                                 struct intel_engine_cs *engine)
2157 {
2158         if (INTEL_GEN(dev_priv) >= 6) {
2159                 engine->irq_enable = gen6_irq_enable;
2160                 engine->irq_disable = gen6_irq_disable;
2161                 engine->irq_seqno_barrier = gen6_seqno_barrier;
2162         } else if (INTEL_GEN(dev_priv) >= 5) {
2163                 engine->irq_enable = gen5_irq_enable;
2164                 engine->irq_disable = gen5_irq_disable;
2165                 engine->irq_seqno_barrier = gen5_seqno_barrier;
2166         } else if (INTEL_GEN(dev_priv) >= 3) {
2167                 engine->irq_enable = i9xx_irq_enable;
2168                 engine->irq_disable = i9xx_irq_disable;
2169         } else {
2170                 engine->irq_enable = i8xx_irq_enable;
2171                 engine->irq_disable = i8xx_irq_disable;
2172         }
2173 }
2174
2175 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
2176 {
2177         engine->submit_request = i9xx_submit_request;
2178         engine->cancel_requests = cancel_requests;
2179
2180         engine->park = NULL;
2181         engine->unpark = NULL;
2182 }
2183
2184 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
2185 {
2186         i9xx_set_default_submission(engine);
2187         engine->submit_request = gen6_bsd_submit_request;
2188 }
2189
2190 static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
2191                                       struct intel_engine_cs *engine)
2192 {
2193         /* gen8+ are only supported with execlists */
2194         GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
2195
2196         intel_ring_init_irq(dev_priv, engine);
2197         intel_ring_init_semaphores(dev_priv, engine);
2198
2199         engine->init_hw = init_ring_common;
2200         engine->reset.prepare = reset_prepare;
2201         engine->reset.reset = reset_ring;
2202         engine->reset.finish = reset_finish;
2203
2204         engine->context_pin = intel_ring_context_pin;
2205         engine->request_alloc = ring_request_alloc;
2206
2207         engine->emit_breadcrumb = i9xx_emit_breadcrumb;
2208         engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
2209         if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
2210                 int num_rings;
2211
2212                 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
2213
2214                 num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
2215                 engine->emit_breadcrumb_sz += num_rings * 3;
2216                 if (num_rings & 1)
2217                         engine->emit_breadcrumb_sz++;
2218         }
2219
2220         engine->set_default_submission = i9xx_set_default_submission;
2221
2222         if (INTEL_GEN(dev_priv) >= 6)
2223                 engine->emit_bb_start = gen6_emit_bb_start;
2224         else if (INTEL_GEN(dev_priv) >= 4)
2225                 engine->emit_bb_start = i965_emit_bb_start;
2226         else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
2227                 engine->emit_bb_start = i830_emit_bb_start;
2228         else
2229                 engine->emit_bb_start = i915_emit_bb_start;
2230 }
2231
2232 int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2233 {
2234         struct drm_i915_private *dev_priv = engine->i915;
2235         int ret;
2236
2237         intel_ring_default_vfuncs(dev_priv, engine);
2238
2239         if (HAS_L3_DPF(dev_priv))
2240                 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2241
2242         engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
2243
2244         if (INTEL_GEN(dev_priv) >= 6) {
2245                 engine->init_context = intel_rcs_ctx_init;
2246                 engine->emit_flush = gen7_render_ring_flush;
2247                 if (IS_GEN6(dev_priv))
2248                         engine->emit_flush = gen6_render_ring_flush;
2249         } else if (IS_GEN5(dev_priv)) {
2250                 engine->emit_flush = gen4_render_ring_flush;
2251         } else {
2252                 if (INTEL_GEN(dev_priv) < 4)
2253                         engine->emit_flush = gen2_render_ring_flush;
2254                 else
2255                         engine->emit_flush = gen4_render_ring_flush;
2256                 engine->irq_enable_mask = I915_USER_INTERRUPT;
2257         }
2258
2259         if (IS_HASWELL(dev_priv))
2260                 engine->emit_bb_start = hsw_emit_bb_start;
2261
2262         engine->init_hw = init_render_ring;
2263
2264         ret = intel_init_ring_buffer(engine);
2265         if (ret)
2266                 return ret;
2267
2268         return 0;
2269 }
2270
2271 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2272 {
2273         struct drm_i915_private *dev_priv = engine->i915;
2274
2275         intel_ring_default_vfuncs(dev_priv, engine);
2276
2277         if (INTEL_GEN(dev_priv) >= 6) {
2278                 /* gen6 bsd needs a special wa for tail updates */
2279                 if (IS_GEN6(dev_priv))
2280                         engine->set_default_submission = gen6_bsd_set_default_submission;
2281                 engine->emit_flush = gen6_bsd_ring_flush;
2282                 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2283         } else {
2284                 engine->emit_flush = bsd_ring_flush;
2285                 if (IS_GEN5(dev_priv))
2286                         engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2287                 else
2288                         engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2289         }
2290
2291         return intel_init_ring_buffer(engine);
2292 }
2293
2294 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2295 {
2296         struct drm_i915_private *dev_priv = engine->i915;
2297
2298         intel_ring_default_vfuncs(dev_priv, engine);
2299
2300         engine->emit_flush = gen6_ring_flush;
2301         engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2302
2303         return intel_init_ring_buffer(engine);
2304 }
2305
2306 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2307 {
2308         struct drm_i915_private *dev_priv = engine->i915;
2309
2310         intel_ring_default_vfuncs(dev_priv, engine);
2311
2312         engine->emit_flush = gen6_ring_flush;
2313         engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2314         engine->irq_enable = hsw_vebox_irq_enable;
2315         engine->irq_disable = hsw_vebox_irq_disable;
2316
2317         return intel_init_ring_buffer(engine);
2318 }