drivers/gpu/drm/i915/intel_pipe_crc.c

   1 /*
   2  * Copyright © 2013 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Author: Damien Lespiau <damien.lespiau@intel.com>
  24  *
  25  */
  26
  27 #include <linux/seq_file.h>
  28 #include <linux/circ_buf.h>
  29 #include <linux/ctype.h>
  30 #include <linux/debugfs.h>
  31 #include "intel_drv.h"
  32
  33 static const char * const pipe_crc_sources[] = {
  34         "none",
  35         "plane1",
  36         "plane2",
  37         "pf",
  38         "pipe",
  39         "TV",
  40         "DP-B",
  41         "DP-C",
  42         "DP-D",
  43         "auto",
  44 };
  45
  46 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
  47                                  uint32_t *val)
  48 {
  49         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
  50                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
  51
  52         switch (*source) {
  53         case INTEL_PIPE_CRC_SOURCE_PIPE:
  54                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
  55                 break;
  56         case INTEL_PIPE_CRC_SOURCE_NONE:
  57                 *val = 0;
  58                 break;
  59         default:
  60                 return -EINVAL;
  61         }
  62
  63         return 0;
  64 }
  65
  66 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
  67                                      enum pipe pipe,
  68                                      enum intel_pipe_crc_source *source)
  69 {
  70         struct drm_device *dev = &dev_priv->drm;
  71         struct intel_encoder *encoder;
  72         struct intel_crtc *crtc;
  73         struct intel_digital_port *dig_port;
  74         int ret = 0;
  75
  76         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
  77
  78         drm_modeset_lock_all(dev);
  79         for_each_intel_encoder(dev, encoder) {
  80                 if (!encoder->base.crtc)
  81                         continue;
  82
  83                 crtc = to_intel_crtc(encoder->base.crtc);
  84
  85                 if (crtc->pipe != pipe)
  86                         continue;
  87
  88                 switch (encoder->type) {
  89                 case INTEL_OUTPUT_TVOUT:
  90                         *source = INTEL_PIPE_CRC_SOURCE_TV;
  91                         break;
  92                 case INTEL_OUTPUT_DP:
  93                 case INTEL_OUTPUT_EDP:
  94                         dig_port = enc_to_dig_port(&encoder->base);
  95                         switch (dig_port->base.port) {
  96                         case PORT_B:
  97                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
  98                                 break;
  99                         case PORT_C:
 100                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
 101                                 break;
 102                         case PORT_D:
 103                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
 104                                 break;
 105                         default:
 106                                 WARN(1, "nonexisting DP port %c\n",
 107                                      port_name(dig_port->base.port));
 108                                 break;
 109                         }
 110                         break;
 111                 default:
 112                         break;
 113                 }
 114         }
 115         drm_modeset_unlock_all(dev);
 116
 117         return ret;
 118 }
 119
 120 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 121                                 enum pipe pipe,
 122                                 enum intel_pipe_crc_source *source,
 123                                 uint32_t *val)
 124 {
 125         bool need_stable_symbols = false;
 126
 127         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
 128                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
 129                 if (ret)
 130                         return ret;
 131         }
 132
 133         switch (*source) {
 134         case INTEL_PIPE_CRC_SOURCE_PIPE:
 135                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
 136                 break;
 137         case INTEL_PIPE_CRC_SOURCE_DP_B:
 138                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
 139                 need_stable_symbols = true;
 140                 break;
 141         case INTEL_PIPE_CRC_SOURCE_DP_C:
 142                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
 143                 need_stable_symbols = true;
 144                 break;
 145         case INTEL_PIPE_CRC_SOURCE_DP_D:
 146                 if (!IS_CHERRYVIEW(dev_priv))
 147                         return -EINVAL;
 148                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
 149                 need_stable_symbols = true;
 150                 break;
 151         case INTEL_PIPE_CRC_SOURCE_NONE:
 152                 *val = 0;
 153                 break;
 154         default:
 155                 return -EINVAL;
 156         }
 157
 158         /*
 159          * When the pipe CRC tap point is after the transcoders we need
 160          * to tweak symbol-level features to produce a deterministic series of
 161          * symbols for a given frame. We need to reset those features only once
 162          * a frame (instead of every nth symbol):
 163          *   - DC-balance: used to ensure a better clock recovery from the data
 164          *     link (SDVO)
 165          *   - DisplayPort scrambling: used for EMI reduction
 166          */
 167         if (need_stable_symbols) {
 168                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 169
 170                 tmp |= DC_BALANCE_RESET_VLV;
 171                 switch (pipe) {
 172                 case PIPE_A:
 173                         tmp |= PIPE_A_SCRAMBLE_RESET;
 174                         break;
 175                 case PIPE_B:
 176                         tmp |= PIPE_B_SCRAMBLE_RESET;
 177                         break;
 178                 case PIPE_C:
 179                         tmp |= PIPE_C_SCRAMBLE_RESET;
 180                         break;
 181                 default:
 182                         return -EINVAL;
 183                 }
 184                 I915_WRITE(PORT_DFT2_G4X, tmp);
 185         }
 186
 187         return 0;
 188 }
 189
 190 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 191                                  enum pipe pipe,
 192                                  enum intel_pipe_crc_source *source,
 193                                  uint32_t *val)
 194 {
 195         bool need_stable_symbols = false;
 196
 197         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
 198                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
 199                 if (ret)
 200                         return ret;
 201         }
 202
 203         switch (*source) {
 204         case INTEL_PIPE_CRC_SOURCE_PIPE:
 205                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
 206                 break;
 207         case INTEL_PIPE_CRC_SOURCE_TV:
 208                 if (!SUPPORTS_TV(dev_priv))
 209                         return -EINVAL;
 210                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
 211                 break;
 212         case INTEL_PIPE_CRC_SOURCE_DP_B:
 213                 if (!IS_G4X(dev_priv))
 214                         return -EINVAL;
 215                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
 216                 need_stable_symbols = true;
 217                 break;
 218         case INTEL_PIPE_CRC_SOURCE_DP_C:
 219                 if (!IS_G4X(dev_priv))
 220                         return -EINVAL;
 221                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
 222                 need_stable_symbols = true;
 223                 break;
 224         case INTEL_PIPE_CRC_SOURCE_DP_D:
 225                 if (!IS_G4X(dev_priv))
 226                         return -EINVAL;
 227                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
 228                 need_stable_symbols = true;
 229                 break;
 230         case INTEL_PIPE_CRC_SOURCE_NONE:
 231                 *val = 0;
 232                 break;
 233         default:
 234                 return -EINVAL;
 235         }
 236
 237         /*
 238          * When the pipe CRC tap point is after the transcoders we need
 239          * to tweak symbol-level features to produce a deterministic series of
 240          * symbols for a given frame. We need to reset those features only once
 241          * a frame (instead of every nth symbol):
 242          *   - DC-balance: used to ensure a better clock recovery from the data
 243          *     link (SDVO)
 244          *   - DisplayPort scrambling: used for EMI reduction
 245          */
 246         if (need_stable_symbols) {
 247                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 248
 249                 WARN_ON(!IS_G4X(dev_priv));
 250
 251                 I915_WRITE(PORT_DFT_I9XX,
 252                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
 253
 254                 if (pipe == PIPE_A)
 255                         tmp |= PIPE_A_SCRAMBLE_RESET;
 256                 else
 257                         tmp |= PIPE_B_SCRAMBLE_RESET;
 258
 259                 I915_WRITE(PORT_DFT2_G4X, tmp);
 260         }
 261
 262         return 0;
 263 }
 264
 265 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
 266                                          enum pipe pipe)
 267 {
 268         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 269
 270         switch (pipe) {
 271         case PIPE_A:
 272                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
 273                 break;
 274         case PIPE_B:
 275                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
 276                 break;
 277         case PIPE_C:
 278                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
 279                 break;
 280         default:
 281                 return;
 282         }
 283         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
 284                 tmp &= ~DC_BALANCE_RESET_VLV;
 285         I915_WRITE(PORT_DFT2_G4X, tmp);
 286
 287 }
 288
 289 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
 290                                          enum pipe pipe)
 291 {
 292         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
 293
 294         if (pipe == PIPE_A)
 295                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
 296         else
 297                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
 298         I915_WRITE(PORT_DFT2_G4X, tmp);
 299
 300         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
 301                 I915_WRITE(PORT_DFT_I9XX,
 302                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
 303         }
 304 }
 305
 306 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
 307                                 uint32_t *val)
 308 {
 309         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
 310                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
 311
 312         switch (*source) {
 313         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 314                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
 315                 break;
 316         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 317                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
 318                 break;
 319         case INTEL_PIPE_CRC_SOURCE_PIPE:
 320                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
 321                 break;
 322         case INTEL_PIPE_CRC_SOURCE_NONE:
 323                 *val = 0;
 324                 break;
 325         default:
 326                 return -EINVAL;
 327         }
 328
 329         return 0;
 330 }
 331
 332 static void hsw_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
 333                               bool enable)
 334 {
 335         struct drm_device *dev = &dev_priv->drm;
 336         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
 337         struct intel_crtc_state *pipe_config;
 338         struct drm_atomic_state *state;
 339         struct drm_modeset_acquire_ctx ctx;
 340         int ret = 0;
 341
 342         drm_modeset_acquire_init(&ctx, 0);
 343
 344         state = drm_atomic_state_alloc(dev);
 345         if (!state) {
 346                 ret = -ENOMEM;
 347                 goto unlock;
 348         }
 349
 350         state->acquire_ctx = &ctx;
 351
 352 retry:
 353         pipe_config = intel_atomic_get_crtc_state(state, crtc);
 354         if (IS_ERR(pipe_config)) {
 355                 ret = PTR_ERR(pipe_config);
 356                 goto put_state;
 357         }
 358
 359         if (HAS_IPS(dev_priv)) {
 360                 /*
 361                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
 362                  * enabled and disabled dynamically based on package C states,
 363                  * user space can't make reliable use of the CRCs, so let's just
 364                  * completely disable it.
 365                  */
 366                 pipe_config->ips_force_disable = enable;
 367         }
 368
 369         if (IS_HASWELL(dev_priv)) {
 370                 pipe_config->pch_pfit.force_thru = enable;
 371                 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
 372                     pipe_config->pch_pfit.enabled != enable)
 373                         pipe_config->base.connectors_changed = true;
 374         }
 375
 376         ret = drm_atomic_commit(state);
 377
 378 put_state:
 379         if (ret == -EDEADLK) {
 380                 drm_atomic_state_clear(state);
 381                 drm_modeset_backoff(&ctx);
 382                 goto retry;
 383         }
 384
 385         drm_atomic_state_put(state);
 386 unlock:
 387         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
 388         drm_modeset_drop_locks(&ctx);
 389         drm_modeset_acquire_fini(&ctx);
 390 }
 391
 392 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 393                                 enum pipe pipe,
 394                                 enum intel_pipe_crc_source *source,
 395                                 uint32_t *val,
 396                                 bool set_wa)
 397 {
 398         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
 399                 *source = INTEL_PIPE_CRC_SOURCE_PF;
 400
 401         switch (*source) {
 402         case INTEL_PIPE_CRC_SOURCE_PLANE1:
 403                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
 404                 break;
 405         case INTEL_PIPE_CRC_SOURCE_PLANE2:
 406                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
 407                 break;
 408         case INTEL_PIPE_CRC_SOURCE_PF:
 409                 if (set_wa && (IS_HASWELL(dev_priv) ||
 410                      IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
 411                         hsw_pipe_A_crc_wa(dev_priv, true);
 412
 413                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
 414                 break;
 415         case INTEL_PIPE_CRC_SOURCE_NONE:
 416                 *val = 0;
 417                 break;
 418         default:
 419                 return -EINVAL;
 420         }
 421
 422         return 0;
 423 }
 424
 425 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
 426                                enum pipe pipe,
 427                                enum intel_pipe_crc_source *source, u32 *val,
 428                                bool set_wa)
 429 {
 430         if (IS_GEN2(dev_priv))
 431                 return i8xx_pipe_crc_ctl_reg(source, val);
 432         else if (INTEL_GEN(dev_priv) < 5)
 433                 return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 434         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 435                 return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
 436         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
 437                 return ilk_pipe_crc_ctl_reg(source, val);
 438         else
 439                 return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
 440 }
 441
 442 static int
 443 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
 444 {
 445         int i;
 446
 447         if (!buf) {
 448                 *s = INTEL_PIPE_CRC_SOURCE_NONE;
 449                 return 0;
 450         }
 451
 452         i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
 453         if (i < 0)
 454                 return i;
 455
 456         *s = i;
 457         return 0;
 458 }
 459
 460 void intel_display_crc_init(struct drm_i915_private *dev_priv)
 461 {
 462         enum pipe pipe;
 463
 464         for_each_pipe(dev_priv, pipe) {
 465                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
 466
 467                 spin_lock_init(&pipe_crc->lock);
 468         }
 469 }
 470
 471 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
 472                               size_t *values_cnt)
 473 {
 474         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 475         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
 476         enum intel_display_power_domain power_domain;
 477         enum intel_pipe_crc_source source;
 478         u32 val = 0; /* shut up gcc */
 479         int ret = 0;
 480
 481         if (display_crc_ctl_parse_source(source_name, &source) < 0) {
 482                 DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
 483                 return -EINVAL;
 484         }
 485
 486         power_domain = POWER_DOMAIN_PIPE(crtc->index);
 487         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
 488                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
 489                 return -EIO;
 490         }
 491
 492         ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val, true);
 493         if (ret != 0)
 494                 goto out;
 495
 496         pipe_crc->source = source;
 497         I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
 498         POSTING_READ(PIPE_CRC_CTL(crtc->index));
 499
 500         if (!source) {
 501                 if (IS_G4X(dev_priv))
 502                         g4x_undo_pipe_scramble_reset(dev_priv, crtc->index);
 503                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 504                         vlv_undo_pipe_scramble_reset(dev_priv, crtc->index);
 505                 else if ((IS_HASWELL(dev_priv) ||
 506                           IS_BROADWELL(dev_priv)) && crtc->index == PIPE_A)
 507                         hsw_pipe_A_crc_wa(dev_priv, false);
 508         }
 509
 510         pipe_crc->skipped = 0;
 511         *values_cnt = 5;
 512
 513 out:
 514         intel_display_power_put(dev_priv, power_domain);
 515
 516         return ret;
 517 }
 518
 519 void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
 520 {
 521         struct drm_crtc *crtc = &intel_crtc->base;
 522         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 523         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
 524         u32 val = 0;
 525
 526         if (!crtc->crc.opened)
 527                 return;
 528
 529         if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val, false) < 0)
 530                 return;
 531
 532         /* Don't need pipe_crc->lock here, IRQs are not generated. */
 533         pipe_crc->skipped = 0;
 534
 535         I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
 536         POSTING_READ(PIPE_CRC_CTL(crtc->index));
 537 }
 538
 539 void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
 540 {
 541         struct drm_crtc *crtc = &intel_crtc->base;
 542         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 543         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
 544
 545         /* Swallow crc's until we stop generating them. */
 546         spin_lock_irq(&pipe_crc->lock);
 547         pipe_crc->skipped = INT_MIN;
 548         spin_unlock_irq(&pipe_crc->lock);
 549
 550         I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
 551         POSTING_READ(PIPE_CRC_CTL(crtc->index));
 552         synchronize_irq(dev_priv->drm.irq);
 553 }