drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_reg.h"
  32 #include "intel_drv.h"
  33 #include "intel_frontbuffer.h"
  34
  35 /* Limits for overlay size. According to intel doc, the real limits are:
  36  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  37  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  38  * the mininum of both.  */
  39 #define IMAGE_MAX_WIDTH         2048
  40 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  41 /* on 830 and 845 these large limits result in the card hanging */
  42 #define IMAGE_MAX_WIDTH_LEGACY  1024
  43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  44
  45 /* overlay register definitions */
  46 /* OCMD register */
  47 #define OCMD_TILED_SURFACE      (0x1<<19)
  48 #define OCMD_MIRROR_MASK        (0x3<<17)
  49 #define OCMD_MIRROR_MODE        (0x3<<17)
  50 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  51 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  52 #define OCMD_MIRROR_BOTH        (0x3<<17)
  53 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  54 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  55 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  56 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  58 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  60 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  61 #define OCMD_YUV_422_PACKED     (0x8<<10)
  62 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  63 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  64 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  65 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  66 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  67 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  68 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  69 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  70 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  71 #define OCMD_TEST_MODE          (0x1<<4)
  72 #define OCMD_BUFFER_SELECT      (0x3<<2)
  73 #define OCMD_BUFFER0            (0x0<<2)
  74 #define OCMD_BUFFER1            (0x1<<2)
  75 #define OCMD_FIELD_SELECT       (0x1<<2)
  76 #define OCMD_FIELD0             (0x0<<1)
  77 #define OCMD_FIELD1             (0x1<<1)
  78 #define OCMD_ENABLE             (0x1<<0)
  79
  80 /* OCONFIG register */
  81 #define OCONF_PIPE_MASK         (0x1<<18)
  82 #define OCONF_PIPE_A            (0x0<<18)
  83 #define OCONF_PIPE_B            (0x1<<18)
  84 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  85 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  86 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  87 #define OCONF_CSC_BYPASS        (0x1<<4)
  88 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  89 #define OCONF_TEST_MODE         (0x1<<2)
  90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  91 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  92
  93 /* DCLRKM (dst-key) register */
  94 #define DST_KEY_ENABLE          (0x1<<31)
  95 #define CLK_RGB24_MASK          0x0
  96 #define CLK_RGB16_MASK          0x070307
  97 #define CLK_RGB15_MASK          0x070707
  98 #define CLK_RGB8I_MASK          0xffffff
  99
 100 #define RGB16_TO_COLORKEY(c) \
 101         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 102 #define RGB15_TO_COLORKEY(c) \
 103         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 104
 105 /* overlay flip addr flag */
 106 #define OFC_UPDATE              0x1
 107
 108 /* polyphase filter coefficients */
 109 #define N_HORIZ_Y_TAPS          5
 110 #define N_VERT_Y_TAPS           3
 111 #define N_HORIZ_UV_TAPS         3
 112 #define N_VERT_UV_TAPS          3
 113 #define N_PHASES                17
 114 #define MAX_TAPS                5
 115
 116 /* memory bufferd overlay registers */
 117 struct overlay_registers {
 118         u32 OBUF_0Y;
 119         u32 OBUF_1Y;
 120         u32 OBUF_0U;
 121         u32 OBUF_0V;
 122         u32 OBUF_1U;
 123         u32 OBUF_1V;
 124         u32 OSTRIDE;
 125         u32 YRGB_VPH;
 126         u32 UV_VPH;
 127         u32 HORZ_PH;
 128         u32 INIT_PHS;
 129         u32 DWINPOS;
 130         u32 DWINSZ;
 131         u32 SWIDTH;
 132         u32 SWIDTHSW;
 133         u32 SHEIGHT;
 134         u32 YRGBSCALE;
 135         u32 UVSCALE;
 136         u32 OCLRC0;
 137         u32 OCLRC1;
 138         u32 DCLRKV;
 139         u32 DCLRKM;
 140         u32 SCLRKVH;
 141         u32 SCLRKVL;
 142         u32 SCLRKEN;
 143         u32 OCONFIG;
 144         u32 OCMD;
 145         u32 RESERVED1; /* 0x6C */
 146         u32 OSTART_0Y;
 147         u32 OSTART_1Y;
 148         u32 OSTART_0U;
 149         u32 OSTART_0V;
 150         u32 OSTART_1U;
 151         u32 OSTART_1V;
 152         u32 OTILEOFF_0Y;
 153         u32 OTILEOFF_1Y;
 154         u32 OTILEOFF_0U;
 155         u32 OTILEOFF_0V;
 156         u32 OTILEOFF_1U;
 157         u32 OTILEOFF_1V;
 158         u32 FASTHSCALE; /* 0xA0 */
 159         u32 UVSCALEV; /* 0xA4 */
 160         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 161         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 162         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 163         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 164         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 165         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 166         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 167         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 168         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 169 };
 170
 171 struct intel_overlay {
 172         struct drm_i915_private *i915;
 173         struct intel_crtc *crtc;
 174         struct i915_vma *vma;
 175         struct i915_vma *old_vma;
 176         bool active;
 177         bool pfit_active;
 178         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 179         u32 color_key:24;
 180         u32 color_key_enabled:1;
 181         u32 brightness, contrast, saturation;
 182         u32 old_xscale, old_yscale;
 183         /* register access */
 184         u32 flip_addr;
 185         struct drm_i915_gem_object *reg_bo;
 186         /* flip handling */
 187         struct i915_gem_active last_flip;
 188 };
 189
 190 static struct overlay_registers __iomem *
 191 intel_overlay_map_regs(struct intel_overlay *overlay)
 192 {
 193         struct drm_i915_private *dev_priv = overlay->i915;
 194         struct overlay_registers __iomem *regs;
 195
 196         if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
 197                 regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr;
 198         else
 199                 regs = io_mapping_map_wc(&dev_priv->ggtt.mappable,
 200                                          overlay->flip_addr,
 201                                          PAGE_SIZE);
 202
 203         return regs;
 204 }
 205
 206 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
 207                                      struct overlay_registers __iomem *regs)
 208 {
 209         if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
 210                 io_mapping_unmap(regs);
 211 }
 212
 213 static void intel_overlay_submit_request(struct intel_overlay *overlay,
 214                                          struct drm_i915_gem_request *req,
 215                                          i915_gem_retire_fn retire)
 216 {
 217         GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
 218                                         &overlay->i915->drm.struct_mutex));
 219         i915_gem_active_set_retire_fn(&overlay->last_flip, retire,
 220                                       &overlay->i915->drm.struct_mutex);
 221         i915_gem_active_set(&overlay->last_flip, req);
 222         i915_add_request(req);
 223 }
 224
 225 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 226                                          struct drm_i915_gem_request *req,
 227                                          i915_gem_retire_fn retire)
 228 {
 229         intel_overlay_submit_request(overlay, req, retire);
 230         return i915_gem_active_retire(&overlay->last_flip,
 231                                       &overlay->i915->drm.struct_mutex);
 232 }
 233
 234 static struct drm_i915_gem_request *alloc_request(struct intel_overlay *overlay)
 235 {
 236         struct drm_i915_private *dev_priv = overlay->i915;
 237         struct intel_engine_cs *engine = &dev_priv->engine[RCS];
 238
 239         return i915_gem_request_alloc(engine, dev_priv->kernel_context);
 240 }
 241
 242 /* overlay needs to be disable in OCMD reg */
 243 static int intel_overlay_on(struct intel_overlay *overlay)
 244 {
 245         struct drm_i915_private *dev_priv = overlay->i915;
 246         struct drm_i915_gem_request *req;
 247         struct intel_ring *ring;
 248         int ret;
 249
 250         WARN_ON(overlay->active);
 251         WARN_ON(IS_I830(dev_priv) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
 252
 253         req = alloc_request(overlay);
 254         if (IS_ERR(req))
 255                 return PTR_ERR(req);
 256
 257         ret = intel_ring_begin(req, 4);
 258         if (ret) {
 259                 i915_add_request_no_flush(req);
 260                 return ret;
 261         }
 262
 263         overlay->active = true;
 264
 265         ring = req->ring;
 266         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
 267         intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE);
 268         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 269         intel_ring_emit(ring, MI_NOOP);
 270         intel_ring_advance(ring);
 271
 272         return intel_overlay_do_wait_request(overlay, req, NULL);
 273 }
 274
 275 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
 276                                        struct i915_vma *vma)
 277 {
 278         enum pipe pipe = overlay->crtc->pipe;
 279
 280         WARN_ON(overlay->old_vma);
 281
 282         i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
 283                           vma ? vma->obj : NULL,
 284                           INTEL_FRONTBUFFER_OVERLAY(pipe));
 285
 286         intel_frontbuffer_flip_prepare(overlay->i915,
 287                                        INTEL_FRONTBUFFER_OVERLAY(pipe));
 288
 289         overlay->old_vma = overlay->vma;
 290         if (vma)
 291                 overlay->vma = i915_vma_get(vma);
 292         else
 293                 overlay->vma = NULL;
 294 }
 295
 296 /* overlay needs to be enabled in OCMD reg */
 297 static int intel_overlay_continue(struct intel_overlay *overlay,
 298                                   struct i915_vma *vma,
 299                                   bool load_polyphase_filter)
 300 {
 301         struct drm_i915_private *dev_priv = overlay->i915;
 302         struct drm_i915_gem_request *req;
 303         struct intel_ring *ring;
 304         u32 flip_addr = overlay->flip_addr;
 305         u32 tmp;
 306         int ret;
 307
 308         WARN_ON(!overlay->active);
 309
 310         if (load_polyphase_filter)
 311                 flip_addr |= OFC_UPDATE;
 312
 313         /* check for underruns */
 314         tmp = I915_READ(DOVSTA);
 315         if (tmp & (1 << 17))
 316                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 317
 318         req = alloc_request(overlay);
 319         if (IS_ERR(req))
 320                 return PTR_ERR(req);
 321
 322         ret = intel_ring_begin(req, 2);
 323         if (ret) {
 324                 i915_add_request_no_flush(req);
 325                 return ret;
 326         }
 327
 328         ring = req->ring;
 329         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 330         intel_ring_emit(ring, flip_addr);
 331         intel_ring_advance(ring);
 332
 333         intel_overlay_flip_prepare(overlay, vma);
 334
 335         intel_overlay_submit_request(overlay, req, NULL);
 336
 337         return 0;
 338 }
 339
 340 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
 341 {
 342         struct i915_vma *vma;
 343
 344         vma = fetch_and_zero(&overlay->old_vma);
 345         if (WARN_ON(!vma))
 346                 return;
 347
 348         intel_frontbuffer_flip_complete(overlay->i915,
 349                                         INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 350
 351         i915_gem_object_unpin_from_display_plane(vma);
 352         i915_vma_put(vma);
 353 }
 354
 355 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
 356                                                struct drm_i915_gem_request *req)
 357 {
 358         struct intel_overlay *overlay =
 359                 container_of(active, typeof(*overlay), last_flip);
 360
 361         intel_overlay_release_old_vma(overlay);
 362 }
 363
 364 static void intel_overlay_off_tail(struct i915_gem_active *active,
 365                                    struct drm_i915_gem_request *req)
 366 {
 367         struct intel_overlay *overlay =
 368                 container_of(active, typeof(*overlay), last_flip);
 369
 370         intel_overlay_release_old_vma(overlay);
 371
 372         overlay->crtc->overlay = NULL;
 373         overlay->crtc = NULL;
 374         overlay->active = false;
 375 }
 376
 377 /* overlay needs to be disabled in OCMD reg */
 378 static int intel_overlay_off(struct intel_overlay *overlay)
 379 {
 380         struct drm_i915_private *dev_priv = overlay->i915;
 381         struct drm_i915_gem_request *req;
 382         struct intel_ring *ring;
 383         u32 flip_addr = overlay->flip_addr;
 384         int ret;
 385
 386         WARN_ON(!overlay->active);
 387
 388         /* According to intel docs the overlay hw may hang (when switching
 389          * off) without loading the filter coeffs. It is however unclear whether
 390          * this applies to the disabling of the overlay or to the switching off
 391          * of the hw. Do it in both cases */
 392         flip_addr |= OFC_UPDATE;
 393
 394         req = alloc_request(overlay);
 395         if (IS_ERR(req))
 396                 return PTR_ERR(req);
 397
 398         ret = intel_ring_begin(req, 6);
 399         if (ret) {
 400                 i915_add_request_no_flush(req);
 401                 return ret;
 402         }
 403
 404         ring = req->ring;
 405         /* wait for overlay to go idle */
 406         intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
 407         intel_ring_emit(ring, flip_addr);
 408         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 409         /* turn overlay off */
 410         if (IS_I830(dev_priv)) {
 411                 /* Workaround: Don't disable the overlay fully, since otherwise
 412                  * it dies on the next OVERLAY_ON cmd. */
 413                 intel_ring_emit(ring, MI_NOOP);
 414                 intel_ring_emit(ring, MI_NOOP);
 415                 intel_ring_emit(ring, MI_NOOP);
 416         } else {
 417                 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
 418                 intel_ring_emit(ring, flip_addr);
 419                 intel_ring_emit(ring,
 420                                 MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 421         }
 422         intel_ring_advance(ring);
 423
 424         intel_overlay_flip_prepare(overlay, NULL);
 425
 426         return intel_overlay_do_wait_request(overlay, req,
 427                                              intel_overlay_off_tail);
 428 }
 429
 430 /* recover from an interruption due to a signal
 431  * We have to be careful not to repeat work forever an make forward progess. */
 432 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 433 {
 434         return i915_gem_active_retire(&overlay->last_flip,
 435                                       &overlay->i915->drm.struct_mutex);
 436 }
 437
 438 /* Wait for pending overlay flip and release old frame.
 439  * Needs to be called before the overlay register are changed
 440  * via intel_overlay_(un)map_regs
 441  */
 442 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 443 {
 444         struct drm_i915_private *dev_priv = overlay->i915;
 445         int ret;
 446
 447         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 448
 449         /* Only wait if there is actually an old frame to release to
 450          * guarantee forward progress.
 451          */
 452         if (!overlay->old_vma)
 453                 return 0;
 454
 455         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 456                 /* synchronous slowpath */
 457                 struct drm_i915_gem_request *req;
 458                 struct intel_ring *ring;
 459
 460                 req = alloc_request(overlay);
 461                 if (IS_ERR(req))
 462                         return PTR_ERR(req);
 463
 464                 ret = intel_ring_begin(req, 2);
 465                 if (ret) {
 466                         i915_add_request_no_flush(req);
 467                         return ret;
 468                 }
 469
 470                 ring = req->ring;
 471                 intel_ring_emit(ring,
 472                                 MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
 473                 intel_ring_emit(ring, MI_NOOP);
 474                 intel_ring_advance(ring);
 475
 476                 ret = intel_overlay_do_wait_request(overlay, req,
 477                                                     intel_overlay_release_old_vid_tail);
 478                 if (ret)
 479                         return ret;
 480         } else
 481                 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
 482
 483         return 0;
 484 }
 485
 486 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 487 {
 488         struct intel_overlay *overlay = dev_priv->overlay;
 489
 490         if (!overlay)
 491                 return;
 492
 493         intel_overlay_release_old_vid(overlay);
 494
 495         overlay->old_xscale = 0;
 496         overlay->old_yscale = 0;
 497         overlay->crtc = NULL;
 498         overlay->active = false;
 499 }
 500
 501 struct put_image_params {
 502         int format;
 503         short dst_x;
 504         short dst_y;
 505         short dst_w;
 506         short dst_h;
 507         short src_w;
 508         short src_scan_h;
 509         short src_scan_w;
 510         short src_h;
 511         short stride_Y;
 512         short stride_UV;
 513         int offset_Y;
 514         int offset_U;
 515         int offset_V;
 516 };
 517
 518 static int packed_depth_bytes(u32 format)
 519 {
 520         switch (format & I915_OVERLAY_DEPTH_MASK) {
 521         case I915_OVERLAY_YUV422:
 522                 return 4;
 523         case I915_OVERLAY_YUV411:
 524                 /* return 6; not implemented */
 525         default:
 526                 return -EINVAL;
 527         }
 528 }
 529
 530 static int packed_width_bytes(u32 format, short width)
 531 {
 532         switch (format & I915_OVERLAY_DEPTH_MASK) {
 533         case I915_OVERLAY_YUV422:
 534                 return width << 1;
 535         default:
 536                 return -EINVAL;
 537         }
 538 }
 539
 540 static int uv_hsubsampling(u32 format)
 541 {
 542         switch (format & I915_OVERLAY_DEPTH_MASK) {
 543         case I915_OVERLAY_YUV422:
 544         case I915_OVERLAY_YUV420:
 545                 return 2;
 546         case I915_OVERLAY_YUV411:
 547         case I915_OVERLAY_YUV410:
 548                 return 4;
 549         default:
 550                 return -EINVAL;
 551         }
 552 }
 553
 554 static int uv_vsubsampling(u32 format)
 555 {
 556         switch (format & I915_OVERLAY_DEPTH_MASK) {
 557         case I915_OVERLAY_YUV420:
 558         case I915_OVERLAY_YUV410:
 559                 return 2;
 560         case I915_OVERLAY_YUV422:
 561         case I915_OVERLAY_YUV411:
 562                 return 1;
 563         default:
 564                 return -EINVAL;
 565         }
 566 }
 567
 568 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
 569 {
 570         u32 mask, shift, ret;
 571         if (IS_GEN2(dev_priv)) {
 572                 mask = 0x1f;
 573                 shift = 5;
 574         } else {
 575                 mask = 0x3f;
 576                 shift = 6;
 577         }
 578         ret = ((offset + width + mask) >> shift) - (offset >> shift);
 579         if (!IS_GEN2(dev_priv))
 580                 ret <<= 1;
 581         ret -= 1;
 582         return ret << 2;
 583 }
 584
 585 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
 586         0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
 587         0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
 588         0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
 589         0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
 590         0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
 591         0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
 592         0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
 593         0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
 594         0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
 595         0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
 596         0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
 597         0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
 598         0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
 599         0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
 600         0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
 601         0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
 602         0xb000, 0x3000, 0x0800, 0x3000, 0xb000
 603 };
 604
 605 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
 606         0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
 607         0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
 608         0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
 609         0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
 610         0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
 611         0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
 612         0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
 613         0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
 614         0x3000, 0x0800, 0x3000
 615 };
 616
 617 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 618 {
 619         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 620         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 621                     sizeof(uv_static_hcoeffs));
 622 }
 623
 624 static bool update_scaling_factors(struct intel_overlay *overlay,
 625                                    struct overlay_registers __iomem *regs,
 626                                    struct put_image_params *params)
 627 {
 628         /* fixed point with a 12 bit shift */
 629         u32 xscale, yscale, xscale_UV, yscale_UV;
 630 #define FP_SHIFT 12
 631 #define FRACT_MASK 0xfff
 632         bool scale_changed = false;
 633         int uv_hscale = uv_hsubsampling(params->format);
 634         int uv_vscale = uv_vsubsampling(params->format);
 635
 636         if (params->dst_w > 1)
 637                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 638                         /(params->dst_w);
 639         else
 640                 xscale = 1 << FP_SHIFT;
 641
 642         if (params->dst_h > 1)
 643                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 644                         /(params->dst_h);
 645         else
 646                 yscale = 1 << FP_SHIFT;
 647
 648         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 649         xscale_UV = xscale/uv_hscale;
 650         yscale_UV = yscale/uv_vscale;
 651         /* make the Y scale to UV scale ratio an exact multiply */
 652         xscale = xscale_UV * uv_hscale;
 653         yscale = yscale_UV * uv_vscale;
 654         /*} else {
 655           xscale_UV = 0;
 656           yscale_UV = 0;
 657           }*/
 658
 659         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 660                 scale_changed = true;
 661         overlay->old_xscale = xscale;
 662         overlay->old_yscale = yscale;
 663
 664         iowrite32(((yscale & FRACT_MASK) << 20) |
 665                   ((xscale >> FP_SHIFT)  << 16) |
 666                   ((xscale & FRACT_MASK) << 3),
 667                  &regs->YRGBSCALE);
 668
 669         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 670                   ((xscale_UV >> FP_SHIFT)  << 16) |
 671                   ((xscale_UV & FRACT_MASK) << 3),
 672                  &regs->UVSCALE);
 673
 674         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 675                    ((yscale_UV >> FP_SHIFT) << 0)),
 676                  &regs->UVSCALEV);
 677
 678         if (scale_changed)
 679                 update_polyphase_filter(regs);
 680
 681         return scale_changed;
 682 }
 683
 684 static void update_colorkey(struct intel_overlay *overlay,
 685                             struct overlay_registers __iomem *regs)
 686 {
 687         u32 key = overlay->color_key;
 688         u32 flags;
 689
 690         flags = 0;
 691         if (overlay->color_key_enabled)
 692                 flags |= DST_KEY_ENABLE;
 693
 694         switch (overlay->crtc->base.primary->fb->bits_per_pixel) {
 695         case 8:
 696                 key = 0;
 697                 flags |= CLK_RGB8I_MASK;
 698                 break;
 699
 700         case 16:
 701                 if (overlay->crtc->base.primary->fb->depth == 15) {
 702                         key = RGB15_TO_COLORKEY(key);
 703                         flags |= CLK_RGB15_MASK;
 704                 } else {
 705                         key = RGB16_TO_COLORKEY(key);
 706                         flags |= CLK_RGB16_MASK;
 707                 }
 708                 break;
 709
 710         case 24:
 711         case 32:
 712                 flags |= CLK_RGB24_MASK;
 713                 break;
 714         }
 715
 716         iowrite32(key, &regs->DCLRKV);
 717         iowrite32(flags, &regs->DCLRKM);
 718 }
 719
 720 static u32 overlay_cmd_reg(struct put_image_params *params)
 721 {
 722         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 723
 724         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 725                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 726                 case I915_OVERLAY_YUV422:
 727                         cmd |= OCMD_YUV_422_PLANAR;
 728                         break;
 729                 case I915_OVERLAY_YUV420:
 730                         cmd |= OCMD_YUV_420_PLANAR;
 731                         break;
 732                 case I915_OVERLAY_YUV411:
 733                 case I915_OVERLAY_YUV410:
 734                         cmd |= OCMD_YUV_410_PLANAR;
 735                         break;
 736                 }
 737         } else { /* YUV packed */
 738                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 739                 case I915_OVERLAY_YUV422:
 740                         cmd |= OCMD_YUV_422_PACKED;
 741                         break;
 742                 case I915_OVERLAY_YUV411:
 743                         cmd |= OCMD_YUV_411_PACKED;
 744                         break;
 745                 }
 746
 747                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 748                 case I915_OVERLAY_NO_SWAP:
 749                         break;
 750                 case I915_OVERLAY_UV_SWAP:
 751                         cmd |= OCMD_UV_SWAP;
 752                         break;
 753                 case I915_OVERLAY_Y_SWAP:
 754                         cmd |= OCMD_Y_SWAP;
 755                         break;
 756                 case I915_OVERLAY_Y_AND_UV_SWAP:
 757                         cmd |= OCMD_Y_AND_UV_SWAP;
 758                         break;
 759                 }
 760         }
 761
 762         return cmd;
 763 }
 764
 765 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 766                                       struct drm_i915_gem_object *new_bo,
 767                                       struct put_image_params *params)
 768 {
 769         int ret, tmp_width;
 770         struct overlay_registers __iomem *regs;
 771         bool scale_changed = false;
 772         struct drm_i915_private *dev_priv = overlay->i915;
 773         u32 swidth, swidthsw, sheight, ostride;
 774         enum pipe pipe = overlay->crtc->pipe;
 775         struct i915_vma *vma;
 776
 777         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 778         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 779
 780         ret = intel_overlay_release_old_vid(overlay);
 781         if (ret != 0)
 782                 return ret;
 783
 784         vma = i915_gem_object_pin_to_display_plane(new_bo, 0,
 785                                                    &i915_ggtt_view_normal);
 786         if (IS_ERR(vma))
 787                 return PTR_ERR(vma);
 788
 789         ret = i915_vma_put_fence(vma);
 790         if (ret)
 791                 goto out_unpin;
 792
 793         if (!overlay->active) {
 794                 u32 oconfig;
 795                 regs = intel_overlay_map_regs(overlay);
 796                 if (!regs) {
 797                         ret = -ENOMEM;
 798                         goto out_unpin;
 799                 }
 800                 oconfig = OCONF_CC_OUT_8BIT;
 801                 if (IS_GEN4(dev_priv))
 802                         oconfig |= OCONF_CSC_MODE_BT709;
 803                 oconfig |= pipe == 0 ?
 804                         OCONF_PIPE_A : OCONF_PIPE_B;
 805                 iowrite32(oconfig, &regs->OCONFIG);
 806                 intel_overlay_unmap_regs(overlay, regs);
 807
 808                 ret = intel_overlay_on(overlay);
 809                 if (ret != 0)
 810                         goto out_unpin;
 811         }
 812
 813         regs = intel_overlay_map_regs(overlay);
 814         if (!regs) {
 815                 ret = -ENOMEM;
 816                 goto out_unpin;
 817         }
 818
 819         iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
 820         iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
 821
 822         if (params->format & I915_OVERLAY_YUV_PACKED)
 823                 tmp_width = packed_width_bytes(params->format, params->src_w);
 824         else
 825                 tmp_width = params->src_w;
 826
 827         swidth = params->src_w;
 828         swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
 829         sheight = params->src_h;
 830         iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 831         ostride = params->stride_Y;
 832
 833         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 834                 int uv_hscale = uv_hsubsampling(params->format);
 835                 int uv_vscale = uv_vsubsampling(params->format);
 836                 u32 tmp_U, tmp_V;
 837                 swidth |= (params->src_w/uv_hscale) << 16;
 838                 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
 839                                       params->src_w/uv_hscale);
 840                 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
 841                                       params->src_w/uv_hscale);
 842                 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
 843                 sheight |= (params->src_h/uv_vscale) << 16;
 844                 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 845                           &regs->OBUF_0U);
 846                 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 847                           &regs->OBUF_0V);
 848                 ostride |= params->stride_UV << 16;
 849         }
 850
 851         iowrite32(swidth, &regs->SWIDTH);
 852         iowrite32(swidthsw, &regs->SWIDTHSW);
 853         iowrite32(sheight, &regs->SHEIGHT);
 854         iowrite32(ostride, &regs->OSTRIDE);
 855
 856         scale_changed = update_scaling_factors(overlay, regs, params);
 857
 858         update_colorkey(overlay, regs);
 859
 860         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 861
 862         intel_overlay_unmap_regs(overlay, regs);
 863
 864         ret = intel_overlay_continue(overlay, vma, scale_changed);
 865         if (ret)
 866                 goto out_unpin;
 867
 868         return 0;
 869
 870 out_unpin:
 871         i915_gem_object_unpin_from_display_plane(vma);
 872         return ret;
 873 }
 874
 875 int intel_overlay_switch_off(struct intel_overlay *overlay)
 876 {
 877         struct drm_i915_private *dev_priv = overlay->i915;
 878         struct overlay_registers __iomem *regs;
 879         int ret;
 880
 881         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 882         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 883
 884         ret = intel_overlay_recover_from_interrupt(overlay);
 885         if (ret != 0)
 886                 return ret;
 887
 888         if (!overlay->active)
 889                 return 0;
 890
 891         ret = intel_overlay_release_old_vid(overlay);
 892         if (ret != 0)
 893                 return ret;
 894
 895         regs = intel_overlay_map_regs(overlay);
 896         iowrite32(0, &regs->OCMD);
 897         intel_overlay_unmap_regs(overlay, regs);
 898
 899         return intel_overlay_off(overlay);
 900 }
 901
 902 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 903                                           struct intel_crtc *crtc)
 904 {
 905         if (!crtc->active)
 906                 return -EINVAL;
 907
 908         /* can't use the overlay with double wide pipe */
 909         if (crtc->config->double_wide)
 910                 return -EINVAL;
 911
 912         return 0;
 913 }
 914
 915 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 916 {
 917         struct drm_i915_private *dev_priv = overlay->i915;
 918         u32 pfit_control = I915_READ(PFIT_CONTROL);
 919         u32 ratio;
 920
 921         /* XXX: This is not the same logic as in the xorg driver, but more in
 922          * line with the intel documentation for the i965
 923          */
 924         if (INTEL_GEN(dev_priv) >= 4) {
 925                 /* on i965 use the PGM reg to read out the autoscaler values */
 926                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 927         } else {
 928                 if (pfit_control & VERT_AUTO_SCALE)
 929                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 930                 else
 931                         ratio = I915_READ(PFIT_PGM_RATIOS);
 932                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 933         }
 934
 935         overlay->pfit_vscale_ratio = ratio;
 936 }
 937
 938 static int check_overlay_dst(struct intel_overlay *overlay,
 939                              struct drm_intel_overlay_put_image *rec)
 940 {
 941         struct drm_display_mode *mode = &overlay->crtc->base.mode;
 942
 943         if (rec->dst_x < mode->hdisplay &&
 944             rec->dst_x + rec->dst_width <= mode->hdisplay &&
 945             rec->dst_y < mode->vdisplay &&
 946             rec->dst_y + rec->dst_height <= mode->vdisplay)
 947                 return 0;
 948         else
 949                 return -EINVAL;
 950 }
 951
 952 static int check_overlay_scaling(struct put_image_params *rec)
 953 {
 954         u32 tmp;
 955
 956         /* downscaling limit is 8.0 */
 957         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 958         if (tmp > 7)
 959                 return -EINVAL;
 960         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 961         if (tmp > 7)
 962                 return -EINVAL;
 963
 964         return 0;
 965 }
 966
 967 static int check_overlay_src(struct drm_i915_private *dev_priv,
 968                              struct drm_intel_overlay_put_image *rec,
 969                              struct drm_i915_gem_object *new_bo)
 970 {
 971         int uv_hscale = uv_hsubsampling(rec->flags);
 972         int uv_vscale = uv_vsubsampling(rec->flags);
 973         u32 stride_mask;
 974         int depth;
 975         u32 tmp;
 976
 977         /* check src dimensions */
 978         if (IS_845G(dev_priv) || IS_I830(dev_priv)) {
 979                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 980                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 981                         return -EINVAL;
 982         } else {
 983                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 984                     rec->src_width  > IMAGE_MAX_WIDTH)
 985                         return -EINVAL;
 986         }
 987
 988         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 989         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 990             rec->src_width  < N_HORIZ_Y_TAPS*4)
 991                 return -EINVAL;
 992
 993         /* check alignment constraints */
 994         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 995         case I915_OVERLAY_RGB:
 996                 /* not implemented */
 997                 return -EINVAL;
 998
 999         case I915_OVERLAY_YUV_PACKED:
1000                 if (uv_vscale != 1)
1001                         return -EINVAL;
1002
1003                 depth = packed_depth_bytes(rec->flags);
1004                 if (depth < 0)
1005                         return depth;
1006
1007                 /* ignore UV planes */
1008                 rec->stride_UV = 0;
1009                 rec->offset_U = 0;
1010                 rec->offset_V = 0;
1011                 /* check pixel alignment */
1012                 if (rec->offset_Y % depth)
1013                         return -EINVAL;
1014                 break;
1015
1016         case I915_OVERLAY_YUV_PLANAR:
1017                 if (uv_vscale < 0 || uv_hscale < 0)
1018                         return -EINVAL;
1019                 /* no offset restrictions for planar formats */
1020                 break;
1021
1022         default:
1023                 return -EINVAL;
1024         }
1025
1026         if (rec->src_width % uv_hscale)
1027                 return -EINVAL;
1028
1029         /* stride checking */
1030         if (IS_I830(dev_priv) || IS_845G(dev_priv))
1031                 stride_mask = 255;
1032         else
1033                 stride_mask = 63;
1034
1035         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1036                 return -EINVAL;
1037         if (IS_GEN4(dev_priv) && rec->stride_Y < 512)
1038                 return -EINVAL;
1039
1040         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1041                 4096 : 8192;
1042         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1043                 return -EINVAL;
1044
1045         /* check buffer dimensions */
1046         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1047         case I915_OVERLAY_RGB:
1048         case I915_OVERLAY_YUV_PACKED:
1049                 /* always 4 Y values per depth pixels */
1050                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1051                         return -EINVAL;
1052
1053                 tmp = rec->stride_Y*rec->src_height;
1054                 if (rec->offset_Y + tmp > new_bo->base.size)
1055                         return -EINVAL;
1056                 break;
1057
1058         case I915_OVERLAY_YUV_PLANAR:
1059                 if (rec->src_width > rec->stride_Y)
1060                         return -EINVAL;
1061                 if (rec->src_width/uv_hscale > rec->stride_UV)
1062                         return -EINVAL;
1063
1064                 tmp = rec->stride_Y * rec->src_height;
1065                 if (rec->offset_Y + tmp > new_bo->base.size)
1066                         return -EINVAL;
1067
1068                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1069                 if (rec->offset_U + tmp > new_bo->base.size ||
1070                     rec->offset_V + tmp > new_bo->base.size)
1071                         return -EINVAL;
1072                 break;
1073         }
1074
1075         return 0;
1076 }
1077
1078 /**
1079  * Return the pipe currently connected to the panel fitter,
1080  * or -1 if the panel fitter is not present or not in use
1081  */
1082 static int intel_panel_fitter_pipe(struct drm_i915_private *dev_priv)
1083 {
1084         u32  pfit_control;
1085
1086         /* i830 doesn't have a panel fitter */
1087         if (INTEL_GEN(dev_priv) <= 3 &&
1088             (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
1089                 return -1;
1090
1091         pfit_control = I915_READ(PFIT_CONTROL);
1092
1093         /* See if the panel fitter is in use */
1094         if ((pfit_control & PFIT_ENABLE) == 0)
1095                 return -1;
1096
1097         /* 965 can place panel fitter on either pipe */
1098         if (IS_GEN4(dev_priv))
1099                 return (pfit_control >> 29) & 0x3;
1100
1101         /* older chips can only use pipe 1 */
1102         return 1;
1103 }
1104
1105 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1106                                   struct drm_file *file_priv)
1107 {
1108         struct drm_intel_overlay_put_image *put_image_rec = data;
1109         struct drm_i915_private *dev_priv = to_i915(dev);
1110         struct intel_overlay *overlay;
1111         struct drm_crtc *drmmode_crtc;
1112         struct intel_crtc *crtc;
1113         struct drm_i915_gem_object *new_bo;
1114         struct put_image_params *params;
1115         int ret;
1116
1117         overlay = dev_priv->overlay;
1118         if (!overlay) {
1119                 DRM_DEBUG("userspace bug: no overlay\n");
1120                 return -ENODEV;
1121         }
1122
1123         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1124                 drm_modeset_lock_all(dev);
1125                 mutex_lock(&dev->struct_mutex);
1126
1127                 ret = intel_overlay_switch_off(overlay);
1128
1129                 mutex_unlock(&dev->struct_mutex);
1130                 drm_modeset_unlock_all(dev);
1131
1132                 return ret;
1133         }
1134
1135         params = kmalloc(sizeof(*params), GFP_KERNEL);
1136         if (!params)
1137                 return -ENOMEM;
1138
1139         drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id);
1140         if (!drmmode_crtc) {
1141                 ret = -ENOENT;
1142                 goto out_free;
1143         }
1144         crtc = to_intel_crtc(drmmode_crtc);
1145
1146         new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle);
1147         if (!new_bo) {
1148                 ret = -ENOENT;
1149                 goto out_free;
1150         }
1151
1152         drm_modeset_lock_all(dev);
1153         mutex_lock(&dev->struct_mutex);
1154
1155         if (i915_gem_object_is_tiled(new_bo)) {
1156                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1157                 ret = -EINVAL;
1158                 goto out_unlock;
1159         }
1160
1161         ret = intel_overlay_recover_from_interrupt(overlay);
1162         if (ret != 0)
1163                 goto out_unlock;
1164
1165         if (overlay->crtc != crtc) {
1166                 struct drm_display_mode *mode = &crtc->base.mode;
1167                 ret = intel_overlay_switch_off(overlay);
1168                 if (ret != 0)
1169                         goto out_unlock;
1170
1171                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1172                 if (ret != 0)
1173                         goto out_unlock;
1174
1175                 overlay->crtc = crtc;
1176                 crtc->overlay = overlay;
1177
1178                 /* line too wide, i.e. one-line-mode */
1179                 if (mode->hdisplay > 1024 &&
1180                     intel_panel_fitter_pipe(dev_priv) == crtc->pipe) {
1181                         overlay->pfit_active = true;
1182                         update_pfit_vscale_ratio(overlay);
1183                 } else
1184                         overlay->pfit_active = false;
1185         }
1186
1187         ret = check_overlay_dst(overlay, put_image_rec);
1188         if (ret != 0)
1189                 goto out_unlock;
1190
1191         if (overlay->pfit_active) {
1192                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1193                                  overlay->pfit_vscale_ratio);
1194                 /* shifting right rounds downwards, so add 1 */
1195                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1196                                  overlay->pfit_vscale_ratio) + 1;
1197         } else {
1198                 params->dst_y = put_image_rec->dst_y;
1199                 params->dst_h = put_image_rec->dst_height;
1200         }
1201         params->dst_x = put_image_rec->dst_x;
1202         params->dst_w = put_image_rec->dst_width;
1203
1204         params->src_w = put_image_rec->src_width;
1205         params->src_h = put_image_rec->src_height;
1206         params->src_scan_w = put_image_rec->src_scan_width;
1207         params->src_scan_h = put_image_rec->src_scan_height;
1208         if (params->src_scan_h > params->src_h ||
1209             params->src_scan_w > params->src_w) {
1210                 ret = -EINVAL;
1211                 goto out_unlock;
1212         }
1213
1214         ret = check_overlay_src(dev_priv, put_image_rec, new_bo);
1215         if (ret != 0)
1216                 goto out_unlock;
1217         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1218         params->stride_Y = put_image_rec->stride_Y;
1219         params->stride_UV = put_image_rec->stride_UV;
1220         params->offset_Y = put_image_rec->offset_Y;
1221         params->offset_U = put_image_rec->offset_U;
1222         params->offset_V = put_image_rec->offset_V;
1223
1224         /* Check scaling after src size to prevent a divide-by-zero. */
1225         ret = check_overlay_scaling(params);
1226         if (ret != 0)
1227                 goto out_unlock;
1228
1229         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1230         if (ret != 0)
1231                 goto out_unlock;
1232
1233         mutex_unlock(&dev->struct_mutex);
1234         drm_modeset_unlock_all(dev);
1235         i915_gem_object_put(new_bo);
1236
1237         kfree(params);
1238
1239         return 0;
1240
1241 out_unlock:
1242         mutex_unlock(&dev->struct_mutex);
1243         drm_modeset_unlock_all(dev);
1244         i915_gem_object_put_unlocked(new_bo);
1245 out_free:
1246         kfree(params);
1247
1248         return ret;
1249 }
1250
1251 static void update_reg_attrs(struct intel_overlay *overlay,
1252                              struct overlay_registers __iomem *regs)
1253 {
1254         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1255                   &regs->OCLRC0);
1256         iowrite32(overlay->saturation, &regs->OCLRC1);
1257 }
1258
1259 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1260 {
1261         int i;
1262
1263         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1264                 return false;
1265
1266         for (i = 0; i < 3; i++) {
1267                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1268                         return false;
1269         }
1270
1271         return true;
1272 }
1273
1274 static bool check_gamma5_errata(u32 gamma5)
1275 {
1276         int i;
1277
1278         for (i = 0; i < 3; i++) {
1279                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1280                         return false;
1281         }
1282
1283         return true;
1284 }
1285
1286 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1287 {
1288         if (!check_gamma_bounds(0, attrs->gamma0) ||
1289             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1290             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1291             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1292             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1293             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1294             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1295                 return -EINVAL;
1296
1297         if (!check_gamma5_errata(attrs->gamma5))
1298                 return -EINVAL;
1299
1300         return 0;
1301 }
1302
1303 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1304                               struct drm_file *file_priv)
1305 {
1306         struct drm_intel_overlay_attrs *attrs = data;
1307         struct drm_i915_private *dev_priv = to_i915(dev);
1308         struct intel_overlay *overlay;
1309         struct overlay_registers __iomem *regs;
1310         int ret;
1311
1312         overlay = dev_priv->overlay;
1313         if (!overlay) {
1314                 DRM_DEBUG("userspace bug: no overlay\n");
1315                 return -ENODEV;
1316         }
1317
1318         drm_modeset_lock_all(dev);
1319         mutex_lock(&dev->struct_mutex);
1320
1321         ret = -EINVAL;
1322         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1323                 attrs->color_key  = overlay->color_key;
1324                 attrs->brightness = overlay->brightness;
1325                 attrs->contrast   = overlay->contrast;
1326                 attrs->saturation = overlay->saturation;
1327
1328                 if (!IS_GEN2(dev_priv)) {
1329                         attrs->gamma0 = I915_READ(OGAMC0);
1330                         attrs->gamma1 = I915_READ(OGAMC1);
1331                         attrs->gamma2 = I915_READ(OGAMC2);
1332                         attrs->gamma3 = I915_READ(OGAMC3);
1333                         attrs->gamma4 = I915_READ(OGAMC4);
1334                         attrs->gamma5 = I915_READ(OGAMC5);
1335                 }
1336         } else {
1337                 if (attrs->brightness < -128 || attrs->brightness > 127)
1338                         goto out_unlock;
1339                 if (attrs->contrast > 255)
1340                         goto out_unlock;
1341                 if (attrs->saturation > 1023)
1342                         goto out_unlock;
1343
1344                 overlay->color_key  = attrs->color_key;
1345                 overlay->brightness = attrs->brightness;
1346                 overlay->contrast   = attrs->contrast;
1347                 overlay->saturation = attrs->saturation;
1348
1349                 regs = intel_overlay_map_regs(overlay);
1350                 if (!regs) {
1351                         ret = -ENOMEM;
1352                         goto out_unlock;
1353                 }
1354
1355                 update_reg_attrs(overlay, regs);
1356
1357                 intel_overlay_unmap_regs(overlay, regs);
1358
1359                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1360                         if (IS_GEN2(dev_priv))
1361                                 goto out_unlock;
1362
1363                         if (overlay->active) {
1364                                 ret = -EBUSY;
1365                                 goto out_unlock;
1366                         }
1367
1368                         ret = check_gamma(attrs);
1369                         if (ret)
1370                                 goto out_unlock;
1371
1372                         I915_WRITE(OGAMC0, attrs->gamma0);
1373                         I915_WRITE(OGAMC1, attrs->gamma1);
1374                         I915_WRITE(OGAMC2, attrs->gamma2);
1375                         I915_WRITE(OGAMC3, attrs->gamma3);
1376                         I915_WRITE(OGAMC4, attrs->gamma4);
1377                         I915_WRITE(OGAMC5, attrs->gamma5);
1378                 }
1379         }
1380         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1381
1382         ret = 0;
1383 out_unlock:
1384         mutex_unlock(&dev->struct_mutex);
1385         drm_modeset_unlock_all(dev);
1386
1387         return ret;
1388 }
1389
1390 void intel_setup_overlay(struct drm_i915_private *dev_priv)
1391 {
1392         struct intel_overlay *overlay;
1393         struct drm_i915_gem_object *reg_bo;
1394         struct overlay_registers __iomem *regs;
1395         struct i915_vma *vma = NULL;
1396         int ret;
1397
1398         if (!HAS_OVERLAY(dev_priv))
1399                 return;
1400
1401         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1402         if (!overlay)
1403                 return;
1404
1405         mutex_lock(&dev_priv->drm.struct_mutex);
1406         if (WARN_ON(dev_priv->overlay))
1407                 goto out_free;
1408
1409         overlay->i915 = dev_priv;
1410
1411         reg_bo = NULL;
1412         if (!OVERLAY_NEEDS_PHYSICAL(dev_priv))
1413                 reg_bo = i915_gem_object_create_stolen(&dev_priv->drm,
1414                                                        PAGE_SIZE);
1415         if (reg_bo == NULL)
1416                 reg_bo = i915_gem_object_create(&dev_priv->drm, PAGE_SIZE);
1417         if (IS_ERR(reg_bo))
1418                 goto out_free;
1419         overlay->reg_bo = reg_bo;
1420
1421         if (OVERLAY_NEEDS_PHYSICAL(dev_priv)) {
1422                 ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE);
1423                 if (ret) {
1424                         DRM_ERROR("failed to attach phys overlay regs\n");
1425                         goto out_free_bo;
1426                 }
1427                 overlay->flip_addr = reg_bo->phys_handle->busaddr;
1428         } else {
1429                 vma = i915_gem_object_ggtt_pin(reg_bo, NULL,
1430                                                0, PAGE_SIZE, PIN_MAPPABLE);
1431                 if (IS_ERR(vma)) {
1432                         DRM_ERROR("failed to pin overlay register bo\n");
1433                         ret = PTR_ERR(vma);
1434                         goto out_free_bo;
1435                 }
1436                 overlay->flip_addr = i915_ggtt_offset(vma);
1437
1438                 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1439                 if (ret) {
1440                         DRM_ERROR("failed to move overlay register bo into the GTT\n");
1441                         goto out_unpin_bo;
1442                 }
1443         }
1444
1445         /* init all values */
1446         overlay->color_key = 0x0101fe;
1447         overlay->color_key_enabled = true;
1448         overlay->brightness = -19;
1449         overlay->contrast = 75;
1450         overlay->saturation = 146;
1451
1452         init_request_active(&overlay->last_flip, NULL);
1453
1454         regs = intel_overlay_map_regs(overlay);
1455         if (!regs)
1456                 goto out_unpin_bo;
1457
1458         memset_io(regs, 0, sizeof(struct overlay_registers));
1459         update_polyphase_filter(regs);
1460         update_reg_attrs(overlay, regs);
1461
1462         intel_overlay_unmap_regs(overlay, regs);
1463
1464         dev_priv->overlay = overlay;
1465         mutex_unlock(&dev_priv->drm.struct_mutex);
1466         DRM_INFO("initialized overlay support\n");
1467         return;
1468
1469 out_unpin_bo:
1470         if (vma)
1471                 i915_vma_unpin(vma);
1472 out_free_bo:
1473         i915_gem_object_put(reg_bo);
1474 out_free:
1475         mutex_unlock(&dev_priv->drm.struct_mutex);
1476         kfree(overlay);
1477         return;
1478 }
1479
1480 void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
1481 {
1482         if (!dev_priv->overlay)
1483                 return;
1484
1485         /* The bo's should be free'd by the generic code already.
1486          * Furthermore modesetting teardown happens beforehand so the
1487          * hardware should be off already */
1488         WARN_ON(dev_priv->overlay->active);
1489
1490         i915_gem_object_put_unlocked(dev_priv->overlay->reg_bo);
1491         kfree(dev_priv->overlay);
1492 }
1493
1494 struct intel_overlay_error_state {
1495         struct overlay_registers regs;
1496         unsigned long base;
1497         u32 dovsta;
1498         u32 isr;
1499 };
1500
1501 static struct overlay_registers __iomem *
1502 intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
1503 {
1504         struct drm_i915_private *dev_priv = overlay->i915;
1505         struct overlay_registers __iomem *regs;
1506
1507         if (OVERLAY_NEEDS_PHYSICAL(dev_priv))
1508                 /* Cast to make sparse happy, but it's wc memory anyway, so
1509                  * equivalent to the wc io mapping on X86. */
1510                 regs = (struct overlay_registers __iomem *)
1511                         overlay->reg_bo->phys_handle->vaddr;
1512         else
1513                 regs = io_mapping_map_atomic_wc(&dev_priv->ggtt.mappable,
1514                                                 overlay->flip_addr);
1515
1516         return regs;
1517 }
1518
1519 static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1520                                         struct overlay_registers __iomem *regs)
1521 {
1522         if (!OVERLAY_NEEDS_PHYSICAL(overlay->i915))
1523                 io_mapping_unmap_atomic(regs);
1524 }
1525
1526 struct intel_overlay_error_state *
1527 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1528 {
1529         struct intel_overlay *overlay = dev_priv->overlay;
1530         struct intel_overlay_error_state *error;
1531         struct overlay_registers __iomem *regs;
1532
1533         if (!overlay || !overlay->active)
1534                 return NULL;
1535
1536         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1537         if (error == NULL)
1538                 return NULL;
1539
1540         error->dovsta = I915_READ(DOVSTA);
1541         error->isr = I915_READ(ISR);
1542         error->base = overlay->flip_addr;
1543
1544         regs = intel_overlay_map_regs_atomic(overlay);
1545         if (!regs)
1546                 goto err;
1547
1548         memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1549         intel_overlay_unmap_regs_atomic(overlay, regs);
1550
1551         return error;
1552
1553 err:
1554         kfree(error);
1555         return NULL;
1556 }
1557
1558 void
1559 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1560                                 struct intel_overlay_error_state *error)
1561 {
1562         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1563                           error->dovsta, error->isr);
1564         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1565                           error->base);
1566
1567 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1568         P(OBUF_0Y);
1569         P(OBUF_1Y);
1570         P(OBUF_0U);
1571         P(OBUF_0V);
1572         P(OBUF_1U);
1573         P(OBUF_1V);
1574         P(OSTRIDE);
1575         P(YRGB_VPH);
1576         P(UV_VPH);
1577         P(HORZ_PH);
1578         P(INIT_PHS);
1579         P(DWINPOS);
1580         P(DWINSZ);
1581         P(SWIDTH);
1582         P(SWIDTHSW);
1583         P(SHEIGHT);
1584         P(YRGBSCALE);
1585         P(UVSCALE);
1586         P(OCLRC0);
1587         P(OCLRC1);
1588         P(DCLRKV);
1589         P(DCLRKM);
1590         P(SCLRKVH);
1591         P(SCLRKVL);
1592         P(SCLRKEN);
1593         P(OCONFIG);
1594         P(OCMD);
1595         P(OSTART_0Y);
1596         P(OSTART_1Y);
1597         P(OSTART_0U);
1598         P(OSTART_0V);
1599         P(OSTART_1U);
1600         P(OSTART_1V);
1601         P(OTILEOFF_0Y);
1602         P(OTILEOFF_1Y);
1603         P(OTILEOFF_0U);
1604         P(OTILEOFF_0V);
1605         P(OTILEOFF_1U);
1606         P(OTILEOFF_1V);
1607         P(FASTHSCALE);
1608         P(UVSCALEV);
1609 #undef P
1610 }