drivers/gpu/drm/i915/intel_overlay.c

   1 /*
   2  * Copyright © 2009
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Daniel Vetter <daniel@ffwll.ch>
  25  *
  26  * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
  27  */
  28 #include <drm/drmP.h>
  29 #include <drm/i915_drm.h>
  30 #include "i915_drv.h"
  31 #include "i915_reg.h"
  32 #include "intel_drv.h"
  33 #include "intel_frontbuffer.h"
  34
  35 /* Limits for overlay size. According to intel doc, the real limits are:
  36  * Y width: 4095, UV width (planar): 2047, Y height: 2047,
  37  * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
  38  * the mininum of both.  */
  39 #define IMAGE_MAX_WIDTH         2048
  40 #define IMAGE_MAX_HEIGHT        2046 /* 2 * 1023 */
  41 /* on 830 and 845 these large limits result in the card hanging */
  42 #define IMAGE_MAX_WIDTH_LEGACY  1024
  43 #define IMAGE_MAX_HEIGHT_LEGACY 1088
  44
  45 /* overlay register definitions */
  46 /* OCMD register */
  47 #define OCMD_TILED_SURFACE      (0x1<<19)
  48 #define OCMD_MIRROR_MASK        (0x3<<17)
  49 #define OCMD_MIRROR_MODE        (0x3<<17)
  50 #define OCMD_MIRROR_HORIZONTAL  (0x1<<17)
  51 #define OCMD_MIRROR_VERTICAL    (0x2<<17)
  52 #define OCMD_MIRROR_BOTH        (0x3<<17)
  53 #define OCMD_BYTEORDER_MASK     (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
  54 #define OCMD_UV_SWAP            (0x1<<14) /* YVYU */
  55 #define OCMD_Y_SWAP             (0x2<<14) /* UYVY or FOURCC UYVY */
  56 #define OCMD_Y_AND_UV_SWAP      (0x3<<14) /* VYUY */
  57 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
  58 #define OCMD_RGB_888            (0x1<<10) /* not in i965 Intel docs */
  59 #define OCMD_RGB_555            (0x2<<10) /* not in i965 Intel docs */
  60 #define OCMD_RGB_565            (0x3<<10) /* not in i965 Intel docs */
  61 #define OCMD_YUV_422_PACKED     (0x8<<10)
  62 #define OCMD_YUV_411_PACKED     (0x9<<10) /* not in i965 Intel docs */
  63 #define OCMD_YUV_420_PLANAR     (0xc<<10)
  64 #define OCMD_YUV_422_PLANAR     (0xd<<10)
  65 #define OCMD_YUV_410_PLANAR     (0xe<<10) /* also 411 */
  66 #define OCMD_TVSYNCFLIP_PARITY  (0x1<<9)
  67 #define OCMD_TVSYNCFLIP_ENABLE  (0x1<<7)
  68 #define OCMD_BUF_TYPE_MASK      (0x1<<5)
  69 #define OCMD_BUF_TYPE_FRAME     (0x0<<5)
  70 #define OCMD_BUF_TYPE_FIELD     (0x1<<5)
  71 #define OCMD_TEST_MODE          (0x1<<4)
  72 #define OCMD_BUFFER_SELECT      (0x3<<2)
  73 #define OCMD_BUFFER0            (0x0<<2)
  74 #define OCMD_BUFFER1            (0x1<<2)
  75 #define OCMD_FIELD_SELECT       (0x1<<2)
  76 #define OCMD_FIELD0             (0x0<<1)
  77 #define OCMD_FIELD1             (0x1<<1)
  78 #define OCMD_ENABLE             (0x1<<0)
  79
  80 /* OCONFIG register */
  81 #define OCONF_PIPE_MASK         (0x1<<18)
  82 #define OCONF_PIPE_A            (0x0<<18)
  83 #define OCONF_PIPE_B            (0x1<<18)
  84 #define OCONF_GAMMA2_ENABLE     (0x1<<16)
  85 #define OCONF_CSC_MODE_BT601    (0x0<<5)
  86 #define OCONF_CSC_MODE_BT709    (0x1<<5)
  87 #define OCONF_CSC_BYPASS        (0x1<<4)
  88 #define OCONF_CC_OUT_8BIT       (0x1<<3)
  89 #define OCONF_TEST_MODE         (0x1<<2)
  90 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
  91 #define OCONF_TWO_LINE_BUFFER   (0x0<<0)
  92
  93 /* DCLRKM (dst-key) register */
  94 #define DST_KEY_ENABLE          (0x1<<31)
  95 #define CLK_RGB24_MASK          0x0
  96 #define CLK_RGB16_MASK          0x070307
  97 #define CLK_RGB15_MASK          0x070707
  98 #define CLK_RGB8I_MASK          0xffffff
  99
 100 #define RGB16_TO_COLORKEY(c) \
 101         (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
 102 #define RGB15_TO_COLORKEY(c) \
 103         (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
 104
 105 /* overlay flip addr flag */
 106 #define OFC_UPDATE              0x1
 107
 108 /* polyphase filter coefficients */
 109 #define N_HORIZ_Y_TAPS          5
 110 #define N_VERT_Y_TAPS           3
 111 #define N_HORIZ_UV_TAPS         3
 112 #define N_VERT_UV_TAPS          3
 113 #define N_PHASES                17
 114 #define MAX_TAPS                5
 115
 116 /* memory bufferd overlay registers */
 117 struct overlay_registers {
 118         u32 OBUF_0Y;
 119         u32 OBUF_1Y;
 120         u32 OBUF_0U;
 121         u32 OBUF_0V;
 122         u32 OBUF_1U;
 123         u32 OBUF_1V;
 124         u32 OSTRIDE;
 125         u32 YRGB_VPH;
 126         u32 UV_VPH;
 127         u32 HORZ_PH;
 128         u32 INIT_PHS;
 129         u32 DWINPOS;
 130         u32 DWINSZ;
 131         u32 SWIDTH;
 132         u32 SWIDTHSW;
 133         u32 SHEIGHT;
 134         u32 YRGBSCALE;
 135         u32 UVSCALE;
 136         u32 OCLRC0;
 137         u32 OCLRC1;
 138         u32 DCLRKV;
 139         u32 DCLRKM;
 140         u32 SCLRKVH;
 141         u32 SCLRKVL;
 142         u32 SCLRKEN;
 143         u32 OCONFIG;
 144         u32 OCMD;
 145         u32 RESERVED1; /* 0x6C */
 146         u32 OSTART_0Y;
 147         u32 OSTART_1Y;
 148         u32 OSTART_0U;
 149         u32 OSTART_0V;
 150         u32 OSTART_1U;
 151         u32 OSTART_1V;
 152         u32 OTILEOFF_0Y;
 153         u32 OTILEOFF_1Y;
 154         u32 OTILEOFF_0U;
 155         u32 OTILEOFF_0V;
 156         u32 OTILEOFF_1U;
 157         u32 OTILEOFF_1V;
 158         u32 FASTHSCALE; /* 0xA0 */
 159         u32 UVSCALEV; /* 0xA4 */
 160         u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
 161         u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
 162         u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
 163         u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
 164         u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
 165         u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
 166         u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
 167         u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
 168         u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
 169 };
 170
 171 struct intel_overlay {
 172         struct drm_i915_private *i915;
 173         struct intel_crtc *crtc;
 174         struct i915_vma *vma;
 175         struct i915_vma *old_vma;
 176         bool active;
 177         bool pfit_active;
 178         u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
 179         u32 color_key:24;
 180         u32 color_key_enabled:1;
 181         u32 brightness, contrast, saturation;
 182         u32 old_xscale, old_yscale;
 183         /* register access */
 184         struct drm_i915_gem_object *reg_bo;
 185         struct overlay_registers __iomem *regs;
 186         u32 flip_addr;
 187         /* flip handling */
 188         struct i915_gem_active last_flip;
 189 };
 190
 191 static void i830_overlay_clock_gating(struct drm_i915_private *dev_priv,
 192                                       bool enable)
 193 {
 194         struct pci_dev *pdev = dev_priv->drm.pdev;
 195         u8 val;
 196
 197         /* WA_OVERLAY_CLKGATE:alm */
 198         if (enable)
 199                 I915_WRITE(DSPCLK_GATE_D, 0);
 200         else
 201                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
 202
 203         /* WA_DISABLE_L2CACHE_CLOCK_GATING:alm */
 204         pci_bus_read_config_byte(pdev->bus,
 205                                  PCI_DEVFN(0, 0), I830_CLOCK_GATE, &val);
 206         if (enable)
 207                 val &= ~I830_L2_CACHE_CLOCK_GATE_DISABLE;
 208         else
 209                 val |= I830_L2_CACHE_CLOCK_GATE_DISABLE;
 210         pci_bus_write_config_byte(pdev->bus,
 211                                   PCI_DEVFN(0, 0), I830_CLOCK_GATE, val);
 212 }
 213
 214 static void intel_overlay_submit_request(struct intel_overlay *overlay,
 215                                          struct i915_request *rq,
 216                                          i915_gem_retire_fn retire)
 217 {
 218         GEM_BUG_ON(i915_gem_active_peek(&overlay->last_flip,
 219                                         &overlay->i915->drm.struct_mutex));
 220         i915_gem_active_set_retire_fn(&overlay->last_flip, retire,
 221                                       &overlay->i915->drm.struct_mutex);
 222         i915_gem_active_set(&overlay->last_flip, rq);
 223         i915_request_add(rq);
 224 }
 225
 226 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
 227                                          struct i915_request *rq,
 228                                          i915_gem_retire_fn retire)
 229 {
 230         intel_overlay_submit_request(overlay, rq, retire);
 231         return i915_gem_active_retire(&overlay->last_flip,
 232                                       &overlay->i915->drm.struct_mutex);
 233 }
 234
 235 static struct i915_request *alloc_request(struct intel_overlay *overlay)
 236 {
 237         struct drm_i915_private *dev_priv = overlay->i915;
 238         struct intel_engine_cs *engine = dev_priv->engine[RCS];
 239
 240         return i915_request_alloc(engine, dev_priv->kernel_context);
 241 }
 242
 243 /* overlay needs to be disable in OCMD reg */
 244 static int intel_overlay_on(struct intel_overlay *overlay)
 245 {
 246         struct drm_i915_private *dev_priv = overlay->i915;
 247         struct i915_request *rq;
 248         u32 *cs;
 249
 250         WARN_ON(overlay->active);
 251
 252         rq = alloc_request(overlay);
 253         if (IS_ERR(rq))
 254                 return PTR_ERR(rq);
 255
 256         cs = intel_ring_begin(rq, 4);
 257         if (IS_ERR(cs)) {
 258                 i915_request_add(rq);
 259                 return PTR_ERR(cs);
 260         }
 261
 262         overlay->active = true;
 263
 264         if (IS_I830(dev_priv))
 265                 i830_overlay_clock_gating(dev_priv, false);
 266
 267         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_ON;
 268         *cs++ = overlay->flip_addr | OFC_UPDATE;
 269         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 270         *cs++ = MI_NOOP;
 271         intel_ring_advance(rq, cs);
 272
 273         return intel_overlay_do_wait_request(overlay, rq, NULL);
 274 }
 275
 276 static void intel_overlay_flip_prepare(struct intel_overlay *overlay,
 277                                        struct i915_vma *vma)
 278 {
 279         enum pipe pipe = overlay->crtc->pipe;
 280
 281         WARN_ON(overlay->old_vma);
 282
 283         i915_gem_track_fb(overlay->vma ? overlay->vma->obj : NULL,
 284                           vma ? vma->obj : NULL,
 285                           INTEL_FRONTBUFFER_OVERLAY(pipe));
 286
 287         intel_frontbuffer_flip_prepare(overlay->i915,
 288                                        INTEL_FRONTBUFFER_OVERLAY(pipe));
 289
 290         overlay->old_vma = overlay->vma;
 291         if (vma)
 292                 overlay->vma = i915_vma_get(vma);
 293         else
 294                 overlay->vma = NULL;
 295 }
 296
 297 /* overlay needs to be enabled in OCMD reg */
 298 static int intel_overlay_continue(struct intel_overlay *overlay,
 299                                   struct i915_vma *vma,
 300                                   bool load_polyphase_filter)
 301 {
 302         struct drm_i915_private *dev_priv = overlay->i915;
 303         struct i915_request *rq;
 304         u32 flip_addr = overlay->flip_addr;
 305         u32 tmp, *cs;
 306
 307         WARN_ON(!overlay->active);
 308
 309         if (load_polyphase_filter)
 310                 flip_addr |= OFC_UPDATE;
 311
 312         /* check for underruns */
 313         tmp = I915_READ(DOVSTA);
 314         if (tmp & (1 << 17))
 315                 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
 316
 317         rq = alloc_request(overlay);
 318         if (IS_ERR(rq))
 319                 return PTR_ERR(rq);
 320
 321         cs = intel_ring_begin(rq, 2);
 322         if (IS_ERR(cs)) {
 323                 i915_request_add(rq);
 324                 return PTR_ERR(cs);
 325         }
 326
 327         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 328         *cs++ = flip_addr;
 329         intel_ring_advance(rq, cs);
 330
 331         intel_overlay_flip_prepare(overlay, vma);
 332
 333         intel_overlay_submit_request(overlay, rq, NULL);
 334
 335         return 0;
 336 }
 337
 338 static void intel_overlay_release_old_vma(struct intel_overlay *overlay)
 339 {
 340         struct i915_vma *vma;
 341
 342         vma = fetch_and_zero(&overlay->old_vma);
 343         if (WARN_ON(!vma))
 344                 return;
 345
 346         intel_frontbuffer_flip_complete(overlay->i915,
 347                                         INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe));
 348
 349         i915_gem_object_unpin_from_display_plane(vma);
 350         i915_vma_put(vma);
 351 }
 352
 353 static void intel_overlay_release_old_vid_tail(struct i915_gem_active *active,
 354                                                struct i915_request *rq)
 355 {
 356         struct intel_overlay *overlay =
 357                 container_of(active, typeof(*overlay), last_flip);
 358
 359         intel_overlay_release_old_vma(overlay);
 360 }
 361
 362 static void intel_overlay_off_tail(struct i915_gem_active *active,
 363                                    struct i915_request *rq)
 364 {
 365         struct intel_overlay *overlay =
 366                 container_of(active, typeof(*overlay), last_flip);
 367         struct drm_i915_private *dev_priv = overlay->i915;
 368
 369         intel_overlay_release_old_vma(overlay);
 370
 371         overlay->crtc->overlay = NULL;
 372         overlay->crtc = NULL;
 373         overlay->active = false;
 374
 375         if (IS_I830(dev_priv))
 376                 i830_overlay_clock_gating(dev_priv, true);
 377 }
 378
 379 /* overlay needs to be disabled in OCMD reg */
 380 static int intel_overlay_off(struct intel_overlay *overlay)
 381 {
 382         struct i915_request *rq;
 383         u32 *cs, flip_addr = overlay->flip_addr;
 384
 385         WARN_ON(!overlay->active);
 386
 387         /* According to intel docs the overlay hw may hang (when switching
 388          * off) without loading the filter coeffs. It is however unclear whether
 389          * this applies to the disabling of the overlay or to the switching off
 390          * of the hw. Do it in both cases */
 391         flip_addr |= OFC_UPDATE;
 392
 393         rq = alloc_request(overlay);
 394         if (IS_ERR(rq))
 395                 return PTR_ERR(rq);
 396
 397         cs = intel_ring_begin(rq, 6);
 398         if (IS_ERR(cs)) {
 399                 i915_request_add(rq);
 400                 return PTR_ERR(cs);
 401         }
 402
 403         /* wait for overlay to go idle */
 404         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE;
 405         *cs++ = flip_addr;
 406         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 407
 408         /* turn overlay off */
 409         *cs++ = MI_OVERLAY_FLIP | MI_OVERLAY_OFF;
 410         *cs++ = flip_addr;
 411         *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 412
 413         intel_ring_advance(rq, cs);
 414
 415         intel_overlay_flip_prepare(overlay, NULL);
 416
 417         return intel_overlay_do_wait_request(overlay, rq,
 418                                              intel_overlay_off_tail);
 419 }
 420
 421 /* recover from an interruption due to a signal
 422  * We have to be careful not to repeat work forever an make forward progess. */
 423 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
 424 {
 425         return i915_gem_active_retire(&overlay->last_flip,
 426                                       &overlay->i915->drm.struct_mutex);
 427 }
 428
 429 /* Wait for pending overlay flip and release old frame.
 430  * Needs to be called before the overlay register are changed
 431  * via intel_overlay_(un)map_regs
 432  */
 433 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
 434 {
 435         struct drm_i915_private *dev_priv = overlay->i915;
 436         u32 *cs;
 437         int ret;
 438
 439         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 440
 441         /* Only wait if there is actually an old frame to release to
 442          * guarantee forward progress.
 443          */
 444         if (!overlay->old_vma)
 445                 return 0;
 446
 447         if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
 448                 /* synchronous slowpath */
 449                 struct i915_request *rq;
 450
 451                 rq = alloc_request(overlay);
 452                 if (IS_ERR(rq))
 453                         return PTR_ERR(rq);
 454
 455                 cs = intel_ring_begin(rq, 2);
 456                 if (IS_ERR(cs)) {
 457                         i915_request_add(rq);
 458                         return PTR_ERR(cs);
 459                 }
 460
 461                 *cs++ = MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP;
 462                 *cs++ = MI_NOOP;
 463                 intel_ring_advance(rq, cs);
 464
 465                 ret = intel_overlay_do_wait_request(overlay, rq,
 466                                                     intel_overlay_release_old_vid_tail);
 467                 if (ret)
 468                         return ret;
 469         } else
 470                 intel_overlay_release_old_vid_tail(&overlay->last_flip, NULL);
 471
 472         return 0;
 473 }
 474
 475 void intel_overlay_reset(struct drm_i915_private *dev_priv)
 476 {
 477         struct intel_overlay *overlay = dev_priv->overlay;
 478
 479         if (!overlay)
 480                 return;
 481
 482         intel_overlay_release_old_vid(overlay);
 483
 484         overlay->old_xscale = 0;
 485         overlay->old_yscale = 0;
 486         overlay->crtc = NULL;
 487         overlay->active = false;
 488 }
 489
 490 struct put_image_params {
 491         int format;
 492         short dst_x;
 493         short dst_y;
 494         short dst_w;
 495         short dst_h;
 496         short src_w;
 497         short src_scan_h;
 498         short src_scan_w;
 499         short src_h;
 500         short stride_Y;
 501         short stride_UV;
 502         int offset_Y;
 503         int offset_U;
 504         int offset_V;
 505 };
 506
 507 static int packed_depth_bytes(u32 format)
 508 {
 509         switch (format & I915_OVERLAY_DEPTH_MASK) {
 510         case I915_OVERLAY_YUV422:
 511                 return 4;
 512         case I915_OVERLAY_YUV411:
 513                 /* return 6; not implemented */
 514         default:
 515                 return -EINVAL;
 516         }
 517 }
 518
 519 static int packed_width_bytes(u32 format, short width)
 520 {
 521         switch (format & I915_OVERLAY_DEPTH_MASK) {
 522         case I915_OVERLAY_YUV422:
 523                 return width << 1;
 524         default:
 525                 return -EINVAL;
 526         }
 527 }
 528
 529 static int uv_hsubsampling(u32 format)
 530 {
 531         switch (format & I915_OVERLAY_DEPTH_MASK) {
 532         case I915_OVERLAY_YUV422:
 533         case I915_OVERLAY_YUV420:
 534                 return 2;
 535         case I915_OVERLAY_YUV411:
 536         case I915_OVERLAY_YUV410:
 537                 return 4;
 538         default:
 539                 return -EINVAL;
 540         }
 541 }
 542
 543 static int uv_vsubsampling(u32 format)
 544 {
 545         switch (format & I915_OVERLAY_DEPTH_MASK) {
 546         case I915_OVERLAY_YUV420:
 547         case I915_OVERLAY_YUV410:
 548                 return 2;
 549         case I915_OVERLAY_YUV422:
 550         case I915_OVERLAY_YUV411:
 551                 return 1;
 552         default:
 553                 return -EINVAL;
 554         }
 555 }
 556
 557 static u32 calc_swidthsw(struct drm_i915_private *dev_priv, u32 offset, u32 width)
 558 {
 559         u32 sw;
 560
 561         if (IS_GEN2(dev_priv))
 562                 sw = ALIGN((offset & 31) + width, 32);
 563         else
 564                 sw = ALIGN((offset & 63) + width, 64);
 565
 566         if (sw == 0)
 567                 return 0;
 568
 569         return (sw - 32) >> 3;
 570 }
 571
 572 static const u16 y_static_hcoeffs[N_PHASES][N_HORIZ_Y_TAPS] = {
 573         [ 0] = { 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, },
 574         [ 1] = { 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, },
 575         [ 2] = { 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, },
 576         [ 3] = { 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, },
 577         [ 4] = { 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, },
 578         [ 5] = { 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, },
 579         [ 6] = { 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, },
 580         [ 7] = { 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, },
 581         [ 8] = { 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, },
 582         [ 9] = { 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, },
 583         [10] = { 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, },
 584         [11] = { 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, },
 585         [12] = { 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, },
 586         [13] = { 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, },
 587         [14] = { 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, },
 588         [15] = { 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, },
 589         [16] = { 0xb000, 0x3000, 0x0800, 0x3000, 0xb000, },
 590 };
 591
 592 static const u16 uv_static_hcoeffs[N_PHASES][N_HORIZ_UV_TAPS] = {
 593         [ 0] = { 0x3000, 0x1800, 0x1800, },
 594         [ 1] = { 0xb000, 0x18d0, 0x2e60, },
 595         [ 2] = { 0xb000, 0x1990, 0x2ce0, },
 596         [ 3] = { 0xb020, 0x1a68, 0x2b40, },
 597         [ 4] = { 0xb040, 0x1b20, 0x29e0, },
 598         [ 5] = { 0xb060, 0x1bd8, 0x2880, },
 599         [ 6] = { 0xb080, 0x1c88, 0x3e60, },
 600         [ 7] = { 0xb0a0, 0x1d28, 0x3c00, },
 601         [ 8] = { 0xb0c0, 0x1db8, 0x39e0, },
 602         [ 9] = { 0xb0e0, 0x1e40, 0x37e0, },
 603         [10] = { 0xb100, 0x1eb8, 0x3620, },
 604         [11] = { 0xb100, 0x1f18, 0x34a0, },
 605         [12] = { 0xb100, 0x1f68, 0x3360, },
 606         [13] = { 0xb0e0, 0x1fa8, 0x3240, },
 607         [14] = { 0xb0c0, 0x1fe0, 0x3140, },
 608         [15] = { 0xb060, 0x1ff0, 0x30a0, },
 609         [16] = { 0x3000, 0x0800, 0x3000, },
 610 };
 611
 612 static void update_polyphase_filter(struct overlay_registers __iomem *regs)
 613 {
 614         memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
 615         memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs,
 616                     sizeof(uv_static_hcoeffs));
 617 }
 618
 619 static bool update_scaling_factors(struct intel_overlay *overlay,
 620                                    struct overlay_registers __iomem *regs,
 621                                    struct put_image_params *params)
 622 {
 623         /* fixed point with a 12 bit shift */
 624         u32 xscale, yscale, xscale_UV, yscale_UV;
 625 #define FP_SHIFT 12
 626 #define FRACT_MASK 0xfff
 627         bool scale_changed = false;
 628         int uv_hscale = uv_hsubsampling(params->format);
 629         int uv_vscale = uv_vsubsampling(params->format);
 630
 631         if (params->dst_w > 1)
 632                 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
 633                         /(params->dst_w);
 634         else
 635                 xscale = 1 << FP_SHIFT;
 636
 637         if (params->dst_h > 1)
 638                 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
 639                         /(params->dst_h);
 640         else
 641                 yscale = 1 << FP_SHIFT;
 642
 643         /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
 644         xscale_UV = xscale/uv_hscale;
 645         yscale_UV = yscale/uv_vscale;
 646         /* make the Y scale to UV scale ratio an exact multiply */
 647         xscale = xscale_UV * uv_hscale;
 648         yscale = yscale_UV * uv_vscale;
 649         /*} else {
 650           xscale_UV = 0;
 651           yscale_UV = 0;
 652           }*/
 653
 654         if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
 655                 scale_changed = true;
 656         overlay->old_xscale = xscale;
 657         overlay->old_yscale = yscale;
 658
 659         iowrite32(((yscale & FRACT_MASK) << 20) |
 660                   ((xscale >> FP_SHIFT)  << 16) |
 661                   ((xscale & FRACT_MASK) << 3),
 662                  &regs->YRGBSCALE);
 663
 664         iowrite32(((yscale_UV & FRACT_MASK) << 20) |
 665                   ((xscale_UV >> FP_SHIFT)  << 16) |
 666                   ((xscale_UV & FRACT_MASK) << 3),
 667                  &regs->UVSCALE);
 668
 669         iowrite32((((yscale    >> FP_SHIFT) << 16) |
 670                    ((yscale_UV >> FP_SHIFT) << 0)),
 671                  &regs->UVSCALEV);
 672
 673         if (scale_changed)
 674                 update_polyphase_filter(regs);
 675
 676         return scale_changed;
 677 }
 678
 679 static void update_colorkey(struct intel_overlay *overlay,
 680                             struct overlay_registers __iomem *regs)
 681 {
 682         const struct intel_plane_state *state =
 683                 to_intel_plane_state(overlay->crtc->base.primary->state);
 684         u32 key = overlay->color_key;
 685         u32 format = 0;
 686         u32 flags = 0;
 687
 688         if (overlay->color_key_enabled)
 689                 flags |= DST_KEY_ENABLE;
 690
 691         if (state->base.visible)
 692                 format = state->base.fb->format->format;
 693
 694         switch (format) {
 695         case DRM_FORMAT_C8:
 696                 key = 0;
 697                 flags |= CLK_RGB8I_MASK;
 698                 break;
 699         case DRM_FORMAT_XRGB1555:
 700                 key = RGB15_TO_COLORKEY(key);
 701                 flags |= CLK_RGB15_MASK;
 702                 break;
 703         case DRM_FORMAT_RGB565:
 704                 key = RGB16_TO_COLORKEY(key);
 705                 flags |= CLK_RGB16_MASK;
 706                 break;
 707         default:
 708                 flags |= CLK_RGB24_MASK;
 709                 break;
 710         }
 711
 712         iowrite32(key, &regs->DCLRKV);
 713         iowrite32(flags, &regs->DCLRKM);
 714 }
 715
 716 static u32 overlay_cmd_reg(struct put_image_params *params)
 717 {
 718         u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
 719
 720         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 721                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 722                 case I915_OVERLAY_YUV422:
 723                         cmd |= OCMD_YUV_422_PLANAR;
 724                         break;
 725                 case I915_OVERLAY_YUV420:
 726                         cmd |= OCMD_YUV_420_PLANAR;
 727                         break;
 728                 case I915_OVERLAY_YUV411:
 729                 case I915_OVERLAY_YUV410:
 730                         cmd |= OCMD_YUV_410_PLANAR;
 731                         break;
 732                 }
 733         } else { /* YUV packed */
 734                 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
 735                 case I915_OVERLAY_YUV422:
 736                         cmd |= OCMD_YUV_422_PACKED;
 737                         break;
 738                 case I915_OVERLAY_YUV411:
 739                         cmd |= OCMD_YUV_411_PACKED;
 740                         break;
 741                 }
 742
 743                 switch (params->format & I915_OVERLAY_SWAP_MASK) {
 744                 case I915_OVERLAY_NO_SWAP:
 745                         break;
 746                 case I915_OVERLAY_UV_SWAP:
 747                         cmd |= OCMD_UV_SWAP;
 748                         break;
 749                 case I915_OVERLAY_Y_SWAP:
 750                         cmd |= OCMD_Y_SWAP;
 751                         break;
 752                 case I915_OVERLAY_Y_AND_UV_SWAP:
 753                         cmd |= OCMD_Y_AND_UV_SWAP;
 754                         break;
 755                 }
 756         }
 757
 758         return cmd;
 759 }
 760
 761 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
 762                                       struct drm_i915_gem_object *new_bo,
 763                                       struct put_image_params *params)
 764 {
 765         struct overlay_registers __iomem *regs = overlay->regs;
 766         struct drm_i915_private *dev_priv = overlay->i915;
 767         u32 swidth, swidthsw, sheight, ostride;
 768         enum pipe pipe = overlay->crtc->pipe;
 769         bool scale_changed = false;
 770         struct i915_vma *vma;
 771         int ret, tmp_width;
 772
 773         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 774         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 775
 776         ret = intel_overlay_release_old_vid(overlay);
 777         if (ret != 0)
 778                 return ret;
 779
 780         atomic_inc(&dev_priv->gpu_error.pending_fb_pin);
 781
 782         vma = i915_gem_object_pin_to_display_plane(new_bo,
 783                                                    0, NULL, PIN_MAPPABLE);
 784         if (IS_ERR(vma)) {
 785                 ret = PTR_ERR(vma);
 786                 goto out_pin_section;
 787         }
 788         intel_fb_obj_flush(new_bo, ORIGIN_DIRTYFB);
 789
 790         ret = i915_vma_put_fence(vma);
 791         if (ret)
 792                 goto out_unpin;
 793
 794         if (!overlay->active) {
 795                 u32 oconfig;
 796
 797                 oconfig = OCONF_CC_OUT_8BIT;
 798                 if (IS_GEN4(dev_priv))
 799                         oconfig |= OCONF_CSC_MODE_BT709;
 800                 oconfig |= pipe == 0 ?
 801                         OCONF_PIPE_A : OCONF_PIPE_B;
 802                 iowrite32(oconfig, &regs->OCONFIG);
 803
 804                 ret = intel_overlay_on(overlay);
 805                 if (ret != 0)
 806                         goto out_unpin;
 807         }
 808
 809         iowrite32((params->dst_y << 16) | params->dst_x, &regs->DWINPOS);
 810         iowrite32((params->dst_h << 16) | params->dst_w, &regs->DWINSZ);
 811
 812         if (params->format & I915_OVERLAY_YUV_PACKED)
 813                 tmp_width = packed_width_bytes(params->format, params->src_w);
 814         else
 815                 tmp_width = params->src_w;
 816
 817         swidth = params->src_w;
 818         swidthsw = calc_swidthsw(dev_priv, params->offset_Y, tmp_width);
 819         sheight = params->src_h;
 820         iowrite32(i915_ggtt_offset(vma) + params->offset_Y, &regs->OBUF_0Y);
 821         ostride = params->stride_Y;
 822
 823         if (params->format & I915_OVERLAY_YUV_PLANAR) {
 824                 int uv_hscale = uv_hsubsampling(params->format);
 825                 int uv_vscale = uv_vsubsampling(params->format);
 826                 u32 tmp_U, tmp_V;
 827                 swidth |= (params->src_w/uv_hscale) << 16;
 828                 tmp_U = calc_swidthsw(dev_priv, params->offset_U,
 829                                       params->src_w/uv_hscale);
 830                 tmp_V = calc_swidthsw(dev_priv, params->offset_V,
 831                                       params->src_w/uv_hscale);
 832                 swidthsw |= max_t(u32, tmp_U, tmp_V) << 16;
 833                 sheight |= (params->src_h/uv_vscale) << 16;
 834                 iowrite32(i915_ggtt_offset(vma) + params->offset_U,
 835                           &regs->OBUF_0U);
 836                 iowrite32(i915_ggtt_offset(vma) + params->offset_V,
 837                           &regs->OBUF_0V);
 838                 ostride |= params->stride_UV << 16;
 839         }
 840
 841         iowrite32(swidth, &regs->SWIDTH);
 842         iowrite32(swidthsw, &regs->SWIDTHSW);
 843         iowrite32(sheight, &regs->SHEIGHT);
 844         iowrite32(ostride, &regs->OSTRIDE);
 845
 846         scale_changed = update_scaling_factors(overlay, regs, params);
 847
 848         update_colorkey(overlay, regs);
 849
 850         iowrite32(overlay_cmd_reg(params), &regs->OCMD);
 851
 852         ret = intel_overlay_continue(overlay, vma, scale_changed);
 853         if (ret)
 854                 goto out_unpin;
 855
 856         return 0;
 857
 858 out_unpin:
 859         i915_gem_object_unpin_from_display_plane(vma);
 860 out_pin_section:
 861         atomic_dec(&dev_priv->gpu_error.pending_fb_pin);
 862
 863         return ret;
 864 }
 865
 866 int intel_overlay_switch_off(struct intel_overlay *overlay)
 867 {
 868         struct drm_i915_private *dev_priv = overlay->i915;
 869         int ret;
 870
 871         lockdep_assert_held(&dev_priv->drm.struct_mutex);
 872         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
 873
 874         ret = intel_overlay_recover_from_interrupt(overlay);
 875         if (ret != 0)
 876                 return ret;
 877
 878         if (!overlay->active)
 879                 return 0;
 880
 881         ret = intel_overlay_release_old_vid(overlay);
 882         if (ret != 0)
 883                 return ret;
 884
 885         iowrite32(0, &overlay->regs->OCMD);
 886
 887         return intel_overlay_off(overlay);
 888 }
 889
 890 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
 891                                           struct intel_crtc *crtc)
 892 {
 893         if (!crtc->active)
 894                 return -EINVAL;
 895
 896         /* can't use the overlay with double wide pipe */
 897         if (crtc->config->double_wide)
 898                 return -EINVAL;
 899
 900         return 0;
 901 }
 902
 903 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
 904 {
 905         struct drm_i915_private *dev_priv = overlay->i915;
 906         u32 pfit_control = I915_READ(PFIT_CONTROL);
 907         u32 ratio;
 908
 909         /* XXX: This is not the same logic as in the xorg driver, but more in
 910          * line with the intel documentation for the i965
 911          */
 912         if (INTEL_GEN(dev_priv) >= 4) {
 913                 /* on i965 use the PGM reg to read out the autoscaler values */
 914                 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
 915         } else {
 916                 if (pfit_control & VERT_AUTO_SCALE)
 917                         ratio = I915_READ(PFIT_AUTO_RATIOS);
 918                 else
 919                         ratio = I915_READ(PFIT_PGM_RATIOS);
 920                 ratio >>= PFIT_VERT_SCALE_SHIFT;
 921         }
 922
 923         overlay->pfit_vscale_ratio = ratio;
 924 }
 925
 926 static int check_overlay_dst(struct intel_overlay *overlay,
 927                              struct drm_intel_overlay_put_image *rec)
 928 {
 929         const struct intel_crtc_state *pipe_config =
 930                 overlay->crtc->config;
 931
 932         if (rec->dst_x < pipe_config->pipe_src_w &&
 933             rec->dst_x + rec->dst_width <= pipe_config->pipe_src_w &&
 934             rec->dst_y < pipe_config->pipe_src_h &&
 935             rec->dst_y + rec->dst_height <= pipe_config->pipe_src_h)
 936                 return 0;
 937         else
 938                 return -EINVAL;
 939 }
 940
 941 static int check_overlay_scaling(struct put_image_params *rec)
 942 {
 943         u32 tmp;
 944
 945         /* downscaling limit is 8.0 */
 946         tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
 947         if (tmp > 7)
 948                 return -EINVAL;
 949         tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
 950         if (tmp > 7)
 951                 return -EINVAL;
 952
 953         return 0;
 954 }
 955
 956 static int check_overlay_src(struct drm_i915_private *dev_priv,
 957                              struct drm_intel_overlay_put_image *rec,
 958                              struct drm_i915_gem_object *new_bo)
 959 {
 960         int uv_hscale = uv_hsubsampling(rec->flags);
 961         int uv_vscale = uv_vsubsampling(rec->flags);
 962         u32 stride_mask;
 963         int depth;
 964         u32 tmp;
 965
 966         /* check src dimensions */
 967         if (IS_I845G(dev_priv) || IS_I830(dev_priv)) {
 968                 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
 969                     rec->src_width  > IMAGE_MAX_WIDTH_LEGACY)
 970                         return -EINVAL;
 971         } else {
 972                 if (rec->src_height > IMAGE_MAX_HEIGHT ||
 973                     rec->src_width  > IMAGE_MAX_WIDTH)
 974                         return -EINVAL;
 975         }
 976
 977         /* better safe than sorry, use 4 as the maximal subsampling ratio */
 978         if (rec->src_height < N_VERT_Y_TAPS*4 ||
 979             rec->src_width  < N_HORIZ_Y_TAPS*4)
 980                 return -EINVAL;
 981
 982         /* check alignment constraints */
 983         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
 984         case I915_OVERLAY_RGB:
 985                 /* not implemented */
 986                 return -EINVAL;
 987
 988         case I915_OVERLAY_YUV_PACKED:
 989                 if (uv_vscale != 1)
 990                         return -EINVAL;
 991
 992                 depth = packed_depth_bytes(rec->flags);
 993                 if (depth < 0)
 994                         return depth;
 995
 996                 /* ignore UV planes */
 997                 rec->stride_UV = 0;
 998                 rec->offset_U = 0;
 999                 rec->offset_V = 0;
1000                 /* check pixel alignment */
1001                 if (rec->offset_Y % depth)
1002                         return -EINVAL;
1003                 break;
1004
1005         case I915_OVERLAY_YUV_PLANAR:
1006                 if (uv_vscale < 0 || uv_hscale < 0)
1007                         return -EINVAL;
1008                 /* no offset restrictions for planar formats */
1009                 break;
1010
1011         default:
1012                 return -EINVAL;
1013         }
1014
1015         if (rec->src_width % uv_hscale)
1016                 return -EINVAL;
1017
1018         /* stride checking */
1019         if (IS_I830(dev_priv) || IS_I845G(dev_priv))
1020                 stride_mask = 255;
1021         else
1022                 stride_mask = 63;
1023
1024         if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1025                 return -EINVAL;
1026         if (IS_GEN4(dev_priv) && rec->stride_Y < 512)
1027                 return -EINVAL;
1028
1029         tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1030                 4096 : 8192;
1031         if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1032                 return -EINVAL;
1033
1034         /* check buffer dimensions */
1035         switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1036         case I915_OVERLAY_RGB:
1037         case I915_OVERLAY_YUV_PACKED:
1038                 /* always 4 Y values per depth pixels */
1039                 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1040                         return -EINVAL;
1041
1042                 tmp = rec->stride_Y*rec->src_height;
1043                 if (rec->offset_Y + tmp > new_bo->base.size)
1044                         return -EINVAL;
1045                 break;
1046
1047         case I915_OVERLAY_YUV_PLANAR:
1048                 if (rec->src_width > rec->stride_Y)
1049                         return -EINVAL;
1050                 if (rec->src_width/uv_hscale > rec->stride_UV)
1051                         return -EINVAL;
1052
1053                 tmp = rec->stride_Y * rec->src_height;
1054                 if (rec->offset_Y + tmp > new_bo->base.size)
1055                         return -EINVAL;
1056
1057                 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1058                 if (rec->offset_U + tmp > new_bo->base.size ||
1059                     rec->offset_V + tmp > new_bo->base.size)
1060                         return -EINVAL;
1061                 break;
1062         }
1063
1064         return 0;
1065 }
1066
1067 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1068                                   struct drm_file *file_priv)
1069 {
1070         struct drm_intel_overlay_put_image *put_image_rec = data;
1071         struct drm_i915_private *dev_priv = to_i915(dev);
1072         struct intel_overlay *overlay;
1073         struct drm_crtc *drmmode_crtc;
1074         struct intel_crtc *crtc;
1075         struct drm_i915_gem_object *new_bo;
1076         struct put_image_params *params;
1077         int ret;
1078
1079         overlay = dev_priv->overlay;
1080         if (!overlay) {
1081                 DRM_DEBUG("userspace bug: no overlay\n");
1082                 return -ENODEV;
1083         }
1084
1085         if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1086                 drm_modeset_lock_all(dev);
1087                 mutex_lock(&dev->struct_mutex);
1088
1089                 ret = intel_overlay_switch_off(overlay);
1090
1091                 mutex_unlock(&dev->struct_mutex);
1092                 drm_modeset_unlock_all(dev);
1093
1094                 return ret;
1095         }
1096
1097         params = kmalloc(sizeof(*params), GFP_KERNEL);
1098         if (!params)
1099                 return -ENOMEM;
1100
1101         drmmode_crtc = drm_crtc_find(dev, file_priv, put_image_rec->crtc_id);
1102         if (!drmmode_crtc) {
1103                 ret = -ENOENT;
1104                 goto out_free;
1105         }
1106         crtc = to_intel_crtc(drmmode_crtc);
1107
1108         new_bo = i915_gem_object_lookup(file_priv, put_image_rec->bo_handle);
1109         if (!new_bo) {
1110                 ret = -ENOENT;
1111                 goto out_free;
1112         }
1113
1114         drm_modeset_lock_all(dev);
1115         mutex_lock(&dev->struct_mutex);
1116
1117         if (i915_gem_object_is_tiled(new_bo)) {
1118                 DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n");
1119                 ret = -EINVAL;
1120                 goto out_unlock;
1121         }
1122
1123         ret = intel_overlay_recover_from_interrupt(overlay);
1124         if (ret != 0)
1125                 goto out_unlock;
1126
1127         if (overlay->crtc != crtc) {
1128                 ret = intel_overlay_switch_off(overlay);
1129                 if (ret != 0)
1130                         goto out_unlock;
1131
1132                 ret = check_overlay_possible_on_crtc(overlay, crtc);
1133                 if (ret != 0)
1134                         goto out_unlock;
1135
1136                 overlay->crtc = crtc;
1137                 crtc->overlay = overlay;
1138
1139                 /* line too wide, i.e. one-line-mode */
1140                 if (crtc->config->pipe_src_w > 1024 &&
1141                     crtc->config->gmch_pfit.control & PFIT_ENABLE) {
1142                         overlay->pfit_active = true;
1143                         update_pfit_vscale_ratio(overlay);
1144                 } else
1145                         overlay->pfit_active = false;
1146         }
1147
1148         ret = check_overlay_dst(overlay, put_image_rec);
1149         if (ret != 0)
1150                 goto out_unlock;
1151
1152         if (overlay->pfit_active) {
1153                 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1154                                  overlay->pfit_vscale_ratio);
1155                 /* shifting right rounds downwards, so add 1 */
1156                 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1157                                  overlay->pfit_vscale_ratio) + 1;
1158         } else {
1159                 params->dst_y = put_image_rec->dst_y;
1160                 params->dst_h = put_image_rec->dst_height;
1161         }
1162         params->dst_x = put_image_rec->dst_x;
1163         params->dst_w = put_image_rec->dst_width;
1164
1165         params->src_w = put_image_rec->src_width;
1166         params->src_h = put_image_rec->src_height;
1167         params->src_scan_w = put_image_rec->src_scan_width;
1168         params->src_scan_h = put_image_rec->src_scan_height;
1169         if (params->src_scan_h > params->src_h ||
1170             params->src_scan_w > params->src_w) {
1171                 ret = -EINVAL;
1172                 goto out_unlock;
1173         }
1174
1175         ret = check_overlay_src(dev_priv, put_image_rec, new_bo);
1176         if (ret != 0)
1177                 goto out_unlock;
1178         params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1179         params->stride_Y = put_image_rec->stride_Y;
1180         params->stride_UV = put_image_rec->stride_UV;
1181         params->offset_Y = put_image_rec->offset_Y;
1182         params->offset_U = put_image_rec->offset_U;
1183         params->offset_V = put_image_rec->offset_V;
1184
1185         /* Check scaling after src size to prevent a divide-by-zero. */
1186         ret = check_overlay_scaling(params);
1187         if (ret != 0)
1188                 goto out_unlock;
1189
1190         ret = intel_overlay_do_put_image(overlay, new_bo, params);
1191         if (ret != 0)
1192                 goto out_unlock;
1193
1194         mutex_unlock(&dev->struct_mutex);
1195         drm_modeset_unlock_all(dev);
1196         i915_gem_object_put(new_bo);
1197
1198         kfree(params);
1199
1200         return 0;
1201
1202 out_unlock:
1203         mutex_unlock(&dev->struct_mutex);
1204         drm_modeset_unlock_all(dev);
1205         i915_gem_object_put(new_bo);
1206 out_free:
1207         kfree(params);
1208
1209         return ret;
1210 }
1211
1212 static void update_reg_attrs(struct intel_overlay *overlay,
1213                              struct overlay_registers __iomem *regs)
1214 {
1215         iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff),
1216                   &regs->OCLRC0);
1217         iowrite32(overlay->saturation, &regs->OCLRC1);
1218 }
1219
1220 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1221 {
1222         int i;
1223
1224         if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1225                 return false;
1226
1227         for (i = 0; i < 3; i++) {
1228                 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1229                         return false;
1230         }
1231
1232         return true;
1233 }
1234
1235 static bool check_gamma5_errata(u32 gamma5)
1236 {
1237         int i;
1238
1239         for (i = 0; i < 3; i++) {
1240                 if (((gamma5 >> i*8) & 0xff) == 0x80)
1241                         return false;
1242         }
1243
1244         return true;
1245 }
1246
1247 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1248 {
1249         if (!check_gamma_bounds(0, attrs->gamma0) ||
1250             !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1251             !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1252             !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1253             !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1254             !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1255             !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1256                 return -EINVAL;
1257
1258         if (!check_gamma5_errata(attrs->gamma5))
1259                 return -EINVAL;
1260
1261         return 0;
1262 }
1263
1264 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1265                               struct drm_file *file_priv)
1266 {
1267         struct drm_intel_overlay_attrs *attrs = data;
1268         struct drm_i915_private *dev_priv = to_i915(dev);
1269         struct intel_overlay *overlay;
1270         int ret;
1271
1272         overlay = dev_priv->overlay;
1273         if (!overlay) {
1274                 DRM_DEBUG("userspace bug: no overlay\n");
1275                 return -ENODEV;
1276         }
1277
1278         drm_modeset_lock_all(dev);
1279         mutex_lock(&dev->struct_mutex);
1280
1281         ret = -EINVAL;
1282         if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1283                 attrs->color_key  = overlay->color_key;
1284                 attrs->brightness = overlay->brightness;
1285                 attrs->contrast   = overlay->contrast;
1286                 attrs->saturation = overlay->saturation;
1287
1288                 if (!IS_GEN2(dev_priv)) {
1289                         attrs->gamma0 = I915_READ(OGAMC0);
1290                         attrs->gamma1 = I915_READ(OGAMC1);
1291                         attrs->gamma2 = I915_READ(OGAMC2);
1292                         attrs->gamma3 = I915_READ(OGAMC3);
1293                         attrs->gamma4 = I915_READ(OGAMC4);
1294                         attrs->gamma5 = I915_READ(OGAMC5);
1295                 }
1296         } else {
1297                 if (attrs->brightness < -128 || attrs->brightness > 127)
1298                         goto out_unlock;
1299                 if (attrs->contrast > 255)
1300                         goto out_unlock;
1301                 if (attrs->saturation > 1023)
1302                         goto out_unlock;
1303
1304                 overlay->color_key  = attrs->color_key;
1305                 overlay->brightness = attrs->brightness;
1306                 overlay->contrast   = attrs->contrast;
1307                 overlay->saturation = attrs->saturation;
1308
1309                 update_reg_attrs(overlay, overlay->regs);
1310
1311                 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1312                         if (IS_GEN2(dev_priv))
1313                                 goto out_unlock;
1314
1315                         if (overlay->active) {
1316                                 ret = -EBUSY;
1317                                 goto out_unlock;
1318                         }
1319
1320                         ret = check_gamma(attrs);
1321                         if (ret)
1322                                 goto out_unlock;
1323
1324                         I915_WRITE(OGAMC0, attrs->gamma0);
1325                         I915_WRITE(OGAMC1, attrs->gamma1);
1326                         I915_WRITE(OGAMC2, attrs->gamma2);
1327                         I915_WRITE(OGAMC3, attrs->gamma3);
1328                         I915_WRITE(OGAMC4, attrs->gamma4);
1329                         I915_WRITE(OGAMC5, attrs->gamma5);
1330                 }
1331         }
1332         overlay->color_key_enabled = (attrs->flags & I915_OVERLAY_DISABLE_DEST_COLORKEY) == 0;
1333
1334         ret = 0;
1335 out_unlock:
1336         mutex_unlock(&dev->struct_mutex);
1337         drm_modeset_unlock_all(dev);
1338
1339         return ret;
1340 }
1341
1342 static int get_registers(struct intel_overlay *overlay, bool use_phys)
1343 {
1344         struct drm_i915_gem_object *obj;
1345         struct i915_vma *vma;
1346         int err;
1347
1348         obj = i915_gem_object_create_stolen(overlay->i915, PAGE_SIZE);
1349         if (obj == NULL)
1350                 obj = i915_gem_object_create_internal(overlay->i915, PAGE_SIZE);
1351         if (IS_ERR(obj))
1352                 return PTR_ERR(obj);
1353
1354         vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE);
1355         if (IS_ERR(vma)) {
1356                 err = PTR_ERR(vma);
1357                 goto err_put_bo;
1358         }
1359
1360         if (use_phys)
1361                 overlay->flip_addr = sg_dma_address(obj->mm.pages->sgl);
1362         else
1363                 overlay->flip_addr = i915_ggtt_offset(vma);
1364         overlay->regs = i915_vma_pin_iomap(vma);
1365         i915_vma_unpin(vma);
1366
1367         if (IS_ERR(overlay->regs)) {
1368                 err = PTR_ERR(overlay->regs);
1369                 goto err_put_bo;
1370         }
1371
1372         overlay->reg_bo = obj;
1373         return 0;
1374
1375 err_put_bo:
1376         i915_gem_object_put(obj);
1377         return err;
1378 }
1379
1380 void intel_setup_overlay(struct drm_i915_private *dev_priv)
1381 {
1382         struct intel_overlay *overlay;
1383         int ret;
1384
1385         if (!HAS_OVERLAY(dev_priv))
1386                 return;
1387
1388         overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
1389         if (!overlay)
1390                 return;
1391
1392         overlay->i915 = dev_priv;
1393
1394         overlay->color_key = 0x0101fe;
1395         overlay->color_key_enabled = true;
1396         overlay->brightness = -19;
1397         overlay->contrast = 75;
1398         overlay->saturation = 146;
1399
1400         init_request_active(&overlay->last_flip, NULL);
1401
1402         mutex_lock(&dev_priv->drm.struct_mutex);
1403
1404         ret = get_registers(overlay, OVERLAY_NEEDS_PHYSICAL(dev_priv));
1405         if (ret)
1406                 goto out_free;
1407
1408         ret = i915_gem_object_set_to_gtt_domain(overlay->reg_bo, true);
1409         if (ret)
1410                 goto out_reg_bo;
1411
1412         mutex_unlock(&dev_priv->drm.struct_mutex);
1413
1414         memset_io(overlay->regs, 0, sizeof(struct overlay_registers));
1415         update_polyphase_filter(overlay->regs);
1416         update_reg_attrs(overlay, overlay->regs);
1417
1418         dev_priv->overlay = overlay;
1419         DRM_INFO("Initialized overlay support.\n");
1420         return;
1421
1422 out_reg_bo:
1423         i915_gem_object_put(overlay->reg_bo);
1424 out_free:
1425         mutex_unlock(&dev_priv->drm.struct_mutex);
1426         kfree(overlay);
1427 }
1428
1429 void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
1430 {
1431         struct intel_overlay *overlay;
1432
1433         overlay = fetch_and_zero(&dev_priv->overlay);
1434         if (!overlay)
1435                 return;
1436
1437         /*
1438          * The bo's should be free'd by the generic code already.
1439          * Furthermore modesetting teardown happens beforehand so the
1440          * hardware should be off already.
1441          */
1442         WARN_ON(overlay->active);
1443
1444         i915_gem_object_put(overlay->reg_bo);
1445
1446         kfree(overlay);
1447 }
1448
1449 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1450
1451 struct intel_overlay_error_state {
1452         struct overlay_registers regs;
1453         unsigned long base;
1454         u32 dovsta;
1455         u32 isr;
1456 };
1457
1458 struct intel_overlay_error_state *
1459 intel_overlay_capture_error_state(struct drm_i915_private *dev_priv)
1460 {
1461         struct intel_overlay *overlay = dev_priv->overlay;
1462         struct intel_overlay_error_state *error;
1463
1464         if (!overlay || !overlay->active)
1465                 return NULL;
1466
1467         error = kmalloc(sizeof(*error), GFP_ATOMIC);
1468         if (error == NULL)
1469                 return NULL;
1470
1471         error->dovsta = I915_READ(DOVSTA);
1472         error->isr = I915_READ(ISR);
1473         error->base = overlay->flip_addr;
1474
1475         memcpy_fromio(&error->regs, overlay->regs, sizeof(error->regs));
1476
1477         return error;
1478 }
1479
1480 void
1481 intel_overlay_print_error_state(struct drm_i915_error_state_buf *m,
1482                                 struct intel_overlay_error_state *error)
1483 {
1484         i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1485                           error->dovsta, error->isr);
1486         i915_error_printf(m, "  Register file at 0x%08lx:\n",
1487                           error->base);
1488
1489 #define P(x) i915_error_printf(m, "    " #x ":  0x%08x\n", error->regs.x)
1490         P(OBUF_0Y);
1491         P(OBUF_1Y);
1492         P(OBUF_0U);
1493         P(OBUF_0V);
1494         P(OBUF_1U);
1495         P(OBUF_1V);
1496         P(OSTRIDE);
1497         P(YRGB_VPH);
1498         P(UV_VPH);
1499         P(HORZ_PH);
1500         P(INIT_PHS);
1501         P(DWINPOS);
1502         P(DWINSZ);
1503         P(SWIDTH);
1504         P(SWIDTHSW);
1505         P(SHEIGHT);
1506         P(YRGBSCALE);
1507         P(UVSCALE);
1508         P(OCLRC0);
1509         P(OCLRC1);
1510         P(DCLRKV);
1511         P(DCLRKM);
1512         P(SCLRKVH);
1513         P(SCLRKVL);
1514         P(SCLRKEN);
1515         P(OCONFIG);
1516         P(OCMD);
1517         P(OSTART_0Y);
1518         P(OSTART_1Y);
1519         P(OSTART_0U);
1520         P(OSTART_0V);
1521         P(OSTART_1U);
1522         P(OSTART_1V);
1523         P(OTILEOFF_0Y);
1524         P(OTILEOFF_1Y);
1525         P(OTILEOFF_0U);
1526         P(OTILEOFF_0V);
1527         P(OTILEOFF_1U);
1528         P(OTILEOFF_1V);
1529         P(FASTHSCALE);
1530         P(UVSCALEV);
1531 #undef P
1532 }
1533
1534 #endif