2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
25 * Michel Thierry <michel.thierry@intel.com>
26 * Thomas Daniel <thomas.daniel@intel.com>
27 * Oscar Mateo <oscar.mateo@intel.com>
32 * DOC: Logical Rings, Logical Ring Contexts and Execlists
35 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
36 * These expanded contexts enable a number of new abilities, especially
37 * "Execlists" (also implemented in this file).
39 * One of the main differences with the legacy HW contexts is that logical
40 * ring contexts incorporate many more things to the context's state, like
41 * PDPs or ringbuffer control registers:
43 * The reason why PDPs are included in the context is straightforward: as
44 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
45 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
46 * instead, the GPU will do it for you on the context switch.
48 * But, what about the ringbuffer control registers (head, tail, etc..)?
49 * shouldn't we just need a set of those per engine command streamer? This is
50 * where the name "Logical Rings" starts to make sense: by virtualizing the
51 * rings, the engine cs shifts to a new "ring buffer" with every context
52 * switch. When you want to submit a workload to the GPU you: A) choose your
53 * context, B) find its appropriate virtualized ring, C) write commands to it
54 * and then, finally, D) tell the GPU to switch to that context.
56 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
57 * to a contexts is via a context execution list, ergo "Execlists".
60 * Regarding the creation of contexts, we have:
62 * - One global default context.
63 * - One local default context for each opened fd.
64 * - One local extra context for each context create ioctl call.
66 * Now that ringbuffers belong per-context (and not per-engine, like before)
67 * and that contexts are uniquely tied to a given engine (and not reusable,
68 * like before) we need:
70 * - One ringbuffer per-engine inside each context.
71 * - One backing object per-engine inside each context.
73 * The global default context starts its life with these new objects fully
74 * allocated and populated. The local default context for each opened fd is
75 * more complex, because we don't know at creation time which engine is going
76 * to use them. To handle this, we have implemented a deferred creation of LR
79 * The local context starts its life as a hollow or blank holder, that only
80 * gets populated for a given engine once we receive an execbuffer. If later
81 * on we receive another execbuffer ioctl for the same context but a different
82 * engine, we allocate/populate a new ringbuffer and context backing object and
85 * Finally, regarding local contexts created using the ioctl call: as they are
86 * only allowed with the render ring, we can allocate & populate them right
87 * away (no need to defer anything, at least for now).
89 * Execlists implementation:
90 * Execlists are the new method by which, on gen8+ hardware, workloads are
91 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
92 * This method works as follows:
94 * When a request is committed, its commands (the BB start and any leading or
95 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
96 * for the appropriate context. The tail pointer in the hardware context is not
97 * updated at this time, but instead, kept by the driver in the ringbuffer
98 * structure. A structure representing this request is added to a request queue
99 * for the appropriate engine: this structure contains a copy of the context's
100 * tail after the request was written to the ring buffer and a pointer to the
103 * If the engine's request queue was empty before the request was added, the
104 * queue is processed immediately. Otherwise the queue will be processed during
105 * a context switch interrupt. In any case, elements on the queue will get sent
106 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
107 * globally unique 20-bits submission ID.
109 * When execution of a request completes, the GPU updates the context status
110 * buffer with a context complete event and generates a context switch interrupt.
111 * During the interrupt handling, the driver examines the events in the buffer:
112 * for each context complete event, if the announced ID matches that on the head
113 * of the request queue, then that request is retired and removed from the queue.
115 * After processing, if any requests were retired and the queue is not empty
116 * then a new execution list can be submitted. The two requests at the front of
117 * the queue are next to be submitted but since a context may not occur twice in
118 * an execution list, if subsequent requests have the same ID as the first then
119 * the two requests must be combined. This is done simply by discarding requests
120 * at the head of the queue until either only one requests is left (in which case
121 * we use a NULL second context) or the first two requests have unique IDs.
123 * By always executing the first two requests in the queue the driver ensures
124 * that the GPU is kept as busy as possible. In the case where a single context
125 * completes but a second context is still executing, the request for this second
126 * context will be at the head of the queue when we remove the first one. This
127 * request will then be resubmitted along with a new request for a different context,
128 * which will cause the hardware to continue executing the second request and queue
129 * the new request (the GPU detects the condition of a context getting preempted
130 * with the same context and optimizes the context switch flow by not doing
131 * preemption, but just sampling the new tail pointer).
134 #include <linux/interrupt.h>
136 #include <drm/drmP.h>
137 #include <drm/i915_drm.h>
138 #include "i915_drv.h"
139 #include "i915_gem_render_state.h"
140 #include "i915_vgpu.h"
141 #include "intel_lrc_reg.h"
142 #include "intel_mocs.h"
143 #include "intel_workarounds.h"
145 #define RING_EXECLIST_QFULL (1 << 0x2)
146 #define RING_EXECLIST1_VALID (1 << 0x3)
147 #define RING_EXECLIST0_VALID (1 << 0x4)
148 #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE)
149 #define RING_EXECLIST1_ACTIVE (1 << 0x11)
150 #define RING_EXECLIST0_ACTIVE (1 << 0x12)
152 #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0)
153 #define GEN8_CTX_STATUS_PREEMPTED (1 << 1)
154 #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2)
155 #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3)
156 #define GEN8_CTX_STATUS_COMPLETE (1 << 4)
157 #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15)
159 #define GEN8_CTX_STATUS_COMPLETED_MASK \
160 (GEN8_CTX_STATUS_COMPLETE | GEN8_CTX_STATUS_PREEMPTED)
162 /* Typical size of the average request (2 pipecontrols and a MI_BB) */
163 #define EXECLISTS_REQUEST_SIZE 64 /* bytes */
164 #define WA_TAIL_DWORDS 2
165 #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS)
167 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
168 struct intel_engine_cs *engine,
169 struct intel_context *ce);
170 static void execlists_init_reg_state(u32 *reg_state,
171 struct i915_gem_context *ctx,
172 struct intel_engine_cs *engine,
173 struct intel_ring *ring);
175 static inline struct i915_priolist *to_priolist(struct rb_node *rb)
177 return rb_entry(rb, struct i915_priolist, node);
180 static inline int rq_prio(const struct i915_request *rq)
182 return rq->sched.attr.priority;
185 static inline bool need_preempt(const struct intel_engine_cs *engine,
186 const struct i915_request *last,
189 return (intel_engine_has_preemption(engine) &&
190 __execlists_need_preempt(prio, rq_prio(last)) &&
191 !i915_request_completed(last));
195 * The context descriptor encodes various attributes of a context,
196 * including its GTT address and some flags. Because it's fairly
197 * expensive to calculate, we'll just do it once and cache the result,
198 * which remains valid until the context is unpinned.
200 * This is what a descriptor looks like, from LSB to MSB::
202 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
203 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
204 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
205 * bits 53-54: mbz, reserved for use by hardware
206 * bits 55-63: group ID, currently unused and set to 0
208 * Starting from Gen11, the upper dword of the descriptor has a new format:
210 * bits 32-36: reserved
211 * bits 37-47: SW context ID
212 * bits 48:53: engine instance
213 * bit 54: mbz, reserved for use by hardware
214 * bits 55-60: SW counter
215 * bits 61-63: engine class
217 * engine info, SW context ID and SW counter need to form a unique number
218 * (Context ID) per lrc.
221 intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
222 struct intel_engine_cs *engine,
223 struct intel_context *ce)
227 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
228 BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
230 desc = ctx->desc_template; /* bits 0-11 */
231 GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
233 desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
235 GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
238 * The following 32bits are copied into the OA reports (dword 2).
239 * Consider updating oa_get_render_ctx_id in i915_perf.c when changing
242 if (INTEL_GEN(ctx->i915) >= 11) {
243 GEM_BUG_ON(ctx->hw_id >= BIT(GEN11_SW_CTX_ID_WIDTH));
244 desc |= (u64)ctx->hw_id << GEN11_SW_CTX_ID_SHIFT;
247 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT;
250 /* TODO: decide what to do with SW counter (bits 55-60) */
252 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT;
255 GEM_BUG_ON(ctx->hw_id >= BIT(GEN8_CTX_ID_WIDTH));
256 desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */
262 static struct i915_priolist *
263 lookup_priolist(struct intel_engine_cs *engine, int prio)
265 struct intel_engine_execlists * const execlists = &engine->execlists;
266 struct i915_priolist *p;
267 struct rb_node **parent, *rb;
270 if (unlikely(execlists->no_priolist))
271 prio = I915_PRIORITY_NORMAL;
274 /* most positive priority is scheduled first, equal priorities fifo */
276 parent = &execlists->queue.rb_root.rb_node;
280 if (prio > p->priority) {
281 parent = &rb->rb_left;
282 } else if (prio < p->priority) {
283 parent = &rb->rb_right;
290 if (prio == I915_PRIORITY_NORMAL) {
291 p = &execlists->default_priolist;
293 p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC);
294 /* Convert an allocation failure to a priority bump */
296 prio = I915_PRIORITY_NORMAL; /* recurses just once */
298 /* To maintain ordering with all rendering, after an
299 * allocation failure we have to disable all scheduling.
300 * Requests will then be executed in fifo, and schedule
301 * will ensure that dependencies are emitted in fifo.
302 * There will be still some reordering with existing
303 * requests, so if userspace lied about their
304 * dependencies that reordering may be visible.
306 execlists->no_priolist = true;
312 INIT_LIST_HEAD(&p->requests);
313 rb_link_node(&p->node, rb, parent);
314 rb_insert_color_cached(&p->node, &execlists->queue, first);
319 static void unwind_wa_tail(struct i915_request *rq)
321 rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES);
322 assert_ring_tail_valid(rq->ring, rq->tail);
325 static void __unwind_incomplete_requests(struct intel_engine_cs *engine)
327 struct i915_request *rq, *rn;
328 struct i915_priolist *uninitialized_var(p);
329 int last_prio = I915_PRIORITY_INVALID;
331 lockdep_assert_held(&engine->timeline.lock);
333 list_for_each_entry_safe_reverse(rq, rn,
334 &engine->timeline.requests,
336 if (i915_request_completed(rq))
339 __i915_request_unsubmit(rq);
342 GEM_BUG_ON(rq_prio(rq) == I915_PRIORITY_INVALID);
343 if (rq_prio(rq) != last_prio) {
344 last_prio = rq_prio(rq);
345 p = lookup_priolist(engine, last_prio);
348 GEM_BUG_ON(p->priority != rq_prio(rq));
349 list_add(&rq->sched.link, &p->requests);
354 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists)
356 struct intel_engine_cs *engine =
357 container_of(execlists, typeof(*engine), execlists);
360 spin_lock_irqsave(&engine->timeline.lock, flags);
362 __unwind_incomplete_requests(engine);
364 spin_unlock_irqrestore(&engine->timeline.lock, flags);
368 execlists_context_status_change(struct i915_request *rq, unsigned long status)
371 * Only used when GVT-g is enabled now. When GVT-g is disabled,
372 * The compiler should eliminate this function as dead-code.
374 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
377 atomic_notifier_call_chain(&rq->engine->context_status_notifier,
382 execlists_user_begin(struct intel_engine_execlists *execlists,
383 const struct execlist_port *port)
385 execlists_set_active_once(execlists, EXECLISTS_ACTIVE_USER);
389 execlists_user_end(struct intel_engine_execlists *execlists)
391 execlists_clear_active(execlists, EXECLISTS_ACTIVE_USER);
395 execlists_context_schedule_in(struct i915_request *rq)
397 execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN);
398 intel_engine_context_in(rq->engine);
402 execlists_context_schedule_out(struct i915_request *rq, unsigned long status)
404 intel_engine_context_out(rq->engine);
405 execlists_context_status_change(rq, status);
406 trace_i915_request_out(rq);
410 execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
412 ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
413 ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
414 ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
415 ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
418 static u64 execlists_update_context(struct i915_request *rq)
420 struct intel_context *ce = rq->hw_context;
421 struct i915_hw_ppgtt *ppgtt =
422 rq->gem_context->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
423 u32 *reg_state = ce->lrc_reg_state;
425 reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
428 * True 32b PPGTT with dynamic page allocation: update PDP
429 * registers and point the unallocated PDPs to scratch page.
430 * PML4 is allocated during ppgtt init, so this is not needed
433 if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
434 execlists_update_context_pdps(ppgtt, reg_state);
437 * Make sure the context image is complete before we submit it to HW.
439 * Ostensibly, writes (including the WCB) should be flushed prior to
440 * an uncached write such as our mmio register access, the empirical
441 * evidence (esp. on Braswell) suggests that the WC write into memory
442 * may not be visible to the HW prior to the completion of the UC
443 * register write and that we may begin execution from the context
444 * before its image is complete leading to invalid PD chasing.
446 * Furthermore, Braswell, at least, wants a full mb to be sure that
447 * the writes are coherent in memory (visible to the GPU) prior to
448 * execution, and not just visible to other CPUs (as is the result of
455 static inline void write_desc(struct intel_engine_execlists *execlists, u64 desc, u32 port)
457 if (execlists->ctrl_reg) {
458 writel(lower_32_bits(desc), execlists->submit_reg + port * 2);
459 writel(upper_32_bits(desc), execlists->submit_reg + port * 2 + 1);
461 writel(upper_32_bits(desc), execlists->submit_reg);
462 writel(lower_32_bits(desc), execlists->submit_reg);
466 static void execlists_submit_ports(struct intel_engine_cs *engine)
468 struct intel_engine_execlists *execlists = &engine->execlists;
469 struct execlist_port *port = execlists->port;
473 * We can skip acquiring intel_runtime_pm_get() here as it was taken
474 * on our behalf by the request (see i915_gem_mark_busy()) and it will
475 * not be relinquished until the device is idle (see
476 * i915_gem_idle_work_handler()). As a precaution, we make sure
477 * that all ELSP are drained i.e. we have processed the CSB,
478 * before allowing ourselves to idle and calling intel_runtime_pm_put().
480 GEM_BUG_ON(!engine->i915->gt.awake);
483 * ELSQ note: the submit queue is not cleared after being submitted
484 * to the HW so we need to make sure we always clean it up. This is
485 * currently ensured by the fact that we always write the same number
486 * of elsq entries, keep this in mind before changing the loop below.
488 for (n = execlists_num_ports(execlists); n--; ) {
489 struct i915_request *rq;
493 rq = port_unpack(&port[n], &count);
495 GEM_BUG_ON(count > !n);
497 execlists_context_schedule_in(rq);
498 port_set(&port[n], port_pack(rq, count));
499 desc = execlists_update_context(rq);
500 GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc));
502 GEM_TRACE("%s in[%d]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
504 port[n].context_id, count,
506 rq->fence.context, rq->fence.seqno,
507 intel_engine_get_seqno(engine),
514 write_desc(execlists, desc, n);
517 /* we need to manually load the submit queue */
518 if (execlists->ctrl_reg)
519 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
521 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
524 static bool ctx_single_port_submission(const struct intel_context *ce)
526 return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
527 i915_gem_context_force_single_submission(ce->gem_context));
530 static bool can_merge_ctx(const struct intel_context *prev,
531 const struct intel_context *next)
536 if (ctx_single_port_submission(prev))
542 static void port_assign(struct execlist_port *port, struct i915_request *rq)
544 GEM_BUG_ON(rq == port_request(port));
546 if (port_isset(port))
547 i915_request_put(port_request(port));
549 port_set(port, port_pack(i915_request_get(rq), port_count(port)));
552 static void inject_preempt_context(struct intel_engine_cs *engine)
554 struct intel_engine_execlists *execlists = &engine->execlists;
555 struct intel_context *ce =
556 to_intel_context(engine->i915->preempt_context, engine);
559 GEM_BUG_ON(execlists->preempt_complete_status !=
560 upper_32_bits(ce->lrc_desc));
561 GEM_BUG_ON((ce->lrc_reg_state[CTX_CONTEXT_CONTROL + 1] &
562 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
563 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT)) !=
564 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
565 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT));
568 * Switch to our empty preempt context so
569 * the state of the GPU is known (idle).
571 GEM_TRACE("%s\n", engine->name);
572 for (n = execlists_num_ports(execlists); --n; )
573 write_desc(execlists, 0, n);
575 write_desc(execlists, ce->lrc_desc, n);
577 /* we need to manually load the submit queue */
578 if (execlists->ctrl_reg)
579 writel(EL_CTRL_LOAD, execlists->ctrl_reg);
581 execlists_clear_active(execlists, EXECLISTS_ACTIVE_HWACK);
582 execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
585 static void complete_preempt_context(struct intel_engine_execlists *execlists)
587 GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_PREEMPT));
589 if (inject_preempt_hang(execlists))
592 execlists_cancel_port_requests(execlists);
593 __unwind_incomplete_requests(container_of(execlists,
594 struct intel_engine_cs,
598 static void execlists_dequeue(struct intel_engine_cs *engine)
600 struct intel_engine_execlists * const execlists = &engine->execlists;
601 struct execlist_port *port = execlists->port;
602 const struct execlist_port * const last_port =
603 &execlists->port[execlists->port_mask];
604 struct i915_request *last = port_request(port);
609 * Hardware submission is through 2 ports. Conceptually each port
610 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
611 * static for a context, and unique to each, so we only execute
612 * requests belonging to a single context from each ring. RING_HEAD
613 * is maintained by the CS in the context image, it marks the place
614 * where it got up to last time, and through RING_TAIL we tell the CS
615 * where we want to execute up to this time.
617 * In this list the requests are in order of execution. Consecutive
618 * requests from the same context are adjacent in the ringbuffer. We
619 * can combine these requests into a single RING_TAIL update:
621 * RING_HEAD...req1...req2
623 * since to execute req2 the CS must first execute req1.
625 * Our goal then is to point each port to the end of a consecutive
626 * sequence of requests as being the most optimal (fewest wake ups
627 * and context switches) submission.
632 * Don't resubmit or switch until all outstanding
633 * preemptions (lite-restore) are seen. Then we
634 * know the next preemption status we see corresponds
635 * to this ELSP update.
637 GEM_BUG_ON(!execlists_is_active(execlists,
638 EXECLISTS_ACTIVE_USER));
639 GEM_BUG_ON(!port_count(&port[0]));
642 * If we write to ELSP a second time before the HW has had
643 * a chance to respond to the previous write, we can confuse
644 * the HW and hit "undefined behaviour". After writing to ELSP,
645 * we must then wait until we see a context-switch event from
646 * the HW to indicate that it has had a chance to respond.
648 if (!execlists_is_active(execlists, EXECLISTS_ACTIVE_HWACK))
651 if (need_preempt(engine, last, execlists->queue_priority)) {
652 inject_preempt_context(engine);
657 * In theory, we could coalesce more requests onto
658 * the second port (the first port is active, with
659 * no preemptions pending). However, that means we
660 * then have to deal with the possible lite-restore
661 * of the second port (as we submit the ELSP, there
662 * may be a context-switch) but also we may complete
663 * the resubmission before the context-switch. Ergo,
664 * coalescing onto the second port will cause a
665 * preemption event, but we cannot predict whether
666 * that will affect port[0] or port[1].
668 * If the second port is already active, we can wait
669 * until the next context-switch before contemplating
670 * new requests. The GPU will be busy and we should be
671 * able to resubmit the new ELSP before it idles,
672 * avoiding pipeline bubbles (momentary pauses where
673 * the driver is unable to keep up the supply of new
674 * work). However, we have to double check that the
675 * priorities of the ports haven't been switch.
677 if (port_count(&port[1]))
681 * WaIdleLiteRestore:bdw,skl
682 * Apply the wa NOOPs to prevent
683 * ring:HEAD == rq:TAIL as we resubmit the
684 * request. See gen8_emit_breadcrumb() for
685 * where we prepare the padding after the
686 * end of the request.
688 last->tail = last->wa_tail;
691 while ((rb = rb_first_cached(&execlists->queue))) {
692 struct i915_priolist *p = to_priolist(rb);
693 struct i915_request *rq, *rn;
695 list_for_each_entry_safe(rq, rn, &p->requests, sched.link) {
697 * Can we combine this request with the current port?
698 * It has to be the same context/ringbuffer and not
699 * have any exceptions (e.g. GVT saying never to
702 * If we can combine the requests, we can execute both
703 * by updating the RING_TAIL to point to the end of the
704 * second request, and so we never need to tell the
705 * hardware about the first.
708 !can_merge_ctx(rq->hw_context, last->hw_context)) {
710 * If we are on the second port and cannot
711 * combine this request with the last, then we
714 if (port == last_port) {
715 __list_del_many(&p->requests,
721 * If GVT overrides us we only ever submit
722 * port[0], leaving port[1] empty. Note that we
723 * also have to be careful that we don't queue
724 * the same context (even though a different
725 * request) to the second port.
727 if (ctx_single_port_submission(last->hw_context) ||
728 ctx_single_port_submission(rq->hw_context)) {
729 __list_del_many(&p->requests,
734 GEM_BUG_ON(last->hw_context == rq->hw_context);
737 port_assign(port, last);
740 GEM_BUG_ON(port_isset(port));
743 INIT_LIST_HEAD(&rq->sched.link);
744 __i915_request_submit(rq);
745 trace_i915_request_in(rq, port_index(port, execlists));
750 rb_erase_cached(&p->node, &execlists->queue);
751 INIT_LIST_HEAD(&p->requests);
752 if (p->priority != I915_PRIORITY_NORMAL)
753 kmem_cache_free(engine->i915->priorities, p);
758 * Here be a bit of magic! Or sleight-of-hand, whichever you prefer.
760 * We choose queue_priority such that if we add a request of greater
761 * priority than this, we kick the submission tasklet to decide on
762 * the right order of submitting the requests to hardware. We must
763 * also be prepared to reorder requests as they are in-flight on the
764 * HW. We derive the queue_priority then as the first "hole" in
765 * the HW submission ports and if there are no available slots,
766 * the priority of the lowest executing request, i.e. last.
768 * When we do receive a higher priority request ready to run from the
769 * user, see queue_request(), the queue_priority is bumped to that
770 * request triggering preemption on the next dequeue (or subsequent
771 * interrupt for secondary ports).
773 execlists->queue_priority =
774 port != execlists->port ? rq_prio(last) : INT_MIN;
777 port_assign(port, last);
778 execlists_submit_ports(engine);
781 /* We must always keep the beast fed if we have work piled up */
782 GEM_BUG_ON(rb_first_cached(&execlists->queue) &&
783 !port_isset(execlists->port));
785 /* Re-evaluate the executing context setup after each preemptive kick */
787 execlists_user_begin(execlists, execlists->port);
789 /* If the engine is now idle, so should be the flag; and vice versa. */
790 GEM_BUG_ON(execlists_is_active(&engine->execlists,
791 EXECLISTS_ACTIVE_USER) ==
792 !port_isset(engine->execlists.port));
796 execlists_cancel_port_requests(struct intel_engine_execlists * const execlists)
798 struct execlist_port *port = execlists->port;
799 unsigned int num_ports = execlists_num_ports(execlists);
801 while (num_ports-- && port_isset(port)) {
802 struct i915_request *rq = port_request(port);
804 GEM_TRACE("%s:port%u global=%d (fence %llx:%d), (current %d)\n",
806 (unsigned int)(port - execlists->port),
808 rq->fence.context, rq->fence.seqno,
809 intel_engine_get_seqno(rq->engine));
811 GEM_BUG_ON(!execlists->active);
812 execlists_context_schedule_out(rq,
813 i915_request_completed(rq) ?
814 INTEL_CONTEXT_SCHEDULE_OUT :
815 INTEL_CONTEXT_SCHEDULE_PREEMPTED);
817 i915_request_put(rq);
819 memset(port, 0, sizeof(*port));
823 execlists_clear_all_active(execlists);
826 static void reset_csb_pointers(struct intel_engine_execlists *execlists)
829 * After a reset, the HW starts writing into CSB entry [0]. We
830 * therefore have to set our HEAD pointer back one entry so that
831 * the *first* entry we check is entry 0. To complicate this further,
832 * as we don't wait for the first interrupt after reset, we have to
833 * fake the HW write to point back to the last entry so that our
834 * inline comparison of our cached head position against the last HW
835 * write works even before the first interrupt.
837 execlists->csb_head = execlists->csb_write_reset;
838 WRITE_ONCE(*execlists->csb_write, execlists->csb_write_reset);
841 static void nop_submission_tasklet(unsigned long data)
843 /* The driver is wedged; don't process any more events. */
846 static void execlists_cancel_requests(struct intel_engine_cs *engine)
848 struct intel_engine_execlists * const execlists = &engine->execlists;
849 struct i915_request *rq, *rn;
853 GEM_TRACE("%s current %d\n",
854 engine->name, intel_engine_get_seqno(engine));
857 * Before we call engine->cancel_requests(), we should have exclusive
858 * access to the submission state. This is arranged for us by the
859 * caller disabling the interrupt generation, the tasklet and other
860 * threads that may then access the same state, giving us a free hand
861 * to reset state. However, we still need to let lockdep be aware that
862 * we know this state may be accessed in hardirq context, so we
863 * disable the irq around this manipulation and we want to keep
864 * the spinlock focused on its duties and not accidentally conflate
865 * coverage to the submission's irq state. (Similarly, although we
866 * shouldn't need to disable irq around the manipulation of the
867 * submission's irq state, we also wish to remind ourselves that
870 spin_lock_irqsave(&engine->timeline.lock, flags);
872 /* Cancel the requests on the HW and clear the ELSP tracker. */
873 execlists_cancel_port_requests(execlists);
874 execlists_user_end(execlists);
876 /* Mark all executing requests as skipped. */
877 list_for_each_entry(rq, &engine->timeline.requests, link) {
878 GEM_BUG_ON(!rq->global_seqno);
879 if (!i915_request_completed(rq))
880 dma_fence_set_error(&rq->fence, -EIO);
883 /* Flush the queued requests to the timeline list (for retiring). */
884 while ((rb = rb_first_cached(&execlists->queue))) {
885 struct i915_priolist *p = to_priolist(rb);
887 list_for_each_entry_safe(rq, rn, &p->requests, sched.link) {
888 INIT_LIST_HEAD(&rq->sched.link);
890 dma_fence_set_error(&rq->fence, -EIO);
891 __i915_request_submit(rq);
894 rb_erase_cached(&p->node, &execlists->queue);
895 INIT_LIST_HEAD(&p->requests);
896 if (p->priority != I915_PRIORITY_NORMAL)
897 kmem_cache_free(engine->i915->priorities, p);
900 /* Remaining _unready_ requests will be nop'ed when submitted */
902 execlists->queue_priority = INT_MIN;
903 execlists->queue = RB_ROOT_CACHED;
904 GEM_BUG_ON(port_isset(execlists->port));
906 GEM_BUG_ON(__tasklet_is_enabled(&execlists->tasklet));
907 execlists->tasklet.func = nop_submission_tasklet;
909 spin_unlock_irqrestore(&engine->timeline.lock, flags);
913 reset_in_progress(const struct intel_engine_execlists *execlists)
915 return unlikely(!__tasklet_is_enabled(&execlists->tasklet));
918 static void process_csb(struct intel_engine_cs *engine)
920 struct intel_engine_execlists * const execlists = &engine->execlists;
921 struct execlist_port *port = execlists->port;
922 const u32 * const buf = execlists->csb_status;
926 * Note that csb_write, csb_status may be either in HWSP or mmio.
927 * When reading from the csb_write mmio register, we have to be
928 * careful to only use the GEN8_CSB_WRITE_PTR portion, which is
929 * the low 4bits. As it happens we know the next 4bits are always
930 * zero and so we can simply masked off the low u8 of the register
931 * and treat it identically to reading from the HWSP (without having
932 * to use explicit shifting and masking, and probably bifurcating
933 * the code to handle the legacy mmio read).
935 head = execlists->csb_head;
936 tail = READ_ONCE(*execlists->csb_write);
937 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail);
938 if (unlikely(head == tail))
942 * Hopefully paired with a wmb() in HW!
944 * We must complete the read of the write pointer before any reads
945 * from the CSB, so that we do not see stale values. Without an rmb
946 * (lfence) the HW may speculatively perform the CSB[] reads *before*
947 * we perform the READ_ONCE(*csb_write).
952 struct i915_request *rq;
956 if (++head == GEN8_CSB_ENTRIES)
960 * We are flying near dragons again.
962 * We hold a reference to the request in execlist_port[]
963 * but no more than that. We are operating in softirq
964 * context and so cannot hold any mutex or sleep. That
965 * prevents us stopping the requests we are processing
966 * in port[] from being retired simultaneously (the
967 * breadcrumb will be complete before we see the
968 * context-switch). As we only hold the reference to the
969 * request, any pointer chasing underneath the request
970 * is subject to a potential use-after-free. Thus we
971 * store all of the bookkeeping within port[] as
972 * required, and avoid using unguarded pointers beneath
973 * request itself. The same applies to the atomic
977 GEM_TRACE("%s csb[%d]: status=0x%08x:0x%08x, active=0x%x\n",
979 buf[2 * head + 0], buf[2 * head + 1],
982 status = buf[2 * head];
983 if (status & (GEN8_CTX_STATUS_IDLE_ACTIVE |
984 GEN8_CTX_STATUS_PREEMPTED))
985 execlists_set_active(execlists,
986 EXECLISTS_ACTIVE_HWACK);
987 if (status & GEN8_CTX_STATUS_ACTIVE_IDLE)
988 execlists_clear_active(execlists,
989 EXECLISTS_ACTIVE_HWACK);
991 if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
994 /* We should never get a COMPLETED | IDLE_ACTIVE! */
995 GEM_BUG_ON(status & GEN8_CTX_STATUS_IDLE_ACTIVE);
997 if (status & GEN8_CTX_STATUS_COMPLETE &&
998 buf[2*head + 1] == execlists->preempt_complete_status) {
999 GEM_TRACE("%s preempt-idle\n", engine->name);
1000 complete_preempt_context(execlists);
1004 if (status & GEN8_CTX_STATUS_PREEMPTED &&
1005 execlists_is_active(execlists,
1006 EXECLISTS_ACTIVE_PREEMPT))
1009 GEM_BUG_ON(!execlists_is_active(execlists,
1010 EXECLISTS_ACTIVE_USER));
1012 rq = port_unpack(port, &count);
1013 GEM_TRACE("%s out[0]: ctx=%d.%d, global=%d (fence %llx:%d) (current %d), prio=%d\n",
1015 port->context_id, count,
1016 rq ? rq->global_seqno : 0,
1017 rq ? rq->fence.context : 0,
1018 rq ? rq->fence.seqno : 0,
1019 intel_engine_get_seqno(engine),
1020 rq ? rq_prio(rq) : 0);
1022 /* Check the context/desc id for this event matches */
1023 GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id);
1025 GEM_BUG_ON(count == 0);
1028 * On the final event corresponding to the
1029 * submission of this context, we expect either
1030 * an element-switch event or a completion
1031 * event (and on completion, the active-idle
1032 * marker). No more preemptions, lite-restore
1035 GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
1036 GEM_BUG_ON(port_isset(&port[1]) &&
1037 !(status & GEN8_CTX_STATUS_ELEMENT_SWITCH));
1038 GEM_BUG_ON(!port_isset(&port[1]) &&
1039 !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
1042 * We rely on the hardware being strongly
1043 * ordered, that the breadcrumb write is
1044 * coherent (visible from the CPU) before the
1045 * user interrupt and CSB is processed.
1047 GEM_BUG_ON(!i915_request_completed(rq));
1049 execlists_context_schedule_out(rq,
1050 INTEL_CONTEXT_SCHEDULE_OUT);
1051 i915_request_put(rq);
1053 GEM_TRACE("%s completed ctx=%d\n",
1054 engine->name, port->context_id);
1056 port = execlists_port_complete(execlists, port);
1057 if (port_isset(port))
1058 execlists_user_begin(execlists, port);
1060 execlists_user_end(execlists);
1062 port_set(port, port_pack(rq, count));
1064 } while (head != tail);
1066 execlists->csb_head = head;
1069 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
1071 lockdep_assert_held(&engine->timeline.lock);
1073 process_csb(engine);
1074 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT))
1075 execlists_dequeue(engine);
1079 * Check the unread Context Status Buffers and manage the submission of new
1080 * contexts to the ELSP accordingly.
1082 static void execlists_submission_tasklet(unsigned long data)
1084 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
1085 unsigned long flags;
1087 GEM_TRACE("%s awake?=%d, active=%x\n",
1089 engine->i915->gt.awake,
1090 engine->execlists.active);
1092 spin_lock_irqsave(&engine->timeline.lock, flags);
1093 __execlists_submission_tasklet(engine);
1094 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1097 static void queue_request(struct intel_engine_cs *engine,
1098 struct i915_sched_node *node,
1101 list_add_tail(&node->link,
1102 &lookup_priolist(engine, prio)->requests);
1105 static void __update_queue(struct intel_engine_cs *engine, int prio)
1107 engine->execlists.queue_priority = prio;
1110 static void __submit_queue_imm(struct intel_engine_cs *engine)
1112 struct intel_engine_execlists * const execlists = &engine->execlists;
1114 if (reset_in_progress(execlists))
1115 return; /* defer until we restart the engine following reset */
1117 if (execlists->tasklet.func == execlists_submission_tasklet)
1118 __execlists_submission_tasklet(engine);
1120 tasklet_hi_schedule(&execlists->tasklet);
1123 static void submit_queue(struct intel_engine_cs *engine, int prio)
1125 if (prio > engine->execlists.queue_priority) {
1126 __update_queue(engine, prio);
1127 __submit_queue_imm(engine);
1131 static void execlists_submit_request(struct i915_request *request)
1133 struct intel_engine_cs *engine = request->engine;
1134 unsigned long flags;
1136 /* Will be called from irq-context when using foreign fences. */
1137 spin_lock_irqsave(&engine->timeline.lock, flags);
1139 queue_request(engine, &request->sched, rq_prio(request));
1141 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root));
1142 GEM_BUG_ON(list_empty(&request->sched.link));
1144 submit_queue(engine, rq_prio(request));
1146 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1149 static struct i915_request *sched_to_request(struct i915_sched_node *node)
1151 return container_of(node, struct i915_request, sched);
1154 static struct intel_engine_cs *
1155 sched_lock_engine(struct i915_sched_node *node, struct intel_engine_cs *locked)
1157 struct intel_engine_cs *engine = sched_to_request(node)->engine;
1159 GEM_BUG_ON(!locked);
1161 if (engine != locked) {
1162 spin_unlock(&locked->timeline.lock);
1163 spin_lock(&engine->timeline.lock);
1169 static void execlists_schedule(struct i915_request *request,
1170 const struct i915_sched_attr *attr)
1172 struct i915_priolist *uninitialized_var(pl);
1173 struct intel_engine_cs *engine, *last;
1174 struct i915_dependency *dep, *p;
1175 struct i915_dependency stack;
1176 const int prio = attr->priority;
1179 GEM_BUG_ON(prio == I915_PRIORITY_INVALID);
1181 if (i915_request_completed(request))
1184 if (prio <= READ_ONCE(request->sched.attr.priority))
1187 /* Need BKL in order to use the temporary link inside i915_dependency */
1188 lockdep_assert_held(&request->i915->drm.struct_mutex);
1190 stack.signaler = &request->sched;
1191 list_add(&stack.dfs_link, &dfs);
1194 * Recursively bump all dependent priorities to match the new request.
1196 * A naive approach would be to use recursion:
1197 * static void update_priorities(struct i915_sched_node *node, prio) {
1198 * list_for_each_entry(dep, &node->signalers_list, signal_link)
1199 * update_priorities(dep->signal, prio)
1200 * queue_request(node);
1202 * but that may have unlimited recursion depth and so runs a very
1203 * real risk of overunning the kernel stack. Instead, we build
1204 * a flat list of all dependencies starting with the current request.
1205 * As we walk the list of dependencies, we add all of its dependencies
1206 * to the end of the list (this may include an already visited
1207 * request) and continue to walk onwards onto the new dependencies. The
1208 * end result is a topological list of requests in reverse order, the
1209 * last element in the list is the request we must execute first.
1211 list_for_each_entry(dep, &dfs, dfs_link) {
1212 struct i915_sched_node *node = dep->signaler;
1215 * Within an engine, there can be no cycle, but we may
1216 * refer to the same dependency chain multiple times
1217 * (redundant dependencies are not eliminated) and across
1220 list_for_each_entry(p, &node->signalers_list, signal_link) {
1221 GEM_BUG_ON(p == dep); /* no cycles! */
1223 if (i915_sched_node_signaled(p->signaler))
1226 GEM_BUG_ON(p->signaler->attr.priority < node->attr.priority);
1227 if (prio > READ_ONCE(p->signaler->attr.priority))
1228 list_move_tail(&p->dfs_link, &dfs);
1233 * If we didn't need to bump any existing priorities, and we haven't
1234 * yet submitted this request (i.e. there is no potential race with
1235 * execlists_submit_request()), we can set our own priority and skip
1236 * acquiring the engine locks.
1238 if (request->sched.attr.priority == I915_PRIORITY_INVALID) {
1239 GEM_BUG_ON(!list_empty(&request->sched.link));
1240 request->sched.attr = *attr;
1241 if (stack.dfs_link.next == stack.dfs_link.prev)
1243 __list_del_entry(&stack.dfs_link);
1247 engine = request->engine;
1248 spin_lock_irq(&engine->timeline.lock);
1250 /* Fifo and depth-first replacement ensure our deps execute before us */
1251 list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
1252 struct i915_sched_node *node = dep->signaler;
1254 INIT_LIST_HEAD(&dep->dfs_link);
1256 engine = sched_lock_engine(node, engine);
1258 if (prio <= node->attr.priority)
1261 node->attr.priority = prio;
1262 if (!list_empty(&node->link)) {
1263 if (last != engine) {
1264 pl = lookup_priolist(engine, prio);
1267 GEM_BUG_ON(pl->priority != prio);
1268 list_move_tail(&node->link, &pl->requests);
1271 if (prio > engine->execlists.queue_priority &&
1272 i915_sw_fence_done(&sched_to_request(node)->submit)) {
1273 /* defer submission until after all of our updates */
1274 __update_queue(engine, prio);
1275 tasklet_hi_schedule(&engine->execlists.tasklet);
1279 spin_unlock_irq(&engine->timeline.lock);
1282 static void execlists_context_destroy(struct intel_context *ce)
1284 GEM_BUG_ON(ce->pin_count);
1289 intel_ring_free(ce->ring);
1291 GEM_BUG_ON(i915_gem_object_is_active(ce->state->obj));
1292 i915_gem_object_put(ce->state->obj);
1295 static void execlists_context_unpin(struct intel_context *ce)
1297 intel_ring_unpin(ce->ring);
1299 ce->state->obj->pin_global--;
1300 i915_gem_object_unpin_map(ce->state->obj);
1301 i915_vma_unpin(ce->state);
1303 i915_gem_context_put(ce->gem_context);
1306 static int __context_pin(struct i915_gem_context *ctx, struct i915_vma *vma)
1312 * Clear this page out of any CPU caches for coherent swap-in/out.
1313 * We only want to do this on the first bind so that we do not stall
1314 * on an active context (which by nature is already on the GPU).
1316 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1317 err = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1322 flags = PIN_GLOBAL | PIN_HIGH;
1323 if (ctx->ggtt_offset_bias)
1324 flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
1326 return i915_vma_pin(vma, 0, GEN8_LR_CONTEXT_ALIGN, flags);
1329 static struct intel_context *
1330 __execlists_context_pin(struct intel_engine_cs *engine,
1331 struct i915_gem_context *ctx,
1332 struct intel_context *ce)
1337 ret = execlists_context_deferred_alloc(ctx, engine, ce);
1340 GEM_BUG_ON(!ce->state);
1342 ret = __context_pin(ctx, ce->state);
1346 vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
1347 if (IS_ERR(vaddr)) {
1348 ret = PTR_ERR(vaddr);
1352 ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias);
1356 intel_lr_context_descriptor_update(ctx, engine, ce);
1358 ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1359 ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
1360 i915_ggtt_offset(ce->ring->vma);
1361 GEM_BUG_ON(!intel_ring_offset_valid(ce->ring, ce->ring->head));
1362 ce->lrc_reg_state[CTX_RING_HEAD+1] = ce->ring->head;
1364 ce->state->obj->pin_global++;
1365 i915_gem_context_get(ctx);
1369 i915_gem_object_unpin_map(ce->state->obj);
1371 __i915_vma_unpin(ce->state);
1374 return ERR_PTR(ret);
1377 static const struct intel_context_ops execlists_context_ops = {
1378 .unpin = execlists_context_unpin,
1379 .destroy = execlists_context_destroy,
1382 static struct intel_context *
1383 execlists_context_pin(struct intel_engine_cs *engine,
1384 struct i915_gem_context *ctx)
1386 struct intel_context *ce = to_intel_context(ctx, engine);
1388 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1390 if (likely(ce->pin_count++))
1392 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1394 ce->ops = &execlists_context_ops;
1396 return __execlists_context_pin(engine, ctx, ce);
1399 static int execlists_request_alloc(struct i915_request *request)
1403 GEM_BUG_ON(!request->hw_context->pin_count);
1405 /* Flush enough space to reduce the likelihood of waiting after
1406 * we start building the request - in which case we will just
1407 * have to repeat work.
1409 request->reserved_space += EXECLISTS_REQUEST_SIZE;
1411 ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1415 /* Note that after this point, we have committed to using
1416 * this request as it is being used to both track the
1417 * state of engine initialisation and liveness of the
1418 * golden renderstate above. Think twice before you try
1419 * to cancel/unwind this request now.
1422 request->reserved_space -= EXECLISTS_REQUEST_SIZE;
1427 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1428 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1429 * but there is a slight complication as this is applied in WA batch where the
1430 * values are only initialized once so we cannot take register value at the
1431 * beginning and reuse it further; hence we save its value to memory, upload a
1432 * constant value with bit21 set and then we restore it back with the saved value.
1433 * To simplify the WA, a constant value is formed by using the default value
1434 * of this register. This shouldn't be a problem because we are only modifying
1435 * it for a short period and this batch in non-premptible. We can ofcourse
1436 * use additional instructions that read the actual value of the register
1437 * at that time and set our bit of interest but it makes the WA complicated.
1439 * This WA is also required for Gen9 so extracting as a function avoids
1443 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1445 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1446 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1447 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1450 *batch++ = MI_LOAD_REGISTER_IMM(1);
1451 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1452 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1454 batch = gen8_emit_pipe_control(batch,
1455 PIPE_CONTROL_CS_STALL |
1456 PIPE_CONTROL_DC_FLUSH_ENABLE,
1459 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1460 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1461 *batch++ = i915_ggtt_offset(engine->scratch) + 256;
1468 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1469 * initialized at the beginning and shared across all contexts but this field
1470 * helps us to have multiple batches at different offsets and select them based
1471 * on a criteria. At the moment this batch always start at the beginning of the page
1472 * and at this point we don't have multiple wa_ctx batch buffers.
1474 * The number of WA applied are not known at the beginning; we use this field
1475 * to return the no of DWORDS written.
1477 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1478 * so it adds NOOPs as padding to make it cacheline aligned.
1479 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1480 * makes a complete batch buffer.
1482 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1484 /* WaDisableCtxRestoreArbitration:bdw,chv */
1485 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1487 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1488 if (IS_BROADWELL(engine->i915))
1489 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1491 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1492 /* Actual scratch location is at 128 bytes offset */
1493 batch = gen8_emit_pipe_control(batch,
1494 PIPE_CONTROL_FLUSH_L3 |
1495 PIPE_CONTROL_GLOBAL_GTT_IVB |
1496 PIPE_CONTROL_CS_STALL |
1497 PIPE_CONTROL_QW_WRITE,
1498 i915_ggtt_offset(engine->scratch) +
1499 2 * CACHELINE_BYTES);
1501 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1503 /* Pad to end of cacheline */
1504 while ((unsigned long)batch % CACHELINE_BYTES)
1508 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1509 * execution depends on the length specified in terms of cache lines
1510 * in the register CTX_RCS_INDIRECT_CTX
1521 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1523 GEM_BUG_ON(!count || count > 63);
1525 *batch++ = MI_LOAD_REGISTER_IMM(count);
1527 *batch++ = i915_mmio_reg_offset(lri->reg);
1528 *batch++ = lri->value;
1529 } while (lri++, --count);
1535 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1537 static const struct lri lri[] = {
1538 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1540 COMMON_SLICE_CHICKEN2,
1541 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1548 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1549 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1555 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1556 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1560 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1562 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1563 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1565 /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */
1566 batch = gen8_emit_pipe_control(batch,
1567 PIPE_CONTROL_FLUSH_L3 |
1568 PIPE_CONTROL_GLOBAL_GTT_IVB |
1569 PIPE_CONTROL_CS_STALL |
1570 PIPE_CONTROL_QW_WRITE,
1571 i915_ggtt_offset(engine->scratch) +
1572 2 * CACHELINE_BYTES);
1574 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1576 /* WaClearSlmSpaceAtContextSwitch:kbl */
1577 /* Actual scratch location is at 128 bytes offset */
1578 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
1579 batch = gen8_emit_pipe_control(batch,
1580 PIPE_CONTROL_FLUSH_L3 |
1581 PIPE_CONTROL_GLOBAL_GTT_IVB |
1582 PIPE_CONTROL_CS_STALL |
1583 PIPE_CONTROL_QW_WRITE,
1584 i915_ggtt_offset(engine->scratch)
1585 + 2 * CACHELINE_BYTES);
1588 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1589 if (HAS_POOLED_EU(engine->i915)) {
1591 * EU pool configuration is setup along with golden context
1592 * during context initialization. This value depends on
1593 * device type (2x6 or 3x6) and needs to be updated based
1594 * on which subslice is disabled especially for 2x6
1595 * devices, however it is safe to load default
1596 * configuration of 3x6 device instead of masking off
1597 * corresponding bits because HW ignores bits of a disabled
1598 * subslice and drops down to appropriate config. Please
1599 * see render_state_setup() in i915_gem_render_state.c for
1600 * possible configurations, to avoid duplication they are
1601 * not shown here again.
1603 *batch++ = GEN9_MEDIA_POOL_STATE;
1604 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1605 *batch++ = 0x00777000;
1611 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1613 /* Pad to end of cacheline */
1614 while ((unsigned long)batch % CACHELINE_BYTES)
1621 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1626 * WaPipeControlBefore3DStateSamplePattern: cnl
1628 * Ensure the engine is idle prior to programming a
1629 * 3DSTATE_SAMPLE_PATTERN during a context restore.
1631 batch = gen8_emit_pipe_control(batch,
1632 PIPE_CONTROL_CS_STALL,
1635 * WaPipeControlBefore3DStateSamplePattern says we need 4 dwords for
1636 * the PIPE_CONTROL followed by 12 dwords of 0x0, so 16 dwords in
1637 * total. However, a PIPE_CONTROL is 6 dwords long, not 4, which is
1638 * confusing. Since gen8_emit_pipe_control() already advances the
1639 * batch by 6 dwords, we advance the other 10 here, completing a
1640 * cacheline. It's not clear if the workaround requires this padding
1641 * before other commands, or if it's just the regular padding we would
1642 * already have for the workaround bb, so leave it here for now.
1644 for (i = 0; i < 10; i++)
1647 /* Pad to end of cacheline */
1648 while ((unsigned long)batch % CACHELINE_BYTES)
1654 #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE)
1656 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine)
1658 struct drm_i915_gem_object *obj;
1659 struct i915_vma *vma;
1662 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE);
1664 return PTR_ERR(obj);
1666 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL);
1672 err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
1676 engine->wa_ctx.vma = vma;
1680 i915_gem_object_put(obj);
1684 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine)
1686 i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1689 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1691 static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1693 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1694 struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx,
1696 wa_bb_func_t wa_bb_fn[2];
1698 void *batch, *batch_ptr;
1702 if (GEM_WARN_ON(engine->id != RCS))
1705 switch (INTEL_GEN(engine->i915)) {
1709 wa_bb_fn[0] = gen10_init_indirectctx_bb;
1713 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1717 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1721 MISSING_CASE(INTEL_GEN(engine->i915));
1725 ret = lrc_setup_wa_ctx(engine);
1727 DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
1731 page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1732 batch = batch_ptr = kmap_atomic(page);
1735 * Emit the two workaround batch buffers, recording the offset from the
1736 * start of the workaround batch buffer object for each and their
1739 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1740 wa_bb[i]->offset = batch_ptr - batch;
1741 if (GEM_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1742 CACHELINE_BYTES))) {
1747 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1748 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1751 BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE);
1753 kunmap_atomic(batch);
1755 lrc_destroy_wa_ctx(engine);
1760 static void enable_execlists(struct intel_engine_cs *engine)
1762 struct drm_i915_private *dev_priv = engine->i915;
1764 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1767 * Make sure we're not enabling the new 12-deep CSB
1768 * FIFO as that requires a slightly updated handling
1769 * in the ctx switch irq. Since we're currently only
1770 * using only 2 elements of the enhanced execlists the
1771 * deeper FIFO it's not needed and it's not worth adding
1772 * more statements to the irq handler to support it.
1774 if (INTEL_GEN(dev_priv) >= 11)
1775 I915_WRITE(RING_MODE_GEN7(engine),
1776 _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
1778 I915_WRITE(RING_MODE_GEN7(engine),
1779 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1781 I915_WRITE(RING_MI_MODE(engine->mmio_base),
1782 _MASKED_BIT_DISABLE(STOP_RING));
1784 I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1785 engine->status_page.ggtt_offset);
1786 POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1789 static bool unexpected_starting_state(struct intel_engine_cs *engine)
1791 struct drm_i915_private *dev_priv = engine->i915;
1792 bool unexpected = false;
1794 if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) {
1795 DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
1802 static int gen8_init_common_ring(struct intel_engine_cs *engine)
1806 ret = intel_mocs_init_engine(engine);
1810 intel_engine_reset_breadcrumbs(engine);
1812 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) {
1813 struct drm_printer p = drm_debug_printer(__func__);
1815 intel_engine_dump(engine, &p, NULL);
1818 enable_execlists(engine);
1823 static int gen8_init_render_ring(struct intel_engine_cs *engine)
1825 struct drm_i915_private *dev_priv = engine->i915;
1828 ret = gen8_init_common_ring(engine);
1832 intel_whitelist_workarounds_apply(engine);
1834 /* We need to disable the AsyncFlip performance optimisations in order
1835 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
1836 * programmed to '1' on all products.
1838 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
1840 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1842 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1847 static int gen9_init_render_ring(struct intel_engine_cs *engine)
1851 ret = gen8_init_common_ring(engine);
1855 intel_whitelist_workarounds_apply(engine);
1860 static struct i915_request *
1861 execlists_reset_prepare(struct intel_engine_cs *engine)
1863 struct intel_engine_execlists * const execlists = &engine->execlists;
1864 struct i915_request *request, *active;
1865 unsigned long flags;
1867 GEM_TRACE("%s\n", engine->name);
1870 * Prevent request submission to the hardware until we have
1871 * completed the reset in i915_gem_reset_finish(). If a request
1872 * is completed by one engine, it may then queue a request
1873 * to a second via its execlists->tasklet *just* as we are
1874 * calling engine->init_hw() and also writing the ELSP.
1875 * Turning off the execlists->tasklet until the reset is over
1876 * prevents the race.
1878 __tasklet_disable_sync_once(&execlists->tasklet);
1880 spin_lock_irqsave(&engine->timeline.lock, flags);
1883 * We want to flush the pending context switches, having disabled
1884 * the tasklet above, we can assume exclusive access to the execlists.
1885 * For this allows us to catch up with an inflight preemption event,
1886 * and avoid blaming an innocent request if the stall was due to the
1887 * preemption itself.
1889 process_csb(engine);
1892 * The last active request can then be no later than the last request
1893 * now in ELSP[0]. So search backwards from there, so that if the GPU
1894 * has advanced beyond the last CSB update, it will be pardoned.
1897 request = port_request(execlists->port);
1900 * Prevent the breadcrumb from advancing before we decide
1901 * which request is currently active.
1903 intel_engine_stop_cs(engine);
1905 list_for_each_entry_from_reverse(request,
1906 &engine->timeline.requests,
1908 if (__i915_request_completed(request,
1909 request->global_seqno))
1916 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1921 static void execlists_reset(struct intel_engine_cs *engine,
1922 struct i915_request *request)
1924 struct intel_engine_execlists * const execlists = &engine->execlists;
1925 unsigned long flags;
1928 GEM_TRACE("%s request global=%x, current=%d\n",
1929 engine->name, request ? request->global_seqno : 0,
1930 intel_engine_get_seqno(engine));
1932 spin_lock_irqsave(&engine->timeline.lock, flags);
1935 * Catch up with any missed context-switch interrupts.
1937 * Ideally we would just read the remaining CSB entries now that we
1938 * know the gpu is idle. However, the CSB registers are sometimes^W
1939 * often trashed across a GPU reset! Instead we have to rely on
1940 * guessing the missed context-switch events by looking at what
1941 * requests were completed.
1943 execlists_cancel_port_requests(execlists);
1945 /* Push back any incomplete requests for replay after the reset. */
1946 __unwind_incomplete_requests(engine);
1948 /* Following the reset, we need to reload the CSB read/write pointers */
1949 reset_csb_pointers(&engine->execlists);
1951 spin_unlock_irqrestore(&engine->timeline.lock, flags);
1954 * If the request was innocent, we leave the request in the ELSP
1955 * and will try to replay it on restarting. The context image may
1956 * have been corrupted by the reset, in which case we may have
1957 * to service a new GPU hang, but more likely we can continue on
1960 * If the request was guilty, we presume the context is corrupt
1961 * and have to at least restore the RING register in the context
1962 * image back to the expected values to skip over the guilty request.
1964 if (!request || request->fence.error != -EIO)
1968 * We want a simple context + ring to execute the breadcrumb update.
1969 * We cannot rely on the context being intact across the GPU hang,
1970 * so clear it and rebuild just what we need for the breadcrumb.
1971 * All pending requests for this context will be zapped, and any
1972 * future request will be after userspace has had the opportunity
1973 * to recreate its own state.
1975 regs = request->hw_context->lrc_reg_state;
1976 if (engine->pinned_default_state) {
1977 memcpy(regs, /* skip restoring the vanilla PPHWSP */
1978 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE,
1979 engine->context_size - PAGE_SIZE);
1981 execlists_init_reg_state(regs,
1982 request->gem_context, engine, request->ring);
1984 /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1985 regs[CTX_RING_BUFFER_START + 1] = i915_ggtt_offset(request->ring->vma);
1987 request->ring->head = intel_ring_wrap(request->ring, request->postfix);
1988 regs[CTX_RING_HEAD + 1] = request->ring->head;
1990 intel_ring_update_space(request->ring);
1992 /* Reset WaIdleLiteRestore:bdw,skl as well */
1993 unwind_wa_tail(request);
1996 static void execlists_reset_finish(struct intel_engine_cs *engine)
1998 struct intel_engine_execlists * const execlists = &engine->execlists;
2000 /* After a GPU reset, we may have requests to replay */
2001 if (!RB_EMPTY_ROOT(&execlists->queue.rb_root))
2002 tasklet_schedule(&execlists->tasklet);
2005 * Flush the tasklet while we still have the forcewake to be sure
2006 * that it is not allowed to sleep before we restart and reload a
2009 * As before (with execlists_reset_prepare) we rely on the caller
2010 * serialising multiple attempts to reset so that we know that we
2011 * are the only one manipulating tasklet state.
2013 __tasklet_enable_sync_once(&execlists->tasklet);
2015 GEM_TRACE("%s\n", engine->name);
2018 static int intel_logical_ring_emit_pdps(struct i915_request *rq)
2020 struct i915_hw_ppgtt *ppgtt = rq->gem_context->ppgtt;
2021 struct intel_engine_cs *engine = rq->engine;
2022 const int num_lri_cmds = GEN8_3LVL_PDPES * 2;
2026 cs = intel_ring_begin(rq, num_lri_cmds * 2 + 2);
2030 *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
2031 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
2032 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
2034 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
2035 *cs++ = upper_32_bits(pd_daddr);
2036 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
2037 *cs++ = lower_32_bits(pd_daddr);
2041 intel_ring_advance(rq, cs);
2046 static int gen8_emit_bb_start(struct i915_request *rq,
2047 u64 offset, u32 len,
2048 const unsigned int flags)
2053 /* Don't rely in hw updating PDPs, specially in lite-restore.
2054 * Ideally, we should set Force PD Restore in ctx descriptor,
2055 * but we can't. Force Restore would be a second option, but
2056 * it is unsafe in case of lite-restore (because the ctx is
2057 * not idle). PML4 is allocated during ppgtt init so this is
2058 * not needed in 48-bit.*/
2059 if (rq->gem_context->ppgtt &&
2060 (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) &&
2061 !i915_vm_is_48bit(&rq->gem_context->ppgtt->vm) &&
2062 !intel_vgpu_active(rq->i915)) {
2063 ret = intel_logical_ring_emit_pdps(rq);
2067 rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine);
2070 cs = intel_ring_begin(rq, 6);
2075 * WaDisableCtxRestoreArbitration:bdw,chv
2077 * We don't need to perform MI_ARB_ENABLE as often as we do (in
2078 * particular all the gen that do not need the w/a at all!), if we
2079 * took care to make sure that on every switch into this context
2080 * (both ordinary and for preemption) that arbitrartion was enabled
2081 * we would be fine. However, there doesn't seem to be a downside to
2082 * being paranoid and making sure it is set before each batch and
2083 * every context-switch.
2085 * Note that if we fail to enable arbitration before the request
2086 * is complete, then we do not see the context-switch interrupt and
2087 * the engine hangs (with RING_HEAD == RING_TAIL).
2089 * That satisfies both the GPGPU w/a and our heavy-handed paranoia.
2091 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2093 /* FIXME(BDW): Address space and security selectors. */
2094 *cs++ = MI_BATCH_BUFFER_START_GEN8 |
2095 (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) |
2096 (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
2097 *cs++ = lower_32_bits(offset);
2098 *cs++ = upper_32_bits(offset);
2100 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
2102 intel_ring_advance(rq, cs);
2107 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
2109 struct drm_i915_private *dev_priv = engine->i915;
2110 I915_WRITE_IMR(engine,
2111 ~(engine->irq_enable_mask | engine->irq_keep_mask));
2112 POSTING_READ_FW(RING_IMR(engine->mmio_base));
2115 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
2117 struct drm_i915_private *dev_priv = engine->i915;
2118 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
2121 static int gen8_emit_flush(struct i915_request *request, u32 mode)
2125 cs = intel_ring_begin(request, 4);
2129 cmd = MI_FLUSH_DW + 1;
2131 /* We always require a command barrier so that subsequent
2132 * commands, such as breadcrumb interrupts, are strictly ordered
2133 * wrt the contents of the write cache being flushed to memory
2134 * (and thus being coherent from the CPU).
2136 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
2138 if (mode & EMIT_INVALIDATE) {
2139 cmd |= MI_INVALIDATE_TLB;
2140 if (request->engine->id == VCS)
2141 cmd |= MI_INVALIDATE_BSD;
2145 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
2146 *cs++ = 0; /* upper addr */
2147 *cs++ = 0; /* value */
2148 intel_ring_advance(request, cs);
2153 static int gen8_emit_flush_render(struct i915_request *request,
2156 struct intel_engine_cs *engine = request->engine;
2158 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
2159 bool vf_flush_wa = false, dc_flush_wa = false;
2163 flags |= PIPE_CONTROL_CS_STALL;
2165 if (mode & EMIT_FLUSH) {
2166 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
2167 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
2168 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
2169 flags |= PIPE_CONTROL_FLUSH_ENABLE;
2172 if (mode & EMIT_INVALIDATE) {
2173 flags |= PIPE_CONTROL_TLB_INVALIDATE;
2174 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
2175 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
2176 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
2177 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
2178 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
2179 flags |= PIPE_CONTROL_QW_WRITE;
2180 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
2183 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
2186 if (IS_GEN9(request->i915))
2189 /* WaForGAMHang:kbl */
2190 if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
2202 cs = intel_ring_begin(request, len);
2207 cs = gen8_emit_pipe_control(cs, 0, 0);
2210 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE,
2213 cs = gen8_emit_pipe_control(cs, flags, scratch_addr);
2216 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0);
2218 intel_ring_advance(request, cs);
2224 * Reserve space for 2 NOOPs at the end of each request to be
2225 * used as a workaround for not being allowed to do lite
2226 * restore with HEAD==TAIL (WaIdleLiteRestore).
2228 static void gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
2230 /* Ensure there's always at least one preemption point per-request. */
2231 *cs++ = MI_ARB_CHECK;
2233 request->wa_tail = intel_ring_offset(request, cs);
2236 static void gen8_emit_breadcrumb(struct i915_request *request, u32 *cs)
2238 /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
2239 BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
2241 cs = gen8_emit_ggtt_write(cs, request->global_seqno,
2242 intel_hws_seqno_address(request->engine));
2243 *cs++ = MI_USER_INTERRUPT;
2244 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2245 request->tail = intel_ring_offset(request, cs);
2246 assert_ring_tail_valid(request->ring, request->tail);
2248 gen8_emit_wa_tail(request, cs);
2250 static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;
2252 static void gen8_emit_breadcrumb_rcs(struct i915_request *request, u32 *cs)
2254 /* We're using qword write, seqno should be aligned to 8 bytes. */
2255 BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);
2257 cs = gen8_emit_ggtt_write_rcs(cs, request->global_seqno,
2258 intel_hws_seqno_address(request->engine));
2259 *cs++ = MI_USER_INTERRUPT;
2260 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
2261 request->tail = intel_ring_offset(request, cs);
2262 assert_ring_tail_valid(request->ring, request->tail);
2264 gen8_emit_wa_tail(request, cs);
2266 static const int gen8_emit_breadcrumb_rcs_sz = 8 + WA_TAIL_DWORDS;
2268 static int gen8_init_rcs_context(struct i915_request *rq)
2272 ret = intel_ctx_workarounds_emit(rq);
2276 ret = intel_rcs_context_init_mocs(rq);
2278 * Failing to program the MOCS is non-fatal.The system will not
2279 * run at peak performance. So generate an error and carry on.
2282 DRM_ERROR("MOCS failed to program: expect performance issues.\n");
2284 return i915_gem_render_state_emit(rq);
2288 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
2289 * @engine: Engine Command Streamer.
2291 void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
2293 struct drm_i915_private *dev_priv;
2296 * Tasklet cannot be active at this point due intel_mark_active/idle
2297 * so this is just for documentation.
2299 if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
2300 &engine->execlists.tasklet.state)))
2301 tasklet_kill(&engine->execlists.tasklet);
2303 dev_priv = engine->i915;
2305 if (engine->buffer) {
2306 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
2309 if (engine->cleanup)
2310 engine->cleanup(engine);
2312 intel_engine_cleanup_common(engine);
2314 lrc_destroy_wa_ctx(engine);
2316 engine->i915 = NULL;
2317 dev_priv->engine[engine->id] = NULL;
2321 void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
2323 engine->submit_request = execlists_submit_request;
2324 engine->cancel_requests = execlists_cancel_requests;
2325 engine->schedule = execlists_schedule;
2326 engine->execlists.tasklet.func = execlists_submission_tasklet;
2328 engine->reset.prepare = execlists_reset_prepare;
2330 engine->park = NULL;
2331 engine->unpark = NULL;
2333 engine->flags |= I915_ENGINE_SUPPORTS_STATS;
2334 if (engine->i915->preempt_context)
2335 engine->flags |= I915_ENGINE_HAS_PREEMPTION;
2337 engine->i915->caps.scheduler =
2338 I915_SCHEDULER_CAP_ENABLED |
2339 I915_SCHEDULER_CAP_PRIORITY;
2340 if (intel_engine_has_preemption(engine))
2341 engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION;
2345 logical_ring_default_vfuncs(struct intel_engine_cs *engine)
2347 /* Default vfuncs which can be overriden by each engine. */
2348 engine->init_hw = gen8_init_common_ring;
2350 engine->reset.prepare = execlists_reset_prepare;
2351 engine->reset.reset = execlists_reset;
2352 engine->reset.finish = execlists_reset_finish;
2354 engine->context_pin = execlists_context_pin;
2355 engine->request_alloc = execlists_request_alloc;
2357 engine->emit_flush = gen8_emit_flush;
2358 engine->emit_breadcrumb = gen8_emit_breadcrumb;
2359 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
2361 engine->set_default_submission = intel_execlists_set_default_submission;
2363 if (INTEL_GEN(engine->i915) < 11) {
2364 engine->irq_enable = gen8_logical_ring_enable_irq;
2365 engine->irq_disable = gen8_logical_ring_disable_irq;
2368 * TODO: On Gen11 interrupt masks need to be clear
2369 * to allow C6 entry. Keep interrupts enabled at
2370 * and take the hit of generating extra interrupts
2371 * until a more refined solution exists.
2374 engine->emit_bb_start = gen8_emit_bb_start;
2378 logical_ring_default_irqs(struct intel_engine_cs *engine)
2380 unsigned int shift = 0;
2382 if (INTEL_GEN(engine->i915) < 11) {
2383 const u8 irq_shifts[] = {
2384 [RCS] = GEN8_RCS_IRQ_SHIFT,
2385 [BCS] = GEN8_BCS_IRQ_SHIFT,
2386 [VCS] = GEN8_VCS1_IRQ_SHIFT,
2387 [VCS2] = GEN8_VCS2_IRQ_SHIFT,
2388 [VECS] = GEN8_VECS_IRQ_SHIFT,
2391 shift = irq_shifts[engine->id];
2394 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
2395 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
2399 logical_ring_setup(struct intel_engine_cs *engine)
2401 intel_engine_setup_common(engine);
2403 /* Intentionally left blank. */
2404 engine->buffer = NULL;
2406 tasklet_init(&engine->execlists.tasklet,
2407 execlists_submission_tasklet, (unsigned long)engine);
2409 logical_ring_default_vfuncs(engine);
2410 logical_ring_default_irqs(engine);
2413 static bool csb_force_mmio(struct drm_i915_private *i915)
2415 /* Older GVT emulation depends upon intercepting CSB mmio */
2416 return intel_vgpu_active(i915) && !intel_vgpu_has_hwsp_emulation(i915);
2419 static int logical_ring_init(struct intel_engine_cs *engine)
2421 struct drm_i915_private *i915 = engine->i915;
2422 struct intel_engine_execlists * const execlists = &engine->execlists;
2425 ret = intel_engine_init_common(engine);
2429 if (HAS_LOGICAL_RING_ELSQ(i915)) {
2430 execlists->submit_reg = i915->regs +
2431 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine));
2432 execlists->ctrl_reg = i915->regs +
2433 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine));
2435 execlists->submit_reg = i915->regs +
2436 i915_mmio_reg_offset(RING_ELSP(engine));
2439 execlists->preempt_complete_status = ~0u;
2440 if (i915->preempt_context) {
2441 struct intel_context *ce =
2442 to_intel_context(i915->preempt_context, engine);
2444 execlists->preempt_complete_status =
2445 upper_32_bits(ce->lrc_desc);
2448 execlists->csb_read =
2449 i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
2450 if (csb_force_mmio(i915)) {
2451 execlists->csb_status = (u32 __force *)
2452 (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));
2454 execlists->csb_write = (u32 __force *)execlists->csb_read;
2455 execlists->csb_write_reset =
2456 _MASKED_FIELD(GEN8_CSB_WRITE_PTR_MASK,
2457 GEN8_CSB_ENTRIES - 1);
2459 execlists->csb_status =
2460 &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
2462 execlists->csb_write =
2463 &engine->status_page.page_addr[intel_hws_csb_write_index(i915)];
2464 execlists->csb_write_reset = GEN8_CSB_ENTRIES - 1;
2466 reset_csb_pointers(execlists);
2471 intel_logical_ring_cleanup(engine);
2475 int logical_render_ring_init(struct intel_engine_cs *engine)
2477 struct drm_i915_private *dev_priv = engine->i915;
2480 logical_ring_setup(engine);
2482 if (HAS_L3_DPF(dev_priv))
2483 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2485 /* Override some for render ring. */
2486 if (INTEL_GEN(dev_priv) >= 9)
2487 engine->init_hw = gen9_init_render_ring;
2489 engine->init_hw = gen8_init_render_ring;
2490 engine->init_context = gen8_init_rcs_context;
2491 engine->emit_flush = gen8_emit_flush_render;
2492 engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs;
2493 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz;
2495 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2499 ret = intel_init_workaround_bb(engine);
2502 * We continue even if we fail to initialize WA batch
2503 * because we only expect rare glitches but nothing
2504 * critical to prevent us from using GPU
2506 DRM_ERROR("WA batch buffer initialization failed: %d\n",
2510 return logical_ring_init(engine);
2513 int logical_xcs_ring_init(struct intel_engine_cs *engine)
2515 logical_ring_setup(engine);
2517 return logical_ring_init(engine);
2521 make_rpcs(struct drm_i915_private *dev_priv)
2526 * No explicit RPCS request is needed to ensure full
2527 * slice/subslice/EU enablement prior to Gen9.
2529 if (INTEL_GEN(dev_priv) < 9)
2533 * Starting in Gen9, render power gating can leave
2534 * slice/subslice/EU in a partially enabled state. We
2535 * must make an explicit request through RPCS for full
2538 if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
2539 rpcs |= GEN8_RPCS_S_CNT_ENABLE;
2540 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
2541 GEN8_RPCS_S_CNT_SHIFT;
2542 rpcs |= GEN8_RPCS_ENABLE;
2545 if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
2546 rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
2547 rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask[0]) <<
2548 GEN8_RPCS_SS_CNT_SHIFT;
2549 rpcs |= GEN8_RPCS_ENABLE;
2552 if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
2553 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2554 GEN8_RPCS_EU_MIN_SHIFT;
2555 rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
2556 GEN8_RPCS_EU_MAX_SHIFT;
2557 rpcs |= GEN8_RPCS_ENABLE;
2563 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
2565 u32 indirect_ctx_offset;
2567 switch (INTEL_GEN(engine->i915)) {
2569 MISSING_CASE(INTEL_GEN(engine->i915));
2572 indirect_ctx_offset =
2573 GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2576 indirect_ctx_offset =
2577 GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2580 indirect_ctx_offset =
2581 GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2584 indirect_ctx_offset =
2585 GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
2589 return indirect_ctx_offset;
2592 static void execlists_init_reg_state(u32 *regs,
2593 struct i915_gem_context *ctx,
2594 struct intel_engine_cs *engine,
2595 struct intel_ring *ring)
2597 struct drm_i915_private *dev_priv = engine->i915;
2598 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
2599 u32 base = engine->mmio_base;
2600 bool rcs = engine->class == RENDER_CLASS;
2602 /* A context is actually a big batch buffer with several
2603 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
2604 * values we are setting here are only for the first context restore:
2605 * on a subsequent save, the GPU will recreate this batchbuffer with new
2606 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
2607 * we are not initializing here).
2609 regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) |
2610 MI_LRI_FORCE_POSTED;
2612 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine),
2613 _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2614 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT) |
2615 _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
2616 (HAS_RESOURCE_STREAMER(dev_priv) ?
2617 CTX_CTRL_RS_CTX_ENABLE : 0)));
2618 CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0);
2619 CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0);
2620 CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0);
2621 CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base),
2622 RING_CTL_SIZE(ring->size) | RING_VALID);
2623 CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0);
2624 CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0);
2625 CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT);
2626 CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0);
2627 CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0);
2628 CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0);
2630 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2632 CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0);
2633 CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET,
2634 RING_INDIRECT_CTX_OFFSET(base), 0);
2635 if (wa_ctx->indirect_ctx.size) {
2636 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2638 regs[CTX_RCS_INDIRECT_CTX + 1] =
2639 (ggtt_offset + wa_ctx->indirect_ctx.offset) |
2640 (wa_ctx->indirect_ctx.size / CACHELINE_BYTES);
2642 regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] =
2643 intel_lr_indirect_ctx_offset(engine) << 6;
2646 CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0);
2647 if (wa_ctx->per_ctx.size) {
2648 u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2650 regs[CTX_BB_PER_CTX_PTR + 1] =
2651 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
2655 regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2657 CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0);
2658 /* PDP values well be assigned later if needed */
2659 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0);
2660 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0);
2661 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0);
2662 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0);
2663 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0);
2664 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0);
2665 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);
2666 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);
2668 if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {
2669 /* 64b PPGTT (48bit canonical)
2670 * PDP0_DESCRIPTOR contains the base address to PML4 and
2671 * other PDP Descriptors are ignored.
2673 ASSIGN_CTX_PML4(ppgtt, regs);
2677 regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2678 CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2679 make_rpcs(dev_priv));
2681 i915_oa_init_reg_state(engine, ctx, regs);
2686 populate_lr_context(struct i915_gem_context *ctx,
2687 struct drm_i915_gem_object *ctx_obj,
2688 struct intel_engine_cs *engine,
2689 struct intel_ring *ring)
2695 ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
2697 DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
2701 vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
2702 if (IS_ERR(vaddr)) {
2703 ret = PTR_ERR(vaddr);
2704 DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
2707 ctx_obj->mm.dirty = true;
2709 if (engine->default_state) {
2711 * We only want to copy over the template context state;
2712 * skipping over the headers reserved for GuC communication,
2713 * leaving those as zero.
2715 const unsigned long start = LRC_HEADER_PAGES * PAGE_SIZE;
2718 defaults = i915_gem_object_pin_map(engine->default_state,
2720 if (IS_ERR(defaults)) {
2721 ret = PTR_ERR(defaults);
2725 memcpy(vaddr + start, defaults + start, engine->context_size);
2726 i915_gem_object_unpin_map(engine->default_state);
2729 /* The second page of the context object contains some fields which must
2730 * be set up prior to the first execution. */
2731 regs = vaddr + LRC_STATE_PN * PAGE_SIZE;
2732 execlists_init_reg_state(regs, ctx, engine, ring);
2733 if (!engine->default_state)
2734 regs[CTX_CONTEXT_CONTROL + 1] |=
2735 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
2736 if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11)
2737 regs[CTX_CONTEXT_CONTROL + 1] |=
2738 _MASKED_BIT_ENABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
2739 CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT);
2742 i915_gem_object_unpin_map(ctx_obj);
2746 static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2747 struct intel_engine_cs *engine,
2748 struct intel_context *ce)
2750 struct drm_i915_gem_object *ctx_obj;
2751 struct i915_vma *vma;
2752 uint32_t context_size;
2753 struct intel_ring *ring;
2754 struct i915_timeline *timeline;
2760 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
2763 * Before the actual start of the context image, we insert a few pages
2764 * for our own use and for sharing with the GuC.
2766 context_size += LRC_HEADER_PAGES * PAGE_SIZE;
2768 ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2769 if (IS_ERR(ctx_obj))
2770 return PTR_ERR(ctx_obj);
2772 vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.vm, NULL);
2775 goto error_deref_obj;
2778 timeline = i915_timeline_create(ctx->i915, ctx->name);
2779 if (IS_ERR(timeline)) {
2780 ret = PTR_ERR(timeline);
2781 goto error_deref_obj;
2784 ring = intel_engine_create_ring(engine, timeline, ctx->ring_size);
2785 i915_timeline_put(timeline);
2787 ret = PTR_ERR(ring);
2788 goto error_deref_obj;
2791 ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2793 DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2794 goto error_ring_free;
2803 intel_ring_free(ring);
2805 i915_gem_object_put(ctx_obj);
2809 void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2811 struct intel_engine_cs *engine;
2812 struct i915_gem_context *ctx;
2813 enum intel_engine_id id;
2815 /* Because we emit WA_TAIL_DWORDS there may be a disparity
2816 * between our bookkeeping in ce->ring->head and ce->ring->tail and
2817 * that stored in context. As we only write new commands from
2818 * ce->ring->tail onwards, everything before that is junk. If the GPU
2819 * starts reading from its RING_HEAD from the context, it may try to
2820 * execute that junk and die.
2822 * So to avoid that we reset the context images upon resume. For
2823 * simplicity, we just zero everything out.
2825 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
2826 for_each_engine(engine, dev_priv, id) {
2827 struct intel_context *ce =
2828 to_intel_context(ctx, engine);
2834 reg = i915_gem_object_pin_map(ce->state->obj,
2836 if (WARN_ON(IS_ERR(reg)))
2839 reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
2840 reg[CTX_RING_HEAD+1] = 0;
2841 reg[CTX_RING_TAIL+1] = 0;
2843 ce->state->obj->mm.dirty = true;
2844 i915_gem_object_unpin_map(ce->state->obj);
2846 intel_ring_reset(ce->ring, 0);
2851 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
2852 #include "selftests/intel_lrc.c"