2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/i2c.h>
30 #include <linux/i2c-algo-bit.h>
31 #include <linux/export.h>
33 #include "intel_drv.h"
34 #include <drm/i915_drm.h>
42 /* Map gmbus pin pairs to names and registers. */
43 static const struct gmbus_pin gmbus_pins[] = {
44 [GMBUS_PIN_SSC] = { "ssc", GPIOB },
45 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
46 [GMBUS_PIN_PANEL] = { "panel", GPIOC },
47 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
48 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
49 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
52 static const struct gmbus_pin gmbus_pins_bdw[] = {
53 [GMBUS_PIN_VGADDC] = { "vga", GPIOA },
54 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
55 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
56 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
59 static const struct gmbus_pin gmbus_pins_skl[] = {
60 [GMBUS_PIN_DPC] = { "dpc", GPIOD },
61 [GMBUS_PIN_DPB] = { "dpb", GPIOE },
62 [GMBUS_PIN_DPD] = { "dpd", GPIOF },
65 static const struct gmbus_pin gmbus_pins_bxt[] = {
66 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
67 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
68 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
71 static const struct gmbus_pin gmbus_pins_cnp[] = {
72 [GMBUS_PIN_1_BXT] = { "dpb", GPIOB },
73 [GMBUS_PIN_2_BXT] = { "dpc", GPIOC },
74 [GMBUS_PIN_3_BXT] = { "misc", GPIOD },
75 [GMBUS_PIN_4_CNP] = { "dpd", GPIOE },
78 /* pin is expected to be valid */
79 static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
82 if (HAS_PCH_CNP(dev_priv))
83 return &gmbus_pins_cnp[pin];
84 else if (IS_GEN9_LP(dev_priv))
85 return &gmbus_pins_bxt[pin];
86 else if (IS_GEN9_BC(dev_priv))
87 return &gmbus_pins_skl[pin];
88 else if (IS_BROADWELL(dev_priv))
89 return &gmbus_pins_bdw[pin];
91 return &gmbus_pins[pin];
94 bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
99 if (HAS_PCH_CNP(dev_priv))
100 size = ARRAY_SIZE(gmbus_pins_cnp);
101 else if (IS_GEN9_LP(dev_priv))
102 size = ARRAY_SIZE(gmbus_pins_bxt);
103 else if (IS_GEN9_BC(dev_priv))
104 size = ARRAY_SIZE(gmbus_pins_skl);
105 else if (IS_BROADWELL(dev_priv))
106 size = ARRAY_SIZE(gmbus_pins_bdw);
108 size = ARRAY_SIZE(gmbus_pins);
111 i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
114 /* Intel GPIO access functions */
116 #define I2C_RISEFALL_TIME 10
118 static inline struct intel_gmbus *
119 to_intel_gmbus(struct i2c_adapter *i2c)
121 return container_of(i2c, struct intel_gmbus, adapter);
125 intel_i2c_reset(struct drm_i915_private *dev_priv)
127 I915_WRITE(GMBUS0, 0);
128 I915_WRITE(GMBUS4, 0);
131 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
135 /* When using bit bashing for I2C, this bit needs to be set to 1 */
136 if (!IS_PINEVIEW(dev_priv))
139 val = I915_READ(DSPCLK_GATE_D);
141 val |= DPCUNIT_CLOCK_GATE_DISABLE;
143 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
144 I915_WRITE(DSPCLK_GATE_D, val);
147 static u32 get_reserved(struct intel_gmbus *bus)
149 struct drm_i915_private *dev_priv = bus->dev_priv;
152 /* On most chips, these bits must be preserved in software. */
153 if (!IS_I830(dev_priv) && !IS_I845G(dev_priv))
154 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
155 (GPIO_DATA_PULLUP_DISABLE |
156 GPIO_CLOCK_PULLUP_DISABLE);
161 static int get_clock(void *data)
163 struct intel_gmbus *bus = data;
164 struct drm_i915_private *dev_priv = bus->dev_priv;
165 u32 reserved = get_reserved(bus);
166 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
167 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
168 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
171 static int get_data(void *data)
173 struct intel_gmbus *bus = data;
174 struct drm_i915_private *dev_priv = bus->dev_priv;
175 u32 reserved = get_reserved(bus);
176 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
177 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
178 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
181 static void set_clock(void *data, int state_high)
183 struct intel_gmbus *bus = data;
184 struct drm_i915_private *dev_priv = bus->dev_priv;
185 u32 reserved = get_reserved(bus);
189 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
191 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
194 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
195 POSTING_READ(bus->gpio_reg);
198 static void set_data(void *data, int state_high)
200 struct intel_gmbus *bus = data;
201 struct drm_i915_private *dev_priv = bus->dev_priv;
202 u32 reserved = get_reserved(bus);
206 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
208 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
211 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
212 POSTING_READ(bus->gpio_reg);
216 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
218 struct intel_gmbus *bus = container_of(adapter,
221 struct drm_i915_private *dev_priv = bus->dev_priv;
223 intel_i2c_reset(dev_priv);
224 intel_i2c_quirk_set(dev_priv, true);
227 udelay(I2C_RISEFALL_TIME);
232 intel_gpio_post_xfer(struct i2c_adapter *adapter)
234 struct intel_gmbus *bus = container_of(adapter,
237 struct drm_i915_private *dev_priv = bus->dev_priv;
241 intel_i2c_quirk_set(dev_priv, false);
245 intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
247 struct drm_i915_private *dev_priv = bus->dev_priv;
248 struct i2c_algo_bit_data *algo;
250 algo = &bus->bit_algo;
252 bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
253 i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
254 bus->adapter.algo_data = algo;
255 algo->setsda = set_data;
256 algo->setscl = set_clock;
257 algo->getsda = get_data;
258 algo->getscl = get_clock;
259 algo->pre_xfer = intel_gpio_pre_xfer;
260 algo->post_xfer = intel_gpio_post_xfer;
261 algo->udelay = I2C_RISEFALL_TIME;
262 algo->timeout = usecs_to_jiffies(2200);
266 static int gmbus_wait(struct drm_i915_private *dev_priv, u32 status, u32 irq_en)
272 /* Important: The hw handles only the first bit, so set only one! Since
273 * we also need to check for NAKs besides the hw ready/idle signal, we
274 * need to wake up periodically and check that ourselves.
276 if (!HAS_GMBUS_IRQ(dev_priv))
279 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
280 I915_WRITE_FW(GMBUS4, irq_en);
282 status |= GMBUS_SATOER;
283 ret = wait_for_us((gmbus2 = I915_READ_FW(GMBUS2)) & status, 2);
285 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50);
287 I915_WRITE_FW(GMBUS4, 0);
288 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
290 if (gmbus2 & GMBUS_SATOER)
297 gmbus_wait_idle(struct drm_i915_private *dev_priv)
303 /* Important: The hw handles only the first bit, so set only one! */
305 if (HAS_GMBUS_IRQ(dev_priv))
306 irq_enable = GMBUS_IDLE_EN;
308 add_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
309 I915_WRITE_FW(GMBUS4, irq_enable);
311 ret = intel_wait_for_register_fw(dev_priv,
312 GMBUS2, GMBUS_ACTIVE, 0,
315 I915_WRITE_FW(GMBUS4, 0);
316 remove_wait_queue(&dev_priv->gmbus_wait_queue, &wait);
322 gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
323 unsigned short addr, u8 *buf, unsigned int len,
326 I915_WRITE_FW(GMBUS1,
329 (len << GMBUS_BYTE_COUNT_SHIFT) |
330 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
331 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
336 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
340 val = I915_READ_FW(GMBUS3);
344 } while (--len && ++loop < 4);
351 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
355 unsigned int rx_size = msg->len;
360 len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
362 ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
363 buf, len, gmbus1_index);
369 } while (rx_size != 0);
375 gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
376 unsigned short addr, u8 *buf, unsigned int len)
378 unsigned int chunk_size = len;
382 while (len && loop < 4) {
383 val |= *buf++ << (8 * loop++);
387 I915_WRITE_FW(GMBUS3, val);
388 I915_WRITE_FW(GMBUS1,
390 (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
391 (addr << GMBUS_SLAVE_ADDR_SHIFT) |
392 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
398 val |= *buf++ << (8 * loop);
399 } while (--len && ++loop < 4);
401 I915_WRITE_FW(GMBUS3, val);
403 ret = gmbus_wait(dev_priv, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
412 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
415 unsigned int tx_size = msg->len;
420 len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
422 ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
428 } while (tx_size != 0);
434 * The gmbus controller can combine a 1 or 2 byte write with a read that
435 * immediately follows it by using an "INDEX" cycle.
438 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
440 return (i + 1 < num &&
441 msgs[i].addr == msgs[i + 1].addr &&
442 !(msgs[i].flags & I2C_M_RD) &&
443 (msgs[i].len == 1 || msgs[i].len == 2) &&
444 (msgs[i + 1].flags & I2C_M_RD));
448 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
450 u32 gmbus1_index = 0;
454 if (msgs[0].len == 2)
455 gmbus5 = GMBUS_2BYTE_INDEX_EN |
456 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
457 if (msgs[0].len == 1)
458 gmbus1_index = GMBUS_CYCLE_INDEX |
459 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
461 /* GMBUS5 holds 16-bit index */
463 I915_WRITE_FW(GMBUS5, gmbus5);
465 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
467 /* Clear GMBUS5 after each index transfer */
469 I915_WRITE_FW(GMBUS5, 0);
475 do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
477 struct intel_gmbus *bus = container_of(adapter,
480 struct drm_i915_private *dev_priv = bus->dev_priv;
481 int i = 0, inc, try = 0;
485 I915_WRITE_FW(GMBUS0, bus->reg0);
487 for (; i < num; i += inc) {
489 if (gmbus_is_index_read(msgs, i, num)) {
490 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
491 inc = 2; /* an index read is two msgs */
492 } else if (msgs[i].flags & I2C_M_RD) {
493 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
495 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
499 ret = gmbus_wait(dev_priv,
500 GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
501 if (ret == -ETIMEDOUT)
507 /* Generate a STOP condition on the bus. Note that gmbus can't generata
508 * a STOP on the very first cycle. To simplify the code we
509 * unconditionally generate the STOP condition with an additional gmbus
511 I915_WRITE_FW(GMBUS1, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
513 /* Mark the GMBUS interface as disabled after waiting for idle.
514 * We will re-enable it at the start of the next xfer,
515 * till then let it sleep.
517 if (gmbus_wait_idle(dev_priv)) {
518 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
522 I915_WRITE_FW(GMBUS0, 0);
528 * Wait for bus to IDLE before clearing NAK.
529 * If we clear the NAK while bus is still active, then it will stay
530 * active and the next transaction may fail.
532 * If no ACK is received during the address phase of a transaction, the
533 * adapter must report -ENXIO. It is not clear what to return if no ACK
534 * is received at other times. But we have to be careful to not return
535 * spurious -ENXIO because that will prevent i2c and drm edid functions
536 * from retrying. So return -ENXIO only when gmbus properly quiescents -
537 * timing out seems to happen when there _is_ a ddc chip present, but
538 * it's slow responding and only answers on the 2nd retry.
541 if (gmbus_wait_idle(dev_priv)) {
542 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
547 /* Toggle the Software Clear Interrupt bit. This has the effect
548 * of resetting the GMBUS controller and so clearing the
549 * BUS_ERROR raised by the slave's NAK.
551 I915_WRITE_FW(GMBUS1, GMBUS_SW_CLR_INT);
552 I915_WRITE_FW(GMBUS1, 0);
553 I915_WRITE_FW(GMBUS0, 0);
555 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
556 adapter->name, msgs[i].addr,
557 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
560 * Passive adapters sometimes NAK the first probe. Retry the first
561 * message once on -ENXIO for GMBUS transfers; the bit banging algorithm
562 * has retries internally. See also the retry loop in
563 * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
565 if (ret == -ENXIO && i == 0 && try++ == 0) {
566 DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
574 DRM_DEBUG_KMS("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
575 bus->adapter.name, bus->reg0 & 0xff);
576 I915_WRITE_FW(GMBUS0, 0);
579 * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
580 * instead. Use EAGAIN to have i2c core retry.
589 gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
591 struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus,
593 struct drm_i915_private *dev_priv = bus->dev_priv;
596 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
598 if (bus->force_bit) {
599 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
601 bus->force_bit &= ~GMBUS_FORCE_BIT_RETRY;
603 ret = do_gmbus_xfer(adapter, msgs, num);
605 bus->force_bit |= GMBUS_FORCE_BIT_RETRY;
608 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
613 static u32 gmbus_func(struct i2c_adapter *adapter)
615 return i2c_bit_algo.functionality(adapter) &
616 (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
617 /* I2C_FUNC_10BIT_ADDR | */
618 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
619 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
622 static const struct i2c_algorithm gmbus_algorithm = {
623 .master_xfer = gmbus_xfer,
624 .functionality = gmbus_func
627 static void gmbus_lock_bus(struct i2c_adapter *adapter,
630 struct intel_gmbus *bus = to_intel_gmbus(adapter);
631 struct drm_i915_private *dev_priv = bus->dev_priv;
633 mutex_lock(&dev_priv->gmbus_mutex);
636 static int gmbus_trylock_bus(struct i2c_adapter *adapter,
639 struct intel_gmbus *bus = to_intel_gmbus(adapter);
640 struct drm_i915_private *dev_priv = bus->dev_priv;
642 return mutex_trylock(&dev_priv->gmbus_mutex);
645 static void gmbus_unlock_bus(struct i2c_adapter *adapter,
648 struct intel_gmbus *bus = to_intel_gmbus(adapter);
649 struct drm_i915_private *dev_priv = bus->dev_priv;
651 mutex_unlock(&dev_priv->gmbus_mutex);
654 static const struct i2c_lock_operations gmbus_lock_ops = {
655 .lock_bus = gmbus_lock_bus,
656 .trylock_bus = gmbus_trylock_bus,
657 .unlock_bus = gmbus_unlock_bus,
661 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
662 * @dev_priv: i915 device private
664 int intel_setup_gmbus(struct drm_i915_private *dev_priv)
666 struct pci_dev *pdev = dev_priv->drm.pdev;
667 struct intel_gmbus *bus;
671 if (HAS_PCH_NOP(dev_priv))
674 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
675 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
676 else if (!HAS_GMCH_DISPLAY(dev_priv))
677 dev_priv->gpio_mmio_base =
678 i915_mmio_reg_offset(PCH_GPIOA) -
679 i915_mmio_reg_offset(GPIOA);
681 mutex_init(&dev_priv->gmbus_mutex);
682 init_waitqueue_head(&dev_priv->gmbus_wait_queue);
684 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
685 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
688 bus = &dev_priv->gmbus[pin];
690 bus->adapter.owner = THIS_MODULE;
691 bus->adapter.class = I2C_CLASS_DDC;
692 snprintf(bus->adapter.name,
693 sizeof(bus->adapter.name),
695 get_gmbus_pin(dev_priv, pin)->name);
697 bus->adapter.dev.parent = &pdev->dev;
698 bus->dev_priv = dev_priv;
700 bus->adapter.algo = &gmbus_algorithm;
701 bus->adapter.lock_ops = &gmbus_lock_ops;
704 * We wish to retry with bit banging
705 * after a timed out GMBUS attempt.
707 bus->adapter.retries = 1;
709 /* By default use a conservative clock rate */
710 bus->reg0 = pin | GMBUS_RATE_100KHZ;
712 /* gmbus seems to be broken on i830 */
713 if (IS_I830(dev_priv))
716 intel_gpio_setup(bus, pin);
718 ret = i2c_add_adapter(&bus->adapter);
723 intel_i2c_reset(dev_priv);
729 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
732 bus = &dev_priv->gmbus[pin];
733 i2c_del_adapter(&bus->adapter);
738 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
741 if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
744 return &dev_priv->gmbus[pin].adapter;
747 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
749 struct intel_gmbus *bus = to_intel_gmbus(adapter);
751 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
754 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
756 struct intel_gmbus *bus = to_intel_gmbus(adapter);
757 struct drm_i915_private *dev_priv = bus->dev_priv;
759 mutex_lock(&dev_priv->gmbus_mutex);
761 bus->force_bit += force_bit ? 1 : -1;
762 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
763 force_bit ? "en" : "dis", adapter->name,
766 mutex_unlock(&dev_priv->gmbus_mutex);
769 void intel_teardown_gmbus(struct drm_i915_private *dev_priv)
771 struct intel_gmbus *bus;
774 for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
775 if (!intel_gmbus_is_valid_pin(dev_priv, pin))
778 bus = &dev_priv->gmbus[pin];
779 i2c_del_adapter(&bus->adapter);