2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include "intel_drv.h"
38 #include <drm/i915_drm.h>
41 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
43 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
47 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
49 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
50 struct drm_i915_private *dev_priv = dev->dev_private;
51 uint32_t enabled_bits;
53 enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
56 "HDMI port enabled, expecting disabled\n");
59 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
61 struct intel_digital_port *intel_dig_port =
62 container_of(encoder, struct intel_digital_port, base.base);
63 return &intel_dig_port->hdmi;
66 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
68 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
71 static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
74 case HDMI_INFOFRAME_TYPE_AVI:
75 return VIDEO_DIP_SELECT_AVI;
76 case HDMI_INFOFRAME_TYPE_SPD:
77 return VIDEO_DIP_SELECT_SPD;
78 case HDMI_INFOFRAME_TYPE_VENDOR:
79 return VIDEO_DIP_SELECT_VENDOR;
81 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
86 static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
89 case HDMI_INFOFRAME_TYPE_AVI:
90 return VIDEO_DIP_ENABLE_AVI;
91 case HDMI_INFOFRAME_TYPE_SPD:
92 return VIDEO_DIP_ENABLE_SPD;
93 case HDMI_INFOFRAME_TYPE_VENDOR:
94 return VIDEO_DIP_ENABLE_VENDOR;
96 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
101 static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
104 case HDMI_INFOFRAME_TYPE_AVI:
105 return VIDEO_DIP_ENABLE_AVI_HSW;
106 case HDMI_INFOFRAME_TYPE_SPD:
107 return VIDEO_DIP_ENABLE_SPD_HSW;
108 case HDMI_INFOFRAME_TYPE_VENDOR:
109 return VIDEO_DIP_ENABLE_VS_HSW;
111 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
116 static u32 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
117 enum transcoder cpu_transcoder,
118 enum hdmi_infoframe_type type,
122 case HDMI_INFOFRAME_TYPE_AVI:
123 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
124 case HDMI_INFOFRAME_TYPE_SPD:
125 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
126 case HDMI_INFOFRAME_TYPE_VENDOR:
127 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
129 DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
134 static void g4x_write_infoframe(struct drm_encoder *encoder,
135 enum hdmi_infoframe_type type,
136 const void *frame, ssize_t len)
138 const uint32_t *data = frame;
139 struct drm_device *dev = encoder->dev;
140 struct drm_i915_private *dev_priv = dev->dev_private;
141 u32 val = I915_READ(VIDEO_DIP_CTL);
144 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
146 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
147 val |= g4x_infoframe_index(type);
149 val &= ~g4x_infoframe_enable(type);
151 I915_WRITE(VIDEO_DIP_CTL, val);
154 for (i = 0; i < len; i += 4) {
155 I915_WRITE(VIDEO_DIP_DATA, *data);
158 /* Write every possible data byte to force correct ECC calculation. */
159 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
160 I915_WRITE(VIDEO_DIP_DATA, 0);
163 val |= g4x_infoframe_enable(type);
164 val &= ~VIDEO_DIP_FREQ_MASK;
165 val |= VIDEO_DIP_FREQ_VSYNC;
167 I915_WRITE(VIDEO_DIP_CTL, val);
168 POSTING_READ(VIDEO_DIP_CTL);
171 static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
173 struct drm_device *dev = encoder->dev;
174 struct drm_i915_private *dev_priv = dev->dev_private;
175 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
176 u32 val = I915_READ(VIDEO_DIP_CTL);
178 if ((val & VIDEO_DIP_ENABLE) == 0)
181 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
184 return val & (VIDEO_DIP_ENABLE_AVI |
185 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
188 static void ibx_write_infoframe(struct drm_encoder *encoder,
189 enum hdmi_infoframe_type type,
190 const void *frame, ssize_t len)
192 const uint32_t *data = frame;
193 struct drm_device *dev = encoder->dev;
194 struct drm_i915_private *dev_priv = dev->dev_private;
195 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
196 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
197 u32 val = I915_READ(reg);
199 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
201 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
202 val |= g4x_infoframe_index(type);
204 val &= ~g4x_infoframe_enable(type);
206 I915_WRITE(reg, val);
209 for (i = 0; i < len; i += 4) {
210 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
213 /* Write every possible data byte to force correct ECC calculation. */
214 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
215 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
218 val |= g4x_infoframe_enable(type);
219 val &= ~VIDEO_DIP_FREQ_MASK;
220 val |= VIDEO_DIP_FREQ_VSYNC;
222 I915_WRITE(reg, val);
226 static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
228 struct drm_device *dev = encoder->dev;
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
231 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
232 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
233 u32 val = I915_READ(reg);
235 if ((val & VIDEO_DIP_ENABLE) == 0)
238 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
241 return val & (VIDEO_DIP_ENABLE_AVI |
242 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
243 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
246 static void cpt_write_infoframe(struct drm_encoder *encoder,
247 enum hdmi_infoframe_type type,
248 const void *frame, ssize_t len)
250 const uint32_t *data = frame;
251 struct drm_device *dev = encoder->dev;
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
254 int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
255 u32 val = I915_READ(reg);
257 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
259 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
260 val |= g4x_infoframe_index(type);
262 /* The DIP control register spec says that we need to update the AVI
263 * infoframe without clearing its enable bit */
264 if (type != HDMI_INFOFRAME_TYPE_AVI)
265 val &= ~g4x_infoframe_enable(type);
267 I915_WRITE(reg, val);
270 for (i = 0; i < len; i += 4) {
271 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
274 /* Write every possible data byte to force correct ECC calculation. */
275 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
276 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
279 val |= g4x_infoframe_enable(type);
280 val &= ~VIDEO_DIP_FREQ_MASK;
281 val |= VIDEO_DIP_FREQ_VSYNC;
283 I915_WRITE(reg, val);
287 static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
289 struct drm_device *dev = encoder->dev;
290 struct drm_i915_private *dev_priv = dev->dev_private;
291 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
292 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
293 u32 val = I915_READ(reg);
295 if ((val & VIDEO_DIP_ENABLE) == 0)
298 return val & (VIDEO_DIP_ENABLE_AVI |
299 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
300 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
303 static void vlv_write_infoframe(struct drm_encoder *encoder,
304 enum hdmi_infoframe_type type,
305 const void *frame, ssize_t len)
307 const uint32_t *data = frame;
308 struct drm_device *dev = encoder->dev;
309 struct drm_i915_private *dev_priv = dev->dev_private;
310 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
311 int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
312 u32 val = I915_READ(reg);
314 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
316 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
317 val |= g4x_infoframe_index(type);
319 val &= ~g4x_infoframe_enable(type);
321 I915_WRITE(reg, val);
324 for (i = 0; i < len; i += 4) {
325 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
328 /* Write every possible data byte to force correct ECC calculation. */
329 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
330 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
333 val |= g4x_infoframe_enable(type);
334 val &= ~VIDEO_DIP_FREQ_MASK;
335 val |= VIDEO_DIP_FREQ_VSYNC;
337 I915_WRITE(reg, val);
341 static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
343 struct drm_device *dev = encoder->dev;
344 struct drm_i915_private *dev_priv = dev->dev_private;
345 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
346 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
347 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
348 u32 val = I915_READ(reg);
350 if ((val & VIDEO_DIP_ENABLE) == 0)
353 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
356 return val & (VIDEO_DIP_ENABLE_AVI |
357 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
358 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
361 static void hsw_write_infoframe(struct drm_encoder *encoder,
362 enum hdmi_infoframe_type type,
363 const void *frame, ssize_t len)
365 const uint32_t *data = frame;
366 struct drm_device *dev = encoder->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
369 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
370 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
373 u32 val = I915_READ(ctl_reg);
375 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
379 val &= ~hsw_infoframe_enable(type);
380 I915_WRITE(ctl_reg, val);
383 for (i = 0; i < len; i += 4) {
384 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
385 type, i >> 2), *data);
388 /* Write every possible data byte to force correct ECC calculation. */
389 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
390 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
394 val |= hsw_infoframe_enable(type);
395 I915_WRITE(ctl_reg, val);
396 POSTING_READ(ctl_reg);
399 static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
401 struct drm_device *dev = encoder->dev;
402 struct drm_i915_private *dev_priv = dev->dev_private;
403 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
404 u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
405 u32 val = I915_READ(ctl_reg);
407 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
408 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
409 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
413 * The data we write to the DIP data buffer registers is 1 byte bigger than the
414 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
415 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
416 * used for both technologies.
418 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
419 * DW1: DB3 | DB2 | DB1 | DB0
420 * DW2: DB7 | DB6 | DB5 | DB4
423 * (HB is Header Byte, DB is Data Byte)
425 * The hdmi pack() functions don't know about that hardware specific hole so we
426 * trick them by giving an offset into the buffer and moving back the header
429 static void intel_write_infoframe(struct drm_encoder *encoder,
430 union hdmi_infoframe *frame)
432 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
433 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
436 /* see comment above for the reason for this offset */
437 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
441 /* Insert the 'hole' (see big comment above) at position 3 */
442 buffer[0] = buffer[1];
443 buffer[1] = buffer[2];
444 buffer[2] = buffer[3];
448 intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
451 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
452 const struct drm_display_mode *adjusted_mode)
454 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
455 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
456 union hdmi_infoframe frame;
459 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
462 DRM_ERROR("couldn't fill AVI infoframe\n");
466 if (intel_hdmi->rgb_quant_range_selectable) {
467 if (intel_crtc->config->limited_color_range)
468 frame.avi.quantization_range =
469 HDMI_QUANTIZATION_RANGE_LIMITED;
471 frame.avi.quantization_range =
472 HDMI_QUANTIZATION_RANGE_FULL;
475 intel_write_infoframe(encoder, &frame);
478 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
480 union hdmi_infoframe frame;
483 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
485 DRM_ERROR("couldn't fill SPD infoframe\n");
489 frame.spd.sdi = HDMI_SPD_SDI_PC;
491 intel_write_infoframe(encoder, &frame);
495 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
496 const struct drm_display_mode *adjusted_mode)
498 union hdmi_infoframe frame;
501 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
506 intel_write_infoframe(encoder, &frame);
509 static void g4x_set_infoframes(struct drm_encoder *encoder,
511 const struct drm_display_mode *adjusted_mode)
513 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
514 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
515 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
516 u32 reg = VIDEO_DIP_CTL;
517 u32 val = I915_READ(reg);
518 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
520 assert_hdmi_port_disabled(intel_hdmi);
522 /* If the registers were not initialized yet, they might be zeroes,
523 * which means we're selecting the AVI DIP and we're setting its
524 * frequency to once. This seems to really confuse the HW and make
525 * things stop working (the register spec says the AVI always needs to
526 * be sent every VSync). So here we avoid writing to the register more
527 * than we need and also explicitly select the AVI DIP and explicitly
528 * set its frequency to every VSync. Avoiding to write it twice seems to
529 * be enough to solve the problem, but being defensive shouldn't hurt us
531 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
534 if (!(val & VIDEO_DIP_ENABLE))
536 if (port != (val & VIDEO_DIP_PORT_MASK)) {
537 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
538 (val & VIDEO_DIP_PORT_MASK) >> 29);
541 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
542 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
543 I915_WRITE(reg, val);
548 if (port != (val & VIDEO_DIP_PORT_MASK)) {
549 if (val & VIDEO_DIP_ENABLE) {
550 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
551 (val & VIDEO_DIP_PORT_MASK) >> 29);
554 val &= ~VIDEO_DIP_PORT_MASK;
558 val |= VIDEO_DIP_ENABLE;
559 val &= ~(VIDEO_DIP_ENABLE_AVI |
560 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
562 I915_WRITE(reg, val);
565 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
566 intel_hdmi_set_spd_infoframe(encoder);
567 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
570 static bool hdmi_sink_is_deep_color(struct drm_encoder *encoder)
572 struct drm_device *dev = encoder->dev;
573 struct drm_connector *connector;
575 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
578 * HDMI cloning is only supported on g4x which doesn't
579 * support deep color or GCP infoframes anyway so no
580 * need to worry about multiple HDMI sinks here.
582 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
583 if (connector->encoder == encoder)
584 return connector->display_info.bpc > 8;
590 * Determine if default_phase=1 can be indicated in the GCP infoframe.
592 * From HDMI specification 1.4a:
593 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
594 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
595 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
596 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
599 static bool gcp_default_phase_possible(int pipe_bpp,
600 const struct drm_display_mode *mode)
602 unsigned int pixels_per_group;
606 /* 4 pixels in 5 clocks */
607 pixels_per_group = 4;
610 /* 2 pixels in 3 clocks */
611 pixels_per_group = 2;
614 /* 1 pixel in 2 clocks */
615 pixels_per_group = 1;
618 /* phase information not relevant for 8bpc */
622 return mode->crtc_hdisplay % pixels_per_group == 0 &&
623 mode->crtc_htotal % pixels_per_group == 0 &&
624 mode->crtc_hblank_start % pixels_per_group == 0 &&
625 mode->crtc_hblank_end % pixels_per_group == 0 &&
626 mode->crtc_hsync_start % pixels_per_group == 0 &&
627 mode->crtc_hsync_end % pixels_per_group == 0 &&
628 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
629 mode->crtc_htotal/2 % pixels_per_group == 0);
632 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder)
634 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
635 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
638 if (HAS_DDI(dev_priv))
639 reg = HSW_TVIDEO_DIP_GCP(crtc->config->cpu_transcoder);
640 else if (IS_VALLEYVIEW(dev_priv))
641 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
642 else if (HAS_PCH_SPLIT(dev_priv->dev))
643 reg = TVIDEO_DIP_GCP(crtc->pipe);
647 /* Indicate color depth whenever the sink supports deep color */
648 if (hdmi_sink_is_deep_color(encoder))
649 val |= GCP_COLOR_INDICATION;
651 /* Enable default_phase whenever the display mode is suitably aligned */
652 if (gcp_default_phase_possible(crtc->config->pipe_bpp,
653 &crtc->config->base.adjusted_mode))
654 val |= GCP_DEFAULT_PHASE_ENABLE;
656 I915_WRITE(reg, val);
661 static void ibx_set_infoframes(struct drm_encoder *encoder,
663 const struct drm_display_mode *adjusted_mode)
665 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
666 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
667 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
668 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
669 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
670 u32 val = I915_READ(reg);
671 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
673 assert_hdmi_port_disabled(intel_hdmi);
675 /* See the big comment in g4x_set_infoframes() */
676 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
679 if (!(val & VIDEO_DIP_ENABLE))
681 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
682 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
683 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
684 I915_WRITE(reg, val);
689 if (port != (val & VIDEO_DIP_PORT_MASK)) {
690 WARN(val & VIDEO_DIP_ENABLE,
691 "DIP already enabled on port %c\n",
692 (val & VIDEO_DIP_PORT_MASK) >> 29);
693 val &= ~VIDEO_DIP_PORT_MASK;
697 val |= VIDEO_DIP_ENABLE;
698 val &= ~(VIDEO_DIP_ENABLE_AVI |
699 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
700 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
702 if (intel_hdmi_set_gcp_infoframe(encoder))
703 val |= VIDEO_DIP_ENABLE_GCP;
705 I915_WRITE(reg, val);
708 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
709 intel_hdmi_set_spd_infoframe(encoder);
710 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
713 static void cpt_set_infoframes(struct drm_encoder *encoder,
715 const struct drm_display_mode *adjusted_mode)
717 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
718 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
719 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
720 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
721 u32 val = I915_READ(reg);
723 assert_hdmi_port_disabled(intel_hdmi);
725 /* See the big comment in g4x_set_infoframes() */
726 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
729 if (!(val & VIDEO_DIP_ENABLE))
731 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
732 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
733 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
734 I915_WRITE(reg, val);
739 /* Set both together, unset both together: see the spec. */
740 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
741 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
742 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
744 if (intel_hdmi_set_gcp_infoframe(encoder))
745 val |= VIDEO_DIP_ENABLE_GCP;
747 I915_WRITE(reg, val);
750 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
751 intel_hdmi_set_spd_infoframe(encoder);
752 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
755 static void vlv_set_infoframes(struct drm_encoder *encoder,
757 const struct drm_display_mode *adjusted_mode)
759 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
760 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
761 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
762 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
763 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
764 u32 val = I915_READ(reg);
765 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
767 assert_hdmi_port_disabled(intel_hdmi);
769 /* See the big comment in g4x_set_infoframes() */
770 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
773 if (!(val & VIDEO_DIP_ENABLE))
775 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
776 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
777 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
778 I915_WRITE(reg, val);
783 if (port != (val & VIDEO_DIP_PORT_MASK)) {
784 WARN(val & VIDEO_DIP_ENABLE,
785 "DIP already enabled on port %c\n",
786 (val & VIDEO_DIP_PORT_MASK) >> 29);
787 val &= ~VIDEO_DIP_PORT_MASK;
791 val |= VIDEO_DIP_ENABLE;
792 val &= ~(VIDEO_DIP_ENABLE_AVI |
793 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
794 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
796 if (intel_hdmi_set_gcp_infoframe(encoder))
797 val |= VIDEO_DIP_ENABLE_GCP;
799 I915_WRITE(reg, val);
802 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
803 intel_hdmi_set_spd_infoframe(encoder);
804 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
807 static void hsw_set_infoframes(struct drm_encoder *encoder,
809 const struct drm_display_mode *adjusted_mode)
811 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
812 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
813 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
814 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config->cpu_transcoder);
815 u32 val = I915_READ(reg);
817 assert_hdmi_port_disabled(intel_hdmi);
819 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
820 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
821 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
824 I915_WRITE(reg, val);
829 if (intel_hdmi_set_gcp_infoframe(encoder))
830 val |= VIDEO_DIP_ENABLE_GCP_HSW;
832 I915_WRITE(reg, val);
835 intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
836 intel_hdmi_set_spd_infoframe(encoder);
837 intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
840 static void intel_hdmi_prepare(struct intel_encoder *encoder)
842 struct drm_device *dev = encoder->base.dev;
843 struct drm_i915_private *dev_priv = dev->dev_private;
844 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
845 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
846 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
849 hdmi_val = SDVO_ENCODING_HDMI;
850 if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range)
851 hdmi_val |= HDMI_COLOR_RANGE_16_235;
852 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
853 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
854 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
855 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
857 if (crtc->config->pipe_bpp > 24)
858 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
860 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
862 if (crtc->config->has_hdmi_sink)
863 hdmi_val |= HDMI_MODE_SELECT_HDMI;
865 if (HAS_PCH_CPT(dev))
866 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
867 else if (IS_CHERRYVIEW(dev))
868 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
870 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
872 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
873 POSTING_READ(intel_hdmi->hdmi_reg);
876 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
879 struct drm_device *dev = encoder->base.dev;
880 struct drm_i915_private *dev_priv = dev->dev_private;
881 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
882 enum intel_display_power_domain power_domain;
885 power_domain = intel_display_port_power_domain(encoder);
886 if (!intel_display_power_is_enabled(dev_priv, power_domain))
889 tmp = I915_READ(intel_hdmi->hdmi_reg);
891 if (!(tmp & SDVO_ENABLE))
894 if (HAS_PCH_CPT(dev))
895 *pipe = PORT_TO_PIPE_CPT(tmp);
896 else if (IS_CHERRYVIEW(dev))
897 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
899 *pipe = PORT_TO_PIPE(tmp);
904 static void intel_hdmi_get_config(struct intel_encoder *encoder,
905 struct intel_crtc_state *pipe_config)
907 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
908 struct drm_device *dev = encoder->base.dev;
909 struct drm_i915_private *dev_priv = dev->dev_private;
913 tmp = I915_READ(intel_hdmi->hdmi_reg);
915 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
916 flags |= DRM_MODE_FLAG_PHSYNC;
918 flags |= DRM_MODE_FLAG_NHSYNC;
920 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
921 flags |= DRM_MODE_FLAG_PVSYNC;
923 flags |= DRM_MODE_FLAG_NVSYNC;
925 if (tmp & HDMI_MODE_SELECT_HDMI)
926 pipe_config->has_hdmi_sink = true;
928 if (intel_hdmi->infoframe_enabled(&encoder->base))
929 pipe_config->has_infoframe = true;
931 if (tmp & SDVO_AUDIO_ENABLE)
932 pipe_config->has_audio = true;
934 if (!HAS_PCH_SPLIT(dev) &&
935 tmp & HDMI_COLOR_RANGE_16_235)
936 pipe_config->limited_color_range = true;
938 pipe_config->base.adjusted_mode.flags |= flags;
940 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
941 dotclock = pipe_config->port_clock * 2 / 3;
943 dotclock = pipe_config->port_clock;
945 if (pipe_config->pixel_multiplier)
946 dotclock /= pipe_config->pixel_multiplier;
948 if (HAS_PCH_SPLIT(dev_priv->dev))
949 ironlake_check_encoder_dotclock(pipe_config, dotclock);
951 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
954 static void intel_enable_hdmi_audio(struct intel_encoder *encoder)
956 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
958 WARN_ON(!crtc->config->has_hdmi_sink);
959 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
960 pipe_name(crtc->pipe));
961 intel_audio_codec_enable(encoder);
964 static void g4x_enable_hdmi(struct intel_encoder *encoder)
966 struct drm_device *dev = encoder->base.dev;
967 struct drm_i915_private *dev_priv = dev->dev_private;
968 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
969 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
972 temp = I915_READ(intel_hdmi->hdmi_reg);
975 if (crtc->config->has_audio)
976 temp |= SDVO_AUDIO_ENABLE;
978 I915_WRITE(intel_hdmi->hdmi_reg, temp);
979 POSTING_READ(intel_hdmi->hdmi_reg);
981 if (crtc->config->has_audio)
982 intel_enable_hdmi_audio(encoder);
985 static void ibx_enable_hdmi(struct intel_encoder *encoder)
987 struct drm_device *dev = encoder->base.dev;
988 struct drm_i915_private *dev_priv = dev->dev_private;
989 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
990 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
993 temp = I915_READ(intel_hdmi->hdmi_reg);
996 if (crtc->config->has_audio)
997 temp |= SDVO_AUDIO_ENABLE;
1000 * HW workaround, need to write this twice for issue
1001 * that may result in first write getting masked.
1003 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1004 POSTING_READ(intel_hdmi->hdmi_reg);
1005 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1006 POSTING_READ(intel_hdmi->hdmi_reg);
1009 * HW workaround, need to toggle enable bit off and on
1010 * for 12bpc with pixel repeat.
1012 * FIXME: BSpec says this should be done at the end of
1013 * of the modeset sequence, so not sure if this isn't too soon.
1015 if (crtc->config->pipe_bpp > 24 &&
1016 crtc->config->pixel_multiplier > 1) {
1017 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1018 POSTING_READ(intel_hdmi->hdmi_reg);
1021 * HW workaround, need to write this twice for issue
1022 * that may result in first write getting masked.
1024 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1025 POSTING_READ(intel_hdmi->hdmi_reg);
1026 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1027 POSTING_READ(intel_hdmi->hdmi_reg);
1030 if (crtc->config->has_audio)
1031 intel_enable_hdmi_audio(encoder);
1034 static void cpt_enable_hdmi(struct intel_encoder *encoder)
1036 struct drm_device *dev = encoder->base.dev;
1037 struct drm_i915_private *dev_priv = dev->dev_private;
1038 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1039 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1040 enum pipe pipe = crtc->pipe;
1043 temp = I915_READ(intel_hdmi->hdmi_reg);
1045 temp |= SDVO_ENABLE;
1046 if (crtc->config->has_audio)
1047 temp |= SDVO_AUDIO_ENABLE;
1050 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1052 * The procedure for 12bpc is as follows:
1053 * 1. disable HDMI clock gating
1054 * 2. enable HDMI with 8bpc
1055 * 3. enable HDMI with 12bpc
1056 * 4. enable HDMI clock gating
1059 if (crtc->config->pipe_bpp > 24) {
1060 I915_WRITE(TRANS_CHICKEN1(pipe),
1061 I915_READ(TRANS_CHICKEN1(pipe)) |
1062 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1064 temp &= ~SDVO_COLOR_FORMAT_MASK;
1065 temp |= SDVO_COLOR_FORMAT_8bpc;
1068 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1069 POSTING_READ(intel_hdmi->hdmi_reg);
1071 if (crtc->config->pipe_bpp > 24) {
1072 temp &= ~SDVO_COLOR_FORMAT_MASK;
1073 temp |= HDMI_COLOR_FORMAT_12bpc;
1075 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1076 POSTING_READ(intel_hdmi->hdmi_reg);
1078 I915_WRITE(TRANS_CHICKEN1(pipe),
1079 I915_READ(TRANS_CHICKEN1(pipe)) &
1080 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1083 if (crtc->config->has_audio)
1084 intel_enable_hdmi_audio(encoder);
1087 static void vlv_enable_hdmi(struct intel_encoder *encoder)
1091 static void intel_disable_hdmi(struct intel_encoder *encoder)
1093 struct drm_device *dev = encoder->base.dev;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1096 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1099 temp = I915_READ(intel_hdmi->hdmi_reg);
1101 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1102 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1103 POSTING_READ(intel_hdmi->hdmi_reg);
1106 * HW workaround for IBX, we need to move the port
1107 * to transcoder A after disabling it to allow the
1108 * matching DP port to be enabled on transcoder A.
1110 if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
1111 temp &= ~SDVO_PIPE_B_SELECT;
1112 temp |= SDVO_ENABLE;
1114 * HW workaround, need to write this twice for issue
1115 * that may result in first write getting masked.
1117 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1118 POSTING_READ(intel_hdmi->hdmi_reg);
1119 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1120 POSTING_READ(intel_hdmi->hdmi_reg);
1122 temp &= ~SDVO_ENABLE;
1123 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1124 POSTING_READ(intel_hdmi->hdmi_reg);
1127 intel_hdmi->set_infoframes(&encoder->base, false, NULL);
1130 static void g4x_disable_hdmi(struct intel_encoder *encoder)
1132 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1134 if (crtc->config->has_audio)
1135 intel_audio_codec_disable(encoder);
1137 intel_disable_hdmi(encoder);
1140 static void pch_disable_hdmi(struct intel_encoder *encoder)
1142 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1144 if (crtc->config->has_audio)
1145 intel_audio_codec_disable(encoder);
1148 static void pch_post_disable_hdmi(struct intel_encoder *encoder)
1150 intel_disable_hdmi(encoder);
1153 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
1155 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1157 if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
1159 else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
1165 static enum drm_mode_status
1166 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1167 int clock, bool respect_dvi_limit)
1169 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1172 return MODE_CLOCK_LOW;
1173 if (clock > hdmi_port_clock_limit(hdmi, respect_dvi_limit))
1174 return MODE_CLOCK_HIGH;
1176 /* BXT DPLL can't generate 223-240 MHz */
1177 if (IS_BROXTON(dev) && clock > 223333 && clock < 240000)
1178 return MODE_CLOCK_RANGE;
1180 /* CHV DPLL can't generate 216-240 MHz */
1181 if (IS_CHERRYVIEW(dev) && clock > 216000 && clock < 240000)
1182 return MODE_CLOCK_RANGE;
1187 static enum drm_mode_status
1188 intel_hdmi_mode_valid(struct drm_connector *connector,
1189 struct drm_display_mode *mode)
1191 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1192 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1193 enum drm_mode_status status;
1196 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1197 return MODE_NO_DBLESCAN;
1199 clock = mode->clock;
1200 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1203 /* check if we can do 8bpc */
1204 status = hdmi_port_clock_valid(hdmi, clock, true);
1206 /* if we can't do 8bpc we may still be able to do 12bpc */
1207 if (!HAS_GMCH_DISPLAY(dev) && status != MODE_OK)
1208 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true);
1213 static bool hdmi_12bpc_possible(struct intel_crtc_state *crtc_state)
1215 struct drm_device *dev = crtc_state->base.crtc->dev;
1216 struct drm_atomic_state *state;
1217 struct intel_encoder *encoder;
1218 struct drm_connector *connector;
1219 struct drm_connector_state *connector_state;
1220 int count = 0, count_hdmi = 0;
1223 if (HAS_GMCH_DISPLAY(dev))
1226 state = crtc_state->base.state;
1228 for_each_connector_in_state(state, connector, connector_state, i) {
1229 if (connector_state->crtc != crtc_state->base.crtc)
1232 encoder = to_intel_encoder(connector_state->best_encoder);
1234 count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
1239 * HDMI 12bpc affects the clocks, so it's only possible
1240 * when not cloning with other encoder types.
1242 return count_hdmi > 0 && count_hdmi == count;
1245 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1246 struct intel_crtc_state *pipe_config)
1248 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1249 struct drm_device *dev = encoder->base.dev;
1250 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1251 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1252 int clock_12bpc = clock_8bpc * 3 / 2;
1255 pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
1257 if (pipe_config->has_hdmi_sink)
1258 pipe_config->has_infoframe = true;
1260 if (intel_hdmi->color_range_auto) {
1261 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1262 pipe_config->limited_color_range =
1263 pipe_config->has_hdmi_sink &&
1264 drm_match_cea_mode(adjusted_mode) > 1;
1266 pipe_config->limited_color_range =
1267 intel_hdmi->limited_color_range;
1270 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1271 pipe_config->pixel_multiplier = 2;
1276 if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
1277 pipe_config->has_pch_encoder = true;
1279 if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
1280 pipe_config->has_audio = true;
1283 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1284 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1285 * outputs. We also need to check that the higher clock still fits
1288 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
1289 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, false) == MODE_OK &&
1290 hdmi_12bpc_possible(pipe_config)) {
1291 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1294 /* Need to adjust the port link by 1.5x for 12bpc. */
1295 pipe_config->port_clock = clock_12bpc;
1297 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1300 pipe_config->port_clock = clock_8bpc;
1303 if (!pipe_config->bw_constrained) {
1304 DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
1305 pipe_config->pipe_bpp = desired_bpp;
1308 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1309 false) != MODE_OK) {
1310 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1314 /* Set user selected PAR to incoming mode's member */
1315 adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;
1321 intel_hdmi_unset_edid(struct drm_connector *connector)
1323 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1325 intel_hdmi->has_hdmi_sink = false;
1326 intel_hdmi->has_audio = false;
1327 intel_hdmi->rgb_quant_range_selectable = false;
1329 kfree(to_intel_connector(connector)->detect_edid);
1330 to_intel_connector(connector)->detect_edid = NULL;
1334 intel_hdmi_set_edid(struct drm_connector *connector)
1336 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1337 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1339 bool connected = false;
1341 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1343 edid = drm_get_edid(connector,
1344 intel_gmbus_get_adapter(dev_priv,
1345 intel_hdmi->ddc_bus));
1347 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1349 to_intel_connector(connector)->detect_edid = edid;
1350 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1351 intel_hdmi->rgb_quant_range_selectable =
1352 drm_rgb_quant_range_selectable(edid);
1354 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1355 if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
1356 intel_hdmi->has_audio =
1357 intel_hdmi->force_audio == HDMI_AUDIO_ON;
1359 if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
1360 intel_hdmi->has_hdmi_sink =
1361 drm_detect_hdmi_monitor(edid);
1369 static enum drm_connector_status
1370 intel_hdmi_detect(struct drm_connector *connector, bool force)
1372 enum drm_connector_status status;
1373 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1375 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1376 connector->base.id, connector->name);
1378 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1380 intel_hdmi_unset_edid(connector);
1382 if (intel_hdmi_set_edid(connector)) {
1383 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1385 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1386 status = connector_status_connected;
1388 status = connector_status_disconnected;
1390 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1396 intel_hdmi_force(struct drm_connector *connector)
1398 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1400 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1401 connector->base.id, connector->name);
1403 intel_hdmi_unset_edid(connector);
1405 if (connector->status != connector_status_connected)
1408 intel_hdmi_set_edid(connector);
1409 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1412 static int intel_hdmi_get_modes(struct drm_connector *connector)
1416 edid = to_intel_connector(connector)->detect_edid;
1420 return intel_connector_update_modes(connector, edid);
1424 intel_hdmi_detect_audio(struct drm_connector *connector)
1426 bool has_audio = false;
1429 edid = to_intel_connector(connector)->detect_edid;
1430 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL)
1431 has_audio = drm_detect_monitor_audio(edid);
1437 intel_hdmi_set_property(struct drm_connector *connector,
1438 struct drm_property *property,
1441 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1442 struct intel_digital_port *intel_dig_port =
1443 hdmi_to_dig_port(intel_hdmi);
1444 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1447 ret = drm_object_property_set_value(&connector->base, property, val);
1451 if (property == dev_priv->force_audio_property) {
1452 enum hdmi_force_audio i = val;
1455 if (i == intel_hdmi->force_audio)
1458 intel_hdmi->force_audio = i;
1460 if (i == HDMI_AUDIO_AUTO)
1461 has_audio = intel_hdmi_detect_audio(connector);
1463 has_audio = (i == HDMI_AUDIO_ON);
1465 if (i == HDMI_AUDIO_OFF_DVI)
1466 intel_hdmi->has_hdmi_sink = 0;
1468 intel_hdmi->has_audio = has_audio;
1472 if (property == dev_priv->broadcast_rgb_property) {
1473 bool old_auto = intel_hdmi->color_range_auto;
1474 bool old_range = intel_hdmi->limited_color_range;
1477 case INTEL_BROADCAST_RGB_AUTO:
1478 intel_hdmi->color_range_auto = true;
1480 case INTEL_BROADCAST_RGB_FULL:
1481 intel_hdmi->color_range_auto = false;
1482 intel_hdmi->limited_color_range = false;
1484 case INTEL_BROADCAST_RGB_LIMITED:
1485 intel_hdmi->color_range_auto = false;
1486 intel_hdmi->limited_color_range = true;
1492 if (old_auto == intel_hdmi->color_range_auto &&
1493 old_range == intel_hdmi->limited_color_range)
1499 if (property == connector->dev->mode_config.aspect_ratio_property) {
1501 case DRM_MODE_PICTURE_ASPECT_NONE:
1502 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1504 case DRM_MODE_PICTURE_ASPECT_4_3:
1505 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
1507 case DRM_MODE_PICTURE_ASPECT_16_9:
1508 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
1519 if (intel_dig_port->base.base.crtc)
1520 intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1525 static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
1527 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1528 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1529 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1531 intel_hdmi_prepare(encoder);
1533 intel_hdmi->set_infoframes(&encoder->base,
1534 intel_crtc->config->has_hdmi_sink,
1538 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1540 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1541 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1542 struct drm_device *dev = encoder->base.dev;
1543 struct drm_i915_private *dev_priv = dev->dev_private;
1544 struct intel_crtc *intel_crtc =
1545 to_intel_crtc(encoder->base.crtc);
1546 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1547 enum dpio_channel port = vlv_dport_to_channel(dport);
1548 int pipe = intel_crtc->pipe;
1551 /* Enable clock channels for this port */
1552 mutex_lock(&dev_priv->sb_lock);
1553 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1560 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1563 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1564 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1565 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1566 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1567 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1568 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1569 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1570 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1572 /* Program lane clock */
1573 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1574 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1575 mutex_unlock(&dev_priv->sb_lock);
1577 intel_hdmi->set_infoframes(&encoder->base,
1578 intel_crtc->config->has_hdmi_sink,
1581 g4x_enable_hdmi(encoder);
1583 vlv_wait_port_ready(dev_priv, dport, 0x0);
1586 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1588 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1589 struct drm_device *dev = encoder->base.dev;
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591 struct intel_crtc *intel_crtc =
1592 to_intel_crtc(encoder->base.crtc);
1593 enum dpio_channel port = vlv_dport_to_channel(dport);
1594 int pipe = intel_crtc->pipe;
1596 intel_hdmi_prepare(encoder);
1598 /* Program Tx lane resets to default */
1599 mutex_lock(&dev_priv->sb_lock);
1600 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1601 DPIO_PCS_TX_LANE2_RESET |
1602 DPIO_PCS_TX_LANE1_RESET);
1603 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1604 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1605 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1606 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1607 DPIO_PCS_CLK_SOFT_RESET);
1609 /* Fix up inter-pair skew failure */
1610 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1611 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1612 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1614 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1615 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1616 mutex_unlock(&dev_priv->sb_lock);
1619 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
1622 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1623 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1624 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1625 enum pipe pipe = crtc->pipe;
1628 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
1630 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1632 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1633 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1635 if (crtc->config->lane_count > 2) {
1636 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1638 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1640 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
1641 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1644 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1645 val |= CHV_PCS_REQ_SOFTRESET_EN;
1647 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1649 val |= DPIO_PCS_CLK_SOFT_RESET;
1650 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1652 if (crtc->config->lane_count > 2) {
1653 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
1654 val |= CHV_PCS_REQ_SOFTRESET_EN;
1656 val &= ~DPIO_PCS_CLK_SOFT_RESET;
1658 val |= DPIO_PCS_CLK_SOFT_RESET;
1659 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
1663 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1665 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1666 struct drm_device *dev = encoder->base.dev;
1667 struct drm_i915_private *dev_priv = dev->dev_private;
1668 struct intel_crtc *intel_crtc =
1669 to_intel_crtc(encoder->base.crtc);
1670 enum dpio_channel ch = vlv_dport_to_channel(dport);
1671 enum pipe pipe = intel_crtc->pipe;
1674 intel_hdmi_prepare(encoder);
1677 * Must trick the second common lane into life.
1678 * Otherwise we can't even access the PLL.
1680 if (ch == DPIO_CH0 && pipe == PIPE_B)
1681 dport->release_cl2_override =
1682 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
1684 chv_phy_powergate_lanes(encoder, true, 0x0);
1686 mutex_lock(&dev_priv->sb_lock);
1688 /* Assert data lane reset */
1689 chv_data_lane_soft_reset(encoder, true);
1691 /* program left/right clock distribution */
1692 if (pipe != PIPE_B) {
1693 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1694 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1696 val |= CHV_BUFLEFTENA1_FORCE;
1698 val |= CHV_BUFRIGHTENA1_FORCE;
1699 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1701 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1702 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1704 val |= CHV_BUFLEFTENA2_FORCE;
1706 val |= CHV_BUFRIGHTENA2_FORCE;
1707 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1710 /* program clock channel usage */
1711 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
1712 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1714 val &= ~CHV_PCS_USEDCLKCHANNEL;
1716 val |= CHV_PCS_USEDCLKCHANNEL;
1717 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
1719 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
1720 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
1722 val &= ~CHV_PCS_USEDCLKCHANNEL;
1724 val |= CHV_PCS_USEDCLKCHANNEL;
1725 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
1728 * This a a bit weird since generally CL
1729 * matches the pipe, but here we need to
1730 * pick the CL based on the port.
1732 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
1734 val &= ~CHV_CMN_USEDCLKCHANNEL;
1736 val |= CHV_CMN_USEDCLKCHANNEL;
1737 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
1739 mutex_unlock(&dev_priv->sb_lock);
1742 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder)
1744 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1745 enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
1748 mutex_lock(&dev_priv->sb_lock);
1750 /* disable left/right clock distribution */
1751 if (pipe != PIPE_B) {
1752 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1753 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1754 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1756 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1757 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1758 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1761 mutex_unlock(&dev_priv->sb_lock);
1764 * Leave the power down bit cleared for at least one
1765 * lane so that chv_powergate_phy_ch() will power
1766 * on something when the channel is otherwise unused.
1767 * When the port is off and the override is removed
1768 * the lanes power down anyway, so otherwise it doesn't
1769 * really matter what the state of power down bits is
1772 chv_phy_powergate_lanes(encoder, false, 0x0);
1775 static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1777 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1778 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1779 struct intel_crtc *intel_crtc =
1780 to_intel_crtc(encoder->base.crtc);
1781 enum dpio_channel port = vlv_dport_to_channel(dport);
1782 int pipe = intel_crtc->pipe;
1784 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1785 mutex_lock(&dev_priv->sb_lock);
1786 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1787 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1788 mutex_unlock(&dev_priv->sb_lock);
1791 static void chv_hdmi_post_disable(struct intel_encoder *encoder)
1793 struct drm_device *dev = encoder->base.dev;
1794 struct drm_i915_private *dev_priv = dev->dev_private;
1796 mutex_lock(&dev_priv->sb_lock);
1798 /* Assert data lane reset */
1799 chv_data_lane_soft_reset(encoder, true);
1801 mutex_unlock(&dev_priv->sb_lock);
1804 static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
1806 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1807 struct intel_hdmi *intel_hdmi = &dport->hdmi;
1808 struct drm_device *dev = encoder->base.dev;
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 struct intel_crtc *intel_crtc =
1811 to_intel_crtc(encoder->base.crtc);
1812 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1813 enum dpio_channel ch = vlv_dport_to_channel(dport);
1814 int pipe = intel_crtc->pipe;
1815 int data, i, stagger;
1818 mutex_lock(&dev_priv->sb_lock);
1820 /* allow hardware to manage TX FIFO reset source */
1821 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1822 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1823 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1825 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1826 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
1827 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1829 /* Program Tx latency optimal setting */
1830 for (i = 0; i < 4; i++) {
1831 /* Set the upar bit */
1832 data = (i == 1) ? 0x0 : 0x1;
1833 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
1834 data << DPIO_UPAR_SHIFT);
1837 /* Data lane stagger programming */
1838 if (intel_crtc->config->port_clock > 270000)
1840 else if (intel_crtc->config->port_clock > 135000)
1842 else if (intel_crtc->config->port_clock > 67500)
1844 else if (intel_crtc->config->port_clock > 33750)
1849 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
1850 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1851 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
1853 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
1854 val |= DPIO_TX2_STAGGER_MASK(0x1f);
1855 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
1857 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
1858 DPIO_LANESTAGGER_STRAP(stagger) |
1859 DPIO_LANESTAGGER_STRAP_OVRD |
1860 DPIO_TX1_STAGGER_MASK(0x1f) |
1861 DPIO_TX1_STAGGER_MULT(6) |
1862 DPIO_TX2_STAGGER_MULT(0));
1864 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
1865 DPIO_LANESTAGGER_STRAP(stagger) |
1866 DPIO_LANESTAGGER_STRAP_OVRD |
1867 DPIO_TX1_STAGGER_MASK(0x1f) |
1868 DPIO_TX1_STAGGER_MULT(7) |
1869 DPIO_TX2_STAGGER_MULT(5));
1871 /* Deassert data lane reset */
1872 chv_data_lane_soft_reset(encoder, false);
1874 /* Clear calc init */
1875 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1876 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1877 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1878 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1879 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1881 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1882 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
1883 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
1884 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
1885 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1887 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
1888 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1889 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1890 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
1892 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
1893 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
1894 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
1895 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
1897 /* FIXME: Program the support xxx V-dB */
1899 for (i = 0; i < 4; i++) {
1900 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
1901 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
1902 val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
1903 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
1906 for (i = 0; i < 4; i++) {
1907 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
1909 val &= ~DPIO_SWING_MARGIN000_MASK;
1910 val |= 102 << DPIO_SWING_MARGIN000_SHIFT;
1913 * Supposedly this value shouldn't matter when unique transition
1914 * scale is disabled, but in fact it does matter. Let's just
1915 * always program the same value and hope it's OK.
1917 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
1918 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
1920 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
1924 * The document said it needs to set bit 27 for ch0 and bit 26
1925 * for ch1. Might be a typo in the doc.
1926 * For now, for this unique transition scale selection, set bit
1927 * 27 for ch0 and ch1.
1929 for (i = 0; i < 4; i++) {
1930 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
1931 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
1932 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
1935 /* Start swing calculation */
1936 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
1937 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1938 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
1940 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
1941 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
1942 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1944 mutex_unlock(&dev_priv->sb_lock);
1946 intel_hdmi->set_infoframes(&encoder->base,
1947 intel_crtc->config->has_hdmi_sink,
1950 g4x_enable_hdmi(encoder);
1952 vlv_wait_port_ready(dev_priv, dport, 0x0);
1954 /* Second common lane will stay alive on its own now */
1955 if (dport->release_cl2_override) {
1956 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
1957 dport->release_cl2_override = false;
1961 static void intel_hdmi_destroy(struct drm_connector *connector)
1963 kfree(to_intel_connector(connector)->detect_edid);
1964 drm_connector_cleanup(connector);
1968 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1969 .dpms = drm_atomic_helper_connector_dpms,
1970 .detect = intel_hdmi_detect,
1971 .force = intel_hdmi_force,
1972 .fill_modes = drm_helper_probe_single_connector_modes,
1973 .set_property = intel_hdmi_set_property,
1974 .atomic_get_property = intel_connector_atomic_get_property,
1975 .destroy = intel_hdmi_destroy,
1976 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1977 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1980 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1981 .get_modes = intel_hdmi_get_modes,
1982 .mode_valid = intel_hdmi_mode_valid,
1983 .best_encoder = intel_best_encoder,
1986 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1987 .destroy = intel_encoder_destroy,
1991 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1993 intel_attach_force_audio_property(connector);
1994 intel_attach_broadcast_rgb_property(connector);
1995 intel_hdmi->color_range_auto = true;
1996 intel_attach_aspect_ratio_property(connector);
1997 intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2000 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
2003 const struct ddi_vbt_port_info *info =
2004 &dev_priv->vbt.ddi_port_info[port];
2007 if (info->alternate_ddc_pin) {
2008 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
2009 info->alternate_ddc_pin, port_name(port));
2010 return info->alternate_ddc_pin;
2015 if (IS_BROXTON(dev_priv))
2016 ddc_pin = GMBUS_PIN_1_BXT;
2018 ddc_pin = GMBUS_PIN_DPB;
2021 if (IS_BROXTON(dev_priv))
2022 ddc_pin = GMBUS_PIN_2_BXT;
2024 ddc_pin = GMBUS_PIN_DPC;
2027 if (IS_CHERRYVIEW(dev_priv))
2028 ddc_pin = GMBUS_PIN_DPD_CHV;
2030 ddc_pin = GMBUS_PIN_DPD;
2034 ddc_pin = GMBUS_PIN_DPB;
2038 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
2039 ddc_pin, port_name(port));
2044 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
2045 struct intel_connector *intel_connector)
2047 struct drm_connector *connector = &intel_connector->base;
2048 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2049 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2050 struct drm_device *dev = intel_encoder->base.dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 enum port port = intel_dig_port->port;
2054 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2057 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2058 DRM_MODE_CONNECTOR_HDMIA);
2059 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2061 connector->interlace_allowed = 1;
2062 connector->doublescan_allowed = 0;
2063 connector->stereo_allowed = 1;
2065 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2070 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2071 * interrupts to check the external panel connection.
2073 if (IS_BROXTON(dev_priv) && (INTEL_REVID(dev) < BXT_REVID_B0))
2074 intel_encoder->hpd_pin = HPD_PORT_A;
2076 intel_encoder->hpd_pin = HPD_PORT_B;
2079 intel_encoder->hpd_pin = HPD_PORT_C;
2082 intel_encoder->hpd_pin = HPD_PORT_D;
2085 intel_encoder->hpd_pin = HPD_PORT_E;
2092 if (IS_VALLEYVIEW(dev)) {
2093 intel_hdmi->write_infoframe = vlv_write_infoframe;
2094 intel_hdmi->set_infoframes = vlv_set_infoframes;
2095 intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
2096 } else if (IS_G4X(dev)) {
2097 intel_hdmi->write_infoframe = g4x_write_infoframe;
2098 intel_hdmi->set_infoframes = g4x_set_infoframes;
2099 intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
2100 } else if (HAS_DDI(dev)) {
2101 intel_hdmi->write_infoframe = hsw_write_infoframe;
2102 intel_hdmi->set_infoframes = hsw_set_infoframes;
2103 intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
2104 } else if (HAS_PCH_IBX(dev)) {
2105 intel_hdmi->write_infoframe = ibx_write_infoframe;
2106 intel_hdmi->set_infoframes = ibx_set_infoframes;
2107 intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
2109 intel_hdmi->write_infoframe = cpt_write_infoframe;
2110 intel_hdmi->set_infoframes = cpt_set_infoframes;
2111 intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
2115 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2117 intel_connector->get_hw_state = intel_connector_get_hw_state;
2118 intel_connector->unregister = intel_connector_unregister;
2120 intel_hdmi_add_properties(intel_hdmi, connector);
2122 intel_connector_attach_encoder(intel_connector, intel_encoder);
2123 drm_connector_register(connector);
2124 intel_hdmi->attached_connector = intel_connector;
2126 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2127 * 0xd. Failure to do so will result in spurious interrupts being
2128 * generated on the port when a cable is not attached.
2130 if (IS_G4X(dev) && !IS_GM45(dev)) {
2131 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2132 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2136 void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
2138 struct intel_digital_port *intel_dig_port;
2139 struct intel_encoder *intel_encoder;
2140 struct intel_connector *intel_connector;
2142 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2143 if (!intel_dig_port)
2146 intel_connector = intel_connector_alloc();
2147 if (!intel_connector) {
2148 kfree(intel_dig_port);
2152 intel_encoder = &intel_dig_port->base;
2154 drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
2155 DRM_MODE_ENCODER_TMDS);
2157 intel_encoder->compute_config = intel_hdmi_compute_config;
2158 if (HAS_PCH_SPLIT(dev)) {
2159 intel_encoder->disable = pch_disable_hdmi;
2160 intel_encoder->post_disable = pch_post_disable_hdmi;
2162 intel_encoder->disable = g4x_disable_hdmi;
2164 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2165 intel_encoder->get_config = intel_hdmi_get_config;
2166 if (IS_CHERRYVIEW(dev)) {
2167 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2168 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2169 intel_encoder->enable = vlv_enable_hdmi;
2170 intel_encoder->post_disable = chv_hdmi_post_disable;
2171 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2172 } else if (IS_VALLEYVIEW(dev)) {
2173 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2174 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2175 intel_encoder->enable = vlv_enable_hdmi;
2176 intel_encoder->post_disable = vlv_hdmi_post_disable;
2178 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2179 if (HAS_PCH_CPT(dev))
2180 intel_encoder->enable = cpt_enable_hdmi;
2181 else if (HAS_PCH_IBX(dev))
2182 intel_encoder->enable = ibx_enable_hdmi;
2184 intel_encoder->enable = g4x_enable_hdmi;
2187 intel_encoder->type = INTEL_OUTPUT_HDMI;
2188 if (IS_CHERRYVIEW(dev)) {
2190 intel_encoder->crtc_mask = 1 << 2;
2192 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2194 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2196 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2198 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2199 * to work on real hardware. And since g4x can send infoframes to
2200 * only one port anyway, nothing is lost by allowing it.
2203 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2205 intel_dig_port->port = port;
2206 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2207 intel_dig_port->dp.output_reg = 0;
2209 intel_hdmi_init_connector(intel_dig_port, intel_connector);