drivers/gpu/drm/i915/intel_drv.h

   1 /*
   2  * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
   3  * Copyright (c) 2007-2008 Intel Corporation
   4  *   Jesse Barnes <jesse.barnes@intel.com>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  23  * IN THE SOFTWARE.
  24  */
  25 #ifndef __INTEL_DRV_H__
  26 #define __INTEL_DRV_H__
  27
  28 #include <linux/async.h>
  29 #include <linux/i2c.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/sched/clock.h>
  32 #include <drm/i915_drm.h>
  33 #include "i915_drv.h"
  34 #include <drm/drm_crtc.h>
  35 #include <drm/drm_crtc_helper.h>
  36 #include <drm/drm_encoder.h>
  37 #include <drm/drm_fb_helper.h>
  38 #include <drm/drm_dp_dual_mode_helper.h>
  39 #include <drm/drm_dp_mst_helper.h>
  40 #include <drm/drm_rect.h>
  41 #include <drm/drm_atomic.h>
  42
  43 /**
  44  * _wait_for - magic (register) wait macro
  45  *
  46  * Does the right thing for modeset paths when run under kdgb or similar atomic
  47  * contexts. Note that it's important that we check the condition again after
  48  * having timed out, since the timeout could be due to preemption or similar and
  49  * we've never had a chance to check the condition before the timeout.
  50  *
  51  * TODO: When modesetting has fully transitioned to atomic, the below
  52  * drm_can_sleep() can be removed and in_atomic()/!in_atomic() asserts
  53  * added.
  54  */
  55 #define _wait_for(COND, US, W) ({ \
  56         unsigned long timeout__ = jiffies + usecs_to_jiffies(US) + 1;   \
  57         int ret__;                                                      \
  58         for (;;) {                                                      \
  59                 bool expired__ = time_after(jiffies, timeout__);        \
  60                 if (COND) {                                             \
  61                         ret__ = 0;                                      \
  62                         break;                                          \
  63                 }                                                       \
  64                 if (expired__) {                                        \
  65                         ret__ = -ETIMEDOUT;                             \
  66                         break;                                          \
  67                 }                                                       \
  68                 if ((W) && drm_can_sleep()) {                           \
  69                         usleep_range((W), (W)*2);                       \
  70                 } else {                                                \
  71                         cpu_relax();                                    \
  72                 }                                                       \
  73         }                                                               \
  74         ret__;                                                          \
  75 })
  76
  77 #define wait_for(COND, MS)              _wait_for((COND), (MS) * 1000, 1000)
  78
  79 /* If CONFIG_PREEMPT_COUNT is disabled, in_atomic() always reports false. */
  80 #if defined(CONFIG_DRM_I915_DEBUG) && defined(CONFIG_PREEMPT_COUNT)
  81 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) WARN_ON_ONCE((ATOMIC) && !in_atomic())
  82 #else
  83 # define _WAIT_FOR_ATOMIC_CHECK(ATOMIC) do { } while (0)
  84 #endif
  85
  86 #define _wait_for_atomic(COND, US, ATOMIC) \
  87 ({ \
  88         int cpu, ret, timeout = (US) * 1000; \
  89         u64 base; \
  90         _WAIT_FOR_ATOMIC_CHECK(ATOMIC); \
  91         if (!(ATOMIC)) { \
  92                 preempt_disable(); \
  93                 cpu = smp_processor_id(); \
  94         } \
  95         base = local_clock(); \
  96         for (;;) { \
  97                 u64 now = local_clock(); \
  98                 if (!(ATOMIC)) \
  99                         preempt_enable(); \
 100                 if (COND) { \
 101                         ret = 0; \
 102                         break; \
 103                 } \
 104                 if (now - base >= timeout) { \
 105                         ret = -ETIMEDOUT; \
 106                         break; \
 107                 } \
 108                 cpu_relax(); \
 109                 if (!(ATOMIC)) { \
 110                         preempt_disable(); \
 111                         if (unlikely(cpu != smp_processor_id())) { \
 112                                 timeout -= now - base; \
 113                                 cpu = smp_processor_id(); \
 114                                 base = local_clock(); \
 115                         } \
 116                 } \
 117         } \
 118         ret; \
 119 })
 120
 121 #define wait_for_us(COND, US) \
 122 ({ \
 123         int ret__; \
 124         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 125         if ((US) > 10) \
 126                 ret__ = _wait_for((COND), (US), 10); \
 127         else \
 128                 ret__ = _wait_for_atomic((COND), (US), 0); \
 129         ret__; \
 130 })
 131
 132 #define wait_for_atomic_us(COND, US) \
 133 ({ \
 134         BUILD_BUG_ON(!__builtin_constant_p(US)); \
 135         BUILD_BUG_ON((US) > 50000); \
 136         _wait_for_atomic((COND), (US), 1); \
 137 })
 138
 139 #define wait_for_atomic(COND, MS) wait_for_atomic_us((COND), (MS) * 1000)
 140
 141 #define KHz(x) (1000 * (x))
 142 #define MHz(x) KHz(1000 * (x))
 143
 144 /*
 145  * Display related stuff
 146  */
 147
 148 /* store information about an Ixxx DVO */
 149 /* The i830->i865 use multiple DVOs with multiple i2cs */
 150 /* the i915, i945 have a single sDVO i2c bus - which is different */
 151 #define MAX_OUTPUTS 6
 152 /* maximum connectors per crtcs in the mode set */
 153
 154 /* Maximum cursor sizes */
 155 #define GEN2_CURSOR_WIDTH 64
 156 #define GEN2_CURSOR_HEIGHT 64
 157 #define MAX_CURSOR_WIDTH 256
 158 #define MAX_CURSOR_HEIGHT 256
 159
 160 #define INTEL_I2C_BUS_DVO 1
 161 #define INTEL_I2C_BUS_SDVO 2
 162
 163 /* these are outputs from the chip - integrated only
 164    external chips are via DVO or SDVO output */
 165 enum intel_output_type {
 166         INTEL_OUTPUT_UNUSED = 0,
 167         INTEL_OUTPUT_ANALOG = 1,
 168         INTEL_OUTPUT_DVO = 2,
 169         INTEL_OUTPUT_SDVO = 3,
 170         INTEL_OUTPUT_LVDS = 4,
 171         INTEL_OUTPUT_TVOUT = 5,
 172         INTEL_OUTPUT_HDMI = 6,
 173         INTEL_OUTPUT_DP = 7,
 174         INTEL_OUTPUT_EDP = 8,
 175         INTEL_OUTPUT_DSI = 9,
 176         INTEL_OUTPUT_UNKNOWN = 10,
 177         INTEL_OUTPUT_DP_MST = 11,
 178 };
 179
 180 #define INTEL_DVO_CHIP_NONE 0
 181 #define INTEL_DVO_CHIP_LVDS 1
 182 #define INTEL_DVO_CHIP_TMDS 2
 183 #define INTEL_DVO_CHIP_TVOUT 4
 184
 185 #define INTEL_DSI_VIDEO_MODE    0
 186 #define INTEL_DSI_COMMAND_MODE  1
 187
 188 struct intel_framebuffer {
 189         struct drm_framebuffer base;
 190         struct drm_i915_gem_object *obj;
 191         struct intel_rotation_info rot_info;
 192
 193         /* for each plane in the normal GTT view */
 194         struct {
 195                 unsigned int x, y;
 196         } normal[2];
 197         /* for each plane in the rotated GTT view */
 198         struct {
 199                 unsigned int x, y;
 200                 unsigned int pitch; /* pixels */
 201         } rotated[2];
 202 };
 203
 204 struct intel_fbdev {
 205         struct drm_fb_helper helper;
 206         struct intel_framebuffer *fb;
 207         struct i915_vma *vma;
 208         async_cookie_t cookie;
 209         int preferred_bpp;
 210 };
 211
 212 struct intel_encoder {
 213         struct drm_encoder base;
 214
 215         enum intel_output_type type;
 216         enum port port;
 217         unsigned int cloneable;
 218         void (*hot_plug)(struct intel_encoder *);
 219         bool (*compute_config)(struct intel_encoder *,
 220                                struct intel_crtc_state *,
 221                                struct drm_connector_state *);
 222         void (*pre_pll_enable)(struct intel_encoder *,
 223                                struct intel_crtc_state *,
 224                                struct drm_connector_state *);
 225         void (*pre_enable)(struct intel_encoder *,
 226                            struct intel_crtc_state *,
 227                            struct drm_connector_state *);
 228         void (*enable)(struct intel_encoder *,
 229                        struct intel_crtc_state *,
 230                        struct drm_connector_state *);
 231         void (*disable)(struct intel_encoder *,
 232                         struct intel_crtc_state *,
 233                         struct drm_connector_state *);
 234         void (*post_disable)(struct intel_encoder *,
 235                              struct intel_crtc_state *,
 236                              struct drm_connector_state *);
 237         void (*post_pll_disable)(struct intel_encoder *,
 238                                  struct intel_crtc_state *,
 239                                  struct drm_connector_state *);
 240         /* Read out the current hw state of this connector, returning true if
 241          * the encoder is active. If the encoder is enabled it also set the pipe
 242          * it is connected to in the pipe parameter. */
 243         bool (*get_hw_state)(struct intel_encoder *, enum pipe *pipe);
 244         /* Reconstructs the equivalent mode flags for the current hardware
 245          * state. This must be called _after_ display->get_pipe_config has
 246          * pre-filled the pipe config. Note that intel_encoder->base.crtc must
 247          * be set correctly before calling this function. */
 248         void (*get_config)(struct intel_encoder *,
 249                            struct intel_crtc_state *pipe_config);
 250         /* Returns a mask of power domains that need to be referenced as part
 251          * of the hardware state readout code. */
 252         u64 (*get_power_domains)(struct intel_encoder *encoder);
 253         /*
 254          * Called during system suspend after all pending requests for the
 255          * encoder are flushed (for example for DP AUX transactions) and
 256          * device interrupts are disabled.
 257          */
 258         void (*suspend)(struct intel_encoder *);
 259         int crtc_mask;
 260         enum hpd_pin hpd_pin;
 261         enum intel_display_power_domain power_domain;
 262         /* for communication with audio component; protected by av_mutex */
 263         const struct drm_connector *audio_connector;
 264 };
 265
 266 struct intel_panel {
 267         struct drm_display_mode *fixed_mode;
 268         struct drm_display_mode *alt_fixed_mode;
 269         struct drm_display_mode *downclock_mode;
 270
 271         /* backlight */
 272         struct {
 273                 bool present;
 274                 u32 level;
 275                 u32 min;
 276                 u32 max;
 277                 bool enabled;
 278                 bool combination_mode;  /* gen 2/4 only */
 279                 bool active_low_pwm;
 280                 bool alternate_pwm_increment;   /* lpt+ */
 281
 282                 /* PWM chip */
 283                 bool util_pin_active_low;       /* bxt+ */
 284                 u8 controller;          /* bxt+ only */
 285                 struct pwm_device *pwm;
 286
 287                 struct backlight_device *device;
 288
 289                 /* Connector and platform specific backlight functions */
 290                 int (*setup)(struct intel_connector *connector, enum pipe pipe);
 291                 uint32_t (*get)(struct intel_connector *connector);
 292                 void (*set)(const struct drm_connector_state *conn_state, uint32_t level);
 293                 void (*disable)(const struct drm_connector_state *conn_state);
 294                 void (*enable)(const struct intel_crtc_state *crtc_state,
 295                                const struct drm_connector_state *conn_state);
 296                 uint32_t (*hz_to_pwm)(struct intel_connector *connector,
 297                                       uint32_t hz);
 298                 void (*power)(struct intel_connector *, bool enable);
 299         } backlight;
 300 };
 301
 302 struct intel_connector {
 303         struct drm_connector base;
 304         /*
 305          * The fixed encoder this connector is connected to.
 306          */
 307         struct intel_encoder *encoder;
 308
 309         /* ACPI device id for ACPI and driver cooperation */
 310         u32 acpi_device_id;
 311
 312         /* Reads out the current hw, returning true if the connector is enabled
 313          * and active (i.e. dpms ON state). */
 314         bool (*get_hw_state)(struct intel_connector *);
 315
 316         /* Panel info for eDP and LVDS */
 317         struct intel_panel panel;
 318
 319         /* Cached EDID for eDP and LVDS. May hold ERR_PTR for invalid EDID. */
 320         struct edid *edid;
 321         struct edid *detect_edid;
 322
 323         /* since POLL and HPD connectors may use the same HPD line keep the native
 324            state of connector->polled in case hotplug storm detection changes it */
 325         u8 polled;
 326
 327         void *port; /* store this opaque as its illegal to dereference it */
 328
 329         struct intel_dp *mst_port;
 330
 331         /* Work struct to schedule a uevent on link train failure */
 332         struct work_struct modeset_retry_work;
 333 };
 334
 335 struct intel_digital_connector_state {
 336         struct drm_connector_state base;
 337
 338         enum hdmi_force_audio force_audio;
 339         int broadcast_rgb;
 340 };
 341
 342 #define to_intel_digital_connector_state(x) container_of(x, struct intel_digital_connector_state, base)
 343
 344 struct dpll {
 345         /* given values */
 346         int n;
 347         int m1, m2;
 348         int p1, p2;
 349         /* derived values */
 350         int     dot;
 351         int     vco;
 352         int     m;
 353         int     p;
 354 };
 355
 356 struct intel_atomic_state {
 357         struct drm_atomic_state base;
 358
 359         struct {
 360                 /*
 361                  * Logical state of cdclk (used for all scaling, watermark,
 362                  * etc. calculations and checks). This is computed as if all
 363                  * enabled crtcs were active.
 364                  */
 365                 struct intel_cdclk_state logical;
 366
 367                 /*
 368                  * Actual state of cdclk, can be different from the logical
 369                  * state only when all crtc's are DPMS off.
 370                  */
 371                 struct intel_cdclk_state actual;
 372         } cdclk;
 373
 374         bool dpll_set, modeset;
 375
 376         /*
 377          * Does this transaction change the pipes that are active?  This mask
 378          * tracks which CRTC's have changed their active state at the end of
 379          * the transaction (not counting the temporary disable during modesets).
 380          * This mask should only be non-zero when intel_state->modeset is true,
 381          * but the converse is not necessarily true; simply changing a mode may
 382          * not flip the final active status of any CRTC's
 383          */
 384         unsigned int active_pipe_changes;
 385
 386         unsigned int active_crtcs;
 387         unsigned int min_pixclk[I915_MAX_PIPES];
 388
 389         struct intel_shared_dpll_state shared_dpll[I915_NUM_PLLS];
 390
 391         /*
 392          * Current watermarks can't be trusted during hardware readout, so
 393          * don't bother calculating intermediate watermarks.
 394          */
 395         bool skip_intermediate_wm;
 396
 397         /* Gen9+ only */
 398         struct skl_wm_values wm_results;
 399
 400         struct i915_sw_fence commit_ready;
 401
 402         struct llist_node freed;
 403 };
 404
 405 struct intel_plane_state {
 406         struct drm_plane_state base;
 407         struct drm_rect clip;
 408         struct i915_vma *vma;
 409
 410         struct {
 411                 u32 offset;
 412                 int x, y;
 413         } main;
 414         struct {
 415                 u32 offset;
 416                 int x, y;
 417         } aux;
 418
 419         /* plane control register */
 420         u32 ctl;
 421
 422         /*
 423          * scaler_id
 424          *    = -1 : not using a scaler
 425          *    >=  0 : using a scalers
 426          *
 427          * plane requiring a scaler:
 428          *   - During check_plane, its bit is set in
 429          *     crtc_state->scaler_state.scaler_users by calling helper function
 430          *     update_scaler_plane.
 431          *   - scaler_id indicates the scaler it got assigned.
 432          *
 433          * plane doesn't require a scaler:
 434          *   - this can happen when scaling is no more required or plane simply
 435          *     got disabled.
 436          *   - During check_plane, corresponding bit is reset in
 437          *     crtc_state->scaler_state.scaler_users by calling helper function
 438          *     update_scaler_plane.
 439          */
 440         int scaler_id;
 441
 442         struct drm_intel_sprite_colorkey ckey;
 443 };
 444
 445 struct intel_initial_plane_config {
 446         struct intel_framebuffer *fb;
 447         unsigned int tiling;
 448         int size;
 449         u32 base;
 450 };
 451
 452 #define SKL_MIN_SRC_W 8
 453 #define SKL_MAX_SRC_W 4096
 454 #define SKL_MIN_SRC_H 8
 455 #define SKL_MAX_SRC_H 4096
 456 #define SKL_MIN_DST_W 8
 457 #define SKL_MAX_DST_W 4096
 458 #define SKL_MIN_DST_H 8
 459 #define SKL_MAX_DST_H 4096
 460
 461 struct intel_scaler {
 462         int in_use;
 463         uint32_t mode;
 464 };
 465
 466 struct intel_crtc_scaler_state {
 467 #define SKL_NUM_SCALERS 2
 468         struct intel_scaler scalers[SKL_NUM_SCALERS];
 469
 470         /*
 471          * scaler_users: keeps track of users requesting scalers on this crtc.
 472          *
 473          *     If a bit is set, a user is using a scaler.
 474          *     Here user can be a plane or crtc as defined below:
 475          *       bits 0-30 - plane (bit position is index from drm_plane_index)
 476          *       bit 31    - crtc
 477          *
 478          * Instead of creating a new index to cover planes and crtc, using
 479          * existing drm_plane_index for planes which is well less than 31
 480          * planes and bit 31 for crtc. This should be fine to cover all
 481          * our platforms.
 482          *
 483          * intel_atomic_setup_scalers will setup available scalers to users
 484          * requesting scalers. It will gracefully fail if request exceeds
 485          * avilability.
 486          */
 487 #define SKL_CRTC_INDEX 31
 488         unsigned scaler_users;
 489
 490         /* scaler used by crtc for panel fitting purpose */
 491         int scaler_id;
 492 };
 493
 494 /* drm_mode->private_flags */
 495 #define I915_MODE_FLAG_INHERITED 1
 496
 497 struct intel_pipe_wm {
 498         struct intel_wm_level wm[5];
 499         uint32_t linetime;
 500         bool fbc_wm_enabled;
 501         bool pipe_enabled;
 502         bool sprites_enabled;
 503         bool sprites_scaled;
 504 };
 505
 506 struct skl_plane_wm {
 507         struct skl_wm_level wm[8];
 508         struct skl_wm_level trans_wm;
 509 };
 510
 511 struct skl_pipe_wm {
 512         struct skl_plane_wm planes[I915_MAX_PLANES];
 513         uint32_t linetime;
 514 };
 515
 516 enum vlv_wm_level {
 517         VLV_WM_LEVEL_PM2,
 518         VLV_WM_LEVEL_PM5,
 519         VLV_WM_LEVEL_DDR_DVFS,
 520         NUM_VLV_WM_LEVELS,
 521 };
 522
 523 struct vlv_wm_state {
 524         struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS];
 525         struct g4x_sr_wm sr[NUM_VLV_WM_LEVELS];
 526         uint8_t num_levels;
 527         bool cxsr;
 528 };
 529
 530 struct vlv_fifo_state {
 531         u16 plane[I915_MAX_PLANES];
 532 };
 533
 534 enum g4x_wm_level {
 535         G4X_WM_LEVEL_NORMAL,
 536         G4X_WM_LEVEL_SR,
 537         G4X_WM_LEVEL_HPLL,
 538         NUM_G4X_WM_LEVELS,
 539 };
 540
 541 struct g4x_wm_state {
 542         struct g4x_pipe_wm wm;
 543         struct g4x_sr_wm sr;
 544         struct g4x_sr_wm hpll;
 545         bool cxsr;
 546         bool hpll_en;
 547         bool fbc_en;
 548 };
 549
 550 struct intel_crtc_wm_state {
 551         union {
 552                 struct {
 553                         /*
 554                          * Intermediate watermarks; these can be
 555                          * programmed immediately since they satisfy
 556                          * both the current configuration we're
 557                          * switching away from and the new
 558                          * configuration we're switching to.
 559                          */
 560                         struct intel_pipe_wm intermediate;
 561
 562                         /*
 563                          * Optimal watermarks, programmed post-vblank
 564                          * when this state is committed.
 565                          */
 566                         struct intel_pipe_wm optimal;
 567                 } ilk;
 568
 569                 struct {
 570                         /* gen9+ only needs 1-step wm programming */
 571                         struct skl_pipe_wm optimal;
 572                         struct skl_ddb_entry ddb;
 573                 } skl;
 574
 575                 struct {
 576                         /* "raw" watermarks (not inverted) */
 577                         struct g4x_pipe_wm raw[NUM_VLV_WM_LEVELS];
 578                         /* intermediate watermarks (inverted) */
 579                         struct vlv_wm_state intermediate;
 580                         /* optimal watermarks (inverted) */
 581                         struct vlv_wm_state optimal;
 582                         /* display FIFO split */
 583                         struct vlv_fifo_state fifo_state;
 584                 } vlv;
 585
 586                 struct {
 587                         /* "raw" watermarks */
 588                         struct g4x_pipe_wm raw[NUM_G4X_WM_LEVELS];
 589                         /* intermediate watermarks */
 590                         struct g4x_wm_state intermediate;
 591                         /* optimal watermarks */
 592                         struct g4x_wm_state optimal;
 593                 } g4x;
 594         };
 595
 596         /*
 597          * Platforms with two-step watermark programming will need to
 598          * update watermark programming post-vblank to switch from the
 599          * safe intermediate watermarks to the optimal final
 600          * watermarks.
 601          */
 602         bool need_postvbl_update;
 603 };
 604
 605 struct intel_crtc_state {
 606         struct drm_crtc_state base;
 607
 608         /**
 609          * quirks - bitfield with hw state readout quirks
 610          *
 611          * For various reasons the hw state readout code might not be able to
 612          * completely faithfully read out the current state. These cases are
 613          * tracked with quirk flags so that fastboot and state checker can act
 614          * accordingly.
 615          */
 616 #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS       (1<<0) /* unreliable sync mode.flags */
 617         unsigned long quirks;
 618
 619         unsigned fb_bits; /* framebuffers to flip */
 620         bool update_pipe; /* can a fast modeset be performed? */
 621         bool disable_cxsr;
 622         bool update_wm_pre, update_wm_post; /* watermarks are updated */
 623         bool fb_changed; /* fb on any of the planes is changed */
 624         bool fifo_changed; /* FIFO split is changed */
 625
 626         /* Pipe source size (ie. panel fitter input size)
 627          * All planes will be positioned inside this space,
 628          * and get clipped at the edges. */
 629         int pipe_src_w, pipe_src_h;
 630
 631         /*
 632          * Pipe pixel rate, adjusted for
 633          * panel fitter/pipe scaler downscaling.
 634          */
 635         unsigned int pixel_rate;
 636
 637         /* Whether to set up the PCH/FDI. Note that we never allow sharing
 638          * between pch encoders and cpu encoders. */
 639         bool has_pch_encoder;
 640
 641         /* Are we sending infoframes on the attached port */
 642         bool has_infoframe;
 643
 644         /* CPU Transcoder for the pipe. Currently this can only differ from the
 645          * pipe on Haswell and later (where we have a special eDP transcoder)
 646          * and Broxton (where we have special DSI transcoders). */
 647         enum transcoder cpu_transcoder;
 648
 649         /*
 650          * Use reduced/limited/broadcast rbg range, compressing from the full
 651          * range fed into the crtcs.
 652          */
 653         bool limited_color_range;
 654
 655         /* Bitmask of encoder types (enum intel_output_type)
 656          * driven by the pipe.
 657          */
 658         unsigned int output_types;
 659
 660         /* Whether we should send NULL infoframes. Required for audio. */
 661         bool has_hdmi_sink;
 662
 663         /* Audio enabled on this pipe. Only valid if either has_hdmi_sink or
 664          * has_dp_encoder is set. */
 665         bool has_audio;
 666
 667         /*
 668          * Enable dithering, used when the selected pipe bpp doesn't match the
 669          * plane bpp.
 670          */
 671         bool dither;
 672
 673         /*
 674          * Dither gets enabled for 18bpp which causes CRC mismatch errors for
 675          * compliance video pattern tests.
 676          * Disable dither only if it is a compliance test request for
 677          * 18bpp.
 678          */
 679         bool dither_force_disable;
 680
 681         /* Controls for the clock computation, to override various stages. */
 682         bool clock_set;
 683
 684         /* SDVO TV has a bunch of special case. To make multifunction encoders
 685          * work correctly, we need to track this at runtime.*/
 686         bool sdvo_tv_clock;
 687
 688         /*
 689          * crtc bandwidth limit, don't increase pipe bpp or clock if not really
 690          * required. This is set in the 2nd loop of calling encoder's
 691          * ->compute_config if the first pick doesn't work out.
 692          */
 693         bool bw_constrained;
 694
 695         /* Settings for the intel dpll used on pretty much everything but
 696          * haswell. */
 697         struct dpll dpll;
 698
 699         /* Selected dpll when shared or NULL. */
 700         struct intel_shared_dpll *shared_dpll;
 701
 702         /* Actual register state of the dpll, for shared dpll cross-checking. */
 703         struct intel_dpll_hw_state dpll_hw_state;
 704
 705         /* DSI PLL registers */
 706         struct {
 707                 u32 ctrl, div;
 708         } dsi_pll;
 709
 710         int pipe_bpp;
 711         struct intel_link_m_n dp_m_n;
 712
 713         /* m2_n2 for eDP downclock */
 714         struct intel_link_m_n dp_m2_n2;
 715         bool has_drrs;
 716
 717         /*
 718          * Frequence the dpll for the port should run at. Differs from the
 719          * adjusted dotclock e.g. for DP or 12bpc hdmi mode. This is also
 720          * already multiplied by pixel_multiplier.
 721          */
 722         int port_clock;
 723
 724         /* Used by SDVO (and if we ever fix it, HDMI). */
 725         unsigned pixel_multiplier;
 726
 727         uint8_t lane_count;
 728
 729         /*
 730          * Used by platforms having DP/HDMI PHY with programmable lane
 731          * latency optimization.
 732          */
 733         uint8_t lane_lat_optim_mask;
 734
 735         /* Panel fitter controls for gen2-gen4 + VLV */
 736         struct {
 737                 u32 control;
 738                 u32 pgm_ratios;
 739                 u32 lvds_border_bits;
 740         } gmch_pfit;
 741
 742         /* Panel fitter placement and size for Ironlake+ */
 743         struct {
 744                 u32 pos;
 745                 u32 size;
 746                 bool enabled;
 747                 bool force_thru;
 748         } pch_pfit;
 749
 750         /* FDI configuration, only valid if has_pch_encoder is set. */
 751         int fdi_lanes;
 752         struct intel_link_m_n fdi_m_n;
 753
 754         bool ips_enabled;
 755
 756         bool enable_fbc;
 757
 758         bool double_wide;
 759
 760         int pbn;
 761
 762         struct intel_crtc_scaler_state scaler_state;
 763
 764         /* w/a for waiting 2 vblanks during crtc enable */
 765         enum pipe hsw_workaround_pipe;
 766
 767         /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
 768         bool disable_lp_wm;
 769
 770         struct intel_crtc_wm_state wm;
 771
 772         /* Gamma mode programmed on the pipe */
 773         uint32_t gamma_mode;
 774
 775         /* bitmask of visible planes (enum plane_id) */
 776         u8 active_planes;
 777
 778         /* HDMI scrambling status */
 779         bool hdmi_scrambling;
 780
 781         /* HDMI High TMDS char rate ratio */
 782         bool hdmi_high_tmds_clock_ratio;
 783
 784         /* output format is YCBCR 4:2:0 */
 785         bool ycbcr420;
 786 };
 787
 788 struct intel_crtc {
 789         struct drm_crtc base;
 790         enum pipe pipe;
 791         enum plane plane;
 792         /*
 793          * Whether the crtc and the connected output pipeline is active. Implies
 794          * that crtc->enabled is set, i.e. the current mode configuration has
 795          * some outputs connected to this crtc.
 796          */
 797         bool active;
 798         bool lowfreq_avail;
 799         u8 plane_ids_mask;
 800         unsigned long long enabled_power_domains;
 801         struct intel_overlay *overlay;
 802
 803         /* Display surface base address adjustement for pageflips. Note that on
 804          * gen4+ this only adjusts up to a tile, offsets within a tile are
 805          * handled in the hw itself (with the TILEOFF register). */
 806         u32 dspaddr_offset;
 807         int adjusted_x;
 808         int adjusted_y;
 809
 810         struct intel_crtc_state *config;
 811
 812         /* global reset count when the last flip was submitted */
 813         unsigned int reset_count;
 814
 815         /* Access to these should be protected by dev_priv->irq_lock. */
 816         bool cpu_fifo_underrun_disabled;
 817         bool pch_fifo_underrun_disabled;
 818
 819         /* per-pipe watermark state */
 820         struct {
 821                 /* watermarks currently being used  */
 822                 union {
 823                         struct intel_pipe_wm ilk;
 824                         struct vlv_wm_state vlv;
 825                         struct g4x_wm_state g4x;
 826                 } active;
 827         } wm;
 828
 829         int scanline_offset;
 830
 831         struct {
 832                 unsigned start_vbl_count;
 833                 ktime_t start_vbl_time;
 834                 int min_vbl, max_vbl;
 835                 int scanline_start;
 836         } debug;
 837
 838         /* scalers available on this crtc */
 839         int num_scalers;
 840 };
 841
 842 struct intel_plane {
 843         struct drm_plane base;
 844         u8 plane;
 845         enum plane_id id;
 846         enum pipe pipe;
 847         bool can_scale;
 848         int max_downscale;
 849         uint32_t frontbuffer_bit;
 850
 851         struct {
 852                 u32 base, cntl, size;
 853         } cursor;
 854
 855         /*
 856          * NOTE: Do not place new plane state fields here (e.g., when adding
 857          * new plane properties).  New runtime state should now be placed in
 858          * the intel_plane_state structure and accessed via plane_state.
 859          */
 860
 861         void (*update_plane)(struct intel_plane *plane,
 862                              const struct intel_crtc_state *crtc_state,
 863                              const struct intel_plane_state *plane_state);
 864         void (*disable_plane)(struct intel_plane *plane,
 865                               struct intel_crtc *crtc);
 866         bool (*get_hw_state)(struct intel_plane *plane);
 867         int (*check_plane)(struct intel_plane *plane,
 868                            struct intel_crtc_state *crtc_state,
 869                            struct intel_plane_state *state);
 870 };
 871
 872 struct intel_watermark_params {
 873         u16 fifo_size;
 874         u16 max_wm;
 875         u8 default_wm;
 876         u8 guard_size;
 877         u8 cacheline_size;
 878 };
 879
 880 struct cxsr_latency {
 881         bool is_desktop : 1;
 882         bool is_ddr3 : 1;
 883         u16 fsb_freq;
 884         u16 mem_freq;
 885         u16 display_sr;
 886         u16 display_hpll_disable;
 887         u16 cursor_sr;
 888         u16 cursor_hpll_disable;
 889 };
 890
 891 #define to_intel_atomic_state(x) container_of(x, struct intel_atomic_state, base)
 892 #define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
 893 #define to_intel_crtc_state(x) container_of(x, struct intel_crtc_state, base)
 894 #define to_intel_connector(x) container_of(x, struct intel_connector, base)
 895 #define to_intel_encoder(x) container_of(x, struct intel_encoder, base)
 896 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 897 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 898 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
 899 #define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
 900
 901 struct intel_hdmi {
 902         i915_reg_t hdmi_reg;
 903         int ddc_bus;
 904         struct {
 905                 enum drm_dp_dual_mode_type type;
 906                 int max_tmds_clock;
 907         } dp_dual_mode;
 908         bool has_hdmi_sink;
 909         bool has_audio;
 910         bool rgb_quant_range_selectable;
 911         struct intel_connector *attached_connector;
 912         void (*write_infoframe)(struct drm_encoder *encoder,
 913                                 const struct intel_crtc_state *crtc_state,
 914                                 enum hdmi_infoframe_type type,
 915                                 const void *frame, ssize_t len);
 916         void (*set_infoframes)(struct drm_encoder *encoder,
 917                                bool enable,
 918                                const struct intel_crtc_state *crtc_state,
 919                                const struct drm_connector_state *conn_state);
 920         bool (*infoframe_enabled)(struct drm_encoder *encoder,
 921                                   const struct intel_crtc_state *pipe_config);
 922 };
 923
 924 struct intel_dp_mst_encoder;
 925 #define DP_MAX_DOWNSTREAM_PORTS         0x10
 926
 927 /*
 928  * enum link_m_n_set:
 929  *      When platform provides two set of M_N registers for dp, we can
 930  *      program them and switch between them incase of DRRS.
 931  *      But When only one such register is provided, we have to program the
 932  *      required divider value on that registers itself based on the DRRS state.
 933  *
 934  * M1_N1        : Program dp_m_n on M1_N1 registers
 935  *                        dp_m2_n2 on M2_N2 registers (If supported)
 936  *
 937  * M2_N2        : Program dp_m2_n2 on M1_N1 registers
 938  *                        M2_N2 registers are not supported
 939  */
 940
 941 enum link_m_n_set {
 942         /* Sets the m1_n1 and m2_n2 */
 943         M1_N1 = 0,
 944         M2_N2
 945 };
 946
 947 struct intel_dp_compliance_data {
 948         unsigned long edid;
 949         uint8_t video_pattern;
 950         uint16_t hdisplay, vdisplay;
 951         uint8_t bpc;
 952 };
 953
 954 struct intel_dp_compliance {
 955         unsigned long test_type;
 956         struct intel_dp_compliance_data test_data;
 957         bool test_active;
 958         int test_link_rate;
 959         u8 test_lane_count;
 960 };
 961
 962 struct intel_dp {
 963         i915_reg_t output_reg;
 964         i915_reg_t aux_ch_ctl_reg;
 965         i915_reg_t aux_ch_data_reg[5];
 966         uint32_t DP;
 967         int link_rate;
 968         uint8_t lane_count;
 969         uint8_t sink_count;
 970         bool link_mst;
 971         bool has_audio;
 972         bool detect_done;
 973         bool channel_eq_status;
 974         bool reset_link_params;
 975         uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
 976         uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
 977         uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
 978         uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
 979         /* source rates */
 980         int num_source_rates;
 981         const int *source_rates;
 982         /* sink rates as reported by DP_MAX_LINK_RATE/DP_SUPPORTED_LINK_RATES */
 983         int num_sink_rates;
 984         int sink_rates[DP_MAX_SUPPORTED_RATES];
 985         bool use_rate_select;
 986         /* intersection of source and sink rates */
 987         int num_common_rates;
 988         int common_rates[DP_MAX_SUPPORTED_RATES];
 989         /* Max lane count for the current link */
 990         int max_link_lane_count;
 991         /* Max rate for the current link */
 992         int max_link_rate;
 993         /* sink or branch descriptor */
 994         struct drm_dp_desc desc;
 995         struct drm_dp_aux aux;
 996         enum intel_display_power_domain aux_power_domain;
 997         uint8_t train_set[4];
 998         int panel_power_up_delay;
 999         int panel_power_down_delay;
1000         int panel_power_cycle_delay;
1001         int backlight_on_delay;
1002         int backlight_off_delay;
1003         struct delayed_work panel_vdd_work;
1004         bool want_panel_vdd;
1005         unsigned long last_power_on;
1006         unsigned long last_backlight_off;
1007         ktime_t panel_power_off_time;
1008
1009         struct notifier_block edp_notifier;
1010
1011         /*
1012          * Pipe whose power sequencer is currently locked into
1013          * this port. Only relevant on VLV/CHV.
1014          */
1015         enum pipe pps_pipe;
1016         /*
1017          * Pipe currently driving the port. Used for preventing
1018          * the use of the PPS for any pipe currentrly driving
1019          * external DP as that will mess things up on VLV.
1020          */
1021         enum pipe active_pipe;
1022         /*
1023          * Set if the sequencer may be reset due to a power transition,
1024          * requiring a reinitialization. Only relevant on BXT.
1025          */
1026         bool pps_reset;
1027         struct edp_power_seq pps_delays;
1028
1029         bool can_mst; /* this port supports mst */
1030         bool is_mst;
1031         int active_mst_links;
1032         /* connector directly attached - won't be use for modeset in mst world */
1033         struct intel_connector *attached_connector;
1034
1035         /* mst connector list */
1036         struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
1037         struct drm_dp_mst_topology_mgr mst_mgr;
1038
1039         uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);
1040         /*
1041          * This function returns the value we have to program the AUX_CTL
1042          * register with to kick off an AUX transaction.
1043          */
1044         uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,
1045                                      bool has_aux_irq,
1046                                      int send_bytes,
1047                                      uint32_t aux_clock_divider);
1048
1049         /* This is called before a link training is starterd */
1050         void (*prepare_link_retrain)(struct intel_dp *intel_dp);
1051
1052         /* Displayport compliance testing */
1053         struct intel_dp_compliance compliance;
1054 };
1055
1056 struct intel_lspcon {
1057         bool active;
1058         enum drm_lspcon_mode mode;
1059 };
1060
1061 struct intel_digital_port {
1062         struct intel_encoder base;
1063         enum port port;
1064         u32 saved_port_bits;
1065         struct intel_dp dp;
1066         struct intel_hdmi hdmi;
1067         struct intel_lspcon lspcon;
1068         enum irqreturn (*hpd_pulse)(struct intel_digital_port *, bool);
1069         bool release_cl2_override;
1070         uint8_t max_lanes;
1071         enum intel_display_power_domain ddi_io_power_domain;
1072 };
1073
1074 struct intel_dp_mst_encoder {
1075         struct intel_encoder base;
1076         enum pipe pipe;
1077         struct intel_digital_port *primary;
1078         struct intel_connector *connector;
1079 };
1080
1081 static inline enum dpio_channel
1082 vlv_dport_to_channel(struct intel_digital_port *dport)
1083 {
1084         switch (dport->port) {
1085         case PORT_B:
1086         case PORT_D:
1087                 return DPIO_CH0;
1088         case PORT_C:
1089                 return DPIO_CH1;
1090         default:
1091                 BUG();
1092         }
1093 }
1094
1095 static inline enum dpio_phy
1096 vlv_dport_to_phy(struct intel_digital_port *dport)
1097 {
1098         switch (dport->port) {
1099         case PORT_B:
1100         case PORT_C:
1101                 return DPIO_PHY0;
1102         case PORT_D:
1103                 return DPIO_PHY1;
1104         default:
1105                 BUG();
1106         }
1107 }
1108
1109 static inline enum dpio_channel
1110 vlv_pipe_to_channel(enum pipe pipe)
1111 {
1112         switch (pipe) {
1113         case PIPE_A:
1114         case PIPE_C:
1115                 return DPIO_CH0;
1116         case PIPE_B:
1117                 return DPIO_CH1;
1118         default:
1119                 BUG();
1120         }
1121 }
1122
1123 static inline struct intel_crtc *
1124 intel_get_crtc_for_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1125 {
1126         return dev_priv->pipe_to_crtc_mapping[pipe];
1127 }
1128
1129 static inline struct intel_crtc *
1130 intel_get_crtc_for_plane(struct drm_i915_private *dev_priv, enum plane plane)
1131 {
1132         return dev_priv->plane_to_crtc_mapping[plane];
1133 }
1134
1135 struct intel_load_detect_pipe {
1136         struct drm_atomic_state *restore_state;
1137 };
1138
1139 static inline struct intel_encoder *
1140 intel_attached_encoder(struct drm_connector *connector)
1141 {
1142         return to_intel_connector(connector)->encoder;
1143 }
1144
1145 static inline struct intel_digital_port *
1146 enc_to_dig_port(struct drm_encoder *encoder)
1147 {
1148         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1149
1150         switch (intel_encoder->type) {
1151         case INTEL_OUTPUT_UNKNOWN:
1152                 WARN_ON(!HAS_DDI(to_i915(encoder->dev)));
1153         case INTEL_OUTPUT_DP:
1154         case INTEL_OUTPUT_EDP:
1155         case INTEL_OUTPUT_HDMI:
1156                 return container_of(encoder, struct intel_digital_port,
1157                                     base.base);
1158         default:
1159                 return NULL;
1160         }
1161 }
1162
1163 static inline struct intel_dp_mst_encoder *
1164 enc_to_mst(struct drm_encoder *encoder)
1165 {
1166         return container_of(encoder, struct intel_dp_mst_encoder, base.base);
1167 }
1168
1169 static inline struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
1170 {
1171         return &enc_to_dig_port(encoder)->dp;
1172 }
1173
1174 static inline struct intel_digital_port *
1175 dp_to_dig_port(struct intel_dp *intel_dp)
1176 {
1177         return container_of(intel_dp, struct intel_digital_port, dp);
1178 }
1179
1180 static inline struct intel_lspcon *
1181 dp_to_lspcon(struct intel_dp *intel_dp)
1182 {
1183         return &dp_to_dig_port(intel_dp)->lspcon;
1184 }
1185
1186 static inline struct intel_digital_port *
1187 hdmi_to_dig_port(struct intel_hdmi *intel_hdmi)
1188 {
1189         return container_of(intel_hdmi, struct intel_digital_port, hdmi);
1190 }
1191
1192 /* intel_fifo_underrun.c */
1193 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1194                                            enum pipe pipe, bool enable);
1195 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,
1196                                            enum pipe pch_transcoder,
1197                                            bool enable);
1198 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1199                                          enum pipe pipe);
1200 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
1201                                          enum pipe pch_transcoder);
1202 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv);
1203 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv);
1204
1205 /* i915_irq.c */
1206 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1207 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1208 void gen6_reset_pm_iir(struct drm_i915_private *dev_priv, u32 mask);
1209 void gen6_mask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1210 void gen6_unmask_pm_irq(struct drm_i915_private *dev_priv, u32 mask);
1211 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1212 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
1213 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv);
1214 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv);
1215 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv);
1216
1217 static inline u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915,
1218                                             u32 mask)
1219 {
1220         return mask & ~i915->rps.pm_intrmsk_mbz;
1221 }
1222
1223 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
1224 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
1225 static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
1226 {
1227         /*
1228          * We only use drm_irq_uninstall() at unload and VT switch, so
1229          * this is the only thing we need to check.
1230          */
1231         return dev_priv->pm.irqs_enabled;
1232 }
1233
1234 int intel_get_crtc_scanline(struct intel_crtc *crtc);
1235 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
1236                                      u8 pipe_mask);
1237 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
1238                                      u8 pipe_mask);
1239 void gen9_reset_guc_interrupts(struct drm_i915_private *dev_priv);
1240 void gen9_enable_guc_interrupts(struct drm_i915_private *dev_priv);
1241 void gen9_disable_guc_interrupts(struct drm_i915_private *dev_priv);
1242
1243 /* intel_crt.c */
1244 void intel_crt_init(struct drm_i915_private *dev_priv);
1245 void intel_crt_reset(struct drm_encoder *encoder);
1246
1247 /* intel_ddi.c */
1248 void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
1249                                 struct intel_crtc_state *old_crtc_state,
1250                                 struct drm_connector_state *old_conn_state);
1251 void hsw_fdi_link_train(struct intel_crtc *crtc,
1252                         const struct intel_crtc_state *crtc_state);
1253 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port);
1254 enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder);
1255 bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
1256 void intel_ddi_enable_transcoder_func(const struct intel_crtc_state *crtc_state);
1257 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
1258 void intel_ddi_enable_pipe_clock(const struct intel_crtc_state *crtc_state);
1259 void intel_ddi_disable_pipe_clock(const  struct intel_crtc_state *crtc_state);
1260 struct intel_encoder *
1261 intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state);
1262 void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state);
1263 void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp);
1264 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
1265 bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
1266                                  struct intel_crtc *intel_crtc);
1267 void intel_ddi_get_config(struct intel_encoder *encoder,
1268                           struct intel_crtc_state *pipe_config);
1269
1270 void intel_ddi_clock_get(struct intel_encoder *encoder,
1271                          struct intel_crtc_state *pipe_config);
1272 void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
1273                                     bool state);
1274 uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
1275 u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
1276
1277 unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
1278                                    int plane, unsigned int height);
1279
1280 /* intel_audio.c */
1281 void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
1282 void intel_audio_codec_enable(struct intel_encoder *encoder,
1283                               const struct intel_crtc_state *crtc_state,
1284                               const struct drm_connector_state *conn_state);
1285 void intel_audio_codec_disable(struct intel_encoder *encoder);
1286 void i915_audio_component_init(struct drm_i915_private *dev_priv);
1287 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv);
1288 void intel_audio_init(struct drm_i915_private *dev_priv);
1289 void intel_audio_deinit(struct drm_i915_private *dev_priv);
1290
1291 /* intel_cdclk.c */
1292 void skl_init_cdclk(struct drm_i915_private *dev_priv);
1293 void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
1294 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
1295 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
1296 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
1297 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
1298 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
1299 void intel_update_max_cdclk(struct drm_i915_private *dev_priv);
1300 void intel_update_cdclk(struct drm_i915_private *dev_priv);
1301 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1302 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1303                                const struct intel_cdclk_state *b);
1304 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1305                      const struct intel_cdclk_state *cdclk_state);
1306
1307 /* intel_display.c */
1308 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1309 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
1310 enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc);
1311 void intel_update_rawclk(struct drm_i915_private *dev_priv);
1312 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv);
1313 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
1314                       const char *name, u32 reg, int ref_freq);
1315 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
1316                            const char *name, u32 reg);
1317 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv);
1318 void lpt_disable_iclkip(struct drm_i915_private *dev_priv);
1319 void intel_init_display_hooks(struct drm_i915_private *dev_priv);
1320 unsigned int intel_fb_xy_to_linear(int x, int y,
1321                                    const struct intel_plane_state *state,
1322                                    int plane);
1323 void intel_add_fb_offsets(int *x, int *y,
1324                           const struct intel_plane_state *state, int plane);
1325 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
1326 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
1327 void intel_mark_busy(struct drm_i915_private *dev_priv);
1328 void intel_mark_idle(struct drm_i915_private *dev_priv);
1329 int intel_display_suspend(struct drm_device *dev);
1330 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv);
1331 void intel_encoder_destroy(struct drm_encoder *encoder);
1332 int intel_connector_init(struct intel_connector *);
1333 struct intel_connector *intel_connector_alloc(void);
1334 bool intel_connector_get_hw_state(struct intel_connector *connector);
1335 void intel_connector_attach_encoder(struct intel_connector *connector,
1336                                     struct intel_encoder *encoder);
1337 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
1338                                              struct drm_crtc *crtc);
1339 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector);
1340 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1341                                 struct drm_file *file_priv);
1342 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1343                                              enum pipe pipe);
1344 static inline bool
1345 intel_crtc_has_type(const struct intel_crtc_state *crtc_state,
1346                     enum intel_output_type type)
1347 {
1348         return crtc_state->output_types & (1 << type);
1349 }
1350 static inline bool
1351 intel_crtc_has_dp_encoder(const struct intel_crtc_state *crtc_state)
1352 {
1353         return crtc_state->output_types &
1354                 ((1 << INTEL_OUTPUT_DP) |
1355                  (1 << INTEL_OUTPUT_DP_MST) |
1356                  (1 << INTEL_OUTPUT_EDP));
1357 }
1358 static inline void
1359 intel_wait_for_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
1360 {
1361         drm_wait_one_vblank(&dev_priv->drm, pipe);
1362 }
1363 static inline void
1364 intel_wait_for_vblank_if_active(struct drm_i915_private *dev_priv, int pipe)
1365 {
1366         const struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1367
1368         if (crtc->active)
1369                 intel_wait_for_vblank(dev_priv, pipe);
1370 }
1371
1372 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc);
1373
1374 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
1375 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1376                          struct intel_digital_port *dport,
1377                          unsigned int expected_mask);
1378 int intel_get_load_detect_pipe(struct drm_connector *connector,
1379                                struct drm_display_mode *mode,
1380                                struct intel_load_detect_pipe *old,
1381                                struct drm_modeset_acquire_ctx *ctx);
1382 void intel_release_load_detect_pipe(struct drm_connector *connector,
1383                                     struct intel_load_detect_pipe *old,
1384                                     struct drm_modeset_acquire_ctx *ctx);
1385 struct i915_vma *
1386 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation);
1387 void intel_unpin_fb_vma(struct i915_vma *vma);
1388 struct drm_framebuffer *
1389 intel_framebuffer_create(struct drm_i915_gem_object *obj,
1390                          struct drm_mode_fb_cmd2 *mode_cmd);
1391 int intel_prepare_plane_fb(struct drm_plane *plane,
1392                            struct drm_plane_state *new_state);
1393 void intel_cleanup_plane_fb(struct drm_plane *plane,
1394                             struct drm_plane_state *old_state);
1395 int intel_plane_atomic_get_property(struct drm_plane *plane,
1396                                     const struct drm_plane_state *state,
1397                                     struct drm_property *property,
1398                                     uint64_t *val);
1399 int intel_plane_atomic_set_property(struct drm_plane *plane,
1400                                     struct drm_plane_state *state,
1401                                     struct drm_property *property,
1402                                     uint64_t val);
1403 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
1404                                     struct drm_plane_state *plane_state);
1405
1406 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1407                                     enum pipe pipe);
1408
1409 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
1410                      const struct dpll *dpll);
1411 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe);
1412 int lpt_get_iclkip(struct drm_i915_private *dev_priv);
1413
1414 /* modesetting asserts */
1415 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1416                            enum pipe pipe);
1417 void assert_pll(struct drm_i915_private *dev_priv,
1418                 enum pipe pipe, bool state);
1419 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1420 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1421 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state);
1422 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1423 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1424 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1425                        enum pipe pipe, bool state);
1426 #define assert_fdi_rx_pll_enabled(d, p) assert_fdi_rx_pll(d, p, true)
1427 #define assert_fdi_rx_pll_disabled(d, p) assert_fdi_rx_pll(d, p, false)
1428 void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
1429 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
1430 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
1431 u32 intel_compute_tile_offset(int *x, int *y,
1432                               const struct intel_plane_state *state, int plane);
1433 void intel_prepare_reset(struct drm_i915_private *dev_priv);
1434 void intel_finish_reset(struct drm_i915_private *dev_priv);
1435 void hsw_enable_pc8(struct drm_i915_private *dev_priv);
1436 void hsw_disable_pc8(struct drm_i915_private *dev_priv);
1437 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
1438 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
1439 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
1440 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
1441 unsigned int skl_cdclk_get_vco(unsigned int freq);
1442 void skl_enable_dc6(struct drm_i915_private *dev_priv);
1443 void skl_disable_dc6(struct drm_i915_private *dev_priv);
1444 void intel_dp_get_m_n(struct intel_crtc *crtc,
1445                       struct intel_crtc_state *pipe_config);
1446 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n);
1447 int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
1448 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1449                         struct dpll *best_clock);
1450 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
1451
1452 bool intel_crtc_active(struct intel_crtc *crtc);
1453 void hsw_enable_ips(struct intel_crtc *crtc);
1454 void hsw_disable_ips(struct intel_crtc *crtc);
1455 enum intel_display_power_domain intel_port_to_power_domain(enum port port);
1456 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
1457                                  struct intel_crtc_state *pipe_config);
1458
1459 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
1460 int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
1461
1462 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
1463 {
1464         return i915_ggtt_offset(state->vma);
1465 }
1466
1467 u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
1468                   const struct intel_plane_state *plane_state);
1469 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
1470                      unsigned int rotation);
1471 int skl_check_plane_surface(struct intel_plane_state *plane_state);
1472 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
1473
1474 /* intel_csr.c */
1475 void intel_csr_ucode_init(struct drm_i915_private *);
1476 void intel_csr_load_program(struct drm_i915_private *);
1477 void intel_csr_ucode_fini(struct drm_i915_private *);
1478 void intel_csr_ucode_suspend(struct drm_i915_private *);
1479 void intel_csr_ucode_resume(struct drm_i915_private *);
1480
1481 /* intel_dp.c */
1482 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
1483                    enum port port);
1484 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
1485                              struct intel_connector *intel_connector);
1486 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1487                               int link_rate, uint8_t lane_count,
1488                               bool link_mst);
1489 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
1490                                             int link_rate, uint8_t lane_count);
1491 void intel_dp_start_link_train(struct intel_dp *intel_dp);
1492 void intel_dp_stop_link_train(struct intel_dp *intel_dp);
1493 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
1494 void intel_dp_encoder_reset(struct drm_encoder *encoder);
1495 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
1496 void intel_dp_encoder_destroy(struct drm_encoder *encoder);
1497 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc);
1498 bool intel_dp_compute_config(struct intel_encoder *encoder,
1499                              struct intel_crtc_state *pipe_config,
1500                              struct drm_connector_state *conn_state);
1501 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port);
1502 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
1503                                   bool long_hpd);
1504 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
1505                             const struct drm_connector_state *conn_state);
1506 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
1507 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
1508 void intel_edp_panel_on(struct intel_dp *intel_dp);
1509 void intel_edp_panel_off(struct intel_dp *intel_dp);
1510 void intel_dp_mst_suspend(struct drm_device *dev);
1511 void intel_dp_mst_resume(struct drm_device *dev);
1512 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
1513 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
1514 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
1515 void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
1516 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
1517 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
1518 void intel_plane_destroy(struct drm_plane *plane);
1519 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
1520                            struct intel_crtc_state *crtc_state);
1521 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
1522                            struct intel_crtc_state *crtc_state);
1523 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
1524                                unsigned int frontbuffer_bits);
1525 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
1526                           unsigned int frontbuffer_bits);
1527
1528 void
1529 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
1530                                        uint8_t dp_train_pat);
1531 void
1532 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
1533 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
1534 uint8_t
1535 intel_dp_voltage_max(struct intel_dp *intel_dp);
1536 uint8_t
1537 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing);
1538 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1539                            uint8_t *link_bw, uint8_t *rate_select);
1540 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
1541 bool
1542 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]);
1543
1544 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
1545 {
1546         return ~((1 << lane_count) - 1) & 0xf;
1547 }
1548
1549 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
1550 int intel_dp_link_required(int pixel_clock, int bpp);
1551 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
1552 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
1553                                   struct intel_digital_port *port);
1554
1555 /* intel_dp_aux_backlight.c */
1556 int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector);
1557
1558 /* intel_dp_mst.c */
1559 int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
1560 void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
1561 /* intel_dsi.c */
1562 void intel_dsi_init(struct drm_i915_private *dev_priv);
1563
1564 /* intel_dsi_dcs_backlight.c */
1565 int intel_dsi_dcs_init_backlight_funcs(struct intel_connector *intel_connector);
1566
1567 /* intel_dvo.c */
1568 void intel_dvo_init(struct drm_i915_private *dev_priv);
1569 /* intel_hotplug.c */
1570 void intel_hpd_poll_init(struct drm_i915_private *dev_priv);
1571
1572
1573 /* legacy fbdev emulation in intel_fbdev.c */
1574 #ifdef CONFIG_DRM_FBDEV_EMULATION
1575 extern int intel_fbdev_init(struct drm_device *dev);
1576 extern void intel_fbdev_initial_config_async(struct drm_device *dev);
1577 extern void intel_fbdev_unregister(struct drm_i915_private *dev_priv);
1578 extern void intel_fbdev_fini(struct drm_i915_private *dev_priv);
1579 extern void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous);
1580 extern void intel_fbdev_output_poll_changed(struct drm_device *dev);
1581 extern void intel_fbdev_restore_mode(struct drm_device *dev);
1582 #else
1583 static inline int intel_fbdev_init(struct drm_device *dev)
1584 {
1585         return 0;
1586 }
1587
1588 static inline void intel_fbdev_initial_config_async(struct drm_device *dev)
1589 {
1590 }
1591
1592 static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv)
1593 {
1594 }
1595
1596 static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv)
1597 {
1598 }
1599
1600 static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous)
1601 {
1602 }
1603
1604 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
1605 {
1606 }
1607
1608 static inline void intel_fbdev_restore_mode(struct drm_device *dev)
1609 {
1610 }
1611 #endif
1612
1613 /* intel_fbc.c */
1614 void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
1615                            struct drm_atomic_state *state);
1616 bool intel_fbc_is_active(struct drm_i915_private *dev_priv);
1617 void intel_fbc_pre_update(struct intel_crtc *crtc,
1618                           struct intel_crtc_state *crtc_state,
1619                           struct intel_plane_state *plane_state);
1620 void intel_fbc_post_update(struct intel_crtc *crtc);
1621 void intel_fbc_init(struct drm_i915_private *dev_priv);
1622 void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv);
1623 void intel_fbc_enable(struct intel_crtc *crtc,
1624                       struct intel_crtc_state *crtc_state,
1625                       struct intel_plane_state *plane_state);
1626 void intel_fbc_disable(struct intel_crtc *crtc);
1627 void intel_fbc_global_disable(struct drm_i915_private *dev_priv);
1628 void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
1629                           unsigned int frontbuffer_bits,
1630                           enum fb_op_origin origin);
1631 void intel_fbc_flush(struct drm_i915_private *dev_priv,
1632                      unsigned int frontbuffer_bits, enum fb_op_origin origin);
1633 void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv);
1634 void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv);
1635
1636 /* intel_hdmi.c */
1637 void intel_hdmi_init(struct drm_i915_private *dev_priv, i915_reg_t hdmi_reg,
1638                      enum port port);
1639 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1640                                struct intel_connector *intel_connector);
1641 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder);
1642 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1643                                struct intel_crtc_state *pipe_config,
1644                                struct drm_connector_state *conn_state);
1645 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *intel_encoder,
1646                                        struct drm_connector *connector,
1647                                        bool high_tmds_clock_ratio,
1648                                        bool scrambling);
1649 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable);
1650
1651
1652 /* intel_lvds.c */
1653 void intel_lvds_init(struct drm_i915_private *dev_priv);
1654 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev);
1655 bool intel_is_dual_link_lvds(struct drm_device *dev);
1656
1657
1658 /* intel_modes.c */
1659 int intel_connector_update_modes(struct drm_connector *connector,
1660                                  struct edid *edid);
1661 int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
1662 void intel_attach_force_audio_property(struct drm_connector *connector);
1663 void intel_attach_broadcast_rgb_property(struct drm_connector *connector);
1664 void intel_attach_aspect_ratio_property(struct drm_connector *connector);
1665
1666
1667 /* intel_overlay.c */
1668 void intel_setup_overlay(struct drm_i915_private *dev_priv);
1669 void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
1670 int intel_overlay_switch_off(struct intel_overlay *overlay);
1671 int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
1672                                   struct drm_file *file_priv);
1673 int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
1674                               struct drm_file *file_priv);
1675 void intel_overlay_reset(struct drm_i915_private *dev_priv);
1676
1677
1678 /* intel_panel.c */
1679 int intel_panel_init(struct intel_panel *panel,
1680                      struct drm_display_mode *fixed_mode,
1681                      struct drm_display_mode *alt_fixed_mode,
1682                      struct drm_display_mode *downclock_mode);
1683 void intel_panel_fini(struct intel_panel *panel);
1684 void intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1685                             struct drm_display_mode *adjusted_mode);
1686 void intel_pch_panel_fitting(struct intel_crtc *crtc,
1687                              struct intel_crtc_state *pipe_config,
1688                              int fitting_mode);
1689 void intel_gmch_panel_fitting(struct intel_crtc *crtc,
1690                               struct intel_crtc_state *pipe_config,
1691                               int fitting_mode);
1692 void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
1693                                     u32 level, u32 max);
1694 int intel_panel_setup_backlight(struct drm_connector *connector,
1695                                 enum pipe pipe);
1696 void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1697                                   const struct drm_connector_state *conn_state);
1698 void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state);
1699 void intel_panel_destroy_backlight(struct drm_connector *connector);
1700 enum drm_connector_status intel_panel_detect(struct drm_i915_private *dev_priv);
1701 extern struct drm_display_mode *intel_find_panel_downclock(
1702                                 struct drm_i915_private *dev_priv,
1703                                 struct drm_display_mode *fixed_mode,
1704                                 struct drm_connector *connector);
1705
1706 #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
1707 int intel_backlight_device_register(struct intel_connector *connector);
1708 void intel_backlight_device_unregister(struct intel_connector *connector);
1709 #else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1710 static inline int intel_backlight_device_register(struct intel_connector *connector)
1711 {
1712         return 0;
1713 }
1714 static inline void intel_backlight_device_unregister(struct intel_connector *connector)
1715 {
1716 }
1717 #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1718
1719
1720 /* intel_psr.c */
1721 void intel_psr_enable(struct intel_dp *intel_dp);
1722 void intel_psr_disable(struct intel_dp *intel_dp);
1723 void intel_psr_invalidate(struct drm_i915_private *dev_priv,
1724                           unsigned frontbuffer_bits);
1725 void intel_psr_flush(struct drm_i915_private *dev_priv,
1726                      unsigned frontbuffer_bits,
1727                      enum fb_op_origin origin);
1728 void intel_psr_init(struct drm_i915_private *dev_priv);
1729 void intel_psr_single_frame_update(struct drm_i915_private *dev_priv,
1730                                    unsigned frontbuffer_bits);
1731
1732 /* intel_runtime_pm.c */
1733 int intel_power_domains_init(struct drm_i915_private *);
1734 void intel_power_domains_fini(struct drm_i915_private *);
1735 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
1736 void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
1737 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
1738 void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
1739 void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
1740 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
1741 const char *
1742 intel_display_power_domain_str(enum intel_display_power_domain domain);
1743
1744 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1745                                     enum intel_display_power_domain domain);
1746 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
1747                                       enum intel_display_power_domain domain);
1748 void intel_display_power_get(struct drm_i915_private *dev_priv,
1749                              enum intel_display_power_domain domain);
1750 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1751                                         enum intel_display_power_domain domain);
1752 void intel_display_power_put(struct drm_i915_private *dev_priv,
1753                              enum intel_display_power_domain domain);
1754
1755 static inline void
1756 assert_rpm_device_not_suspended(struct drm_i915_private *dev_priv)
1757 {
1758         WARN_ONCE(dev_priv->pm.suspended,
1759                   "Device suspended during HW access\n");
1760 }
1761
1762 static inline void
1763 assert_rpm_wakelock_held(struct drm_i915_private *dev_priv)
1764 {
1765         assert_rpm_device_not_suspended(dev_priv);
1766         WARN_ONCE(!atomic_read(&dev_priv->pm.wakeref_count),
1767                   "RPM wakelock ref not held during HW access");
1768 }
1769
1770 /**
1771  * disable_rpm_wakeref_asserts - disable the RPM assert checks
1772  * @dev_priv: i915 device instance
1773  *
1774  * This function disable asserts that check if we hold an RPM wakelock
1775  * reference, while keeping the device-not-suspended checks still enabled.
1776  * It's meant to be used only in special circumstances where our rule about
1777  * the wakelock refcount wrt. the device power state doesn't hold. According
1778  * to this rule at any point where we access the HW or want to keep the HW in
1779  * an active state we must hold an RPM wakelock reference acquired via one of
1780  * the intel_runtime_pm_get() helpers. Currently there are a few special spots
1781  * where this rule doesn't hold: the IRQ and suspend/resume handlers, the
1782  * forcewake release timer, and the GPU RPS and hangcheck works. All other
1783  * users should avoid using this function.
1784  *
1785  * Any calls to this function must have a symmetric call to
1786  * enable_rpm_wakeref_asserts().
1787  */
1788 static inline void
1789 disable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1790 {
1791         atomic_inc(&dev_priv->pm.wakeref_count);
1792 }
1793
1794 /**
1795  * enable_rpm_wakeref_asserts - re-enable the RPM assert checks
1796  * @dev_priv: i915 device instance
1797  *
1798  * This function re-enables the RPM assert checks after disabling them with
1799  * disable_rpm_wakeref_asserts. It's meant to be used only in special
1800  * circumstances otherwise its use should be avoided.
1801  *
1802  * Any calls to this function must have a symmetric call to
1803  * disable_rpm_wakeref_asserts().
1804  */
1805 static inline void
1806 enable_rpm_wakeref_asserts(struct drm_i915_private *dev_priv)
1807 {
1808         atomic_dec(&dev_priv->pm.wakeref_count);
1809 }
1810
1811 void intel_runtime_pm_get(struct drm_i915_private *dev_priv);
1812 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv);
1813 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv);
1814 void intel_runtime_pm_put(struct drm_i915_private *dev_priv);
1815
1816 void intel_display_set_init_power(struct drm_i915_private *dev, bool enable);
1817
1818 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1819                              bool override, unsigned int mask);
1820 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1821                           enum dpio_channel ch, bool override);
1822
1823
1824 /* intel_pm.c */
1825 void intel_init_clock_gating(struct drm_i915_private *dev_priv);
1826 void intel_suspend_hw(struct drm_i915_private *dev_priv);
1827 int ilk_wm_max_level(const struct drm_i915_private *dev_priv);
1828 void intel_update_watermarks(struct intel_crtc *crtc);
1829 void intel_init_pm(struct drm_i915_private *dev_priv);
1830 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv);
1831 void intel_pm_setup(struct drm_i915_private *dev_priv);
1832 void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
1833 void intel_gpu_ips_teardown(void);
1834 void intel_init_gt_powersave(struct drm_i915_private *dev_priv);
1835 void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv);
1836 void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv);
1837 void intel_enable_gt_powersave(struct drm_i915_private *dev_priv);
1838 void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv);
1839 void intel_disable_gt_powersave(struct drm_i915_private *dev_priv);
1840 void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv);
1841 bool i915_rc6_ctx_wa_check(struct drm_i915_private *i915);
1842 void i915_rc6_ctx_wa_suspend(struct drm_i915_private *i915);
1843 void i915_rc6_ctx_wa_resume(struct drm_i915_private *i915);
1844 void gen6_rps_busy(struct drm_i915_private *dev_priv);
1845 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv);
1846 void gen6_rps_idle(struct drm_i915_private *dev_priv);
1847 void gen6_rps_boost(struct drm_i915_gem_request *rq,
1848                     struct intel_rps_client *rps);
1849 void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req);
1850 void g4x_wm_get_hw_state(struct drm_device *dev);
1851 void vlv_wm_get_hw_state(struct drm_device *dev);
1852 void ilk_wm_get_hw_state(struct drm_device *dev);
1853 void skl_wm_get_hw_state(struct drm_device *dev);
1854 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
1855                           struct skl_ddb_allocation *ddb /* out */);
1856 void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
1857                               struct skl_pipe_wm *out);
1858 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
1859 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
1860 bool intel_can_enable_sagv(struct drm_atomic_state *state);
1861 int intel_enable_sagv(struct drm_i915_private *dev_priv);
1862 int intel_disable_sagv(struct drm_i915_private *dev_priv);
1863 bool skl_wm_level_equals(const struct skl_wm_level *l1,
1864                          const struct skl_wm_level *l2);
1865 bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
1866                                  const struct skl_ddb_entry *ddb,
1867                                  int ignore);
1868 bool ilk_disable_lp_wm(struct drm_device *dev);
1869 int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6);
1870 int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
1871                                   struct intel_crtc_state *cstate);
1872 static inline int intel_enable_rc6(void)
1873 {
1874         return i915.enable_rc6;
1875 }
1876
1877 /* intel_sdvo.c */
1878 bool intel_sdvo_init(struct drm_i915_private *dev_priv,
1879                      i915_reg_t reg, enum port port);
1880
1881
1882 /* intel_sprite.c */
1883 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
1884                              int usecs);
1885 struct intel_plane *intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1886                                               enum pipe pipe, int plane);
1887 int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1888                               struct drm_file *file_priv);
1889 void intel_pipe_update_start(struct intel_crtc *crtc);
1890 void intel_pipe_update_end(struct intel_crtc *crtc);
1891 bool skl_plane_get_hw_state(struct intel_plane *plane);
1892
1893 /* intel_tv.c */
1894 void intel_tv_init(struct drm_i915_private *dev_priv);
1895
1896 /* intel_atomic.c */
1897 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
1898                                                 const struct drm_connector_state *state,
1899                                                 struct drm_property *property,
1900                                                 uint64_t *val);
1901 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
1902                                                 struct drm_connector_state *state,
1903                                                 struct drm_property *property,
1904                                                 uint64_t val);
1905 int intel_digital_connector_atomic_check(struct drm_connector *conn,
1906                                          struct drm_connector_state *new_state);
1907 struct drm_connector_state *
1908 intel_digital_connector_duplicate_state(struct drm_connector *connector);
1909
1910 struct drm_crtc_state *intel_crtc_duplicate_state(struct drm_crtc *crtc);
1911 void intel_crtc_destroy_state(struct drm_crtc *crtc,
1912                                struct drm_crtc_state *state);
1913 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
1914 void intel_atomic_state_clear(struct drm_atomic_state *);
1915
1916 static inline struct intel_crtc_state *
1917 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
1918                             struct intel_crtc *crtc)
1919 {
1920         struct drm_crtc_state *crtc_state;
1921         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
1922         if (IS_ERR(crtc_state))
1923                 return ERR_CAST(crtc_state);
1924
1925         return to_intel_crtc_state(crtc_state);
1926 }
1927
1928 static inline struct intel_crtc_state *
1929 intel_atomic_get_existing_crtc_state(struct drm_atomic_state *state,
1930                                      struct intel_crtc *crtc)
1931 {
1932         struct drm_crtc_state *crtc_state;
1933
1934         crtc_state = drm_atomic_get_existing_crtc_state(state, &crtc->base);
1935
1936         if (crtc_state)
1937                 return to_intel_crtc_state(crtc_state);
1938         else
1939                 return NULL;
1940 }
1941
1942 static inline struct intel_plane_state *
1943 intel_atomic_get_existing_plane_state(struct drm_atomic_state *state,
1944                                       struct intel_plane *plane)
1945 {
1946         struct drm_plane_state *plane_state;
1947
1948         plane_state = drm_atomic_get_existing_plane_state(state, &plane->base);
1949
1950         return to_intel_plane_state(plane_state);
1951 }
1952
1953 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
1954                                struct intel_crtc *intel_crtc,
1955                                struct intel_crtc_state *crtc_state);
1956
1957 /* intel_atomic_plane.c */
1958 struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
1959 struct drm_plane_state *intel_plane_duplicate_state(struct drm_plane *plane);
1960 void intel_plane_destroy_state(struct drm_plane *plane,
1961                                struct drm_plane_state *state);
1962 extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
1963 int intel_plane_atomic_check_with_state(struct intel_crtc_state *crtc_state,
1964                                         struct intel_plane_state *intel_state);
1965
1966 /* intel_color.c */
1967 void intel_color_init(struct drm_crtc *crtc);
1968 int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
1969 void intel_color_set_csc(struct drm_crtc_state *crtc_state);
1970 void intel_color_load_luts(struct drm_crtc_state *crtc_state);
1971
1972 /* intel_lspcon.c */
1973 bool lspcon_init(struct intel_digital_port *intel_dig_port);
1974 void lspcon_resume(struct intel_lspcon *lspcon);
1975 void lspcon_wait_pcon_mode(struct intel_lspcon *lspcon);
1976
1977 /* intel_pipe_crc.c */
1978 int intel_pipe_crc_create(struct drm_minor *minor);
1979 #ifdef CONFIG_DEBUG_FS
1980 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
1981                               size_t *values_cnt);
1982 #else
1983 #define intel_crtc_set_crc_source NULL
1984 #endif
1985 extern const struct file_operations i915_display_crc_ctl_fops;
1986 #endif /* __INTEL_DRV_H__ */