1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
7 #include "intel_dram.h"
9 struct dram_dimm_info {
10 u8 size, width, ranks;
13 struct dram_channel_info {
14 struct dram_dimm_info dimm_l, dimm_s;
19 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
21 static const char *intel_dram_type_str(enum intel_dram_type type)
23 static const char * const str[] = {
24 DRAM_TYPE_STR(UNKNOWN),
27 DRAM_TYPE_STR(LPDDR3),
28 DRAM_TYPE_STR(LPDDR4),
31 if (type >= ARRAY_SIZE(str))
32 type = INTEL_DRAM_UNKNOWN;
39 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
41 return dimm->ranks * 64 / (dimm->width ?: 1);
44 /* Returns total GB for the whole DIMM */
45 static int skl_get_dimm_size(u16 val)
47 return val & SKL_DRAM_SIZE_MASK;
50 static int skl_get_dimm_width(u16 val)
52 if (skl_get_dimm_size(val) == 0)
55 switch (val & SKL_DRAM_WIDTH_MASK) {
56 case SKL_DRAM_WIDTH_X8:
57 case SKL_DRAM_WIDTH_X16:
58 case SKL_DRAM_WIDTH_X32:
59 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
67 static int skl_get_dimm_ranks(u16 val)
69 if (skl_get_dimm_size(val) == 0)
72 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
77 /* Returns total GB for the whole DIMM */
78 static int cnl_get_dimm_size(u16 val)
80 return (val & CNL_DRAM_SIZE_MASK) / 2;
83 static int cnl_get_dimm_width(u16 val)
85 if (cnl_get_dimm_size(val) == 0)
88 switch (val & CNL_DRAM_WIDTH_MASK) {
89 case CNL_DRAM_WIDTH_X8:
90 case CNL_DRAM_WIDTH_X16:
91 case CNL_DRAM_WIDTH_X32:
92 val = (val & CNL_DRAM_WIDTH_MASK) >> CNL_DRAM_WIDTH_SHIFT;
100 static int cnl_get_dimm_ranks(u16 val)
102 if (cnl_get_dimm_size(val) == 0)
105 val = (val & CNL_DRAM_RANK_MASK) >> CNL_DRAM_RANK_SHIFT;
111 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
113 /* Convert total GB to Gb per DRAM device */
114 return 8 * dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
118 skl_dram_get_dimm_info(struct drm_i915_private *i915,
119 struct dram_dimm_info *dimm,
120 int channel, char dimm_name, u16 val)
122 if (INTEL_GEN(i915) >= 10) {
123 dimm->size = cnl_get_dimm_size(val);
124 dimm->width = cnl_get_dimm_width(val);
125 dimm->ranks = cnl_get_dimm_ranks(val);
127 dimm->size = skl_get_dimm_size(val);
128 dimm->width = skl_get_dimm_width(val);
129 dimm->ranks = skl_get_dimm_ranks(val);
132 drm_dbg_kms(&i915->drm,
133 "CH%u DIMM %c size: %u GB, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
134 channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
135 yesno(skl_is_16gb_dimm(dimm)));
139 skl_dram_get_channel_info(struct drm_i915_private *i915,
140 struct dram_channel_info *ch,
141 int channel, u32 val)
143 skl_dram_get_dimm_info(i915, &ch->dimm_l,
144 channel, 'L', val & 0xffff);
145 skl_dram_get_dimm_info(i915, &ch->dimm_s,
146 channel, 'S', val >> 16);
148 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
149 drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
153 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
155 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
160 ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||
161 skl_is_16gb_dimm(&ch->dimm_s);
163 drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
164 channel, ch->ranks, yesno(ch->is_16gb_dimm));
170 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
171 const struct dram_channel_info *ch1)
173 return !memcmp(ch0, ch1, sizeof(*ch0)) &&
174 (ch0->dimm_s.size == 0 ||
175 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
179 skl_dram_get_channels_info(struct drm_i915_private *i915)
181 struct dram_info *dram_info = &i915->dram_info;
182 struct dram_channel_info ch0 = {}, ch1 = {};
186 val = intel_uncore_read(&i915->uncore,
187 SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
188 ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
190 dram_info->num_channels++;
192 val = intel_uncore_read(&i915->uncore,
193 SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
194 ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
196 dram_info->num_channels++;
198 if (dram_info->num_channels == 0) {
199 drm_info(&i915->drm, "Number of memory channels is zero\n");
204 * If any of the channel is single rank channel, worst case output
205 * will be same as if single rank memory, so consider single rank
208 if (ch0.ranks == 1 || ch1.ranks == 1)
209 dram_info->ranks = 1;
211 dram_info->ranks = max(ch0.ranks, ch1.ranks);
213 if (dram_info->ranks == 0) {
214 drm_info(&i915->drm, "couldn't get memory rank information\n");
218 dram_info->is_16gb_dimm = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
220 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
222 drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
223 yesno(dram_info->symmetric_memory));
228 static enum intel_dram_type
229 skl_get_dram_type(struct drm_i915_private *i915)
233 val = intel_uncore_read(&i915->uncore,
234 SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
236 switch (val & SKL_DRAM_DDR_TYPE_MASK) {
237 case SKL_DRAM_DDR_TYPE_DDR3:
238 return INTEL_DRAM_DDR3;
239 case SKL_DRAM_DDR_TYPE_DDR4:
240 return INTEL_DRAM_DDR4;
241 case SKL_DRAM_DDR_TYPE_LPDDR3:
242 return INTEL_DRAM_LPDDR3;
243 case SKL_DRAM_DDR_TYPE_LPDDR4:
244 return INTEL_DRAM_LPDDR4;
247 return INTEL_DRAM_UNKNOWN;
252 skl_get_dram_info(struct drm_i915_private *i915)
254 struct dram_info *dram_info = &i915->dram_info;
255 u32 mem_freq_khz, val;
258 dram_info->type = skl_get_dram_type(i915);
259 drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
260 intel_dram_type_str(dram_info->type));
262 ret = skl_dram_get_channels_info(i915);
266 val = intel_uncore_read(&i915->uncore,
267 SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
268 mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
269 SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
271 dram_info->bandwidth_kbps = dram_info->num_channels *
274 if (dram_info->bandwidth_kbps == 0) {
276 "Couldn't get system memory bandwidth\n");
280 dram_info->valid = true;
284 /* Returns Gb per DRAM device */
285 static int bxt_get_dimm_size(u32 val)
287 switch (val & BXT_DRAM_SIZE_MASK) {
288 case BXT_DRAM_SIZE_4GBIT:
290 case BXT_DRAM_SIZE_6GBIT:
292 case BXT_DRAM_SIZE_8GBIT:
294 case BXT_DRAM_SIZE_12GBIT:
296 case BXT_DRAM_SIZE_16GBIT:
304 static int bxt_get_dimm_width(u32 val)
306 if (!bxt_get_dimm_size(val))
309 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
314 static int bxt_get_dimm_ranks(u32 val)
316 if (!bxt_get_dimm_size(val))
319 switch (val & BXT_DRAM_RANK_MASK) {
320 case BXT_DRAM_RANK_SINGLE:
322 case BXT_DRAM_RANK_DUAL:
330 static enum intel_dram_type bxt_get_dimm_type(u32 val)
332 if (!bxt_get_dimm_size(val))
333 return INTEL_DRAM_UNKNOWN;
335 switch (val & BXT_DRAM_TYPE_MASK) {
336 case BXT_DRAM_TYPE_DDR3:
337 return INTEL_DRAM_DDR3;
338 case BXT_DRAM_TYPE_LPDDR3:
339 return INTEL_DRAM_LPDDR3;
340 case BXT_DRAM_TYPE_DDR4:
341 return INTEL_DRAM_DDR4;
342 case BXT_DRAM_TYPE_LPDDR4:
343 return INTEL_DRAM_LPDDR4;
346 return INTEL_DRAM_UNKNOWN;
350 static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
352 dimm->width = bxt_get_dimm_width(val);
353 dimm->ranks = bxt_get_dimm_ranks(val);
356 * Size in register is Gb per DRAM device. Convert to total
357 * GB to match the way we report this for non-LP platforms.
359 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm) / 8;
362 static int bxt_get_dram_info(struct drm_i915_private *i915)
364 struct dram_info *dram_info = &i915->dram_info;
366 u32 mem_freq_khz, val;
367 u8 num_active_channels;
370 val = intel_uncore_read(&i915->uncore, BXT_P_CR_MC_BIOS_REQ_0_0_0);
371 mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
372 BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
374 dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
375 num_active_channels = hweight32(dram_channels);
377 /* Each active bit represents 4-byte channel */
378 dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
380 if (dram_info->bandwidth_kbps == 0) {
382 "Couldn't get system memory bandwidth\n");
387 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
389 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
390 struct dram_dimm_info dimm;
391 enum intel_dram_type type;
393 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
394 if (val == 0xFFFFFFFF)
397 dram_info->num_channels++;
399 bxt_get_dimm_info(&dimm, val);
400 type = bxt_get_dimm_type(val);
402 drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&
403 dram_info->type != INTEL_DRAM_UNKNOWN &&
404 dram_info->type != type);
406 drm_dbg_kms(&i915->drm,
407 "CH%u DIMM size: %u GB, width: X%u, ranks: %u, type: %s\n",
408 i - BXT_D_CR_DRP0_DUNIT_START,
409 dimm.size, dimm.width, dimm.ranks,
410 intel_dram_type_str(type));
413 * If any of the channel is single rank channel,
414 * worst case output will be same as if single rank
415 * memory, so consider single rank memory.
417 if (dram_info->ranks == 0)
418 dram_info->ranks = dimm.ranks;
419 else if (dimm.ranks == 1)
420 dram_info->ranks = 1;
422 if (type != INTEL_DRAM_UNKNOWN)
423 dram_info->type = type;
426 if (dram_info->type == INTEL_DRAM_UNKNOWN || dram_info->ranks == 0) {
427 drm_info(&i915->drm, "couldn't get memory information\n");
431 dram_info->valid = true;
436 void intel_dram_detect(struct drm_i915_private *i915)
438 struct dram_info *dram_info = &i915->dram_info;
442 * Assume 16Gb DIMMs are present until proven otherwise.
443 * This is only used for the level 0 watermark latency
444 * w/a which does not apply to bxt/glk.
446 dram_info->is_16gb_dimm = !IS_GEN9_LP(i915);
448 if (INTEL_GEN(i915) < 9 || !HAS_DISPLAY(i915))
451 if (IS_GEN9_LP(i915))
452 ret = bxt_get_dram_info(i915);
454 ret = skl_get_dram_info(i915);
458 drm_dbg_kms(&i915->drm, "DRAM bandwidth: %u kBps, channels: %u\n",
459 dram_info->bandwidth_kbps, dram_info->num_channels);
461 drm_dbg_kms(&i915->drm, "DRAM ranks: %u, 16Gb DIMMs: %s\n",
462 dram_info->ranks, yesno(dram_info->is_16gb_dimm));
465 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
467 static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
468 static const u8 sets[4] = { 1, 1, 2, 2 };
470 return EDRAM_NUM_BANKS(cap) *
471 ways[EDRAM_WAYS_IDX(cap)] *
472 sets[EDRAM_SETS_IDX(cap)];
475 void intel_dram_edram_detect(struct drm_i915_private *i915)
479 if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || INTEL_GEN(i915) >= 9))
482 edram_cap = __raw_uncore_read32(&i915->uncore, HSW_EDRAM_CAP);
484 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
486 if (!(edram_cap & EDRAM_ENABLED))
490 * The needed capability bits for size calculation are not there with
491 * pre gen9 so return 128MB always.
493 if (INTEL_GEN(i915) < 9)
494 i915->edram_size_mb = 128;
496 i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
498 drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);