drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_dp_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_hdcp.h>
  42 #include "intel_drv.h"
  43 #include <drm/i915_drm.h>
  44 #include "i915_drv.h"
  45
  46 #define DP_DPRX_ESI_LEN 14
  47
  48 /* Compliance test status bits  */
  49 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  50 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  52 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  53
  54 struct dp_link_dpll {
  55         int clock;
  56         struct dpll dpll;
  57 };
  58
  59 static const struct dp_link_dpll g4x_dpll[] = {
  60         { 162000,
  61                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  62         { 270000,
  63                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  64 };
  65
  66 static const struct dp_link_dpll pch_dpll[] = {
  67         { 162000,
  68                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  69         { 270000,
  70                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  71 };
  72
  73 static const struct dp_link_dpll vlv_dpll[] = {
  74         { 162000,
  75                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  76         { 270000,
  77                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  78 };
  79
  80 /*
  81  * CHV supports eDP 1.4 that have  more link rates.
  82  * Below only provides the fixed rate but exclude variable rate.
  83  */
  84 static const struct dp_link_dpll chv_dpll[] = {
  85         /*
  86          * CHV requires to program fractional division for m2.
  87          * m2 is stored in fixed point format using formula below
  88          * (m2_int << 22) | m2_fraction
  89          */
  90         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  91                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  92         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  94 };
  95
  96 /**
  97  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  98  * @intel_dp: DP struct
  99  *
 100  * If a CPU or PCH DP output is attached to an eDP panel, this function
 101  * will return true, and false otherwise.
 102  */
 103 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 104 {
 105         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 106
 107         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 108 }
 109
 110 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 111 {
 112         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 113
 114         return intel_dig_port->base.base.dev;
 115 }
 116
 117 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 118 {
 119         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 120 }
 121
 122 static void intel_dp_link_down(struct intel_encoder *encoder,
 123                                const struct intel_crtc_state *old_crtc_state);
 124 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 125 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 126 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 127                                            const struct intel_crtc_state *crtc_state);
 128 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 129                                       enum pipe pipe);
 130 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 131
 132 /* update sink rates from dpcd */
 133 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 134 {
 135         static const int dp_rates[] = {
 136                 162000, 270000, 540000, 810000
 137         };
 138         int i, max_rate;
 139
 140         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 141
 142         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 143                 if (dp_rates[i] > max_rate)
 144                         break;
 145                 intel_dp->sink_rates[i] = dp_rates[i];
 146         }
 147
 148         intel_dp->num_sink_rates = i;
 149 }
 150
 151 /* Get length of rates array potentially limited by max_rate. */
 152 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 153 {
 154         int i;
 155
 156         /* Limit results by potentially reduced max rate */
 157         for (i = 0; i < len; i++) {
 158                 if (rates[len - i - 1] <= max_rate)
 159                         return len - i;
 160         }
 161
 162         return 0;
 163 }
 164
 165 /* Get length of common rates array potentially limited by max_rate. */
 166 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 167                                           int max_rate)
 168 {
 169         return intel_dp_rate_limit_len(intel_dp->common_rates,
 170                                        intel_dp->num_common_rates, max_rate);
 171 }
 172
 173 /* Theoretical max between source and sink */
 174 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 175 {
 176         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 177 }
 178
 179 /* Theoretical max between source and sink */
 180 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 181 {
 182         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 183         int source_max = intel_dig_port->max_lanes;
 184         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 185
 186         return min(source_max, sink_max);
 187 }
 188
 189 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 190 {
 191         return intel_dp->max_link_lane_count;
 192 }
 193
 194 int
 195 intel_dp_link_required(int pixel_clock, int bpp)
 196 {
 197         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 198         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 199 }
 200
 201 int
 202 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 203 {
 204         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 205          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 206          * is transmitted every LS_Clk per lane, there is no need to account for
 207          * the channel encoding that is done in the PHY layer here.
 208          */
 209
 210         return max_link_clock * max_lanes;
 211 }
 212
 213 static int
 214 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 215 {
 216         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 217         struct intel_encoder *encoder = &intel_dig_port->base;
 218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 219         int max_dotclk = dev_priv->max_dotclk_freq;
 220         int ds_max_dotclk;
 221
 222         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 223
 224         if (type != DP_DS_PORT_TYPE_VGA)
 225                 return max_dotclk;
 226
 227         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 228                                                     intel_dp->downstream_ports);
 229
 230         if (ds_max_dotclk != 0)
 231                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 232
 233         return max_dotclk;
 234 }
 235
 236 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 237 {
 238         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 239         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 240         enum port port = dig_port->base.port;
 241
 242         u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 243
 244         /* Low voltage SKUs are limited to max of 5.4G */
 245         if (voltage == VOLTAGE_INFO_0_85V)
 246                 return 540000;
 247
 248         /* For this SKU 8.1G is supported in all ports */
 249         if (IS_CNL_WITH_PORT_F(dev_priv))
 250                 return 810000;
 251
 252         /* For other SKUs, max rate on ports A and D is 5.4G */
 253         if (port == PORT_A || port == PORT_D)
 254                 return 540000;
 255
 256         return 810000;
 257 }
 258
 259 static int icl_max_source_rate(struct intel_dp *intel_dp)
 260 {
 261         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 262         enum port port = dig_port->base.port;
 263
 264         if (port == PORT_B)
 265                 return 540000;
 266
 267         return 810000;
 268 }
 269
 270 static void
 271 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 272 {
 273         /* The values must be in increasing order */
 274         static const int cnl_rates[] = {
 275                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 276         };
 277         static const int bxt_rates[] = {
 278                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 279         };
 280         static const int skl_rates[] = {
 281                 162000, 216000, 270000, 324000, 432000, 540000
 282         };
 283         static const int hsw_rates[] = {
 284                 162000, 270000, 540000
 285         };
 286         static const int g4x_rates[] = {
 287                 162000, 270000
 288         };
 289         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 290         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 291         const struct ddi_vbt_port_info *info =
 292                 &dev_priv->vbt.ddi_port_info[dig_port->base.port];
 293         const int *source_rates;
 294         int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate;
 295
 296         /* This should only be done once */
 297         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 298
 299         if (INTEL_GEN(dev_priv) >= 10) {
 300                 source_rates = cnl_rates;
 301                 size = ARRAY_SIZE(cnl_rates);
 302                 if (INTEL_GEN(dev_priv) == 10)
 303                         max_rate = cnl_max_source_rate(intel_dp);
 304                 else
 305                         max_rate = icl_max_source_rate(intel_dp);
 306         } else if (IS_GEN9_LP(dev_priv)) {
 307                 source_rates = bxt_rates;
 308                 size = ARRAY_SIZE(bxt_rates);
 309         } else if (IS_GEN9_BC(dev_priv)) {
 310                 source_rates = skl_rates;
 311                 size = ARRAY_SIZE(skl_rates);
 312         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 313                    IS_BROADWELL(dev_priv)) {
 314                 source_rates = hsw_rates;
 315                 size = ARRAY_SIZE(hsw_rates);
 316         } else {
 317                 source_rates = g4x_rates;
 318                 size = ARRAY_SIZE(g4x_rates);
 319         }
 320
 321         if (max_rate && vbt_max_rate)
 322                 max_rate = min(max_rate, vbt_max_rate);
 323         else if (vbt_max_rate)
 324                 max_rate = vbt_max_rate;
 325
 326         if (max_rate)
 327                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 328
 329         intel_dp->source_rates = source_rates;
 330         intel_dp->num_source_rates = size;
 331 }
 332
 333 static int intersect_rates(const int *source_rates, int source_len,
 334                            const int *sink_rates, int sink_len,
 335                            int *common_rates)
 336 {
 337         int i = 0, j = 0, k = 0;
 338
 339         while (i < source_len && j < sink_len) {
 340                 if (source_rates[i] == sink_rates[j]) {
 341                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 342                                 return k;
 343                         common_rates[k] = source_rates[i];
 344                         ++k;
 345                         ++i;
 346                         ++j;
 347                 } else if (source_rates[i] < sink_rates[j]) {
 348                         ++i;
 349                 } else {
 350                         ++j;
 351                 }
 352         }
 353         return k;
 354 }
 355
 356 /* return index of rate in rates array, or -1 if not found */
 357 static int intel_dp_rate_index(const int *rates, int len, int rate)
 358 {
 359         int i;
 360
 361         for (i = 0; i < len; i++)
 362                 if (rate == rates[i])
 363                         return i;
 364
 365         return -1;
 366 }
 367
 368 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 369 {
 370         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 371
 372         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 373                                                      intel_dp->num_source_rates,
 374                                                      intel_dp->sink_rates,
 375                                                      intel_dp->num_sink_rates,
 376                                                      intel_dp->common_rates);
 377
 378         /* Paranoia, there should always be something in common. */
 379         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 380                 intel_dp->common_rates[0] = 162000;
 381                 intel_dp->num_common_rates = 1;
 382         }
 383 }
 384
 385 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 386                                        uint8_t lane_count)
 387 {
 388         /*
 389          * FIXME: we need to synchronize the current link parameters with
 390          * hardware readout. Currently fast link training doesn't work on
 391          * boot-up.
 392          */
 393         if (link_rate == 0 ||
 394             link_rate > intel_dp->max_link_rate)
 395                 return false;
 396
 397         if (lane_count == 0 ||
 398             lane_count > intel_dp_max_lane_count(intel_dp))
 399                 return false;
 400
 401         return true;
 402 }
 403
 404 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 405                                                      int link_rate,
 406                                                      uint8_t lane_count)
 407 {
 408         const struct drm_display_mode *fixed_mode =
 409                 intel_dp->attached_connector->panel.fixed_mode;
 410         int mode_rate, max_rate;
 411
 412         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 413         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 414         if (mode_rate > max_rate)
 415                 return false;
 416
 417         return true;
 418 }
 419
 420 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 421                                             int link_rate, uint8_t lane_count)
 422 {
 423         int index;
 424
 425         index = intel_dp_rate_index(intel_dp->common_rates,
 426                                     intel_dp->num_common_rates,
 427                                     link_rate);
 428         if (index > 0) {
 429                 if (intel_dp_is_edp(intel_dp) &&
 430                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 431                                                               intel_dp->common_rates[index - 1],
 432                                                               lane_count)) {
 433                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 434                         return 0;
 435                 }
 436                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 437                 intel_dp->max_link_lane_count = lane_count;
 438         } else if (lane_count > 1) {
 439                 if (intel_dp_is_edp(intel_dp) &&
 440                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 441                                                               intel_dp_max_common_rate(intel_dp),
 442                                                               lane_count >> 1)) {
 443                         DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n");
 444                         return 0;
 445                 }
 446                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 447                 intel_dp->max_link_lane_count = lane_count >> 1;
 448         } else {
 449                 DRM_ERROR("Link Training Unsuccessful\n");
 450                 return -1;
 451         }
 452
 453         return 0;
 454 }
 455
 456 static enum drm_mode_status
 457 intel_dp_mode_valid(struct drm_connector *connector,
 458                     struct drm_display_mode *mode)
 459 {
 460         struct intel_dp *intel_dp = intel_attached_dp(connector);
 461         struct intel_connector *intel_connector = to_intel_connector(connector);
 462         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 463         int target_clock = mode->clock;
 464         int max_rate, mode_rate, max_lanes, max_link_clock;
 465         int max_dotclk;
 466
 467         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 468                 return MODE_NO_DBLESCAN;
 469
 470         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 471
 472         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 473                 if (mode->hdisplay > fixed_mode->hdisplay)
 474                         return MODE_PANEL;
 475
 476                 if (mode->vdisplay > fixed_mode->vdisplay)
 477                         return MODE_PANEL;
 478
 479                 target_clock = fixed_mode->clock;
 480         }
 481
 482         max_link_clock = intel_dp_max_link_rate(intel_dp);
 483         max_lanes = intel_dp_max_lane_count(intel_dp);
 484
 485         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 486         mode_rate = intel_dp_link_required(target_clock, 18);
 487
 488         if (mode_rate > max_rate || target_clock > max_dotclk)
 489                 return MODE_CLOCK_HIGH;
 490
 491         if (mode->clock < 10000)
 492                 return MODE_CLOCK_LOW;
 493
 494         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 495                 return MODE_H_ILLEGAL;
 496
 497         return MODE_OK;
 498 }
 499
 500 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 501 {
 502         int     i;
 503         uint32_t v = 0;
 504
 505         if (src_bytes > 4)
 506                 src_bytes = 4;
 507         for (i = 0; i < src_bytes; i++)
 508                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 509         return v;
 510 }
 511
 512 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 513 {
 514         int i;
 515         if (dst_bytes > 4)
 516                 dst_bytes = 4;
 517         for (i = 0; i < dst_bytes; i++)
 518                 dst[i] = src >> ((3-i) * 8);
 519 }
 520
 521 static void
 522 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 523 static void
 524 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 525                                               bool force_disable_vdd);
 526 static void
 527 intel_dp_pps_init(struct intel_dp *intel_dp);
 528
 529 static void pps_lock(struct intel_dp *intel_dp)
 530 {
 531         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 532
 533         /*
 534          * See intel_power_sequencer_reset() why we need
 535          * a power domain reference here.
 536          */
 537         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 538
 539         mutex_lock(&dev_priv->pps_mutex);
 540 }
 541
 542 static void pps_unlock(struct intel_dp *intel_dp)
 543 {
 544         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 545
 546         mutex_unlock(&dev_priv->pps_mutex);
 547
 548         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 549 }
 550
 551 static void
 552 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 553 {
 554         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 555         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 556         enum pipe pipe = intel_dp->pps_pipe;
 557         bool pll_enabled, release_cl_override = false;
 558         enum dpio_phy phy = DPIO_PHY(pipe);
 559         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 560         uint32_t DP;
 561
 562         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 563                  "skipping pipe %c power sequencer kick due to port %c being active\n",
 564                  pipe_name(pipe), port_name(intel_dig_port->base.port)))
 565                 return;
 566
 567         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 568                       pipe_name(pipe), port_name(intel_dig_port->base.port));
 569
 570         /* Preserve the BIOS-computed detected bit. This is
 571          * supposed to be read-only.
 572          */
 573         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 574         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 575         DP |= DP_PORT_WIDTH(1);
 576         DP |= DP_LINK_TRAIN_PAT_1;
 577
 578         if (IS_CHERRYVIEW(dev_priv))
 579                 DP |= DP_PIPE_SEL_CHV(pipe);
 580         else
 581                 DP |= DP_PIPE_SEL(pipe);
 582
 583         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 584
 585         /*
 586          * The DPLL for the pipe must be enabled for this to work.
 587          * So enable temporarily it if it's not already enabled.
 588          */
 589         if (!pll_enabled) {
 590                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 591                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 592
 593                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 594                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 595                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 596                                   pipe_name(pipe));
 597                         return;
 598                 }
 599         }
 600
 601         /*
 602          * Similar magic as in intel_dp_enable_port().
 603          * We _must_ do this port enable + disable trick
 604          * to make this power sequencer lock onto the port.
 605          * Otherwise even VDD force bit won't work.
 606          */
 607         I915_WRITE(intel_dp->output_reg, DP);
 608         POSTING_READ(intel_dp->output_reg);
 609
 610         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 611         POSTING_READ(intel_dp->output_reg);
 612
 613         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 614         POSTING_READ(intel_dp->output_reg);
 615
 616         if (!pll_enabled) {
 617                 vlv_force_pll_off(dev_priv, pipe);
 618
 619                 if (release_cl_override)
 620                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 621         }
 622 }
 623
 624 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 625 {
 626         struct intel_encoder *encoder;
 627         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 628
 629         /*
 630          * We don't have power sequencer currently.
 631          * Pick one that's not used by other ports.
 632          */
 633         for_each_intel_dp(&dev_priv->drm, encoder) {
 634                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 635
 636                 if (encoder->type == INTEL_OUTPUT_EDP) {
 637                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 638                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 639
 640                         if (intel_dp->pps_pipe != INVALID_PIPE)
 641                                 pipes &= ~(1 << intel_dp->pps_pipe);
 642                 } else {
 643                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 644
 645                         if (intel_dp->active_pipe != INVALID_PIPE)
 646                                 pipes &= ~(1 << intel_dp->active_pipe);
 647                 }
 648         }
 649
 650         if (pipes == 0)
 651                 return INVALID_PIPE;
 652
 653         return ffs(pipes) - 1;
 654 }
 655
 656 static enum pipe
 657 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 658 {
 659         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 660         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 661         enum pipe pipe;
 662
 663         lockdep_assert_held(&dev_priv->pps_mutex);
 664
 665         /* We should never land here with regular DP ports */
 666         WARN_ON(!intel_dp_is_edp(intel_dp));
 667
 668         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 669                 intel_dp->active_pipe != intel_dp->pps_pipe);
 670
 671         if (intel_dp->pps_pipe != INVALID_PIPE)
 672                 return intel_dp->pps_pipe;
 673
 674         pipe = vlv_find_free_pps(dev_priv);
 675
 676         /*
 677          * Didn't find one. This should not happen since there
 678          * are two power sequencers and up to two eDP ports.
 679          */
 680         if (WARN_ON(pipe == INVALID_PIPE))
 681                 pipe = PIPE_A;
 682
 683         vlv_steal_power_sequencer(dev_priv, pipe);
 684         intel_dp->pps_pipe = pipe;
 685
 686         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 687                       pipe_name(intel_dp->pps_pipe),
 688                       port_name(intel_dig_port->base.port));
 689
 690         /* init power sequencer on this pipe and port */
 691         intel_dp_init_panel_power_sequencer(intel_dp);
 692         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
 693
 694         /*
 695          * Even vdd force doesn't work until we've made
 696          * the power sequencer lock in on the port.
 697          */
 698         vlv_power_sequencer_kick(intel_dp);
 699
 700         return intel_dp->pps_pipe;
 701 }
 702
 703 static int
 704 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 705 {
 706         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 707         int backlight_controller = dev_priv->vbt.backlight.controller;
 708
 709         lockdep_assert_held(&dev_priv->pps_mutex);
 710
 711         /* We should never land here with regular DP ports */
 712         WARN_ON(!intel_dp_is_edp(intel_dp));
 713
 714         if (!intel_dp->pps_reset)
 715                 return backlight_controller;
 716
 717         intel_dp->pps_reset = false;
 718
 719         /*
 720          * Only the HW needs to be reprogrammed, the SW state is fixed and
 721          * has been setup during connector init.
 722          */
 723         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 724
 725         return backlight_controller;
 726 }
 727
 728 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 729                                enum pipe pipe);
 730
 731 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 732                                enum pipe pipe)
 733 {
 734         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 735 }
 736
 737 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 738                                 enum pipe pipe)
 739 {
 740         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 741 }
 742
 743 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 744                          enum pipe pipe)
 745 {
 746         return true;
 747 }
 748
 749 static enum pipe
 750 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 751                      enum port port,
 752                      vlv_pipe_check pipe_check)
 753 {
 754         enum pipe pipe;
 755
 756         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 757                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 758                         PANEL_PORT_SELECT_MASK;
 759
 760                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 761                         continue;
 762
 763                 if (!pipe_check(dev_priv, pipe))
 764                         continue;
 765
 766                 return pipe;
 767         }
 768
 769         return INVALID_PIPE;
 770 }
 771
 772 static void
 773 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 774 {
 775         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 776         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 777         enum port port = intel_dig_port->base.port;
 778
 779         lockdep_assert_held(&dev_priv->pps_mutex);
 780
 781         /* try to find a pipe with this port selected */
 782         /* first pick one where the panel is on */
 783         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 784                                                   vlv_pipe_has_pp_on);
 785         /* didn't find one? pick one where vdd is on */
 786         if (intel_dp->pps_pipe == INVALID_PIPE)
 787                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 788                                                           vlv_pipe_has_vdd_on);
 789         /* didn't find one? pick one with just the correct port */
 790         if (intel_dp->pps_pipe == INVALID_PIPE)
 791                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 792                                                           vlv_pipe_any);
 793
 794         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 795         if (intel_dp->pps_pipe == INVALID_PIPE) {
 796                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 797                               port_name(port));
 798                 return;
 799         }
 800
 801         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 802                       port_name(port), pipe_name(intel_dp->pps_pipe));
 803
 804         intel_dp_init_panel_power_sequencer(intel_dp);
 805         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
 806 }
 807
 808 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 809 {
 810         struct intel_encoder *encoder;
 811
 812         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 813                     !IS_GEN9_LP(dev_priv)))
 814                 return;
 815
 816         /*
 817          * We can't grab pps_mutex here due to deadlock with power_domain
 818          * mutex when power_domain functions are called while holding pps_mutex.
 819          * That also means that in order to use pps_pipe the code needs to
 820          * hold both a power domain reference and pps_mutex, and the power domain
 821          * reference get/put must be done while _not_ holding pps_mutex.
 822          * pps_{lock,unlock}() do these steps in the correct order, so one
 823          * should use them always.
 824          */
 825
 826         for_each_intel_dp(&dev_priv->drm, encoder) {
 827                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
 828
 829                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 830
 831                 if (encoder->type != INTEL_OUTPUT_EDP)
 832                         continue;
 833
 834                 if (IS_GEN9_LP(dev_priv))
 835                         intel_dp->pps_reset = true;
 836                 else
 837                         intel_dp->pps_pipe = INVALID_PIPE;
 838         }
 839 }
 840
 841 struct pps_registers {
 842         i915_reg_t pp_ctrl;
 843         i915_reg_t pp_stat;
 844         i915_reg_t pp_on;
 845         i915_reg_t pp_off;
 846         i915_reg_t pp_div;
 847 };
 848
 849 static void intel_pps_get_registers(struct intel_dp *intel_dp,
 850                                     struct pps_registers *regs)
 851 {
 852         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 853         int pps_idx = 0;
 854
 855         memset(regs, 0, sizeof(*regs));
 856
 857         if (IS_GEN9_LP(dev_priv))
 858                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 859         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 860                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 861
 862         regs->pp_ctrl = PP_CONTROL(pps_idx);
 863         regs->pp_stat = PP_STATUS(pps_idx);
 864         regs->pp_on = PP_ON_DELAYS(pps_idx);
 865         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 866         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
 867             !HAS_PCH_ICP(dev_priv))
 868                 regs->pp_div = PP_DIVISOR(pps_idx);
 869 }
 870
 871 static i915_reg_t
 872 _pp_ctrl_reg(struct intel_dp *intel_dp)
 873 {
 874         struct pps_registers regs;
 875
 876         intel_pps_get_registers(intel_dp, &regs);
 877
 878         return regs.pp_ctrl;
 879 }
 880
 881 static i915_reg_t
 882 _pp_stat_reg(struct intel_dp *intel_dp)
 883 {
 884         struct pps_registers regs;
 885
 886         intel_pps_get_registers(intel_dp, &regs);
 887
 888         return regs.pp_stat;
 889 }
 890
 891 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 892    This function only applicable when panel PM state is not to be tracked */
 893 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 894                               void *unused)
 895 {
 896         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 897                                                  edp_notifier);
 898         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 899
 900         if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART)
 901                 return 0;
 902
 903         pps_lock(intel_dp);
 904
 905         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 906                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 907                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 908                 u32 pp_div;
 909
 910                 pp_ctrl_reg = PP_CONTROL(pipe);
 911                 pp_div_reg  = PP_DIVISOR(pipe);
 912                 pp_div = I915_READ(pp_div_reg);
 913                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 914
 915                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 916                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 917                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 918                 msleep(intel_dp->panel_power_cycle_delay);
 919         }
 920
 921         pps_unlock(intel_dp);
 922
 923         return 0;
 924 }
 925
 926 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 927 {
 928         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 929
 930         lockdep_assert_held(&dev_priv->pps_mutex);
 931
 932         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 933             intel_dp->pps_pipe == INVALID_PIPE)
 934                 return false;
 935
 936         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 937 }
 938
 939 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 940 {
 941         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 942
 943         lockdep_assert_held(&dev_priv->pps_mutex);
 944
 945         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 946             intel_dp->pps_pipe == INVALID_PIPE)
 947                 return false;
 948
 949         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 950 }
 951
 952 static void
 953 intel_dp_check_edp(struct intel_dp *intel_dp)
 954 {
 955         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 956
 957         if (!intel_dp_is_edp(intel_dp))
 958                 return;
 959
 960         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 961                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 962                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 963                               I915_READ(_pp_stat_reg(intel_dp)),
 964                               I915_READ(_pp_ctrl_reg(intel_dp)));
 965         }
 966 }
 967
 968 static uint32_t
 969 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
 970 {
 971         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 972         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
 973         uint32_t status;
 974         bool done;
 975
 976 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 977         done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 978                                   msecs_to_jiffies_timeout(10));
 979         if (!done)
 980                 DRM_ERROR("dp aux hw did not signal timeout!\n");
 981 #undef C
 982
 983         return status;
 984 }
 985
 986 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 987 {
 988         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
 989
 990         if (index)
 991                 return 0;
 992
 993         /*
 994          * The clock divider is based off the hrawclk, and would like to run at
 995          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 996          */
 997         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 998 }
 999
1000 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1001 {
1002         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1003
1004         if (index)
1005                 return 0;
1006
1007         /*
1008          * The clock divider is based off the cdclk or PCH rawclk, and would
1009          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1010          * divide by 2000 and use that
1011          */
1012         if (intel_dp->aux_ch == AUX_CH_A)
1013                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
1014         else
1015                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
1016 }
1017
1018 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1019 {
1020         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1021
1022         if (intel_dp->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1023                 /* Workaround for non-ULT HSW */
1024                 switch (index) {
1025                 case 0: return 63;
1026                 case 1: return 72;
1027                 default: return 0;
1028                 }
1029         }
1030
1031         return ilk_get_aux_clock_divider(intel_dp, index);
1032 }
1033
1034 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1035 {
1036         /*
1037          * SKL doesn't need us to program the AUX clock divider (Hardware will
1038          * derive the clock from CDCLK automatically). We still implement the
1039          * get_aux_clock_divider vfunc to plug-in into the existing code.
1040          */
1041         return index ? 0 : 1;
1042 }
1043
1044 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1045                                      int send_bytes,
1046                                      uint32_t aux_clock_divider)
1047 {
1048         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1049         struct drm_i915_private *dev_priv =
1050                         to_i915(intel_dig_port->base.base.dev);
1051         uint32_t precharge, timeout;
1052
1053         if (IS_GEN6(dev_priv))
1054                 precharge = 3;
1055         else
1056                 precharge = 5;
1057
1058         if (IS_BROADWELL(dev_priv))
1059                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1060         else
1061                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1062
1063         return DP_AUX_CH_CTL_SEND_BUSY |
1064                DP_AUX_CH_CTL_DONE |
1065                DP_AUX_CH_CTL_INTERRUPT |
1066                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1067                timeout |
1068                DP_AUX_CH_CTL_RECEIVE_ERROR |
1069                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1070                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1071                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1072 }
1073
1074 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1075                                       int send_bytes,
1076                                       uint32_t unused)
1077 {
1078         return DP_AUX_CH_CTL_SEND_BUSY |
1079                DP_AUX_CH_CTL_DONE |
1080                DP_AUX_CH_CTL_INTERRUPT |
1081                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1082                DP_AUX_CH_CTL_TIME_OUT_MAX |
1083                DP_AUX_CH_CTL_RECEIVE_ERROR |
1084                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1085                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1086                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1087 }
1088
1089 static int
1090 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1091                   const uint8_t *send, int send_bytes,
1092                   uint8_t *recv, int recv_size,
1093                   u32 aux_send_ctl_flags)
1094 {
1095         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1096         struct drm_i915_private *dev_priv =
1097                         to_i915(intel_dig_port->base.base.dev);
1098         i915_reg_t ch_ctl, ch_data[5];
1099         uint32_t aux_clock_divider;
1100         int i, ret, recv_bytes;
1101         uint32_t status;
1102         int try, clock = 0;
1103         bool vdd;
1104
1105         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1106         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1107                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1108
1109         pps_lock(intel_dp);
1110
1111         /*
1112          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1113          * In such cases we want to leave VDD enabled and it's up to upper layers
1114          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1115          * ourselves.
1116          */
1117         vdd = edp_panel_vdd_on(intel_dp);
1118
1119         /* dp aux is extremely sensitive to irq latency, hence request the
1120          * lowest possible wakeup latency and so prevent the cpu from going into
1121          * deep sleep states.
1122          */
1123         pm_qos_update_request(&dev_priv->pm_qos, 0);
1124
1125         intel_dp_check_edp(intel_dp);
1126
1127         /* Try to wait for any previous AUX channel activity */
1128         for (try = 0; try < 3; try++) {
1129                 status = I915_READ_NOTRACE(ch_ctl);
1130                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1131                         break;
1132                 msleep(1);
1133         }
1134
1135         if (try == 3) {
1136                 static u32 last_status = -1;
1137                 const u32 status = I915_READ(ch_ctl);
1138
1139                 if (status != last_status) {
1140                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1141                              status);
1142                         last_status = status;
1143                 }
1144
1145                 ret = -EBUSY;
1146                 goto out;
1147         }
1148
1149         /* Only 5 data registers! */
1150         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1151                 ret = -E2BIG;
1152                 goto out;
1153         }
1154
1155         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1156                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1157                                                           send_bytes,
1158                                                           aux_clock_divider);
1159
1160                 send_ctl |= aux_send_ctl_flags;
1161
1162                 /* Must try at least 3 times according to DP spec */
1163                 for (try = 0; try < 5; try++) {
1164                         /* Load the send data into the aux channel data registers */
1165                         for (i = 0; i < send_bytes; i += 4)
1166                                 I915_WRITE(ch_data[i >> 2],
1167                                            intel_dp_pack_aux(send + i,
1168                                                              send_bytes - i));
1169
1170                         /* Send the command and wait for it to complete */
1171                         I915_WRITE(ch_ctl, send_ctl);
1172
1173                         status = intel_dp_aux_wait_done(intel_dp);
1174
1175                         /* Clear done status and any errors */
1176                         I915_WRITE(ch_ctl,
1177                                    status |
1178                                    DP_AUX_CH_CTL_DONE |
1179                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1180                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1181
1182                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1183                          *   400us delay required for errors and timeouts
1184                          *   Timeout errors from the HW already meet this
1185                          *   requirement so skip to next iteration
1186                          */
1187                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1188                                 continue;
1189
1190                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1191                                 usleep_range(400, 500);
1192                                 continue;
1193                         }
1194                         if (status & DP_AUX_CH_CTL_DONE)
1195                                 goto done;
1196                 }
1197         }
1198
1199         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1200                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1201                 ret = -EBUSY;
1202                 goto out;
1203         }
1204
1205 done:
1206         /* Check for timeout or receive error.
1207          * Timeouts occur when the sink is not connected
1208          */
1209         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1210                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1211                 ret = -EIO;
1212                 goto out;
1213         }
1214
1215         /* Timeouts occur when the device isn't connected, so they're
1216          * "normal" -- don't fill the kernel log with these */
1217         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1218                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1219                 ret = -ETIMEDOUT;
1220                 goto out;
1221         }
1222
1223         /* Unload any bytes sent back from the other side */
1224         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1225                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1226
1227         /*
1228          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1229          * We have no idea of what happened so we return -EBUSY so
1230          * drm layer takes care for the necessary retries.
1231          */
1232         if (recv_bytes == 0 || recv_bytes > 20) {
1233                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1234                               recv_bytes);
1235                 ret = -EBUSY;
1236                 goto out;
1237         }
1238
1239         if (recv_bytes > recv_size)
1240                 recv_bytes = recv_size;
1241
1242         for (i = 0; i < recv_bytes; i += 4)
1243                 intel_dp_unpack_aux(I915_READ(ch_data[i >> 2]),
1244                                     recv + i, recv_bytes - i);
1245
1246         ret = recv_bytes;
1247 out:
1248         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1249
1250         if (vdd)
1251                 edp_panel_vdd_off(intel_dp, false);
1252
1253         pps_unlock(intel_dp);
1254
1255         return ret;
1256 }
1257
1258 #define BARE_ADDRESS_SIZE       3
1259 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1260
1261 static void
1262 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1263                     const struct drm_dp_aux_msg *msg)
1264 {
1265         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1266         txbuf[1] = (msg->address >> 8) & 0xff;
1267         txbuf[2] = msg->address & 0xff;
1268         txbuf[3] = msg->size - 1;
1269 }
1270
1271 static ssize_t
1272 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1273 {
1274         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1275         uint8_t txbuf[20], rxbuf[20];
1276         size_t txsize, rxsize;
1277         int ret;
1278
1279         intel_dp_aux_header(txbuf, msg);
1280
1281         switch (msg->request & ~DP_AUX_I2C_MOT) {
1282         case DP_AUX_NATIVE_WRITE:
1283         case DP_AUX_I2C_WRITE:
1284         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1285                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1286                 rxsize = 2; /* 0 or 1 data bytes */
1287
1288                 if (WARN_ON(txsize > 20))
1289                         return -E2BIG;
1290
1291                 WARN_ON(!msg->buffer != !msg->size);
1292
1293                 if (msg->buffer)
1294                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1295
1296                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1297                                         rxbuf, rxsize, 0);
1298                 if (ret > 0) {
1299                         msg->reply = rxbuf[0] >> 4;
1300
1301                         if (ret > 1) {
1302                                 /* Number of bytes written in a short write. */
1303                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1304                         } else {
1305                                 /* Return payload size. */
1306                                 ret = msg->size;
1307                         }
1308                 }
1309                 break;
1310
1311         case DP_AUX_NATIVE_READ:
1312         case DP_AUX_I2C_READ:
1313                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1314                 rxsize = msg->size + 1;
1315
1316                 if (WARN_ON(rxsize > 20))
1317                         return -E2BIG;
1318
1319                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1320                                         rxbuf, rxsize, 0);
1321                 if (ret > 0) {
1322                         msg->reply = rxbuf[0] >> 4;
1323                         /*
1324                          * Assume happy day, and copy the data. The caller is
1325                          * expected to check msg->reply before touching it.
1326                          *
1327                          * Return payload size.
1328                          */
1329                         ret--;
1330                         memcpy(msg->buffer, rxbuf + 1, ret);
1331                 }
1332                 break;
1333
1334         default:
1335                 ret = -EINVAL;
1336                 break;
1337         }
1338
1339         return ret;
1340 }
1341
1342 static enum aux_ch intel_aux_ch(struct intel_dp *intel_dp)
1343 {
1344         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1345         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1346         enum port port = encoder->port;
1347         const struct ddi_vbt_port_info *info =
1348                 &dev_priv->vbt.ddi_port_info[port];
1349         enum aux_ch aux_ch;
1350
1351         if (!info->alternate_aux_channel) {
1352                 aux_ch = (enum aux_ch) port;
1353
1354                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1355                               aux_ch_name(aux_ch), port_name(port));
1356                 return aux_ch;
1357         }
1358
1359         switch (info->alternate_aux_channel) {
1360         case DP_AUX_A:
1361                 aux_ch = AUX_CH_A;
1362                 break;
1363         case DP_AUX_B:
1364                 aux_ch = AUX_CH_B;
1365                 break;
1366         case DP_AUX_C:
1367                 aux_ch = AUX_CH_C;
1368                 break;
1369         case DP_AUX_D:
1370                 aux_ch = AUX_CH_D;
1371                 break;
1372         case DP_AUX_E:
1373                 aux_ch = AUX_CH_E;
1374                 break;
1375         case DP_AUX_F:
1376                 aux_ch = AUX_CH_F;
1377                 break;
1378         default:
1379                 MISSING_CASE(info->alternate_aux_channel);
1380                 aux_ch = AUX_CH_A;
1381                 break;
1382         }
1383
1384         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1385                       aux_ch_name(aux_ch), port_name(port));
1386
1387         return aux_ch;
1388 }
1389
1390 static enum intel_display_power_domain
1391 intel_aux_power_domain(struct intel_dp *intel_dp)
1392 {
1393         switch (intel_dp->aux_ch) {
1394         case AUX_CH_A:
1395                 return POWER_DOMAIN_AUX_A;
1396         case AUX_CH_B:
1397                 return POWER_DOMAIN_AUX_B;
1398         case AUX_CH_C:
1399                 return POWER_DOMAIN_AUX_C;
1400         case AUX_CH_D:
1401                 return POWER_DOMAIN_AUX_D;
1402         case AUX_CH_E:
1403                 return POWER_DOMAIN_AUX_E;
1404         case AUX_CH_F:
1405                 return POWER_DOMAIN_AUX_F;
1406         default:
1407                 MISSING_CASE(intel_dp->aux_ch);
1408                 return POWER_DOMAIN_AUX_A;
1409         }
1410 }
1411
1412 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1413 {
1414         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1415         enum aux_ch aux_ch = intel_dp->aux_ch;
1416
1417         switch (aux_ch) {
1418         case AUX_CH_B:
1419         case AUX_CH_C:
1420         case AUX_CH_D:
1421                 return DP_AUX_CH_CTL(aux_ch);
1422         default:
1423                 MISSING_CASE(aux_ch);
1424                 return DP_AUX_CH_CTL(AUX_CH_B);
1425         }
1426 }
1427
1428 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1429 {
1430         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1431         enum aux_ch aux_ch = intel_dp->aux_ch;
1432
1433         switch (aux_ch) {
1434         case AUX_CH_B:
1435         case AUX_CH_C:
1436         case AUX_CH_D:
1437                 return DP_AUX_CH_DATA(aux_ch, index);
1438         default:
1439                 MISSING_CASE(aux_ch);
1440                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1441         }
1442 }
1443
1444 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1445 {
1446         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1447         enum aux_ch aux_ch = intel_dp->aux_ch;
1448
1449         switch (aux_ch) {
1450         case AUX_CH_A:
1451                 return DP_AUX_CH_CTL(aux_ch);
1452         case AUX_CH_B:
1453         case AUX_CH_C:
1454         case AUX_CH_D:
1455                 return PCH_DP_AUX_CH_CTL(aux_ch);
1456         default:
1457                 MISSING_CASE(aux_ch);
1458                 return DP_AUX_CH_CTL(AUX_CH_A);
1459         }
1460 }
1461
1462 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1463 {
1464         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1465         enum aux_ch aux_ch = intel_dp->aux_ch;
1466
1467         switch (aux_ch) {
1468         case AUX_CH_A:
1469                 return DP_AUX_CH_DATA(aux_ch, index);
1470         case AUX_CH_B:
1471         case AUX_CH_C:
1472         case AUX_CH_D:
1473                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1474         default:
1475                 MISSING_CASE(aux_ch);
1476                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1477         }
1478 }
1479
1480 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1481 {
1482         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1483         enum aux_ch aux_ch = intel_dp->aux_ch;
1484
1485         switch (aux_ch) {
1486         case AUX_CH_A:
1487         case AUX_CH_B:
1488         case AUX_CH_C:
1489         case AUX_CH_D:
1490         case AUX_CH_E:
1491         case AUX_CH_F:
1492                 return DP_AUX_CH_CTL(aux_ch);
1493         default:
1494                 MISSING_CASE(aux_ch);
1495                 return DP_AUX_CH_CTL(AUX_CH_A);
1496         }
1497 }
1498
1499 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1500 {
1501         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1502         enum aux_ch aux_ch = intel_dp->aux_ch;
1503
1504         switch (aux_ch) {
1505         case AUX_CH_A:
1506         case AUX_CH_B:
1507         case AUX_CH_C:
1508         case AUX_CH_D:
1509         case AUX_CH_E:
1510         case AUX_CH_F:
1511                 return DP_AUX_CH_DATA(aux_ch, index);
1512         default:
1513                 MISSING_CASE(aux_ch);
1514                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1515         }
1516 }
1517
1518 static void
1519 intel_dp_aux_fini(struct intel_dp *intel_dp)
1520 {
1521         kfree(intel_dp->aux.name);
1522 }
1523
1524 static void
1525 intel_dp_aux_init(struct intel_dp *intel_dp)
1526 {
1527         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1528         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1529
1530         intel_dp->aux_ch = intel_aux_ch(intel_dp);
1531         intel_dp->aux_power_domain = intel_aux_power_domain(intel_dp);
1532
1533         if (INTEL_GEN(dev_priv) >= 9) {
1534                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1535                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1536         } else if (HAS_PCH_SPLIT(dev_priv)) {
1537                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1538                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1539         } else {
1540                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1541                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1542         }
1543
1544         if (INTEL_GEN(dev_priv) >= 9)
1545                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1546         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1547                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1548         else if (HAS_PCH_SPLIT(dev_priv))
1549                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1550         else
1551                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1552
1553         if (INTEL_GEN(dev_priv) >= 9)
1554                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1555         else
1556                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1557
1558         drm_dp_aux_init(&intel_dp->aux);
1559
1560         /* Failure to allocate our preferred name is not critical */
1561         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c",
1562                                        port_name(encoder->port));
1563         intel_dp->aux.transfer = intel_dp_aux_transfer;
1564 }
1565
1566 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1567 {
1568         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1569
1570         return max_rate >= 540000;
1571 }
1572
1573 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1574 {
1575         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1576
1577         return max_rate >= 810000;
1578 }
1579
1580 static void
1581 intel_dp_set_clock(struct intel_encoder *encoder,
1582                    struct intel_crtc_state *pipe_config)
1583 {
1584         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1585         const struct dp_link_dpll *divisor = NULL;
1586         int i, count = 0;
1587
1588         if (IS_G4X(dev_priv)) {
1589                 divisor = g4x_dpll;
1590                 count = ARRAY_SIZE(g4x_dpll);
1591         } else if (HAS_PCH_SPLIT(dev_priv)) {
1592                 divisor = pch_dpll;
1593                 count = ARRAY_SIZE(pch_dpll);
1594         } else if (IS_CHERRYVIEW(dev_priv)) {
1595                 divisor = chv_dpll;
1596                 count = ARRAY_SIZE(chv_dpll);
1597         } else if (IS_VALLEYVIEW(dev_priv)) {
1598                 divisor = vlv_dpll;
1599                 count = ARRAY_SIZE(vlv_dpll);
1600         }
1601
1602         if (divisor && count) {
1603                 for (i = 0; i < count; i++) {
1604                         if (pipe_config->port_clock == divisor[i].clock) {
1605                                 pipe_config->dpll = divisor[i].dpll;
1606                                 pipe_config->clock_set = true;
1607                                 break;
1608                         }
1609                 }
1610         }
1611 }
1612
1613 static void snprintf_int_array(char *str, size_t len,
1614                                const int *array, int nelem)
1615 {
1616         int i;
1617
1618         str[0] = '\0';
1619
1620         for (i = 0; i < nelem; i++) {
1621                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1622                 if (r >= len)
1623                         return;
1624                 str += r;
1625                 len -= r;
1626         }
1627 }
1628
1629 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1630 {
1631         char str[128]; /* FIXME: too big for stack? */
1632
1633         if ((drm_debug & DRM_UT_KMS) == 0)
1634                 return;
1635
1636         snprintf_int_array(str, sizeof(str),
1637                            intel_dp->source_rates, intel_dp->num_source_rates);
1638         DRM_DEBUG_KMS("source rates: %s\n", str);
1639
1640         snprintf_int_array(str, sizeof(str),
1641                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1642         DRM_DEBUG_KMS("sink rates: %s\n", str);
1643
1644         snprintf_int_array(str, sizeof(str),
1645                            intel_dp->common_rates, intel_dp->num_common_rates);
1646         DRM_DEBUG_KMS("common rates: %s\n", str);
1647 }
1648
1649 int
1650 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1651 {
1652         int len;
1653
1654         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1655         if (WARN_ON(len <= 0))
1656                 return 162000;
1657
1658         return intel_dp->common_rates[len - 1];
1659 }
1660
1661 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1662 {
1663         int i = intel_dp_rate_index(intel_dp->sink_rates,
1664                                     intel_dp->num_sink_rates, rate);
1665
1666         if (WARN_ON(i < 0))
1667                 i = 0;
1668
1669         return i;
1670 }
1671
1672 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1673                            uint8_t *link_bw, uint8_t *rate_select)
1674 {
1675         /* eDP 1.4 rate select method. */
1676         if (intel_dp->use_rate_select) {
1677                 *link_bw = 0;
1678                 *rate_select =
1679                         intel_dp_rate_select(intel_dp, port_clock);
1680         } else {
1681                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1682                 *rate_select = 0;
1683         }
1684 }
1685
1686 struct link_config_limits {
1687         int min_clock, max_clock;
1688         int min_lane_count, max_lane_count;
1689         int min_bpp, max_bpp;
1690 };
1691
1692 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1693                                 struct intel_crtc_state *pipe_config)
1694 {
1695         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1696         struct intel_connector *intel_connector = intel_dp->attached_connector;
1697         int bpp, bpc;
1698
1699         bpp = pipe_config->pipe_bpp;
1700         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1701
1702         if (bpc > 0)
1703                 bpp = min(bpp, 3*bpc);
1704
1705         if (intel_dp_is_edp(intel_dp)) {
1706                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1707                 if (intel_connector->base.display_info.bpc == 0 &&
1708                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
1709                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1710                                       dev_priv->vbt.edp.bpp);
1711                         bpp = dev_priv->vbt.edp.bpp;
1712                 }
1713         }
1714
1715         return bpp;
1716 }
1717
1718 /* Adjust link config limits based on compliance test requests. */
1719 static void
1720 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
1721                                   struct intel_crtc_state *pipe_config,
1722                                   struct link_config_limits *limits)
1723 {
1724         /* For DP Compliance we override the computed bpp for the pipe */
1725         if (intel_dp->compliance.test_data.bpc != 0) {
1726                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
1727
1728                 limits->min_bpp = limits->max_bpp = bpp;
1729                 pipe_config->dither_force_disable = bpp == 6 * 3;
1730
1731                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
1732         }
1733
1734         /* Use values requested by Compliance Test Request */
1735         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1736                 int index;
1737
1738                 /* Validate the compliance test data since max values
1739                  * might have changed due to link train fallback.
1740                  */
1741                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
1742                                                intel_dp->compliance.test_lane_count)) {
1743                         index = intel_dp_rate_index(intel_dp->common_rates,
1744                                                     intel_dp->num_common_rates,
1745                                                     intel_dp->compliance.test_link_rate);
1746                         if (index >= 0)
1747                                 limits->min_clock = limits->max_clock = index;
1748                         limits->min_lane_count = limits->max_lane_count =
1749                                 intel_dp->compliance.test_lane_count;
1750                 }
1751         }
1752 }
1753
1754 /* Optimize link config in order: max bpp, min clock, min lanes */
1755 static bool
1756 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
1757                                   struct intel_crtc_state *pipe_config,
1758                                   const struct link_config_limits *limits)
1759 {
1760         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1761         int bpp, clock, lane_count;
1762         int mode_rate, link_clock, link_avail;
1763
1764         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
1765                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1766                                                    bpp);
1767
1768                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
1769                         for (lane_count = limits->min_lane_count;
1770                              lane_count <= limits->max_lane_count;
1771                              lane_count <<= 1) {
1772                                 link_clock = intel_dp->common_rates[clock];
1773                                 link_avail = intel_dp_max_data_rate(link_clock,
1774                                                                     lane_count);
1775
1776                                 if (mode_rate <= link_avail) {
1777                                         pipe_config->lane_count = lane_count;
1778                                         pipe_config->pipe_bpp = bpp;
1779                                         pipe_config->port_clock = link_clock;
1780
1781                                         return true;
1782                                 }
1783                         }
1784                 }
1785         }
1786
1787         return false;
1788 }
1789
1790 static bool
1791 intel_dp_compute_link_config(struct intel_encoder *encoder,
1792                              struct intel_crtc_state *pipe_config)
1793 {
1794         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1795         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1796         struct link_config_limits limits;
1797         int common_len;
1798
1799         common_len = intel_dp_common_len_rate_limit(intel_dp,
1800                                                     intel_dp->max_link_rate);
1801
1802         /* No common link rates between source and sink */
1803         WARN_ON(common_len <= 0);
1804
1805         limits.min_clock = 0;
1806         limits.max_clock = common_len - 1;
1807
1808         limits.min_lane_count = 1;
1809         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
1810
1811         limits.min_bpp = 6 * 3;
1812         limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1813
1814         if (intel_dp_is_edp(intel_dp)) {
1815                 /*
1816                  * Use the maximum clock and number of lanes the eDP panel
1817                  * advertizes being capable of. The panels are generally
1818                  * designed to support only a single clock and lane
1819                  * configuration, and typically these values correspond to the
1820                  * native resolution of the panel.
1821                  */
1822                 limits.min_lane_count = limits.max_lane_count;
1823                 limits.min_clock = limits.max_clock;
1824         }
1825
1826         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
1827
1828         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1829                       "max rate %d max bpp %d pixel clock %iKHz\n",
1830                       limits.max_lane_count,
1831                       intel_dp->common_rates[limits.max_clock],
1832                       limits.max_bpp, adjusted_mode->crtc_clock);
1833
1834         /*
1835          * Optimize for slow and wide. This is the place to add alternative
1836          * optimization policy.
1837          */
1838         if (!intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits))
1839                 return false;
1840
1841         DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n",
1842                       pipe_config->lane_count, pipe_config->port_clock,
1843                       pipe_config->pipe_bpp);
1844
1845         DRM_DEBUG_KMS("DP link rate required %i available %i\n",
1846                       intel_dp_link_required(adjusted_mode->crtc_clock,
1847                                              pipe_config->pipe_bpp),
1848                       intel_dp_max_data_rate(pipe_config->port_clock,
1849                                              pipe_config->lane_count));
1850
1851         return true;
1852 }
1853
1854 bool
1855 intel_dp_compute_config(struct intel_encoder *encoder,
1856                         struct intel_crtc_state *pipe_config,
1857                         struct drm_connector_state *conn_state)
1858 {
1859         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1860         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1861         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1862         enum port port = encoder->port;
1863         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1864         struct intel_connector *intel_connector = intel_dp->attached_connector;
1865         struct intel_digital_connector_state *intel_conn_state =
1866                 to_intel_digital_connector_state(conn_state);
1867         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1868                                            DP_DPCD_QUIRK_LIMITED_M_N);
1869
1870         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1871                 pipe_config->has_pch_encoder = true;
1872
1873         pipe_config->has_drrs = false;
1874         if (IS_G4X(dev_priv) || port == PORT_A)
1875                 pipe_config->has_audio = false;
1876         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1877                 pipe_config->has_audio = intel_dp->has_audio;
1878         else
1879                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
1880
1881         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1882                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1883                                        adjusted_mode);
1884
1885                 if (INTEL_GEN(dev_priv) >= 9) {
1886                         int ret;
1887
1888                         ret = skl_update_scaler_crtc(pipe_config);
1889                         if (ret)
1890                                 return ret;
1891                 }
1892
1893                 if (HAS_GMCH_DISPLAY(dev_priv))
1894                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1895                                                  conn_state->scaling_mode);
1896                 else
1897                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1898                                                 conn_state->scaling_mode);
1899         }
1900
1901         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1902                 return false;
1903
1904         if (HAS_GMCH_DISPLAY(dev_priv) &&
1905             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
1906                 return false;
1907
1908         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1909                 return false;
1910
1911         if (!intel_dp_compute_link_config(encoder, pipe_config))
1912                 return false;
1913
1914         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1915                 /*
1916                  * See:
1917                  * CEA-861-E - 5.1 Default Encoding Parameters
1918                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1919                  */
1920                 pipe_config->limited_color_range =
1921                         pipe_config->pipe_bpp != 18 &&
1922                         drm_default_rgb_quant_range(adjusted_mode) ==
1923                         HDMI_QUANTIZATION_RANGE_LIMITED;
1924         } else {
1925                 pipe_config->limited_color_range =
1926                         intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1927         }
1928
1929         intel_link_compute_m_n(pipe_config->pipe_bpp, pipe_config->lane_count,
1930                                adjusted_mode->crtc_clock,
1931                                pipe_config->port_clock,
1932                                &pipe_config->dp_m_n,
1933                                reduce_m_n);
1934
1935         if (intel_connector->panel.downclock_mode != NULL &&
1936                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1937                         pipe_config->has_drrs = true;
1938                         intel_link_compute_m_n(pipe_config->pipe_bpp,
1939                                                pipe_config->lane_count,
1940                                                intel_connector->panel.downclock_mode->clock,
1941                                                pipe_config->port_clock,
1942                                                &pipe_config->dp_m2_n2,
1943                                                reduce_m_n);
1944         }
1945
1946         if (!HAS_DDI(dev_priv))
1947                 intel_dp_set_clock(encoder, pipe_config);
1948
1949         intel_psr_compute_config(intel_dp, pipe_config);
1950
1951         return true;
1952 }
1953
1954 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1955                               int link_rate, uint8_t lane_count,
1956                               bool link_mst)
1957 {
1958         intel_dp->link_trained = false;
1959         intel_dp->link_rate = link_rate;
1960         intel_dp->lane_count = lane_count;
1961         intel_dp->link_mst = link_mst;
1962 }
1963
1964 static void intel_dp_prepare(struct intel_encoder *encoder,
1965                              const struct intel_crtc_state *pipe_config)
1966 {
1967         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1968         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1969         enum port port = encoder->port;
1970         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1971         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1972
1973         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1974                                  pipe_config->lane_count,
1975                                  intel_crtc_has_type(pipe_config,
1976                                                      INTEL_OUTPUT_DP_MST));
1977
1978         /*
1979          * There are four kinds of DP registers:
1980          *
1981          *      IBX PCH
1982          *      SNB CPU
1983          *      IVB CPU
1984          *      CPT PCH
1985          *
1986          * IBX PCH and CPU are the same for almost everything,
1987          * except that the CPU DP PLL is configured in this
1988          * register
1989          *
1990          * CPT PCH is quite different, having many bits moved
1991          * to the TRANS_DP_CTL register instead. That
1992          * configuration happens (oddly) in ironlake_pch_enable
1993          */
1994
1995         /* Preserve the BIOS-computed detected bit. This is
1996          * supposed to be read-only.
1997          */
1998         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1999
2000         /* Handle DP bits in common between all three register formats */
2001         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2002         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2003
2004         /* Split out the IBX/CPU vs CPT settings */
2005
2006         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2007                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2008                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2009                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2010                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2011                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2012
2013                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2014                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2015
2016                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2017         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2018                 u32 trans_dp;
2019
2020                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2021
2022                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2023                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2024                         trans_dp |= TRANS_DP_ENH_FRAMING;
2025                 else
2026                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2027                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
2028         } else {
2029                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2030                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2031
2032                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2033                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2034                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2035                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2036                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2037
2038                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2039                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2040
2041                 if (IS_CHERRYVIEW(dev_priv))
2042                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2043                 else
2044                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2045         }
2046 }
2047
2048 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2049 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2050
2051 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2052 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2053
2054 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2055 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2056
2057 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2058
2059 static void wait_panel_status(struct intel_dp *intel_dp,
2060                                        u32 mask,
2061                                        u32 value)
2062 {
2063         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2064         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2065
2066         lockdep_assert_held(&dev_priv->pps_mutex);
2067
2068         intel_pps_verify_state(intel_dp);
2069
2070         pp_stat_reg = _pp_stat_reg(intel_dp);
2071         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2072
2073         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
2074                         mask, value,
2075                         I915_READ(pp_stat_reg),
2076                         I915_READ(pp_ctrl_reg));
2077
2078         if (intel_wait_for_register(dev_priv,
2079                                     pp_stat_reg, mask, value,
2080                                     5000))
2081                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
2082                                 I915_READ(pp_stat_reg),
2083                                 I915_READ(pp_ctrl_reg));
2084
2085         DRM_DEBUG_KMS("Wait complete\n");
2086 }
2087
2088 static void wait_panel_on(struct intel_dp *intel_dp)
2089 {
2090         DRM_DEBUG_KMS("Wait for panel power on\n");
2091         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
2092 }
2093
2094 static void wait_panel_off(struct intel_dp *intel_dp)
2095 {
2096         DRM_DEBUG_KMS("Wait for panel power off time\n");
2097         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
2098 }
2099
2100 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
2101 {
2102         ktime_t panel_power_on_time;
2103         s64 panel_power_off_duration;
2104
2105         DRM_DEBUG_KMS("Wait for panel power cycle\n");
2106
2107         /* take the difference of currrent time and panel power off time
2108          * and then make panel wait for t11_t12 if needed. */
2109         panel_power_on_time = ktime_get_boottime();
2110         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
2111
2112         /* When we disable the VDD override bit last we have to do the manual
2113          * wait. */
2114         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
2115                 wait_remaining_ms_from_jiffies(jiffies,
2116                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
2117
2118         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
2119 }
2120
2121 static void wait_backlight_on(struct intel_dp *intel_dp)
2122 {
2123         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
2124                                        intel_dp->backlight_on_delay);
2125 }
2126
2127 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
2128 {
2129         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
2130                                        intel_dp->backlight_off_delay);
2131 }
2132
2133 /* Read the current pp_control value, unlocking the register if it
2134  * is locked
2135  */
2136
2137 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2138 {
2139         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2140         u32 control;
2141
2142         lockdep_assert_held(&dev_priv->pps_mutex);
2143
2144         control = I915_READ(_pp_ctrl_reg(intel_dp));
2145         if (WARN_ON(!HAS_DDI(dev_priv) &&
2146                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2147                 control &= ~PANEL_UNLOCK_MASK;
2148                 control |= PANEL_UNLOCK_REGS;
2149         }
2150         return control;
2151 }
2152
2153 /*
2154  * Must be paired with edp_panel_vdd_off().
2155  * Must hold pps_mutex around the whole on/off sequence.
2156  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2157  */
2158 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2159 {
2160         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2161         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2162         u32 pp;
2163         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2164         bool need_to_disable = !intel_dp->want_panel_vdd;
2165
2166         lockdep_assert_held(&dev_priv->pps_mutex);
2167
2168         if (!intel_dp_is_edp(intel_dp))
2169                 return false;
2170
2171         cancel_delayed_work(&intel_dp->panel_vdd_work);
2172         intel_dp->want_panel_vdd = true;
2173
2174         if (edp_have_panel_vdd(intel_dp))
2175                 return need_to_disable;
2176
2177         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2178
2179         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2180                       port_name(intel_dig_port->base.port));
2181
2182         if (!edp_have_panel_power(intel_dp))
2183                 wait_panel_power_cycle(intel_dp);
2184
2185         pp = ironlake_get_pp_control(intel_dp);
2186         pp |= EDP_FORCE_VDD;
2187
2188         pp_stat_reg = _pp_stat_reg(intel_dp);
2189         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2190
2191         I915_WRITE(pp_ctrl_reg, pp);
2192         POSTING_READ(pp_ctrl_reg);
2193         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2194                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2195         /*
2196          * If the panel wasn't on, delay before accessing aux channel
2197          */
2198         if (!edp_have_panel_power(intel_dp)) {
2199                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2200                               port_name(intel_dig_port->base.port));
2201                 msleep(intel_dp->panel_power_up_delay);
2202         }
2203
2204         return need_to_disable;
2205 }
2206
2207 /*
2208  * Must be paired with intel_edp_panel_vdd_off() or
2209  * intel_edp_panel_off().
2210  * Nested calls to these functions are not allowed since
2211  * we drop the lock. Caller must use some higher level
2212  * locking to prevent nested calls from other threads.
2213  */
2214 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2215 {
2216         bool vdd;
2217
2218         if (!intel_dp_is_edp(intel_dp))
2219                 return;
2220
2221         pps_lock(intel_dp);
2222         vdd = edp_panel_vdd_on(intel_dp);
2223         pps_unlock(intel_dp);
2224
2225         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2226              port_name(dp_to_dig_port(intel_dp)->base.port));
2227 }
2228
2229 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2230 {
2231         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2232         struct intel_digital_port *intel_dig_port =
2233                 dp_to_dig_port(intel_dp);
2234         u32 pp;
2235         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2236
2237         lockdep_assert_held(&dev_priv->pps_mutex);
2238
2239         WARN_ON(intel_dp->want_panel_vdd);
2240
2241         if (!edp_have_panel_vdd(intel_dp))
2242                 return;
2243
2244         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2245                       port_name(intel_dig_port->base.port));
2246
2247         pp = ironlake_get_pp_control(intel_dp);
2248         pp &= ~EDP_FORCE_VDD;
2249
2250         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2251         pp_stat_reg = _pp_stat_reg(intel_dp);
2252
2253         I915_WRITE(pp_ctrl_reg, pp);
2254         POSTING_READ(pp_ctrl_reg);
2255
2256         /* Make sure sequencer is idle before allowing subsequent activity */
2257         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2258         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2259
2260         if ((pp & PANEL_POWER_ON) == 0)
2261                 intel_dp->panel_power_off_time = ktime_get_boottime();
2262
2263         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2264 }
2265
2266 static void edp_panel_vdd_work(struct work_struct *__work)
2267 {
2268         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2269                                                  struct intel_dp, panel_vdd_work);
2270
2271         pps_lock(intel_dp);
2272         if (!intel_dp->want_panel_vdd)
2273                 edp_panel_vdd_off_sync(intel_dp);
2274         pps_unlock(intel_dp);
2275 }
2276
2277 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2278 {
2279         unsigned long delay;
2280
2281         /*
2282          * Queue the timer to fire a long time from now (relative to the power
2283          * down delay) to keep the panel power up across a sequence of
2284          * operations.
2285          */
2286         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2287         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2288 }
2289
2290 /*
2291  * Must be paired with edp_panel_vdd_on().
2292  * Must hold pps_mutex around the whole on/off sequence.
2293  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2294  */
2295 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2296 {
2297         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2298
2299         lockdep_assert_held(&dev_priv->pps_mutex);
2300
2301         if (!intel_dp_is_edp(intel_dp))
2302                 return;
2303
2304         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2305              port_name(dp_to_dig_port(intel_dp)->base.port));
2306
2307         intel_dp->want_panel_vdd = false;
2308
2309         if (sync)
2310                 edp_panel_vdd_off_sync(intel_dp);
2311         else
2312                 edp_panel_vdd_schedule_off(intel_dp);
2313 }
2314
2315 static void edp_panel_on(struct intel_dp *intel_dp)
2316 {
2317         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2318         u32 pp;
2319         i915_reg_t pp_ctrl_reg;
2320
2321         lockdep_assert_held(&dev_priv->pps_mutex);
2322
2323         if (!intel_dp_is_edp(intel_dp))
2324                 return;
2325
2326         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2327                       port_name(dp_to_dig_port(intel_dp)->base.port));
2328
2329         if (WARN(edp_have_panel_power(intel_dp),
2330                  "eDP port %c panel power already on\n",
2331                  port_name(dp_to_dig_port(intel_dp)->base.port)))
2332                 return;
2333
2334         wait_panel_power_cycle(intel_dp);
2335
2336         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2337         pp = ironlake_get_pp_control(intel_dp);
2338         if (IS_GEN5(dev_priv)) {
2339                 /* ILK workaround: disable reset around power sequence */
2340                 pp &= ~PANEL_POWER_RESET;
2341                 I915_WRITE(pp_ctrl_reg, pp);
2342                 POSTING_READ(pp_ctrl_reg);
2343         }
2344
2345         pp |= PANEL_POWER_ON;
2346         if (!IS_GEN5(dev_priv))
2347                 pp |= PANEL_POWER_RESET;
2348
2349         I915_WRITE(pp_ctrl_reg, pp);
2350         POSTING_READ(pp_ctrl_reg);
2351
2352         wait_panel_on(intel_dp);
2353         intel_dp->last_power_on = jiffies;
2354
2355         if (IS_GEN5(dev_priv)) {
2356                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2357                 I915_WRITE(pp_ctrl_reg, pp);
2358                 POSTING_READ(pp_ctrl_reg);
2359         }
2360 }
2361
2362 void intel_edp_panel_on(struct intel_dp *intel_dp)
2363 {
2364         if (!intel_dp_is_edp(intel_dp))
2365                 return;
2366
2367         pps_lock(intel_dp);
2368         edp_panel_on(intel_dp);
2369         pps_unlock(intel_dp);
2370 }
2371
2372
2373 static void edp_panel_off(struct intel_dp *intel_dp)
2374 {
2375         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2376         u32 pp;
2377         i915_reg_t pp_ctrl_reg;
2378
2379         lockdep_assert_held(&dev_priv->pps_mutex);
2380
2381         if (!intel_dp_is_edp(intel_dp))
2382                 return;
2383
2384         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2385                       port_name(dp_to_dig_port(intel_dp)->base.port));
2386
2387         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2388              port_name(dp_to_dig_port(intel_dp)->base.port));
2389
2390         pp = ironlake_get_pp_control(intel_dp);
2391         /* We need to switch off panel power _and_ force vdd, for otherwise some
2392          * panels get very unhappy and cease to work. */
2393         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2394                 EDP_BLC_ENABLE);
2395
2396         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2397
2398         intel_dp->want_panel_vdd = false;
2399
2400         I915_WRITE(pp_ctrl_reg, pp);
2401         POSTING_READ(pp_ctrl_reg);
2402
2403         wait_panel_off(intel_dp);
2404         intel_dp->panel_power_off_time = ktime_get_boottime();
2405
2406         /* We got a reference when we enabled the VDD. */
2407         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2408 }
2409
2410 void intel_edp_panel_off(struct intel_dp *intel_dp)
2411 {
2412         if (!intel_dp_is_edp(intel_dp))
2413                 return;
2414
2415         pps_lock(intel_dp);
2416         edp_panel_off(intel_dp);
2417         pps_unlock(intel_dp);
2418 }
2419
2420 /* Enable backlight in the panel power control. */
2421 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2422 {
2423         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2424         u32 pp;
2425         i915_reg_t pp_ctrl_reg;
2426
2427         /*
2428          * If we enable the backlight right away following a panel power
2429          * on, we may see slight flicker as the panel syncs with the eDP
2430          * link.  So delay a bit to make sure the image is solid before
2431          * allowing it to appear.
2432          */
2433         wait_backlight_on(intel_dp);
2434
2435         pps_lock(intel_dp);
2436
2437         pp = ironlake_get_pp_control(intel_dp);
2438         pp |= EDP_BLC_ENABLE;
2439
2440         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2441
2442         I915_WRITE(pp_ctrl_reg, pp);
2443         POSTING_READ(pp_ctrl_reg);
2444
2445         pps_unlock(intel_dp);
2446 }
2447
2448 /* Enable backlight PWM and backlight PP control. */
2449 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
2450                             const struct drm_connector_state *conn_state)
2451 {
2452         struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder);
2453
2454         if (!intel_dp_is_edp(intel_dp))
2455                 return;
2456
2457         DRM_DEBUG_KMS("\n");
2458
2459         intel_panel_enable_backlight(crtc_state, conn_state);
2460         _intel_edp_backlight_on(intel_dp);
2461 }
2462
2463 /* Disable backlight in the panel power control. */
2464 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2465 {
2466         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2467         u32 pp;
2468         i915_reg_t pp_ctrl_reg;
2469
2470         if (!intel_dp_is_edp(intel_dp))
2471                 return;
2472
2473         pps_lock(intel_dp);
2474
2475         pp = ironlake_get_pp_control(intel_dp);
2476         pp &= ~EDP_BLC_ENABLE;
2477
2478         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2479
2480         I915_WRITE(pp_ctrl_reg, pp);
2481         POSTING_READ(pp_ctrl_reg);
2482
2483         pps_unlock(intel_dp);
2484
2485         intel_dp->last_backlight_off = jiffies;
2486         edp_wait_backlight_off(intel_dp);
2487 }
2488
2489 /* Disable backlight PP control and backlight PWM. */
2490 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
2491 {
2492         struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder);
2493
2494         if (!intel_dp_is_edp(intel_dp))
2495                 return;
2496
2497         DRM_DEBUG_KMS("\n");
2498
2499         _intel_edp_backlight_off(intel_dp);
2500         intel_panel_disable_backlight(old_conn_state);
2501 }
2502
2503 /*
2504  * Hook for controlling the panel power control backlight through the bl_power
2505  * sysfs attribute. Take care to handle multiple calls.
2506  */
2507 static void intel_edp_backlight_power(struct intel_connector *connector,
2508                                       bool enable)
2509 {
2510         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2511         bool is_enabled;
2512
2513         pps_lock(intel_dp);
2514         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2515         pps_unlock(intel_dp);
2516
2517         if (is_enabled == enable)
2518                 return;
2519
2520         DRM_DEBUG_KMS("panel power control backlight %s\n",
2521                       enable ? "enable" : "disable");
2522
2523         if (enable)
2524                 _intel_edp_backlight_on(intel_dp);
2525         else
2526                 _intel_edp_backlight_off(intel_dp);
2527 }
2528
2529 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2530 {
2531         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2532         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2533         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2534
2535         I915_STATE_WARN(cur_state != state,
2536                         "DP port %c state assertion failure (expected %s, current %s)\n",
2537                         port_name(dig_port->base.port),
2538                         onoff(state), onoff(cur_state));
2539 }
2540 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2541
2542 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2543 {
2544         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2545
2546         I915_STATE_WARN(cur_state != state,
2547                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2548                         onoff(state), onoff(cur_state));
2549 }
2550 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2551 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2552
2553 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2554                                 const struct intel_crtc_state *pipe_config)
2555 {
2556         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2557         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2558
2559         assert_pipe_disabled(dev_priv, crtc->pipe);
2560         assert_dp_port_disabled(intel_dp);
2561         assert_edp_pll_disabled(dev_priv);
2562
2563         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2564                       pipe_config->port_clock);
2565
2566         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2567
2568         if (pipe_config->port_clock == 162000)
2569                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2570         else
2571                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2572
2573         I915_WRITE(DP_A, intel_dp->DP);
2574         POSTING_READ(DP_A);
2575         udelay(500);
2576
2577         /*
2578          * [DevILK] Work around required when enabling DP PLL
2579          * while a pipe is enabled going to FDI:
2580          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2581          * 2. Program DP PLL enable
2582          */
2583         if (IS_GEN5(dev_priv))
2584                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2585
2586         intel_dp->DP |= DP_PLL_ENABLE;
2587
2588         I915_WRITE(DP_A, intel_dp->DP);
2589         POSTING_READ(DP_A);
2590         udelay(200);
2591 }
2592
2593 static void ironlake_edp_pll_off(struct intel_dp *intel_dp,
2594                                  const struct intel_crtc_state *old_crtc_state)
2595 {
2596         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
2597         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2598
2599         assert_pipe_disabled(dev_priv, crtc->pipe);
2600         assert_dp_port_disabled(intel_dp);
2601         assert_edp_pll_enabled(dev_priv);
2602
2603         DRM_DEBUG_KMS("disabling eDP PLL\n");
2604
2605         intel_dp->DP &= ~DP_PLL_ENABLE;
2606
2607         I915_WRITE(DP_A, intel_dp->DP);
2608         POSTING_READ(DP_A);
2609         udelay(200);
2610 }
2611
2612 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
2613 {
2614         /*
2615          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
2616          * be capable of signalling downstream hpd with a long pulse.
2617          * Whether or not that means D3 is safe to use is not clear,
2618          * but let's assume so until proven otherwise.
2619          *
2620          * FIXME should really check all downstream ports...
2621          */
2622         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
2623                 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
2624                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
2625 }
2626
2627 /* If the sink supports it, try to set the power state appropriately */
2628 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2629 {
2630         int ret, i;
2631
2632         /* Should have a valid DPCD by this point */
2633         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2634                 return;
2635
2636         if (mode != DRM_MODE_DPMS_ON) {
2637                 if (downstream_hpd_needs_d0(intel_dp))
2638                         return;
2639
2640                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2641                                          DP_SET_POWER_D3);
2642         } else {
2643                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2644
2645                 /*
2646                  * When turning on, we need to retry for 1ms to give the sink
2647                  * time to wake up.
2648                  */
2649                 for (i = 0; i < 3; i++) {
2650                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2651                                                  DP_SET_POWER_D0);
2652                         if (ret == 1)
2653                                 break;
2654                         msleep(1);
2655                 }
2656
2657                 if (ret == 1 && lspcon->active)
2658                         lspcon_wait_pcon_mode(lspcon);
2659         }
2660
2661         if (ret != 1)
2662                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2663                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2664 }
2665
2666 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
2667                                  enum port port, enum pipe *pipe)
2668 {
2669         enum pipe p;
2670
2671         for_each_pipe(dev_priv, p) {
2672                 u32 val = I915_READ(TRANS_DP_CTL(p));
2673
2674                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
2675                         *pipe = p;
2676                         return true;
2677                 }
2678         }
2679
2680         DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port));
2681
2682         /* must initialize pipe to something for the asserts */
2683         *pipe = PIPE_A;
2684
2685         return false;
2686 }
2687
2688 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
2689                            i915_reg_t dp_reg, enum port port,
2690                            enum pipe *pipe)
2691 {
2692         bool ret;
2693         u32 val;
2694
2695         val = I915_READ(dp_reg);
2696
2697         ret = val & DP_PORT_EN;
2698
2699         /* asserts want to know the pipe even if the port is disabled */
2700         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
2701                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
2702         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
2703                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
2704         else if (IS_CHERRYVIEW(dev_priv))
2705                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
2706         else
2707                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
2708
2709         return ret;
2710 }
2711
2712 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2713                                   enum pipe *pipe)
2714 {
2715         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2716         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2717         bool ret;
2718
2719         if (!intel_display_power_get_if_enabled(dev_priv,
2720                                                 encoder->power_domain))
2721                 return false;
2722
2723         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
2724                                     encoder->port, pipe);
2725
2726         intel_display_power_put(dev_priv, encoder->power_domain);
2727
2728         return ret;
2729 }
2730
2731 static void intel_dp_get_config(struct intel_encoder *encoder,
2732                                 struct intel_crtc_state *pipe_config)
2733 {
2734         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2735         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2736         u32 tmp, flags = 0;
2737         enum port port = encoder->port;
2738         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2739
2740         if (encoder->type == INTEL_OUTPUT_EDP)
2741                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
2742         else
2743                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
2744
2745         tmp = I915_READ(intel_dp->output_reg);
2746
2747         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2748
2749         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2750                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2751
2752                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2753                         flags |= DRM_MODE_FLAG_PHSYNC;
2754                 else
2755                         flags |= DRM_MODE_FLAG_NHSYNC;
2756
2757                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2758                         flags |= DRM_MODE_FLAG_PVSYNC;
2759                 else
2760                         flags |= DRM_MODE_FLAG_NVSYNC;
2761         } else {
2762                 if (tmp & DP_SYNC_HS_HIGH)
2763                         flags |= DRM_MODE_FLAG_PHSYNC;
2764                 else
2765                         flags |= DRM_MODE_FLAG_NHSYNC;
2766
2767                 if (tmp & DP_SYNC_VS_HIGH)
2768                         flags |= DRM_MODE_FLAG_PVSYNC;
2769                 else
2770                         flags |= DRM_MODE_FLAG_NVSYNC;
2771         }
2772
2773         pipe_config->base.adjusted_mode.flags |= flags;
2774
2775         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2776                 pipe_config->limited_color_range = true;
2777
2778         pipe_config->lane_count =
2779                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2780
2781         intel_dp_get_m_n(crtc, pipe_config);
2782
2783         if (port == PORT_A) {
2784                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2785                         pipe_config->port_clock = 162000;
2786                 else
2787                         pipe_config->port_clock = 270000;
2788         }
2789
2790         pipe_config->base.adjusted_mode.crtc_clock =
2791                 intel_dotclock_calculate(pipe_config->port_clock,
2792                                          &pipe_config->dp_m_n);
2793
2794         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2795             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2796                 /*
2797                  * This is a big fat ugly hack.
2798                  *
2799                  * Some machines in UEFI boot mode provide us a VBT that has 18
2800                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2801                  * unknown we fail to light up. Yet the same BIOS boots up with
2802                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2803                  * max, not what it tells us to use.
2804                  *
2805                  * Note: This will still be broken if the eDP panel is not lit
2806                  * up by the BIOS, and thus we can't get the mode at module
2807                  * load.
2808                  */
2809                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2810                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2811                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2812         }
2813 }
2814
2815 static void intel_disable_dp(struct intel_encoder *encoder,
2816                              const struct intel_crtc_state *old_crtc_state,
2817                              const struct drm_connector_state *old_conn_state)
2818 {
2819         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2820
2821         intel_dp->link_trained = false;
2822
2823         if (old_crtc_state->has_audio)
2824                 intel_audio_codec_disable(encoder,
2825                                           old_crtc_state, old_conn_state);
2826
2827         /* Make sure the panel is off before trying to change the mode. But also
2828          * ensure that we have vdd while we switch off the panel. */
2829         intel_edp_panel_vdd_on(intel_dp);
2830         intel_edp_backlight_off(old_conn_state);
2831         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2832         intel_edp_panel_off(intel_dp);
2833 }
2834
2835 static void g4x_disable_dp(struct intel_encoder *encoder,
2836                            const struct intel_crtc_state *old_crtc_state,
2837                            const struct drm_connector_state *old_conn_state)
2838 {
2839         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2840 }
2841
2842 static void vlv_disable_dp(struct intel_encoder *encoder,
2843                            const struct intel_crtc_state *old_crtc_state,
2844                            const struct drm_connector_state *old_conn_state)
2845 {
2846         intel_disable_dp(encoder, old_crtc_state, old_conn_state);
2847 }
2848
2849 static void g4x_post_disable_dp(struct intel_encoder *encoder,
2850                                 const struct intel_crtc_state *old_crtc_state,
2851                                 const struct drm_connector_state *old_conn_state)
2852 {
2853         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2854         enum port port = encoder->port;
2855
2856         /*
2857          * Bspec does not list a specific disable sequence for g4x DP.
2858          * Follow the ilk+ sequence (disable pipe before the port) for
2859          * g4x DP as it does not suffer from underruns like the normal
2860          * g4x modeset sequence (disable pipe after the port).
2861          */
2862         intel_dp_link_down(encoder, old_crtc_state);
2863
2864         /* Only ilk+ has port A */
2865         if (port == PORT_A)
2866                 ironlake_edp_pll_off(intel_dp, old_crtc_state);
2867 }
2868
2869 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2870                                 const struct intel_crtc_state *old_crtc_state,
2871                                 const struct drm_connector_state *old_conn_state)
2872 {
2873         intel_dp_link_down(encoder, old_crtc_state);
2874 }
2875
2876 static void chv_post_disable_dp(struct intel_encoder *encoder,
2877                                 const struct intel_crtc_state *old_crtc_state,
2878                                 const struct drm_connector_state *old_conn_state)
2879 {
2880         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2881
2882         intel_dp_link_down(encoder, old_crtc_state);
2883
2884         mutex_lock(&dev_priv->sb_lock);
2885
2886         /* Assert data lane reset */
2887         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2888
2889         mutex_unlock(&dev_priv->sb_lock);
2890 }
2891
2892 static void
2893 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2894                          uint32_t *DP,
2895                          uint8_t dp_train_pat)
2896 {
2897         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2898         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2899         enum port port = intel_dig_port->base.port;
2900         uint8_t train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
2901
2902         if (dp_train_pat & train_pat_mask)
2903                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2904                               dp_train_pat & train_pat_mask);
2905
2906         if (HAS_DDI(dev_priv)) {
2907                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2908
2909                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2910                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2911                 else
2912                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2913
2914                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2915                 switch (dp_train_pat & train_pat_mask) {
2916                 case DP_TRAINING_PATTERN_DISABLE:
2917                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2918
2919                         break;
2920                 case DP_TRAINING_PATTERN_1:
2921                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2922                         break;
2923                 case DP_TRAINING_PATTERN_2:
2924                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2925                         break;
2926                 case DP_TRAINING_PATTERN_3:
2927                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2928                         break;
2929                 case DP_TRAINING_PATTERN_4:
2930                         temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
2931                         break;
2932                 }
2933                 I915_WRITE(DP_TP_CTL(port), temp);
2934
2935         } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
2936                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2937                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2938
2939                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2940                 case DP_TRAINING_PATTERN_DISABLE:
2941                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2942                         break;
2943                 case DP_TRAINING_PATTERN_1:
2944                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2945                         break;
2946                 case DP_TRAINING_PATTERN_2:
2947                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2948                         break;
2949                 case DP_TRAINING_PATTERN_3:
2950                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2951                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2952                         break;
2953                 }
2954
2955         } else {
2956                 *DP &= ~DP_LINK_TRAIN_MASK;
2957
2958                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2959                 case DP_TRAINING_PATTERN_DISABLE:
2960                         *DP |= DP_LINK_TRAIN_OFF;
2961                         break;
2962                 case DP_TRAINING_PATTERN_1:
2963                         *DP |= DP_LINK_TRAIN_PAT_1;
2964                         break;
2965                 case DP_TRAINING_PATTERN_2:
2966                         *DP |= DP_LINK_TRAIN_PAT_2;
2967                         break;
2968                 case DP_TRAINING_PATTERN_3:
2969                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2970                         *DP |= DP_LINK_TRAIN_PAT_2;
2971                         break;
2972                 }
2973         }
2974 }
2975
2976 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2977                                  const struct intel_crtc_state *old_crtc_state)
2978 {
2979         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2980
2981         /* enable with pattern 1 (as per spec) */
2982
2983         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2984
2985         /*
2986          * Magic for VLV/CHV. We _must_ first set up the register
2987          * without actually enabling the port, and then do another
2988          * write to enable the port. Otherwise link training will
2989          * fail when the power sequencer is freshly used for this port.
2990          */
2991         intel_dp->DP |= DP_PORT_EN;
2992         if (old_crtc_state->has_audio)
2993                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2994
2995         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2996         POSTING_READ(intel_dp->output_reg);
2997 }
2998
2999 static void intel_enable_dp(struct intel_encoder *encoder,
3000                             const struct intel_crtc_state *pipe_config,
3001                             const struct drm_connector_state *conn_state)
3002 {
3003         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3004         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3005         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
3006         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
3007         enum pipe pipe = crtc->pipe;
3008
3009         if (WARN_ON(dp_reg & DP_PORT_EN))
3010                 return;
3011
3012         pps_lock(intel_dp);
3013
3014         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3015                 vlv_init_panel_power_sequencer(encoder, pipe_config);
3016
3017         intel_dp_enable_port(intel_dp, pipe_config);
3018
3019         edp_panel_vdd_on(intel_dp);
3020         edp_panel_on(intel_dp);
3021         edp_panel_vdd_off(intel_dp, true);
3022
3023         pps_unlock(intel_dp);
3024
3025         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3026                 unsigned int lane_mask = 0x0;
3027
3028                 if (IS_CHERRYVIEW(dev_priv))
3029                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
3030
3031                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
3032                                     lane_mask);
3033         }
3034
3035         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3036         intel_dp_start_link_train(intel_dp);
3037         intel_dp_stop_link_train(intel_dp);
3038
3039         if (pipe_config->has_audio) {
3040                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
3041                                  pipe_name(pipe));
3042                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
3043         }
3044 }
3045
3046 static void g4x_enable_dp(struct intel_encoder *encoder,
3047                           const struct intel_crtc_state *pipe_config,
3048                           const struct drm_connector_state *conn_state)
3049 {
3050         intel_enable_dp(encoder, pipe_config, conn_state);
3051         intel_edp_backlight_on(pipe_config, conn_state);
3052 }
3053
3054 static void vlv_enable_dp(struct intel_encoder *encoder,
3055                           const struct intel_crtc_state *pipe_config,
3056                           const struct drm_connector_state *conn_state)
3057 {
3058         intel_edp_backlight_on(pipe_config, conn_state);
3059 }
3060
3061 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
3062                               const struct intel_crtc_state *pipe_config,
3063                               const struct drm_connector_state *conn_state)
3064 {
3065         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3066         enum port port = encoder->port;
3067
3068         intel_dp_prepare(encoder, pipe_config);
3069
3070         /* Only ilk+ has port A */
3071         if (port == PORT_A)
3072                 ironlake_edp_pll_on(intel_dp, pipe_config);
3073 }
3074
3075 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
3076 {
3077         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3078         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
3079         enum pipe pipe = intel_dp->pps_pipe;
3080         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
3081
3082         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3083
3084         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
3085                 return;
3086
3087         edp_panel_vdd_off_sync(intel_dp);
3088
3089         /*
3090          * VLV seems to get confused when multiple power sequencers
3091          * have the same port selected (even if only one has power/vdd
3092          * enabled). The failure manifests as vlv_wait_port_ready() failing
3093          * CHV on the other hand doesn't seem to mind having the same port
3094          * selected in multiple power sequencers, but let's clear the
3095          * port select always when logically disconnecting a power sequencer
3096          * from a port.
3097          */
3098         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
3099                       pipe_name(pipe), port_name(intel_dig_port->base.port));
3100         I915_WRITE(pp_on_reg, 0);
3101         POSTING_READ(pp_on_reg);
3102
3103         intel_dp->pps_pipe = INVALID_PIPE;
3104 }
3105
3106 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
3107                                       enum pipe pipe)
3108 {
3109         struct intel_encoder *encoder;
3110
3111         lockdep_assert_held(&dev_priv->pps_mutex);
3112
3113         for_each_intel_dp(&dev_priv->drm, encoder) {
3114                 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3115                 enum port port = encoder->port;
3116
3117                 WARN(intel_dp->active_pipe == pipe,
3118                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
3119                      pipe_name(pipe), port_name(port));
3120
3121                 if (intel_dp->pps_pipe != pipe)
3122                         continue;
3123
3124                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
3125                               pipe_name(pipe), port_name(port));
3126
3127                 /* make sure vdd is off before we steal it */
3128                 vlv_detach_power_sequencer(intel_dp);
3129         }
3130 }
3131
3132 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
3133                                            const struct intel_crtc_state *crtc_state)
3134 {
3135         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3136         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3137         struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
3138
3139         lockdep_assert_held(&dev_priv->pps_mutex);
3140
3141         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
3142
3143         if (intel_dp->pps_pipe != INVALID_PIPE &&
3144             intel_dp->pps_pipe != crtc->pipe) {
3145                 /*
3146                  * If another power sequencer was being used on this
3147                  * port previously make sure to turn off vdd there while
3148                  * we still have control of it.
3149                  */
3150                 vlv_detach_power_sequencer(intel_dp);
3151         }
3152
3153         /*
3154          * We may be stealing the power
3155          * sequencer from another port.
3156          */
3157         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
3158
3159         intel_dp->active_pipe = crtc->pipe;
3160
3161         if (!intel_dp_is_edp(intel_dp))
3162                 return;
3163
3164         /* now it's all ours */
3165         intel_dp->pps_pipe = crtc->pipe;
3166
3167         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3168                       pipe_name(intel_dp->pps_pipe), port_name(encoder->port));
3169
3170         /* init power sequencer on this pipe and port */
3171         intel_dp_init_panel_power_sequencer(intel_dp);
3172         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
3173 }
3174
3175 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3176                               const struct intel_crtc_state *pipe_config,
3177                               const struct drm_connector_state *conn_state)
3178 {
3179         vlv_phy_pre_encoder_enable(encoder, pipe_config);
3180
3181         intel_enable_dp(encoder, pipe_config, conn_state);
3182 }
3183
3184 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3185                                   const struct intel_crtc_state *pipe_config,
3186                                   const struct drm_connector_state *conn_state)
3187 {
3188         intel_dp_prepare(encoder, pipe_config);
3189
3190         vlv_phy_pre_pll_enable(encoder, pipe_config);
3191 }
3192
3193 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3194                               const struct intel_crtc_state *pipe_config,
3195                               const struct drm_connector_state *conn_state)
3196 {
3197         chv_phy_pre_encoder_enable(encoder, pipe_config);
3198
3199         intel_enable_dp(encoder, pipe_config, conn_state);
3200
3201         /* Second common lane will stay alive on its own now */
3202         chv_phy_release_cl2_override(encoder);
3203 }
3204
3205 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3206                                   const struct intel_crtc_state *pipe_config,
3207                                   const struct drm_connector_state *conn_state)
3208 {
3209         intel_dp_prepare(encoder, pipe_config);
3210
3211         chv_phy_pre_pll_enable(encoder, pipe_config);
3212 }
3213
3214 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3215                                     const struct intel_crtc_state *old_crtc_state,
3216                                     const struct drm_connector_state *old_conn_state)
3217 {
3218         chv_phy_post_pll_disable(encoder, old_crtc_state);
3219 }
3220
3221 /*
3222  * Fetch AUX CH registers 0x202 - 0x207 which contain
3223  * link status information
3224  */
3225 bool
3226 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3227 {
3228         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3229                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3230 }
3231
3232 /* These are source-specific values. */
3233 uint8_t
3234 intel_dp_voltage_max(struct intel_dp *intel_dp)
3235 {
3236         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3237         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3238         enum port port = encoder->port;
3239
3240         if (HAS_DDI(dev_priv))
3241                 return intel_ddi_dp_voltage_max(encoder);
3242         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3243                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3244         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3245                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3246         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3247                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3248         else
3249                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3250 }
3251
3252 uint8_t
3253 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3254 {
3255         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3256         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3257         enum port port = encoder->port;
3258
3259         if (HAS_DDI(dev_priv)) {
3260                 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing);
3261         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3262                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3263                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3264                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3265                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3266                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3267                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3268                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3269                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3270                 default:
3271                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3272                 }
3273         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3274                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3275                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3276                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3277                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3278                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3279                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3280                 default:
3281                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3282                 }
3283         } else {
3284                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3285                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3286                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3287                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3288                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3289                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3290                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3291                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3292                 default:
3293                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3294                 }
3295         }
3296 }
3297
3298 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3299 {
3300         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3301         unsigned long demph_reg_value, preemph_reg_value,
3302                 uniqtranscale_reg_value;
3303         uint8_t train_set = intel_dp->train_set[0];
3304
3305         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3306         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3307                 preemph_reg_value = 0x0004000;
3308                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3309                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3310                         demph_reg_value = 0x2B405555;
3311                         uniqtranscale_reg_value = 0x552AB83A;
3312                         break;
3313                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3314                         demph_reg_value = 0x2B404040;
3315                         uniqtranscale_reg_value = 0x5548B83A;
3316                         break;
3317                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3318                         demph_reg_value = 0x2B245555;
3319                         uniqtranscale_reg_value = 0x5560B83A;
3320                         break;
3321                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3322                         demph_reg_value = 0x2B405555;
3323                         uniqtranscale_reg_value = 0x5598DA3A;
3324                         break;
3325                 default:
3326                         return 0;
3327                 }
3328                 break;
3329         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3330                 preemph_reg_value = 0x0002000;
3331                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3332                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3333                         demph_reg_value = 0x2B404040;
3334                         uniqtranscale_reg_value = 0x5552B83A;
3335                         break;
3336                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3337                         demph_reg_value = 0x2B404848;
3338                         uniqtranscale_reg_value = 0x5580B83A;
3339                         break;
3340                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3341                         demph_reg_value = 0x2B404040;
3342                         uniqtranscale_reg_value = 0x55ADDA3A;
3343                         break;
3344                 default:
3345                         return 0;
3346                 }
3347                 break;
3348         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3349                 preemph_reg_value = 0x0000000;
3350                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3351                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3352                         demph_reg_value = 0x2B305555;
3353                         uniqtranscale_reg_value = 0x5570B83A;
3354                         break;
3355                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3356                         demph_reg_value = 0x2B2B4040;
3357                         uniqtranscale_reg_value = 0x55ADDA3A;
3358                         break;
3359                 default:
3360                         return 0;
3361                 }
3362                 break;
3363         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3364                 preemph_reg_value = 0x0006000;
3365                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3366                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3367                         demph_reg_value = 0x1B405555;
3368                         uniqtranscale_reg_value = 0x55ADDA3A;
3369                         break;
3370                 default:
3371                         return 0;
3372                 }
3373                 break;
3374         default:
3375                 return 0;
3376         }
3377
3378         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3379                                  uniqtranscale_reg_value, 0);
3380
3381         return 0;
3382 }
3383
3384 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3385 {
3386         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3387         u32 deemph_reg_value, margin_reg_value;
3388         bool uniq_trans_scale = false;
3389         uint8_t train_set = intel_dp->train_set[0];
3390
3391         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3392         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3393                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3394                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3395                         deemph_reg_value = 128;
3396                         margin_reg_value = 52;
3397                         break;
3398                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3399                         deemph_reg_value = 128;
3400                         margin_reg_value = 77;
3401                         break;
3402                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3403                         deemph_reg_value = 128;
3404                         margin_reg_value = 102;
3405                         break;
3406                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3407                         deemph_reg_value = 128;
3408                         margin_reg_value = 154;
3409                         uniq_trans_scale = true;
3410                         break;
3411                 default:
3412                         return 0;
3413                 }
3414                 break;
3415         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3416                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3417                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3418                         deemph_reg_value = 85;
3419                         margin_reg_value = 78;
3420                         break;
3421                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3422                         deemph_reg_value = 85;
3423                         margin_reg_value = 116;
3424                         break;
3425                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3426                         deemph_reg_value = 85;
3427                         margin_reg_value = 154;
3428                         break;
3429                 default:
3430                         return 0;
3431                 }
3432                 break;
3433         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3434                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3435                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3436                         deemph_reg_value = 64;
3437                         margin_reg_value = 104;
3438                         break;
3439                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3440                         deemph_reg_value = 64;
3441                         margin_reg_value = 154;
3442                         break;
3443                 default:
3444                         return 0;
3445                 }
3446                 break;
3447         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3448                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3449                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3450                         deemph_reg_value = 43;
3451                         margin_reg_value = 154;
3452                         break;
3453                 default:
3454                         return 0;
3455                 }
3456                 break;
3457         default:
3458                 return 0;
3459         }
3460
3461         chv_set_phy_signal_level(encoder, deemph_reg_value,
3462                                  margin_reg_value, uniq_trans_scale);
3463
3464         return 0;
3465 }
3466
3467 static uint32_t
3468 g4x_signal_levels(uint8_t train_set)
3469 {
3470         uint32_t        signal_levels = 0;
3471
3472         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3473         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3474         default:
3475                 signal_levels |= DP_VOLTAGE_0_4;
3476                 break;
3477         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3478                 signal_levels |= DP_VOLTAGE_0_6;
3479                 break;
3480         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3481                 signal_levels |= DP_VOLTAGE_0_8;
3482                 break;
3483         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3484                 signal_levels |= DP_VOLTAGE_1_2;
3485                 break;
3486         }
3487         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3488         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3489         default:
3490                 signal_levels |= DP_PRE_EMPHASIS_0;
3491                 break;
3492         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3493                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3494                 break;
3495         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3496                 signal_levels |= DP_PRE_EMPHASIS_6;
3497                 break;
3498         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3499                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3500                 break;
3501         }
3502         return signal_levels;
3503 }
3504
3505 /* SNB CPU eDP voltage swing and pre-emphasis control */
3506 static uint32_t
3507 snb_cpu_edp_signal_levels(uint8_t train_set)
3508 {
3509         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3510                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3511         switch (signal_levels) {
3512         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3513         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3514                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3515         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3516                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3517         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3518         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3519                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3520         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3521         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3522                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3523         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3524         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3525                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3526         default:
3527                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3528                               "0x%x\n", signal_levels);
3529                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3530         }
3531 }
3532
3533 /* IVB CPU eDP voltage swing and pre-emphasis control */
3534 static uint32_t
3535 ivb_cpu_edp_signal_levels(uint8_t train_set)
3536 {
3537         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3538                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3539         switch (signal_levels) {
3540         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3541                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3542         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3543                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3544         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3545                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3546
3547         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3548                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3549         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3550                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3551
3552         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3553                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3554         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3555                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3556
3557         default:
3558                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3559                               "0x%x\n", signal_levels);
3560                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3561         }
3562 }
3563
3564 void
3565 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3566 {
3567         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3568         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3569         enum port port = intel_dig_port->base.port;
3570         uint32_t signal_levels, mask = 0;
3571         uint8_t train_set = intel_dp->train_set[0];
3572
3573         if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
3574                 signal_levels = bxt_signal_levels(intel_dp);
3575         } else if (HAS_DDI(dev_priv)) {
3576                 signal_levels = ddi_signal_levels(intel_dp);
3577                 mask = DDI_BUF_EMP_MASK;
3578         } else if (IS_CHERRYVIEW(dev_priv)) {
3579                 signal_levels = chv_signal_levels(intel_dp);
3580         } else if (IS_VALLEYVIEW(dev_priv)) {
3581                 signal_levels = vlv_signal_levels(intel_dp);
3582         } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
3583                 signal_levels = ivb_cpu_edp_signal_levels(train_set);
3584                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3585         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3586                 signal_levels = snb_cpu_edp_signal_levels(train_set);
3587                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3588         } else {
3589                 signal_levels = g4x_signal_levels(train_set);
3590                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3591         }
3592
3593         if (mask)
3594                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3595
3596         DRM_DEBUG_KMS("Using vswing level %d\n",
3597                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3598         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3599                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3600                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3601
3602         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3603
3604         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3605         POSTING_READ(intel_dp->output_reg);
3606 }
3607
3608 void
3609 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3610                                        uint8_t dp_train_pat)
3611 {
3612         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3613         struct drm_i915_private *dev_priv =
3614                 to_i915(intel_dig_port->base.base.dev);
3615
3616         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3617
3618         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3619         POSTING_READ(intel_dp->output_reg);
3620 }
3621
3622 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3623 {
3624         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3625         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3626         enum port port = intel_dig_port->base.port;
3627         uint32_t val;
3628
3629         if (!HAS_DDI(dev_priv))
3630                 return;
3631
3632         val = I915_READ(DP_TP_CTL(port));
3633         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3634         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3635         I915_WRITE(DP_TP_CTL(port), val);
3636
3637         /*
3638          * On PORT_A we can have only eDP in SST mode. There the only reason
3639          * we need to set idle transmission mode is to work around a HW issue
3640          * where we enable the pipe while not in idle link-training mode.
3641          * In this case there is requirement to wait for a minimum number of
3642          * idle patterns to be sent.
3643          */
3644         if (port == PORT_A)
3645                 return;
3646
3647         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3648                                     DP_TP_STATUS_IDLE_DONE,
3649                                     DP_TP_STATUS_IDLE_DONE,
3650                                     1))
3651                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3652 }
3653
3654 static void
3655 intel_dp_link_down(struct intel_encoder *encoder,
3656                    const struct intel_crtc_state *old_crtc_state)
3657 {
3658         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3659         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
3660         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
3661         enum port port = encoder->port;
3662         uint32_t DP = intel_dp->DP;
3663
3664         if (WARN_ON(HAS_DDI(dev_priv)))
3665                 return;
3666
3667         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3668                 return;
3669
3670         DRM_DEBUG_KMS("\n");
3671
3672         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
3673             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3674                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3675                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3676         } else {
3677                 DP &= ~DP_LINK_TRAIN_MASK;
3678                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3679         }
3680         I915_WRITE(intel_dp->output_reg, DP);
3681         POSTING_READ(intel_dp->output_reg);
3682
3683         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3684         I915_WRITE(intel_dp->output_reg, DP);
3685         POSTING_READ(intel_dp->output_reg);
3686
3687         /*
3688          * HW workaround for IBX, we need to move the port
3689          * to transcoder A after disabling it to allow the
3690          * matching HDMI port to be enabled on transcoder A.
3691          */
3692         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3693                 /*
3694                  * We get CPU/PCH FIFO underruns on the other pipe when
3695                  * doing the workaround. Sweep them under the rug.
3696                  */
3697                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3698                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3699
3700                 /* always enable with pattern 1 (as per spec) */
3701                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
3702                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
3703                         DP_LINK_TRAIN_PAT_1;
3704                 I915_WRITE(intel_dp->output_reg, DP);
3705                 POSTING_READ(intel_dp->output_reg);
3706
3707                 DP &= ~DP_PORT_EN;
3708                 I915_WRITE(intel_dp->output_reg, DP);
3709                 POSTING_READ(intel_dp->output_reg);
3710
3711                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3712                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3713                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3714         }
3715
3716         msleep(intel_dp->panel_power_down_delay);
3717
3718         intel_dp->DP = DP;
3719
3720         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3721                 pps_lock(intel_dp);
3722                 intel_dp->active_pipe = INVALID_PIPE;
3723                 pps_unlock(intel_dp);
3724         }
3725 }
3726
3727 bool
3728 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3729 {
3730         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3731                              sizeof(intel_dp->dpcd)) < 0)
3732                 return false; /* aux transfer failed */
3733
3734         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3735
3736         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3737 }
3738
3739 static bool
3740 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3741 {
3742         struct drm_i915_private *dev_priv =
3743                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3744
3745         /* this function is meant to be called only once */
3746         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3747
3748         if (!intel_dp_read_dpcd(intel_dp))
3749                 return false;
3750
3751         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3752                          drm_dp_is_branch(intel_dp->dpcd));
3753
3754         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3755                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3756                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3757
3758         /*
3759          * Read the eDP display control registers.
3760          *
3761          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
3762          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
3763          * set, but require eDP 1.4+ detection (e.g. for supported link rates
3764          * method). The display control registers should read zero if they're
3765          * not supported anyway.
3766          */
3767         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3768                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3769                              sizeof(intel_dp->edp_dpcd))
3770                 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3771                               intel_dp->edp_dpcd);
3772
3773         /*
3774          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
3775          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
3776          */
3777         intel_psr_init_dpcd(intel_dp);
3778
3779         /* Read the eDP 1.4+ supported link rates. */
3780         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
3781                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3782                 int i;
3783
3784                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3785                                 sink_rates, sizeof(sink_rates));
3786
3787                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3788                         int val = le16_to_cpu(sink_rates[i]);
3789
3790                         if (val == 0)
3791                                 break;
3792
3793                         /* Value read multiplied by 200kHz gives the per-lane
3794                          * link rate in kHz. The source rates are, however,
3795                          * stored in terms of LS_Clk kHz. The full conversion
3796                          * back to symbols is
3797                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3798                          */
3799                         intel_dp->sink_rates[i] = (val * 200) / 10;
3800                 }
3801                 intel_dp->num_sink_rates = i;
3802         }
3803
3804         /*
3805          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
3806          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
3807          */
3808         if (intel_dp->num_sink_rates)
3809                 intel_dp->use_rate_select = true;
3810         else
3811                 intel_dp_set_sink_rates(intel_dp);
3812
3813         intel_dp_set_common_rates(intel_dp);
3814
3815         return true;
3816 }
3817
3818
3819 static bool
3820 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3821 {
3822         u8 sink_count;
3823
3824         if (!intel_dp_read_dpcd(intel_dp))
3825                 return false;
3826
3827         /* Don't clobber cached eDP rates. */
3828         if (!intel_dp_is_edp(intel_dp)) {
3829                 intel_dp_set_sink_rates(intel_dp);
3830                 intel_dp_set_common_rates(intel_dp);
3831         }
3832
3833         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3834                 return false;
3835
3836         /*
3837          * Sink count can change between short pulse hpd hence
3838          * a member variable in intel_dp will track any changes
3839          * between short pulse interrupts.
3840          */
3841         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3842
3843         /*
3844          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3845          * a dongle is present but no display. Unless we require to know
3846          * if a dongle is present or not, we don't need to update
3847          * downstream port information. So, an early return here saves
3848          * time from performing other operations which are not required.
3849          */
3850         if (!intel_dp_is_edp(intel_dp) && !intel_dp->sink_count)
3851                 return false;
3852
3853         if (!drm_dp_is_branch(intel_dp->dpcd))
3854                 return true; /* native DP sink */
3855
3856         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3857                 return true; /* no per-port downstream info */
3858
3859         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3860                              intel_dp->downstream_ports,
3861                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3862                 return false; /* downstream port status fetch failed */
3863
3864         return true;
3865 }
3866
3867 static bool
3868 intel_dp_can_mst(struct intel_dp *intel_dp)
3869 {
3870         u8 mstm_cap;
3871
3872         if (!i915_modparams.enable_dp_mst)
3873                 return false;
3874
3875         if (!intel_dp->can_mst)
3876                 return false;
3877
3878         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3879                 return false;
3880
3881         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3882                 return false;
3883
3884         return mstm_cap & DP_MST_CAP;
3885 }
3886
3887 static void
3888 intel_dp_configure_mst(struct intel_dp *intel_dp)
3889 {
3890         if (!i915_modparams.enable_dp_mst)
3891                 return;
3892
3893         if (!intel_dp->can_mst)
3894                 return;
3895
3896         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3897
3898         if (intel_dp->is_mst)
3899                 DRM_DEBUG_KMS("Sink is MST capable\n");
3900         else
3901                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3902
3903         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3904                                         intel_dp->is_mst);
3905 }
3906
3907 static bool
3908 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3909 {
3910         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3911                                  sink_irq_vector) == 1;
3912 }
3913
3914 static bool
3915 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3916 {
3917         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
3918                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
3919                 DP_DPRX_ESI_LEN;
3920 }
3921
3922 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3923 {
3924         int status = 0;
3925         int test_link_rate;
3926         uint8_t test_lane_count, test_link_bw;
3927         /* (DP CTS 1.2)
3928          * 4.3.1.11
3929          */
3930         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3931         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3932                                    &test_lane_count);
3933
3934         if (status <= 0) {
3935                 DRM_DEBUG_KMS("Lane count read failed\n");
3936                 return DP_TEST_NAK;
3937         }
3938         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3939
3940         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3941                                    &test_link_bw);
3942         if (status <= 0) {
3943                 DRM_DEBUG_KMS("Link Rate read failed\n");
3944                 return DP_TEST_NAK;
3945         }
3946         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3947
3948         /* Validate the requested link rate and lane count */
3949         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
3950                                         test_lane_count))
3951                 return DP_TEST_NAK;
3952
3953         intel_dp->compliance.test_lane_count = test_lane_count;
3954         intel_dp->compliance.test_link_rate = test_link_rate;
3955
3956         return DP_TEST_ACK;
3957 }
3958
3959 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
3960 {
3961         uint8_t test_pattern;
3962         uint8_t test_misc;
3963         __be16 h_width, v_height;
3964         int status = 0;
3965
3966         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
3967         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
3968                                    &test_pattern);
3969         if (status <= 0) {
3970                 DRM_DEBUG_KMS("Test pattern read failed\n");
3971                 return DP_TEST_NAK;
3972         }
3973         if (test_pattern != DP_COLOR_RAMP)
3974                 return DP_TEST_NAK;
3975
3976         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
3977                                   &h_width, 2);
3978         if (status <= 0) {
3979                 DRM_DEBUG_KMS("H Width read failed\n");
3980                 return DP_TEST_NAK;
3981         }
3982
3983         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
3984                                   &v_height, 2);
3985         if (status <= 0) {
3986                 DRM_DEBUG_KMS("V Height read failed\n");
3987                 return DP_TEST_NAK;
3988         }
3989
3990         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
3991                                    &test_misc);
3992         if (status <= 0) {
3993                 DRM_DEBUG_KMS("TEST MISC read failed\n");
3994                 return DP_TEST_NAK;
3995         }
3996         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
3997                 return DP_TEST_NAK;
3998         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
3999                 return DP_TEST_NAK;
4000         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4001         case DP_TEST_BIT_DEPTH_6:
4002                 intel_dp->compliance.test_data.bpc = 6;
4003                 break;
4004         case DP_TEST_BIT_DEPTH_8:
4005                 intel_dp->compliance.test_data.bpc = 8;
4006                 break;
4007         default:
4008                 return DP_TEST_NAK;
4009         }
4010
4011         intel_dp->compliance.test_data.video_pattern = test_pattern;
4012         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4013         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4014         /* Set test active flag here so userspace doesn't interrupt things */
4015         intel_dp->compliance.test_active = 1;
4016
4017         return DP_TEST_ACK;
4018 }
4019
4020 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4021 {
4022         uint8_t test_result = DP_TEST_ACK;
4023         struct intel_connector *intel_connector = intel_dp->attached_connector;
4024         struct drm_connector *connector = &intel_connector->base;
4025
4026         if (intel_connector->detect_edid == NULL ||
4027             connector->edid_corrupt ||
4028             intel_dp->aux.i2c_defer_count > 6) {
4029                 /* Check EDID read for NACKs, DEFERs and corruption
4030                  * (DP CTS 1.2 Core r1.1)
4031                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4032                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4033                  *    4.2.2.6 : EDID corruption detected
4034                  * Use failsafe mode for all cases
4035                  */
4036                 if (intel_dp->aux.i2c_nack_count > 0 ||
4037                         intel_dp->aux.i2c_defer_count > 0)
4038                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4039                                       intel_dp->aux.i2c_nack_count,
4040                                       intel_dp->aux.i2c_defer_count);
4041                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4042         } else {
4043                 struct edid *block = intel_connector->detect_edid;
4044
4045                 /* We have to write the checksum
4046                  * of the last block read
4047                  */
4048                 block += intel_connector->detect_edid->extensions;
4049
4050                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4051                                        block->checksum) <= 0)
4052                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4053
4054                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4055                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4056         }
4057
4058         /* Set test active flag here so userspace doesn't interrupt things */
4059         intel_dp->compliance.test_active = 1;
4060
4061         return test_result;
4062 }
4063
4064 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4065 {
4066         uint8_t test_result = DP_TEST_NAK;
4067         return test_result;
4068 }
4069
4070 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4071 {
4072         uint8_t response = DP_TEST_NAK;
4073         uint8_t request = 0;
4074         int status;
4075
4076         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4077         if (status <= 0) {
4078                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4079                 goto update_status;
4080         }
4081
4082         switch (request) {
4083         case DP_TEST_LINK_TRAINING:
4084                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4085                 response = intel_dp_autotest_link_training(intel_dp);
4086                 break;
4087         case DP_TEST_LINK_VIDEO_PATTERN:
4088                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4089                 response = intel_dp_autotest_video_pattern(intel_dp);
4090                 break;
4091         case DP_TEST_LINK_EDID_READ:
4092                 DRM_DEBUG_KMS("EDID test requested\n");
4093                 response = intel_dp_autotest_edid(intel_dp);
4094                 break;
4095         case DP_TEST_LINK_PHY_TEST_PATTERN:
4096                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4097                 response = intel_dp_autotest_phy_pattern(intel_dp);
4098                 break;
4099         default:
4100                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4101                 break;
4102         }
4103
4104         if (response & DP_TEST_ACK)
4105                 intel_dp->compliance.test_type = request;
4106
4107 update_status:
4108         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4109         if (status <= 0)
4110                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4111 }
4112
4113 static int
4114 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4115 {
4116         bool bret;
4117
4118         if (intel_dp->is_mst) {
4119                 u8 esi[DP_DPRX_ESI_LEN] = { 0 };
4120                 int ret = 0;
4121                 int retry;
4122                 bool handled;
4123                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4124 go_again:
4125                 if (bret == true) {
4126
4127                         /* check link status - esi[10] = 0x200c */
4128                         if (intel_dp->active_mst_links &&
4129                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4130                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4131                                 intel_dp_start_link_train(intel_dp);
4132                                 intel_dp_stop_link_train(intel_dp);
4133                         }
4134
4135                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4136                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4137
4138                         if (handled) {
4139                                 for (retry = 0; retry < 3; retry++) {
4140                                         int wret;
4141                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4142                                                                  DP_SINK_COUNT_ESI+1,
4143                                                                  &esi[1], 3);
4144                                         if (wret == 3) {
4145                                                 break;
4146                                         }
4147                                 }
4148
4149                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4150                                 if (bret == true) {
4151                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4152                                         goto go_again;
4153                                 }
4154                         } else
4155                                 ret = 0;
4156
4157                         return ret;
4158                 } else {
4159                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4160                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4161                         intel_dp->is_mst = false;
4162                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4163                         /* send a hotplug event */
4164                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4165                 }
4166         }
4167         return -EINVAL;
4168 }
4169
4170 static bool
4171 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
4172 {
4173         u8 link_status[DP_LINK_STATUS_SIZE];
4174
4175         if (!intel_dp->link_trained)
4176                 return false;
4177
4178         if (!intel_dp_get_link_status(intel_dp, link_status))
4179                 return false;
4180
4181         /*
4182          * Validate the cached values of intel_dp->link_rate and
4183          * intel_dp->lane_count before attempting to retrain.
4184          */
4185         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
4186                                         intel_dp->lane_count))
4187                 return false;
4188
4189         /* Retrain if Channel EQ or CR not ok */
4190         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
4191 }
4192
4193 int intel_dp_retrain_link(struct intel_encoder *encoder,
4194                           struct drm_modeset_acquire_ctx *ctx)
4195 {
4196         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4197         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
4198         struct intel_connector *connector = intel_dp->attached_connector;
4199         struct drm_connector_state *conn_state;
4200         struct intel_crtc_state *crtc_state;
4201         struct intel_crtc *crtc;
4202         int ret;
4203
4204         /* FIXME handle the MST connectors as well */
4205
4206         if (!connector || connector->base.status != connector_status_connected)
4207                 return 0;
4208
4209         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4210                                ctx);
4211         if (ret)
4212                 return ret;
4213
4214         conn_state = connector->base.state;
4215
4216         crtc = to_intel_crtc(conn_state->crtc);
4217         if (!crtc)
4218                 return 0;
4219
4220         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4221         if (ret)
4222                 return ret;
4223
4224         crtc_state = to_intel_crtc_state(crtc->base.state);
4225
4226         WARN_ON(!intel_crtc_has_dp_encoder(crtc_state));
4227
4228         if (!crtc_state->base.active)
4229                 return 0;
4230
4231         if (conn_state->commit &&
4232             !try_wait_for_completion(&conn_state->commit->hw_done))
4233                 return 0;
4234
4235         if (!intel_dp_needs_link_retrain(intel_dp))
4236                 return 0;
4237
4238         /* Suppress underruns caused by re-training */
4239         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4240         if (crtc->config->has_pch_encoder)
4241                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4242                                                       intel_crtc_pch_transcoder(crtc), false);
4243
4244         intel_dp_start_link_train(intel_dp);
4245         intel_dp_stop_link_train(intel_dp);
4246
4247         /* Keep underrun reporting disabled until things are stable */
4248         intel_wait_for_vblank(dev_priv, crtc->pipe);
4249
4250         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4251         if (crtc->config->has_pch_encoder)
4252                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4253                                                       intel_crtc_pch_transcoder(crtc), true);
4254
4255         return 0;
4256 }
4257
4258 /*
4259  * If display is now connected check links status,
4260  * there has been known issues of link loss triggering
4261  * long pulse.
4262  *
4263  * Some sinks (eg. ASUS PB287Q) seem to perform some
4264  * weird HPD ping pong during modesets. So we can apparently
4265  * end up with HPD going low during a modeset, and then
4266  * going back up soon after. And once that happens we must
4267  * retrain the link to get a picture. That's in case no
4268  * userspace component reacted to intermittent HPD dip.
4269  */
4270 static bool intel_dp_hotplug(struct intel_encoder *encoder,
4271                              struct intel_connector *connector)
4272 {
4273         struct drm_modeset_acquire_ctx ctx;
4274         bool changed;
4275         int ret;
4276
4277         changed = intel_encoder_hotplug(encoder, connector);
4278
4279         drm_modeset_acquire_init(&ctx, 0);
4280
4281         for (;;) {
4282                 ret = intel_dp_retrain_link(encoder, &ctx);
4283
4284                 if (ret == -EDEADLK) {
4285                         drm_modeset_backoff(&ctx);
4286                         continue;
4287                 }
4288
4289                 break;
4290         }
4291
4292         drm_modeset_drop_locks(&ctx);
4293         drm_modeset_acquire_fini(&ctx);
4294         WARN(ret, "Acquiring modeset locks failed with %i\n", ret);
4295
4296         return changed;
4297 }
4298
4299 /*
4300  * According to DP spec
4301  * 5.1.2:
4302  *  1. Read DPCD
4303  *  2. Configure link according to Receiver Capabilities
4304  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4305  *  4. Check link status on receipt of hot-plug interrupt
4306  *
4307  * intel_dp_short_pulse -  handles short pulse interrupts
4308  * when full detection is not required.
4309  * Returns %true if short pulse is handled and full detection
4310  * is NOT required and %false otherwise.
4311  */
4312 static bool
4313 intel_dp_short_pulse(struct intel_dp *intel_dp)
4314 {
4315         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
4316         u8 sink_irq_vector = 0;
4317         u8 old_sink_count = intel_dp->sink_count;
4318         bool ret;
4319
4320         /*
4321          * Clearing compliance test variables to allow capturing
4322          * of values for next automated test request.
4323          */
4324         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4325
4326         /*
4327          * Now read the DPCD to see if it's actually running
4328          * If the current value of sink count doesn't match with
4329          * the value that was stored earlier or dpcd read failed
4330          * we need to do full detection
4331          */
4332         ret = intel_dp_get_dpcd(intel_dp);
4333
4334         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4335                 /* No need to proceed if we are going to do full detect */
4336                 return false;
4337         }
4338
4339         /* Try to read the source of the interrupt */
4340         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4341             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4342             sink_irq_vector != 0) {
4343                 /* Clear interrupt source */
4344                 drm_dp_dpcd_writeb(&intel_dp->aux,
4345                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4346                                    sink_irq_vector);
4347
4348                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4349                         intel_dp_handle_test_request(intel_dp);
4350                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4351                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4352         }
4353
4354         /* Handle CEC interrupts, if any */
4355         drm_dp_cec_irq(&intel_dp->aux);
4356
4357         /* defer to the hotplug work for link retraining if needed */
4358         if (intel_dp_needs_link_retrain(intel_dp))
4359                 return false;
4360
4361         intel_psr_short_pulse(intel_dp);
4362
4363         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4364                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4365                 /* Send a Hotplug Uevent to userspace to start modeset */
4366                 drm_kms_helper_hotplug_event(&dev_priv->drm);
4367         }
4368
4369         return true;
4370 }
4371
4372 /* XXX this is probably wrong for multiple downstream ports */
4373 static enum drm_connector_status
4374 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4375 {
4376         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4377         uint8_t *dpcd = intel_dp->dpcd;
4378         uint8_t type;
4379
4380         if (lspcon->active)
4381                 lspcon_resume(lspcon);
4382
4383         if (!intel_dp_get_dpcd(intel_dp))
4384                 return connector_status_disconnected;
4385
4386         if (intel_dp_is_edp(intel_dp))
4387                 return connector_status_connected;
4388
4389         /* if there's no downstream port, we're done */
4390         if (!drm_dp_is_branch(dpcd))
4391                 return connector_status_connected;
4392
4393         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4394         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4395             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4396
4397                 return intel_dp->sink_count ?
4398                 connector_status_connected : connector_status_disconnected;
4399         }
4400
4401         if (intel_dp_can_mst(intel_dp))
4402                 return connector_status_connected;
4403
4404         /* If no HPD, poke DDC gently */
4405         if (drm_probe_ddc(&intel_dp->aux.ddc))
4406                 return connector_status_connected;
4407
4408         /* Well we tried, say unknown for unreliable port types */
4409         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4410                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4411                 if (type == DP_DS_PORT_TYPE_VGA ||
4412                     type == DP_DS_PORT_TYPE_NON_EDID)
4413                         return connector_status_unknown;
4414         } else {
4415                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4416                         DP_DWN_STRM_PORT_TYPE_MASK;
4417                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4418                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4419                         return connector_status_unknown;
4420         }
4421
4422         /* Anything else is out of spec, warn and ignore */
4423         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4424         return connector_status_disconnected;
4425 }
4426
4427 static enum drm_connector_status
4428 edp_detect(struct intel_dp *intel_dp)
4429 {
4430         return connector_status_connected;
4431 }
4432
4433 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
4434 {
4435         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4436         u32 bit;
4437
4438         switch (encoder->hpd_pin) {
4439         case HPD_PORT_B:
4440                 bit = SDE_PORTB_HOTPLUG;
4441                 break;
4442         case HPD_PORT_C:
4443                 bit = SDE_PORTC_HOTPLUG;
4444                 break;
4445         case HPD_PORT_D:
4446                 bit = SDE_PORTD_HOTPLUG;
4447                 break;
4448         default:
4449                 MISSING_CASE(encoder->hpd_pin);
4450                 return false;
4451         }
4452
4453         return I915_READ(SDEISR) & bit;
4454 }
4455
4456 static bool cpt_digital_port_connected(struct intel_encoder *encoder)
4457 {
4458         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4459         u32 bit;
4460
4461         switch (encoder->hpd_pin) {
4462         case HPD_PORT_B:
4463                 bit = SDE_PORTB_HOTPLUG_CPT;
4464                 break;
4465         case HPD_PORT_C:
4466                 bit = SDE_PORTC_HOTPLUG_CPT;
4467                 break;
4468         case HPD_PORT_D:
4469                 bit = SDE_PORTD_HOTPLUG_CPT;
4470                 break;
4471         default:
4472                 MISSING_CASE(encoder->hpd_pin);
4473                 return false;
4474         }
4475
4476         return I915_READ(SDEISR) & bit;
4477 }
4478
4479 static bool spt_digital_port_connected(struct intel_encoder *encoder)
4480 {
4481         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4482         u32 bit;
4483
4484         switch (encoder->hpd_pin) {
4485         case HPD_PORT_A:
4486                 bit = SDE_PORTA_HOTPLUG_SPT;
4487                 break;
4488         case HPD_PORT_E:
4489                 bit = SDE_PORTE_HOTPLUG_SPT;
4490                 break;
4491         default:
4492                 return cpt_digital_port_connected(encoder);
4493         }
4494
4495         return I915_READ(SDEISR) & bit;
4496 }
4497
4498 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
4499 {
4500         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4501         u32 bit;
4502
4503         switch (encoder->hpd_pin) {
4504         case HPD_PORT_B:
4505                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4506                 break;
4507         case HPD_PORT_C:
4508                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4509                 break;
4510         case HPD_PORT_D:
4511                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4512                 break;
4513         default:
4514                 MISSING_CASE(encoder->hpd_pin);
4515                 return false;
4516         }
4517
4518         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4519 }
4520
4521 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
4522 {
4523         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4524         u32 bit;
4525
4526         switch (encoder->hpd_pin) {
4527         case HPD_PORT_B:
4528                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4529                 break;
4530         case HPD_PORT_C:
4531                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4532                 break;
4533         case HPD_PORT_D:
4534                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4535                 break;
4536         default:
4537                 MISSING_CASE(encoder->hpd_pin);
4538                 return false;
4539         }
4540
4541         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4542 }
4543
4544 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
4545 {
4546         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4547
4548         if (encoder->hpd_pin == HPD_PORT_A)
4549                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4550         else
4551                 return ibx_digital_port_connected(encoder);
4552 }
4553
4554 static bool snb_digital_port_connected(struct intel_encoder *encoder)
4555 {
4556         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4557
4558         if (encoder->hpd_pin == HPD_PORT_A)
4559                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG;
4560         else
4561                 return cpt_digital_port_connected(encoder);
4562 }
4563
4564 static bool ivb_digital_port_connected(struct intel_encoder *encoder)
4565 {
4566         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4567
4568         if (encoder->hpd_pin == HPD_PORT_A)
4569                 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB;
4570         else
4571                 return cpt_digital_port_connected(encoder);
4572 }
4573
4574 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4575 {
4576         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4577
4578         if (encoder->hpd_pin == HPD_PORT_A)
4579                 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG;
4580         else
4581                 return cpt_digital_port_connected(encoder);
4582 }
4583
4584 static bool bxt_digital_port_connected(struct intel_encoder *encoder)
4585 {
4586         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4587         u32 bit;
4588
4589         switch (encoder->hpd_pin) {
4590         case HPD_PORT_A:
4591                 bit = BXT_DE_PORT_HP_DDIA;
4592                 break;
4593         case HPD_PORT_B:
4594                 bit = BXT_DE_PORT_HP_DDIB;
4595                 break;
4596         case HPD_PORT_C:
4597                 bit = BXT_DE_PORT_HP_DDIC;
4598                 break;
4599         default:
4600                 MISSING_CASE(encoder->hpd_pin);
4601                 return false;
4602         }
4603
4604         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4605 }
4606
4607 /*
4608  * intel_digital_port_connected - is the specified port connected?
4609  * @encoder: intel_encoder
4610  *
4611  * Return %true if port is connected, %false otherwise.
4612  */
4613 bool intel_digital_port_connected(struct intel_encoder *encoder)
4614 {
4615         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4616
4617         if (HAS_GMCH_DISPLAY(dev_priv)) {
4618                 if (IS_GM45(dev_priv))
4619                         return gm45_digital_port_connected(encoder);
4620                 else
4621                         return g4x_digital_port_connected(encoder);
4622         }
4623
4624         if (IS_GEN5(dev_priv))
4625                 return ilk_digital_port_connected(encoder);
4626         else if (IS_GEN6(dev_priv))
4627                 return snb_digital_port_connected(encoder);
4628         else if (IS_GEN7(dev_priv))
4629                 return ivb_digital_port_connected(encoder);
4630         else if (IS_GEN8(dev_priv))
4631                 return bdw_digital_port_connected(encoder);
4632         else if (IS_GEN9_LP(dev_priv))
4633                 return bxt_digital_port_connected(encoder);
4634         else
4635                 return spt_digital_port_connected(encoder);
4636 }
4637
4638 static struct edid *
4639 intel_dp_get_edid(struct intel_dp *intel_dp)
4640 {
4641         struct intel_connector *intel_connector = intel_dp->attached_connector;
4642
4643         /* use cached edid if we have one */
4644         if (intel_connector->edid) {
4645                 /* invalid edid */
4646                 if (IS_ERR(intel_connector->edid))
4647                         return NULL;
4648
4649                 return drm_edid_duplicate(intel_connector->edid);
4650         } else
4651                 return drm_get_edid(&intel_connector->base,
4652                                     &intel_dp->aux.ddc);
4653 }
4654
4655 static void
4656 intel_dp_set_edid(struct intel_dp *intel_dp)
4657 {
4658         struct intel_connector *intel_connector = intel_dp->attached_connector;
4659         struct edid *edid;
4660
4661         intel_dp_unset_edid(intel_dp);
4662         edid = intel_dp_get_edid(intel_dp);
4663         intel_connector->detect_edid = edid;
4664
4665         intel_dp->has_audio = drm_detect_monitor_audio(edid);
4666         drm_dp_cec_set_edid(&intel_dp->aux, edid);
4667 }
4668
4669 static void
4670 intel_dp_unset_edid(struct intel_dp *intel_dp)
4671 {
4672         struct intel_connector *intel_connector = intel_dp->attached_connector;
4673
4674         drm_dp_cec_unset_edid(&intel_dp->aux);
4675         kfree(intel_connector->detect_edid);
4676         intel_connector->detect_edid = NULL;
4677
4678         intel_dp->has_audio = false;
4679 }
4680
4681 static int
4682 intel_dp_long_pulse(struct intel_connector *connector,
4683                     struct drm_modeset_acquire_ctx *ctx)
4684 {
4685         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
4686         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
4687         enum drm_connector_status status;
4688         u8 sink_irq_vector = 0;
4689
4690         WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
4691
4692         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4693
4694         /* Can't disconnect eDP */
4695         if (intel_dp_is_edp(intel_dp))
4696                 status = edp_detect(intel_dp);
4697         else if (intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base))
4698                 status = intel_dp_detect_dpcd(intel_dp);
4699         else
4700                 status = connector_status_disconnected;
4701
4702         if (status == connector_status_disconnected) {
4703                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4704
4705                 if (intel_dp->is_mst) {
4706                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4707                                       intel_dp->is_mst,
4708                                       intel_dp->mst_mgr.mst_state);
4709                         intel_dp->is_mst = false;
4710                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4711                                                         intel_dp->is_mst);
4712                 }
4713
4714                 goto out;
4715         }
4716
4717         if (intel_dp->reset_link_params) {
4718                 /* Initial max link lane count */
4719                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4720
4721                 /* Initial max link rate */
4722                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4723
4724                 intel_dp->reset_link_params = false;
4725         }
4726
4727         intel_dp_print_rates(intel_dp);
4728
4729         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4730                          drm_dp_is_branch(intel_dp->dpcd));
4731
4732         intel_dp_configure_mst(intel_dp);
4733
4734         if (intel_dp->is_mst) {
4735                 /*
4736                  * If we are in MST mode then this connector
4737                  * won't appear connected or have anything
4738                  * with EDID on it
4739                  */
4740                 status = connector_status_disconnected;
4741                 goto out;
4742         } else {
4743                 /*
4744                  * If display is now connected check links status,
4745                  * there has been known issues of link loss triggering
4746                  * long pulse.
4747                  *
4748                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4749                  * weird HPD ping pong during modesets. So we can apparently
4750                  * end up with HPD going low during a modeset, and then
4751                  * going back up soon after. And once that happens we must
4752                  * retrain the link to get a picture. That's in case no
4753                  * userspace component reacted to intermittent HPD dip.
4754                  */
4755                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4756
4757                 intel_dp_retrain_link(encoder, ctx);
4758         }
4759
4760         /*
4761          * Some external monitors do not signal loss of link synchronization
4762          * with an IRQ_HPD, so force a link status check.
4763          */
4764         if (!intel_dp_is_edp(intel_dp)) {
4765                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4766
4767                 intel_dp_retrain_link(encoder, ctx);
4768         }
4769
4770         /*
4771          * Clearing NACK and defer counts to get their exact values
4772          * while reading EDID which are required by Compliance tests
4773          * 4.2.2.4 and 4.2.2.5
4774          */
4775         intel_dp->aux.i2c_nack_count = 0;
4776         intel_dp->aux.i2c_defer_count = 0;
4777
4778         intel_dp_set_edid(intel_dp);
4779         if (intel_dp_is_edp(intel_dp) || connector->detect_edid)
4780                 status = connector_status_connected;
4781         intel_dp->detect_done = true;
4782
4783         /* Try to read the source of the interrupt */
4784         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4785             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4786             sink_irq_vector != 0) {
4787                 /* Clear interrupt source */
4788                 drm_dp_dpcd_writeb(&intel_dp->aux,
4789                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4790                                    sink_irq_vector);
4791
4792                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4793                         intel_dp_handle_test_request(intel_dp);
4794                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4795                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4796         }
4797
4798 out:
4799         if (status != connector_status_connected && !intel_dp->is_mst)
4800                 intel_dp_unset_edid(intel_dp);
4801
4802         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4803         return status;
4804 }
4805
4806 static int
4807 intel_dp_detect(struct drm_connector *connector,
4808                 struct drm_modeset_acquire_ctx *ctx,
4809                 bool force)
4810 {
4811         struct intel_dp *intel_dp = intel_attached_dp(connector);
4812         int status = connector->status;
4813
4814         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4815                       connector->base.id, connector->name);
4816
4817         /* If full detect is not performed yet, do a full detect */
4818         if (!intel_dp->detect_done) {
4819                 struct drm_crtc *crtc;
4820                 int ret;
4821
4822                 crtc = connector->state->crtc;
4823                 if (crtc) {
4824                         ret = drm_modeset_lock(&crtc->mutex, ctx);
4825                         if (ret)
4826                                 return ret;
4827                 }
4828
4829                 status = intel_dp_long_pulse(intel_dp->attached_connector, ctx);
4830         }
4831
4832         intel_dp->detect_done = false;
4833
4834         return status;
4835 }
4836
4837 static void
4838 intel_dp_force(struct drm_connector *connector)
4839 {
4840         struct intel_dp *intel_dp = intel_attached_dp(connector);
4841         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4842         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4843
4844         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4845                       connector->base.id, connector->name);
4846         intel_dp_unset_edid(intel_dp);
4847
4848         if (connector->status != connector_status_connected)
4849                 return;
4850
4851         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4852
4853         intel_dp_set_edid(intel_dp);
4854
4855         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4856 }
4857
4858 static int intel_dp_get_modes(struct drm_connector *connector)
4859 {
4860         struct intel_connector *intel_connector = to_intel_connector(connector);
4861         struct edid *edid;
4862
4863         edid = intel_connector->detect_edid;
4864         if (edid) {
4865                 int ret = intel_connector_update_modes(connector, edid);
4866                 if (ret)
4867                         return ret;
4868         }
4869
4870         /* if eDP has no EDID, fall back to fixed mode */
4871         if (intel_dp_is_edp(intel_attached_dp(connector)) &&
4872             intel_connector->panel.fixed_mode) {
4873                 struct drm_display_mode *mode;
4874
4875                 mode = drm_mode_duplicate(connector->dev,
4876                                           intel_connector->panel.fixed_mode);
4877                 if (mode) {
4878                         drm_mode_probed_add(connector, mode);
4879                         return 1;
4880                 }
4881         }
4882
4883         return 0;
4884 }
4885
4886 static int
4887 intel_dp_connector_register(struct drm_connector *connector)
4888 {
4889         struct intel_dp *intel_dp = intel_attached_dp(connector);
4890         struct drm_device *dev = connector->dev;
4891         int ret;
4892
4893         ret = intel_connector_register(connector);
4894         if (ret)
4895                 return ret;
4896
4897         i915_debugfs_connector_add(connector);
4898
4899         DRM_DEBUG_KMS("registering %s bus for %s\n",
4900                       intel_dp->aux.name, connector->kdev->kobj.name);
4901
4902         intel_dp->aux.dev = connector->kdev;
4903         ret = drm_dp_aux_register(&intel_dp->aux);
4904         if (!ret)
4905                 drm_dp_cec_register_connector(&intel_dp->aux,
4906                                               connector->name, dev->dev);
4907         return ret;
4908 }
4909
4910 static void
4911 intel_dp_connector_unregister(struct drm_connector *connector)
4912 {
4913         struct intel_dp *intel_dp = intel_attached_dp(connector);
4914
4915         drm_dp_cec_unregister_connector(&intel_dp->aux);
4916         drm_dp_aux_unregister(&intel_dp->aux);
4917         intel_connector_unregister(connector);
4918 }
4919
4920 static void
4921 intel_dp_connector_destroy(struct drm_connector *connector)
4922 {
4923         struct intel_connector *intel_connector = to_intel_connector(connector);
4924
4925         kfree(intel_connector->detect_edid);
4926
4927         if (!IS_ERR_OR_NULL(intel_connector->edid))
4928                 kfree(intel_connector->edid);
4929
4930         /*
4931          * Can't call intel_dp_is_edp() since the encoder may have been
4932          * destroyed already.
4933          */
4934         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4935                 intel_panel_fini(&intel_connector->panel);
4936
4937         drm_connector_cleanup(connector);
4938         kfree(connector);
4939 }
4940
4941 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4942 {
4943         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4944         struct intel_dp *intel_dp = &intel_dig_port->dp;
4945
4946         intel_dp_mst_encoder_cleanup(intel_dig_port);
4947         if (intel_dp_is_edp(intel_dp)) {
4948                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4949                 /*
4950                  * vdd might still be enabled do to the delayed vdd off.
4951                  * Make sure vdd is actually turned off here.
4952                  */
4953                 pps_lock(intel_dp);
4954                 edp_panel_vdd_off_sync(intel_dp);
4955                 pps_unlock(intel_dp);
4956
4957                 if (intel_dp->edp_notifier.notifier_call) {
4958                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4959                         intel_dp->edp_notifier.notifier_call = NULL;
4960                 }
4961         }
4962
4963         intel_dp_aux_fini(intel_dp);
4964
4965         drm_encoder_cleanup(encoder);
4966         kfree(intel_dig_port);
4967 }
4968
4969 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4970 {
4971         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4972
4973         if (!intel_dp_is_edp(intel_dp))
4974                 return;
4975
4976         /*
4977          * vdd might still be enabled do to the delayed vdd off.
4978          * Make sure vdd is actually turned off here.
4979          */
4980         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4981         pps_lock(intel_dp);
4982         edp_panel_vdd_off_sync(intel_dp);
4983         pps_unlock(intel_dp);
4984 }
4985
4986 static
4987 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port,
4988                                 u8 *an)
4989 {
4990         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base);
4991         static const struct drm_dp_aux_msg msg = {
4992                 .request = DP_AUX_NATIVE_WRITE,
4993                 .address = DP_AUX_HDCP_AKSV,
4994                 .size = DRM_HDCP_KSV_LEN,
4995         };
4996         uint8_t txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0;
4997         ssize_t dpcd_ret;
4998         int ret;
4999
5000         /* Output An first, that's easy */
5001         dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN,
5002                                      an, DRM_HDCP_AN_LEN);
5003         if (dpcd_ret != DRM_HDCP_AN_LEN) {
5004                 DRM_ERROR("Failed to write An over DP/AUX (%zd)\n", dpcd_ret);
5005                 return dpcd_ret >= 0 ? -EIO : dpcd_ret;
5006         }
5007
5008         /*
5009          * Since Aksv is Oh-So-Secret, we can't access it in software. So in
5010          * order to get it on the wire, we need to create the AUX header as if
5011          * we were writing the data, and then tickle the hardware to output the
5012          * data once the header is sent out.
5013          */
5014         intel_dp_aux_header(txbuf, &msg);
5015
5016         ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size,
5017                                 rxbuf, sizeof(rxbuf),
5018                                 DP_AUX_CH_CTL_AUX_AKSV_SELECT);
5019         if (ret < 0) {
5020                 DRM_ERROR("Write Aksv over DP/AUX failed (%d)\n", ret);
5021                 return ret;
5022         } else if (ret == 0) {
5023                 DRM_ERROR("Aksv write over DP/AUX was empty\n");
5024                 return -EIO;
5025         }
5026
5027         reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK;
5028         return reply == DP_AUX_NATIVE_REPLY_ACK ? 0 : -EIO;
5029 }
5030
5031 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port,
5032                                    u8 *bksv)
5033 {
5034         ssize_t ret;
5035         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
5036                                DRM_HDCP_KSV_LEN);
5037         if (ret != DRM_HDCP_KSV_LEN) {
5038                 DRM_ERROR("Read Bksv from DP/AUX failed (%zd)\n", ret);
5039                 return ret >= 0 ? -EIO : ret;
5040         }
5041         return 0;
5042 }
5043
5044 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port,
5045                                       u8 *bstatus)
5046 {
5047         ssize_t ret;
5048         /*
5049          * For some reason the HDMI and DP HDCP specs call this register
5050          * definition by different names. In the HDMI spec, it's called BSTATUS,
5051          * but in DP it's called BINFO.
5052          */
5053         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO,
5054                                bstatus, DRM_HDCP_BSTATUS_LEN);
5055         if (ret != DRM_HDCP_BSTATUS_LEN) {
5056                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5057                 return ret >= 0 ? -EIO : ret;
5058         }
5059         return 0;
5060 }
5061
5062 static
5063 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port,
5064                              u8 *bcaps)
5065 {
5066         ssize_t ret;
5067
5068         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
5069                                bcaps, 1);
5070         if (ret != 1) {
5071                 DRM_ERROR("Read bcaps from DP/AUX failed (%zd)\n", ret);
5072                 return ret >= 0 ? -EIO : ret;
5073         }
5074
5075         return 0;
5076 }
5077
5078 static
5079 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port,
5080                                    bool *repeater_present)
5081 {
5082         ssize_t ret;
5083         u8 bcaps;
5084
5085         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5086         if (ret)
5087                 return ret;
5088
5089         *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
5090         return 0;
5091 }
5092
5093 static
5094 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port,
5095                                 u8 *ri_prime)
5096 {
5097         ssize_t ret;
5098         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
5099                                ri_prime, DRM_HDCP_RI_LEN);
5100         if (ret != DRM_HDCP_RI_LEN) {
5101                 DRM_ERROR("Read Ri' from DP/AUX failed (%zd)\n", ret);
5102                 return ret >= 0 ? -EIO : ret;
5103         }
5104         return 0;
5105 }
5106
5107 static
5108 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port,
5109                                  bool *ksv_ready)
5110 {
5111         ssize_t ret;
5112         u8 bstatus;
5113         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5114                                &bstatus, 1);
5115         if (ret != 1) {
5116                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5117                 return ret >= 0 ? -EIO : ret;
5118         }
5119         *ksv_ready = bstatus & DP_BSTATUS_READY;
5120         return 0;
5121 }
5122
5123 static
5124 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port,
5125                                 int num_downstream, u8 *ksv_fifo)
5126 {
5127         ssize_t ret;
5128         int i;
5129
5130         /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
5131         for (i = 0; i < num_downstream; i += 3) {
5132                 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
5133                 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5134                                        DP_AUX_HDCP_KSV_FIFO,
5135                                        ksv_fifo + i * DRM_HDCP_KSV_LEN,
5136                                        len);
5137                 if (ret != len) {
5138                         DRM_ERROR("Read ksv[%d] from DP/AUX failed (%zd)\n", i,
5139                                   ret);
5140                         return ret >= 0 ? -EIO : ret;
5141                 }
5142         }
5143         return 0;
5144 }
5145
5146 static
5147 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port,
5148                                     int i, u32 *part)
5149 {
5150         ssize_t ret;
5151
5152         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
5153                 return -EINVAL;
5154
5155         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux,
5156                                DP_AUX_HDCP_V_PRIME(i), part,
5157                                DRM_HDCP_V_PRIME_PART_LEN);
5158         if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
5159                 DRM_ERROR("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
5160                 return ret >= 0 ? -EIO : ret;
5161         }
5162         return 0;
5163 }
5164
5165 static
5166 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port,
5167                                     bool enable)
5168 {
5169         /* Not used for single stream DisplayPort setups */
5170         return 0;
5171 }
5172
5173 static
5174 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port)
5175 {
5176         ssize_t ret;
5177         u8 bstatus;
5178
5179         ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
5180                                &bstatus, 1);
5181         if (ret != 1) {
5182                 DRM_ERROR("Read bstatus from DP/AUX failed (%zd)\n", ret);
5183                 return false;
5184         }
5185
5186         return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
5187 }
5188
5189 static
5190 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port,
5191                           bool *hdcp_capable)
5192 {
5193         ssize_t ret;
5194         u8 bcaps;
5195
5196         ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps);
5197         if (ret)
5198                 return ret;
5199
5200         *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
5201         return 0;
5202 }
5203
5204 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
5205         .write_an_aksv = intel_dp_hdcp_write_an_aksv,
5206         .read_bksv = intel_dp_hdcp_read_bksv,
5207         .read_bstatus = intel_dp_hdcp_read_bstatus,
5208         .repeater_present = intel_dp_hdcp_repeater_present,
5209         .read_ri_prime = intel_dp_hdcp_read_ri_prime,
5210         .read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
5211         .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
5212         .read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
5213         .toggle_signalling = intel_dp_hdcp_toggle_signalling,
5214         .check_link = intel_dp_hdcp_check_link,
5215         .hdcp_capable = intel_dp_hdcp_capable,
5216 };
5217
5218 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
5219 {
5220         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5221
5222         lockdep_assert_held(&dev_priv->pps_mutex);
5223
5224         if (!edp_have_panel_vdd(intel_dp))
5225                 return;
5226
5227         /*
5228          * The VDD bit needs a power domain reference, so if the bit is
5229          * already enabled when we boot or resume, grab this reference and
5230          * schedule a vdd off, so we don't hold on to the reference
5231          * indefinitely.
5232          */
5233         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5234         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5235
5236         edp_panel_vdd_schedule_off(intel_dp);
5237 }
5238
5239 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5240 {
5241         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5242         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
5243         enum pipe pipe;
5244
5245         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
5246                                   encoder->port, &pipe))
5247                 return pipe;
5248
5249         return INVALID_PIPE;
5250 }
5251
5252 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5253 {
5254         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5255         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5256         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5257
5258         if (!HAS_DDI(dev_priv))
5259                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5260
5261         if (lspcon->active)
5262                 lspcon_resume(lspcon);
5263
5264         intel_dp->reset_link_params = true;
5265
5266         pps_lock(intel_dp);
5267
5268         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5269                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5270
5271         if (intel_dp_is_edp(intel_dp)) {
5272                 /* Reinit the power sequencer, in case BIOS did something with it. */
5273                 intel_dp_pps_init(intel_dp);
5274                 intel_edp_panel_vdd_sanitize(intel_dp);
5275         }
5276
5277         pps_unlock(intel_dp);
5278 }
5279
5280 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5281         .force = intel_dp_force,
5282         .fill_modes = drm_helper_probe_single_connector_modes,
5283         .atomic_get_property = intel_digital_connector_atomic_get_property,
5284         .atomic_set_property = intel_digital_connector_atomic_set_property,
5285         .late_register = intel_dp_connector_register,
5286         .early_unregister = intel_dp_connector_unregister,
5287         .destroy = intel_dp_connector_destroy,
5288         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5289         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
5290 };
5291
5292 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5293         .detect_ctx = intel_dp_detect,
5294         .get_modes = intel_dp_get_modes,
5295         .mode_valid = intel_dp_mode_valid,
5296         .atomic_check = intel_digital_connector_atomic_check,
5297 };
5298
5299 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5300         .reset = intel_dp_encoder_reset,
5301         .destroy = intel_dp_encoder_destroy,
5302 };
5303
5304 enum irqreturn
5305 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5306 {
5307         struct intel_dp *intel_dp = &intel_dig_port->dp;
5308         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5309         enum irqreturn ret = IRQ_NONE;
5310
5311         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5312                 /*
5313                  * vdd off can generate a long pulse on eDP which
5314                  * would require vdd on to handle it, and thus we
5315                  * would end up in an endless cycle of
5316                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5317                  */
5318                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5319                               port_name(intel_dig_port->base.port));
5320                 return IRQ_HANDLED;
5321         }
5322
5323         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5324                       port_name(intel_dig_port->base.port),
5325                       long_hpd ? "long" : "short");
5326
5327         if (long_hpd) {
5328                 intel_dp->reset_link_params = true;
5329                 intel_dp->detect_done = false;
5330                 return IRQ_NONE;
5331         }
5332
5333         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5334
5335         if (intel_dp->is_mst) {
5336                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5337                         /*
5338                          * If we were in MST mode, and device is not
5339                          * there, get out of MST mode
5340                          */
5341                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5342                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5343                         intel_dp->is_mst = false;
5344                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5345                                                         intel_dp->is_mst);
5346                         intel_dp->detect_done = false;
5347                         goto put_power;
5348                 }
5349         }
5350
5351         if (!intel_dp->is_mst) {
5352                 bool handled;
5353
5354                 handled = intel_dp_short_pulse(intel_dp);
5355
5356                 /* Short pulse can signify loss of hdcp authentication */
5357                 intel_hdcp_check_link(intel_dp->attached_connector);
5358
5359                 if (!handled) {
5360                         intel_dp->detect_done = false;
5361                         goto put_power;
5362                 }
5363         }
5364
5365         ret = IRQ_HANDLED;
5366
5367 put_power:
5368         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5369
5370         return ret;
5371 }
5372
5373 /* check the VBT to see whether the eDP is on another port */
5374 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
5375 {
5376         /*
5377          * eDP not supported on g4x. so bail out early just
5378          * for a bit extra safety in case the VBT is bonkers.
5379          */
5380         if (INTEL_GEN(dev_priv) < 5)
5381                 return false;
5382
5383         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5384                 return true;
5385
5386         return intel_bios_is_port_edp(dev_priv, port);
5387 }
5388
5389 static void
5390 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5391 {
5392         struct drm_i915_private *dev_priv = to_i915(connector->dev);
5393         enum port port = dp_to_dig_port(intel_dp)->base.port;
5394
5395         if (!IS_G4X(dev_priv) && port != PORT_A)
5396                 intel_attach_force_audio_property(connector);
5397
5398         intel_attach_broadcast_rgb_property(connector);
5399
5400         if (intel_dp_is_edp(intel_dp)) {
5401                 u32 allowed_scalers;
5402
5403                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
5404                 if (!HAS_GMCH_DISPLAY(dev_priv))
5405                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
5406
5407                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
5408
5409                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
5410
5411         }
5412 }
5413
5414 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5415 {
5416         intel_dp->panel_power_off_time = ktime_get_boottime();
5417         intel_dp->last_power_on = jiffies;
5418         intel_dp->last_backlight_off = jiffies;
5419 }
5420
5421 static void
5422 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
5423 {
5424         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5425         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5426         struct pps_registers regs;
5427
5428         intel_pps_get_registers(intel_dp, &regs);
5429
5430         /* Workaround: Need to write PP_CONTROL with the unlock key as
5431          * the very first thing. */
5432         pp_ctl = ironlake_get_pp_control(intel_dp);
5433
5434         pp_on = I915_READ(regs.pp_on);
5435         pp_off = I915_READ(regs.pp_off);
5436         if (!IS_GEN9_LP(dev_priv) && !HAS_PCH_CNP(dev_priv) &&
5437             !HAS_PCH_ICP(dev_priv)) {
5438                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5439                 pp_div = I915_READ(regs.pp_div);
5440         }
5441
5442         /* Pull timing values out of registers */
5443         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5444                      PANEL_POWER_UP_DELAY_SHIFT;
5445
5446         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5447                   PANEL_LIGHT_ON_DELAY_SHIFT;
5448
5449         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5450                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5451
5452         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5453                    PANEL_POWER_DOWN_DELAY_SHIFT;
5454
5455         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5456             HAS_PCH_ICP(dev_priv)) {
5457                 seq->t11_t12 = ((pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5458                                 BXT_POWER_CYCLE_DELAY_SHIFT) * 1000;
5459         } else {
5460                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5461                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5462         }
5463 }
5464
5465 static void
5466 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5467 {
5468         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5469                       state_name,
5470                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5471 }
5472
5473 static void
5474 intel_pps_verify_state(struct intel_dp *intel_dp)
5475 {
5476         struct edp_power_seq hw;
5477         struct edp_power_seq *sw = &intel_dp->pps_delays;
5478
5479         intel_pps_readout_hw_state(intel_dp, &hw);
5480
5481         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5482             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5483                 DRM_ERROR("PPS state mismatch\n");
5484                 intel_pps_dump_state("sw", sw);
5485                 intel_pps_dump_state("hw", &hw);
5486         }
5487 }
5488
5489 static void
5490 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
5491 {
5492         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5493         struct edp_power_seq cur, vbt, spec,
5494                 *final = &intel_dp->pps_delays;
5495
5496         lockdep_assert_held(&dev_priv->pps_mutex);
5497
5498         /* already initialized? */
5499         if (final->t11_t12 != 0)
5500                 return;
5501
5502         intel_pps_readout_hw_state(intel_dp, &cur);
5503
5504         intel_pps_dump_state("cur", &cur);
5505
5506         vbt = dev_priv->vbt.edp.pps;
5507         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
5508          * of 500ms appears to be too short. Ocassionally the panel
5509          * just fails to power back on. Increasing the delay to 800ms
5510          * seems sufficient to avoid this problem.
5511          */
5512         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
5513                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
5514                 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n",
5515                               vbt.t11_t12);
5516         }
5517         /* T11_T12 delay is special and actually in units of 100ms, but zero
5518          * based in the hw (so we need to add 100 ms). But the sw vbt
5519          * table multiplies it with 1000 to make it in units of 100usec,
5520          * too. */
5521         vbt.t11_t12 += 100 * 10;
5522
5523         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5524          * our hw here, which are all in 100usec. */
5525         spec.t1_t3 = 210 * 10;
5526         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5527         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5528         spec.t10 = 500 * 10;
5529         /* This one is special and actually in units of 100ms, but zero
5530          * based in the hw (so we need to add 100 ms). But the sw vbt
5531          * table multiplies it with 1000 to make it in units of 100usec,
5532          * too. */
5533         spec.t11_t12 = (510 + 100) * 10;
5534
5535         intel_pps_dump_state("vbt", &vbt);
5536
5537         /* Use the max of the register settings and vbt. If both are
5538          * unset, fall back to the spec limits. */
5539 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5540                                        spec.field : \
5541                                        max(cur.field, vbt.field))
5542         assign_final(t1_t3);
5543         assign_final(t8);
5544         assign_final(t9);
5545         assign_final(t10);
5546         assign_final(t11_t12);
5547 #undef assign_final
5548
5549 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5550         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5551         intel_dp->backlight_on_delay = get_delay(t8);
5552         intel_dp->backlight_off_delay = get_delay(t9);
5553         intel_dp->panel_power_down_delay = get_delay(t10);
5554         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5555 #undef get_delay
5556
5557         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5558                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5559                       intel_dp->panel_power_cycle_delay);
5560
5561         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5562                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5563
5564         /*
5565          * We override the HW backlight delays to 1 because we do manual waits
5566          * on them. For T8, even BSpec recommends doing it. For T9, if we
5567          * don't do this, we'll end up waiting for the backlight off delay
5568          * twice: once when we do the manual sleep, and once when we disable
5569          * the panel and wait for the PP_STATUS bit to become zero.
5570          */
5571         final->t8 = 1;
5572         final->t9 = 1;
5573
5574         /*
5575          * HW has only a 100msec granularity for t11_t12 so round it up
5576          * accordingly.
5577          */
5578         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
5579 }
5580
5581 static void
5582 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
5583                                               bool force_disable_vdd)
5584 {
5585         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5586         u32 pp_on, pp_off, pp_div, port_sel = 0;
5587         int div = dev_priv->rawclk_freq / 1000;
5588         struct pps_registers regs;
5589         enum port port = dp_to_dig_port(intel_dp)->base.port;
5590         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5591
5592         lockdep_assert_held(&dev_priv->pps_mutex);
5593
5594         intel_pps_get_registers(intel_dp, &regs);
5595
5596         /*
5597          * On some VLV machines the BIOS can leave the VDD
5598          * enabled even on power sequencers which aren't
5599          * hooked up to any port. This would mess up the
5600          * power domain tracking the first time we pick
5601          * one of these power sequencers for use since
5602          * edp_panel_vdd_on() would notice that the VDD was
5603          * already on and therefore wouldn't grab the power
5604          * domain reference. Disable VDD first to avoid this.
5605          * This also avoids spuriously turning the VDD on as
5606          * soon as the new power sequencer gets initialized.
5607          */
5608         if (force_disable_vdd) {
5609                 u32 pp = ironlake_get_pp_control(intel_dp);
5610
5611                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5612
5613                 if (pp & EDP_FORCE_VDD)
5614                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5615
5616                 pp &= ~EDP_FORCE_VDD;
5617
5618                 I915_WRITE(regs.pp_ctrl, pp);
5619         }
5620
5621         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5622                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5623         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5624                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5625         /* Compute the divisor for the pp clock, simply match the Bspec
5626          * formula. */
5627         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5628             HAS_PCH_ICP(dev_priv)) {
5629                 pp_div = I915_READ(regs.pp_ctrl);
5630                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5631                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5632                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5633         } else {
5634                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5635                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5636                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5637         }
5638
5639         /* Haswell doesn't have any port selection bits for the panel
5640          * power sequencer any more. */
5641         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5642                 port_sel = PANEL_PORT_SELECT_VLV(port);
5643         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5644                 switch (port) {
5645                 case PORT_A:
5646                         port_sel = PANEL_PORT_SELECT_DPA;
5647                         break;
5648                 case PORT_C:
5649                         port_sel = PANEL_PORT_SELECT_DPC;
5650                         break;
5651                 case PORT_D:
5652                         port_sel = PANEL_PORT_SELECT_DPD;
5653                         break;
5654                 default:
5655                         MISSING_CASE(port);
5656                         break;
5657                 }
5658         }
5659
5660         pp_on |= port_sel;
5661
5662         I915_WRITE(regs.pp_on, pp_on);
5663         I915_WRITE(regs.pp_off, pp_off);
5664         if (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv) ||
5665             HAS_PCH_ICP(dev_priv))
5666                 I915_WRITE(regs.pp_ctrl, pp_div);
5667         else
5668                 I915_WRITE(regs.pp_div, pp_div);
5669
5670         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5671                       I915_READ(regs.pp_on),
5672                       I915_READ(regs.pp_off),
5673                       (IS_GEN9_LP(dev_priv) || HAS_PCH_CNP(dev_priv)  ||
5674                        HAS_PCH_ICP(dev_priv)) ?
5675                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5676                       I915_READ(regs.pp_div));
5677 }
5678
5679 static void intel_dp_pps_init(struct intel_dp *intel_dp)
5680 {
5681         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5682
5683         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5684                 vlv_initial_power_sequencer_setup(intel_dp);
5685         } else {
5686                 intel_dp_init_panel_power_sequencer(intel_dp);
5687                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
5688         }
5689 }
5690
5691 /**
5692  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5693  * @dev_priv: i915 device
5694  * @crtc_state: a pointer to the active intel_crtc_state
5695  * @refresh_rate: RR to be programmed
5696  *
5697  * This function gets called when refresh rate (RR) has to be changed from
5698  * one frequency to another. Switches can be between high and low RR
5699  * supported by the panel or to any other RR based on media playback (in
5700  * this case, RR value needs to be passed from user space).
5701  *
5702  * The caller of this function needs to take a lock on dev_priv->drrs.
5703  */
5704 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5705                                     const struct intel_crtc_state *crtc_state,
5706                                     int refresh_rate)
5707 {
5708         struct intel_encoder *encoder;
5709         struct intel_digital_port *dig_port = NULL;
5710         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5711         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5712         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5713
5714         if (refresh_rate <= 0) {
5715                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5716                 return;
5717         }
5718
5719         if (intel_dp == NULL) {
5720                 DRM_DEBUG_KMS("DRRS not supported.\n");
5721                 return;
5722         }
5723
5724         dig_port = dp_to_dig_port(intel_dp);
5725         encoder = &dig_port->base;
5726
5727         if (!intel_crtc) {
5728                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5729                 return;
5730         }
5731
5732         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5733                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5734                 return;
5735         }
5736
5737         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5738                         refresh_rate)
5739                 index = DRRS_LOW_RR;
5740
5741         if (index == dev_priv->drrs.refresh_rate_type) {
5742                 DRM_DEBUG_KMS(
5743                         "DRRS requested for previously set RR...ignoring\n");
5744                 return;
5745         }
5746
5747         if (!crtc_state->base.active) {
5748                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5749                 return;
5750         }
5751
5752         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5753                 switch (index) {
5754                 case DRRS_HIGH_RR:
5755                         intel_dp_set_m_n(intel_crtc, M1_N1);
5756                         break;
5757                 case DRRS_LOW_RR:
5758                         intel_dp_set_m_n(intel_crtc, M2_N2);
5759                         break;
5760                 case DRRS_MAX_RR:
5761                 default:
5762                         DRM_ERROR("Unsupported refreshrate type\n");
5763                 }
5764         } else if (INTEL_GEN(dev_priv) > 6) {
5765                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5766                 u32 val;
5767
5768                 val = I915_READ(reg);
5769                 if (index > DRRS_HIGH_RR) {
5770                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5771                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5772                         else
5773                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5774                 } else {
5775                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5776                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5777                         else
5778                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5779                 }
5780                 I915_WRITE(reg, val);
5781         }
5782
5783         dev_priv->drrs.refresh_rate_type = index;
5784
5785         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5786 }
5787
5788 /**
5789  * intel_edp_drrs_enable - init drrs struct if supported
5790  * @intel_dp: DP struct
5791  * @crtc_state: A pointer to the active crtc state.
5792  *
5793  * Initializes frontbuffer_bits and drrs.dp
5794  */
5795 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5796                            const struct intel_crtc_state *crtc_state)
5797 {
5798         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5799
5800         if (!crtc_state->has_drrs) {
5801                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5802                 return;
5803         }
5804
5805         if (dev_priv->psr.enabled) {
5806                 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n");
5807                 return;
5808         }
5809
5810         mutex_lock(&dev_priv->drrs.mutex);
5811         if (WARN_ON(dev_priv->drrs.dp)) {
5812                 DRM_ERROR("DRRS already enabled\n");
5813                 goto unlock;
5814         }
5815
5816         dev_priv->drrs.busy_frontbuffer_bits = 0;
5817
5818         dev_priv->drrs.dp = intel_dp;
5819
5820 unlock:
5821         mutex_unlock(&dev_priv->drrs.mutex);
5822 }
5823
5824 /**
5825  * intel_edp_drrs_disable - Disable DRRS
5826  * @intel_dp: DP struct
5827  * @old_crtc_state: Pointer to old crtc_state.
5828  *
5829  */
5830 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5831                             const struct intel_crtc_state *old_crtc_state)
5832 {
5833         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5834
5835         if (!old_crtc_state->has_drrs)
5836                 return;
5837
5838         mutex_lock(&dev_priv->drrs.mutex);
5839         if (!dev_priv->drrs.dp) {
5840                 mutex_unlock(&dev_priv->drrs.mutex);
5841                 return;
5842         }
5843
5844         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5845                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5846                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5847
5848         dev_priv->drrs.dp = NULL;
5849         mutex_unlock(&dev_priv->drrs.mutex);
5850
5851         cancel_delayed_work_sync(&dev_priv->drrs.work);
5852 }
5853
5854 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5855 {
5856         struct drm_i915_private *dev_priv =
5857                 container_of(work, typeof(*dev_priv), drrs.work.work);
5858         struct intel_dp *intel_dp;
5859
5860         mutex_lock(&dev_priv->drrs.mutex);
5861
5862         intel_dp = dev_priv->drrs.dp;
5863
5864         if (!intel_dp)
5865                 goto unlock;
5866
5867         /*
5868          * The delayed work can race with an invalidate hence we need to
5869          * recheck.
5870          */
5871
5872         if (dev_priv->drrs.busy_frontbuffer_bits)
5873                 goto unlock;
5874
5875         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5876                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5877
5878                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5879                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5880         }
5881
5882 unlock:
5883         mutex_unlock(&dev_priv->drrs.mutex);
5884 }
5885
5886 /**
5887  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5888  * @dev_priv: i915 device
5889  * @frontbuffer_bits: frontbuffer plane tracking bits
5890  *
5891  * This function gets called everytime rendering on the given planes start.
5892  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5893  *
5894  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5895  */
5896 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5897                                unsigned int frontbuffer_bits)
5898 {
5899         struct drm_crtc *crtc;
5900         enum pipe pipe;
5901
5902         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5903                 return;
5904
5905         cancel_delayed_work(&dev_priv->drrs.work);
5906
5907         mutex_lock(&dev_priv->drrs.mutex);
5908         if (!dev_priv->drrs.dp) {
5909                 mutex_unlock(&dev_priv->drrs.mutex);
5910                 return;
5911         }
5912
5913         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5914         pipe = to_intel_crtc(crtc)->pipe;
5915
5916         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5917         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5918
5919         /* invalidate means busy screen hence upclock */
5920         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5921                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5922                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5923
5924         mutex_unlock(&dev_priv->drrs.mutex);
5925 }
5926
5927 /**
5928  * intel_edp_drrs_flush - Restart Idleness DRRS
5929  * @dev_priv: i915 device
5930  * @frontbuffer_bits: frontbuffer plane tracking bits
5931  *
5932  * This function gets called every time rendering on the given planes has
5933  * completed or flip on a crtc is completed. So DRRS should be upclocked
5934  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5935  * if no other planes are dirty.
5936  *
5937  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5938  */
5939 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5940                           unsigned int frontbuffer_bits)
5941 {
5942         struct drm_crtc *crtc;
5943         enum pipe pipe;
5944
5945         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5946                 return;
5947
5948         cancel_delayed_work(&dev_priv->drrs.work);
5949
5950         mutex_lock(&dev_priv->drrs.mutex);
5951         if (!dev_priv->drrs.dp) {
5952                 mutex_unlock(&dev_priv->drrs.mutex);
5953                 return;
5954         }
5955
5956         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5957         pipe = to_intel_crtc(crtc)->pipe;
5958
5959         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5960         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5961
5962         /* flush means busy screen hence upclock */
5963         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5964                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5965                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5966
5967         /*
5968          * flush also means no more activity hence schedule downclock, if all
5969          * other fbs are quiescent too
5970          */
5971         if (!dev_priv->drrs.busy_frontbuffer_bits)
5972                 schedule_delayed_work(&dev_priv->drrs.work,
5973                                 msecs_to_jiffies(1000));
5974         mutex_unlock(&dev_priv->drrs.mutex);
5975 }
5976
5977 /**
5978  * DOC: Display Refresh Rate Switching (DRRS)
5979  *
5980  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5981  * which enables swtching between low and high refresh rates,
5982  * dynamically, based on the usage scenario. This feature is applicable
5983  * for internal panels.
5984  *
5985  * Indication that the panel supports DRRS is given by the panel EDID, which
5986  * would list multiple refresh rates for one resolution.
5987  *
5988  * DRRS is of 2 types - static and seamless.
5989  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5990  * (may appear as a blink on screen) and is used in dock-undock scenario.
5991  * Seamless DRRS involves changing RR without any visual effect to the user
5992  * and can be used during normal system usage. This is done by programming
5993  * certain registers.
5994  *
5995  * Support for static/seamless DRRS may be indicated in the VBT based on
5996  * inputs from the panel spec.
5997  *
5998  * DRRS saves power by switching to low RR based on usage scenarios.
5999  *
6000  * The implementation is based on frontbuffer tracking implementation.  When
6001  * there is a disturbance on the screen triggered by user activity or a periodic
6002  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
6003  * no movement on screen, after a timeout of 1 second, a switch to low RR is
6004  * made.
6005  *
6006  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
6007  * and intel_edp_drrs_flush() are called.
6008  *
6009  * DRRS can be further extended to support other internal panels and also
6010  * the scenario of video playback wherein RR is set based on the rate
6011  * requested by userspace.
6012  */
6013
6014 /**
6015  * intel_dp_drrs_init - Init basic DRRS work and mutex.
6016  * @connector: eDP connector
6017  * @fixed_mode: preferred mode of panel
6018  *
6019  * This function is  called only once at driver load to initialize basic
6020  * DRRS stuff.
6021  *
6022  * Returns:
6023  * Downclock mode if panel supports it, else return NULL.
6024  * DRRS support is determined by the presence of downclock mode (apart
6025  * from VBT setting).
6026  */
6027 static struct drm_display_mode *
6028 intel_dp_drrs_init(struct intel_connector *connector,
6029                    struct drm_display_mode *fixed_mode)
6030 {
6031         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6032         struct drm_display_mode *downclock_mode = NULL;
6033
6034         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
6035         mutex_init(&dev_priv->drrs.mutex);
6036
6037         if (INTEL_GEN(dev_priv) <= 6) {
6038                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
6039                 return NULL;
6040         }
6041
6042         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
6043                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
6044                 return NULL;
6045         }
6046
6047         downclock_mode = intel_find_panel_downclock(dev_priv, fixed_mode,
6048                                                     &connector->base);
6049
6050         if (!downclock_mode) {
6051                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
6052                 return NULL;
6053         }
6054
6055         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
6056
6057         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
6058         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
6059         return downclock_mode;
6060 }
6061
6062 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
6063                                      struct intel_connector *intel_connector)
6064 {
6065         struct drm_device *dev = intel_dp_to_dev(intel_dp);
6066         struct drm_i915_private *dev_priv = to_i915(dev);
6067         struct drm_connector *connector = &intel_connector->base;
6068         struct drm_display_mode *fixed_mode = NULL;
6069         struct drm_display_mode *downclock_mode = NULL;
6070         bool has_dpcd;
6071         struct drm_display_mode *scan;
6072         struct edid *edid;
6073         enum pipe pipe = INVALID_PIPE;
6074
6075         if (!intel_dp_is_edp(intel_dp))
6076                 return true;
6077
6078         /*
6079          * On IBX/CPT we may get here with LVDS already registered. Since the
6080          * driver uses the only internal power sequencer available for both
6081          * eDP and LVDS bail out early in this case to prevent interfering
6082          * with an already powered-on LVDS power sequencer.
6083          */
6084         if (intel_get_lvds_encoder(&dev_priv->drm)) {
6085                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
6086                 DRM_INFO("LVDS was detected, not registering eDP\n");
6087
6088                 return false;
6089         }
6090
6091         pps_lock(intel_dp);
6092
6093         intel_dp_init_panel_power_timestamps(intel_dp);
6094         intel_dp_pps_init(intel_dp);
6095         intel_edp_panel_vdd_sanitize(intel_dp);
6096
6097         pps_unlock(intel_dp);
6098
6099         /* Cache DPCD and EDID for edp. */
6100         has_dpcd = intel_edp_init_dpcd(intel_dp);
6101
6102         if (!has_dpcd) {
6103                 /* if this fails, presume the device is a ghost */
6104                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
6105                 goto out_vdd_off;
6106         }
6107
6108         mutex_lock(&dev->mode_config.mutex);
6109         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
6110         if (edid) {
6111                 if (drm_add_edid_modes(connector, edid)) {
6112                         drm_connector_update_edid_property(connector,
6113                                                                 edid);
6114                 } else {
6115                         kfree(edid);
6116                         edid = ERR_PTR(-EINVAL);
6117                 }
6118         } else {
6119                 edid = ERR_PTR(-ENOENT);
6120         }
6121         intel_connector->edid = edid;
6122
6123         /* prefer fixed mode from EDID if available */
6124         list_for_each_entry(scan, &connector->probed_modes, head) {
6125                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
6126                         fixed_mode = drm_mode_duplicate(dev, scan);
6127                         downclock_mode = intel_dp_drrs_init(
6128                                                 intel_connector, fixed_mode);
6129                         break;
6130                 }
6131         }
6132
6133         /* fallback to VBT if available for eDP */
6134         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
6135                 fixed_mode = drm_mode_duplicate(dev,
6136                                         dev_priv->vbt.lfp_lvds_vbt_mode);
6137                 if (fixed_mode) {
6138                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
6139                         connector->display_info.width_mm = fixed_mode->width_mm;
6140                         connector->display_info.height_mm = fixed_mode->height_mm;
6141                 }
6142         }
6143         mutex_unlock(&dev->mode_config.mutex);
6144
6145         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6146                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
6147                 register_reboot_notifier(&intel_dp->edp_notifier);
6148
6149                 /*
6150                  * Figure out the current pipe for the initial backlight setup.
6151                  * If the current pipe isn't valid, try the PPS pipe, and if that
6152                  * fails just assume pipe A.
6153                  */
6154                 pipe = vlv_active_pipe(intel_dp);
6155
6156                 if (pipe != PIPE_A && pipe != PIPE_B)
6157                         pipe = intel_dp->pps_pipe;
6158
6159                 if (pipe != PIPE_A && pipe != PIPE_B)
6160                         pipe = PIPE_A;
6161
6162                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
6163                               pipe_name(pipe));
6164         }
6165
6166         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
6167         intel_connector->panel.backlight.power = intel_edp_backlight_power;
6168         intel_panel_setup_backlight(connector, pipe);
6169
6170         return true;
6171
6172 out_vdd_off:
6173         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6174         /*
6175          * vdd might still be enabled do to the delayed vdd off.
6176          * Make sure vdd is actually turned off here.
6177          */
6178         pps_lock(intel_dp);
6179         edp_panel_vdd_off_sync(intel_dp);
6180         pps_unlock(intel_dp);
6181
6182         return false;
6183 }
6184
6185 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
6186 {
6187         struct intel_connector *intel_connector;
6188         struct drm_connector *connector;
6189
6190         intel_connector = container_of(work, typeof(*intel_connector),
6191                                        modeset_retry_work);
6192         connector = &intel_connector->base;
6193         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
6194                       connector->name);
6195
6196         /* Grab the locks before changing connector property*/
6197         mutex_lock(&connector->dev->mode_config.mutex);
6198         /* Set connector link status to BAD and send a Uevent to notify
6199          * userspace to do a modeset.
6200          */
6201         drm_connector_set_link_status_property(connector,
6202                                                DRM_MODE_LINK_STATUS_BAD);
6203         mutex_unlock(&connector->dev->mode_config.mutex);
6204         /* Send Hotplug uevent so userspace can reprobe */
6205         drm_kms_helper_hotplug_event(connector->dev);
6206 }
6207
6208 bool
6209 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
6210                         struct intel_connector *intel_connector)
6211 {
6212         struct drm_connector *connector = &intel_connector->base;
6213         struct intel_dp *intel_dp = &intel_dig_port->dp;
6214         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6215         struct drm_device *dev = intel_encoder->base.dev;
6216         struct drm_i915_private *dev_priv = to_i915(dev);
6217         enum port port = intel_encoder->port;
6218         int type;
6219
6220         /* Initialize the work for modeset in case of link train failure */
6221         INIT_WORK(&intel_connector->modeset_retry_work,
6222                   intel_dp_modeset_retry_work_fn);
6223
6224         if (WARN(intel_dig_port->max_lanes < 1,
6225                  "Not enough lanes (%d) for DP on port %c\n",
6226                  intel_dig_port->max_lanes, port_name(port)))
6227                 return false;
6228
6229         intel_dp_set_source_rates(intel_dp);
6230
6231         intel_dp->reset_link_params = true;
6232         intel_dp->pps_pipe = INVALID_PIPE;
6233         intel_dp->active_pipe = INVALID_PIPE;
6234
6235         /* intel_dp vfuncs */
6236         if (HAS_DDI(dev_priv))
6237                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6238
6239         /* Preserve the current hw state. */
6240         intel_dp->DP = I915_READ(intel_dp->output_reg);
6241         intel_dp->attached_connector = intel_connector;
6242
6243         if (intel_dp_is_port_edp(dev_priv, port))
6244                 type = DRM_MODE_CONNECTOR_eDP;
6245         else
6246                 type = DRM_MODE_CONNECTOR_DisplayPort;
6247
6248         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6249                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6250
6251         /*
6252          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6253          * for DP the encoder type can be set by the caller to
6254          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6255          */
6256         if (type == DRM_MODE_CONNECTOR_eDP)
6257                 intel_encoder->type = INTEL_OUTPUT_EDP;
6258
6259         /* eDP only on port B and/or C on vlv/chv */
6260         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6261                     intel_dp_is_edp(intel_dp) &&
6262                     port != PORT_B && port != PORT_C))
6263                 return false;
6264
6265         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6266                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6267                         port_name(port));
6268
6269         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6270         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6271
6272         if (!HAS_GMCH_DISPLAY(dev_priv))
6273                 connector->interlace_allowed = true;
6274         connector->doublescan_allowed = 0;
6275
6276         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
6277
6278         intel_dp_aux_init(intel_dp);
6279
6280         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6281                           edp_panel_vdd_work);
6282
6283         intel_connector_attach_encoder(intel_connector, intel_encoder);
6284
6285         if (HAS_DDI(dev_priv))
6286                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6287         else
6288                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6289
6290         /* init MST on ports that can support it */
6291         intel_dp_mst_encoder_init(intel_dig_port,
6292                                   intel_connector->base.base.id);
6293
6294         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6295                 intel_dp_aux_fini(intel_dp);
6296                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6297                 goto fail;
6298         }
6299
6300         intel_dp_add_properties(intel_dp, connector);
6301
6302         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
6303                 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim);
6304                 if (ret)
6305                         DRM_DEBUG_KMS("HDCP init failed, skipping.\n");
6306         }
6307
6308         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6309          * 0xd.  Failure to do so will result in spurious interrupts being
6310          * generated on the port when a cable is not attached.
6311          */
6312         if (IS_G45(dev_priv)) {
6313                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6314                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6315         }
6316
6317         return true;
6318
6319 fail:
6320         drm_connector_cleanup(connector);
6321
6322         return false;
6323 }
6324
6325 bool intel_dp_init(struct drm_i915_private *dev_priv,
6326                    i915_reg_t output_reg,
6327                    enum port port)
6328 {
6329         struct intel_digital_port *intel_dig_port;
6330         struct intel_encoder *intel_encoder;
6331         struct drm_encoder *encoder;
6332         struct intel_connector *intel_connector;
6333
6334         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6335         if (!intel_dig_port)
6336                 return false;
6337
6338         intel_connector = intel_connector_alloc();
6339         if (!intel_connector)
6340                 goto err_connector_alloc;
6341
6342         intel_encoder = &intel_dig_port->base;
6343         encoder = &intel_encoder->base;
6344
6345         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6346                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6347                              "DP %c", port_name(port)))
6348                 goto err_encoder_init;
6349
6350         intel_encoder->hotplug = intel_dp_hotplug;
6351         intel_encoder->compute_config = intel_dp_compute_config;
6352         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6353         intel_encoder->get_config = intel_dp_get_config;
6354         intel_encoder->suspend = intel_dp_encoder_suspend;
6355         if (IS_CHERRYVIEW(dev_priv)) {
6356                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6357                 intel_encoder->pre_enable = chv_pre_enable_dp;
6358                 intel_encoder->enable = vlv_enable_dp;
6359                 intel_encoder->disable = vlv_disable_dp;
6360                 intel_encoder->post_disable = chv_post_disable_dp;
6361                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6362         } else if (IS_VALLEYVIEW(dev_priv)) {
6363                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6364                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6365                 intel_encoder->enable = vlv_enable_dp;
6366                 intel_encoder->disable = vlv_disable_dp;
6367                 intel_encoder->post_disable = vlv_post_disable_dp;
6368         } else {
6369                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6370                 intel_encoder->enable = g4x_enable_dp;
6371                 intel_encoder->disable = g4x_disable_dp;
6372                 intel_encoder->post_disable = g4x_post_disable_dp;
6373         }
6374
6375         intel_dig_port->dp.output_reg = output_reg;
6376         intel_dig_port->max_lanes = 4;
6377
6378         intel_encoder->type = INTEL_OUTPUT_DP;
6379         intel_encoder->power_domain = intel_port_to_power_domain(port);
6380         if (IS_CHERRYVIEW(dev_priv)) {
6381                 if (port == PORT_D)
6382                         intel_encoder->crtc_mask = 1 << 2;
6383                 else
6384                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6385         } else {
6386                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6387         }
6388         intel_encoder->cloneable = 0;
6389         intel_encoder->port = port;
6390
6391         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6392
6393         if (port != PORT_A)
6394                 intel_infoframe_init(intel_dig_port);
6395
6396         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6397                 goto err_init_connector;
6398
6399         return true;
6400
6401 err_init_connector:
6402         drm_encoder_cleanup(encoder);
6403 err_encoder_init:
6404         kfree(intel_connector);
6405 err_connector_alloc:
6406         kfree(intel_dig_port);
6407         return false;
6408 }
6409
6410 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
6411 {
6412         struct intel_encoder *encoder;
6413
6414         for_each_intel_encoder(&dev_priv->drm, encoder) {
6415                 struct intel_dp *intel_dp;
6416
6417                 if (encoder->type != INTEL_OUTPUT_DDI)
6418                         continue;
6419
6420                 intel_dp = enc_to_intel_dp(&encoder->base);
6421
6422                 if (!intel_dp->can_mst)
6423                         continue;
6424
6425                 if (intel_dp->is_mst)
6426                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
6427         }
6428 }
6429
6430 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
6431 {
6432         struct intel_encoder *encoder;
6433
6434         for_each_intel_encoder(&dev_priv->drm, encoder) {
6435                 struct intel_dp *intel_dp;
6436                 int ret;
6437
6438                 if (encoder->type != INTEL_OUTPUT_DDI)
6439                         continue;
6440
6441                 intel_dp = enc_to_intel_dp(&encoder->base);
6442
6443                 if (!intel_dp->can_mst)
6444                         continue;
6445
6446                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr);
6447                 if (ret)
6448                         intel_dp_check_mst_status(intel_dp);
6449         }
6450 }