2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include "intel_frontbuffer.h"
38 #include <drm/i915_drm.h>
40 #include "i915_gem_dmabuf.h"
41 #include "intel_dsi.h"
42 #include "i915_trace.h"
43 #include <drm/drm_atomic.h>
44 #include <drm/drm_atomic_helper.h>
45 #include <drm/drm_dp_helper.h>
46 #include <drm/drm_crtc_helper.h>
47 #include <drm/drm_plane_helper.h>
48 #include <drm/drm_rect.h>
49 #include <linux/dma_remapping.h>
50 #include <linux/reservation.h>
52 static bool is_mmio_work(struct intel_flip_work *work)
54 return work->mmio_work.func;
57 /* Primary plane formats for gen <= 3 */
58 static const uint32_t i8xx_primary_formats[] = {
65 /* Primary plane formats for gen >= 4 */
66 static const uint32_t i965_primary_formats[] = {
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
75 static const uint32_t skl_primary_formats[] = {
82 DRM_FORMAT_XRGB2101010,
83 DRM_FORMAT_XBGR2101010,
91 static const uint32_t intel_cursor_formats[] = {
95 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
96 struct intel_crtc_state *pipe_config);
97 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
98 struct intel_crtc_state *pipe_config);
100 static int intel_framebuffer_init(struct drm_device *dev,
101 struct intel_framebuffer *ifb,
102 struct drm_mode_fb_cmd2 *mode_cmd,
103 struct drm_i915_gem_object *obj);
104 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
105 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
106 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
107 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
108 struct intel_link_m_n *m_n,
109 struct intel_link_m_n *m2_n2);
110 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
111 static void haswell_set_pipeconf(struct drm_crtc *crtc);
112 static void haswell_set_pipemisc(struct drm_crtc *crtc);
113 static void vlv_prepare_pll(struct intel_crtc *crtc,
114 const struct intel_crtc_state *pipe_config);
115 static void chv_prepare_pll(struct intel_crtc *crtc,
116 const struct intel_crtc_state *pipe_config);
117 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
118 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
119 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
120 struct intel_crtc_state *crtc_state);
121 static void skylake_pfit_enable(struct intel_crtc *crtc);
122 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
123 static void ironlake_pfit_enable(struct intel_crtc *crtc);
124 static void intel_modeset_setup_hw_state(struct drm_device *dev);
125 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
126 static int ilk_max_pixel_rate(struct drm_atomic_state *state);
127 static int bxt_calc_cdclk(int max_pixclk);
132 } dot, vco, n, m, m1, m2, p, p1;
136 int p2_slow, p2_fast;
140 /* returns HPLL frequency in kHz */
141 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
143 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
145 /* Obtain SKU information */
146 mutex_lock(&dev_priv->sb_lock);
147 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
148 CCK_FUSE_HPLL_FREQ_MASK;
149 mutex_unlock(&dev_priv->sb_lock);
151 return vco_freq[hpll_freq] * 1000;
154 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
155 const char *name, u32 reg, int ref_freq)
160 mutex_lock(&dev_priv->sb_lock);
161 val = vlv_cck_read(dev_priv, reg);
162 mutex_unlock(&dev_priv->sb_lock);
164 divider = val & CCK_FREQUENCY_VALUES;
166 WARN((val & CCK_FREQUENCY_STATUS) !=
167 (divider << CCK_FREQUENCY_STATUS_SHIFT),
168 "%s change in progress\n", name);
170 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
173 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
174 const char *name, u32 reg)
176 if (dev_priv->hpll_freq == 0)
177 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
179 return vlv_get_cck_clock(dev_priv, name, reg,
180 dev_priv->hpll_freq);
184 intel_pch_rawclk(struct drm_i915_private *dev_priv)
186 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
190 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
192 /* RAWCLK_FREQ_VLV register updated from power well code */
193 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
194 CCK_DISPLAY_REF_CLOCK_CONTROL);
198 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
202 /* hrawclock is 1/4 the FSB frequency */
203 clkcfg = I915_READ(CLKCFG);
204 switch (clkcfg & CLKCFG_FSB_MASK) {
213 case CLKCFG_FSB_1067:
215 case CLKCFG_FSB_1333:
217 /* these two are just a guess; one of them might be right */
218 case CLKCFG_FSB_1600:
219 case CLKCFG_FSB_1600_ALT:
226 void intel_update_rawclk(struct drm_i915_private *dev_priv)
228 if (HAS_PCH_SPLIT(dev_priv))
229 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
230 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
231 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
232 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
233 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
235 return; /* no rawclk on other platforms, or no need to know it */
237 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
240 static void intel_update_czclk(struct drm_i915_private *dev_priv)
242 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
245 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
246 CCK_CZ_CLOCK_CONTROL);
248 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
251 static inline u32 /* units of 100MHz */
252 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
253 const struct intel_crtc_state *pipe_config)
255 if (HAS_DDI(dev_priv))
256 return pipe_config->port_clock; /* SPLL */
257 else if (IS_GEN5(dev_priv))
258 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
263 static const struct intel_limit intel_limits_i8xx_dac = {
264 .dot = { .min = 25000, .max = 350000 },
265 .vco = { .min = 908000, .max = 1512000 },
266 .n = { .min = 2, .max = 16 },
267 .m = { .min = 96, .max = 140 },
268 .m1 = { .min = 18, .max = 26 },
269 .m2 = { .min = 6, .max = 16 },
270 .p = { .min = 4, .max = 128 },
271 .p1 = { .min = 2, .max = 33 },
272 .p2 = { .dot_limit = 165000,
273 .p2_slow = 4, .p2_fast = 2 },
276 static const struct intel_limit intel_limits_i8xx_dvo = {
277 .dot = { .min = 25000, .max = 350000 },
278 .vco = { .min = 908000, .max = 1512000 },
279 .n = { .min = 2, .max = 16 },
280 .m = { .min = 96, .max = 140 },
281 .m1 = { .min = 18, .max = 26 },
282 .m2 = { .min = 6, .max = 16 },
283 .p = { .min = 4, .max = 128 },
284 .p1 = { .min = 2, .max = 33 },
285 .p2 = { .dot_limit = 165000,
286 .p2_slow = 4, .p2_fast = 4 },
289 static const struct intel_limit intel_limits_i8xx_lvds = {
290 .dot = { .min = 25000, .max = 350000 },
291 .vco = { .min = 908000, .max = 1512000 },
292 .n = { .min = 2, .max = 16 },
293 .m = { .min = 96, .max = 140 },
294 .m1 = { .min = 18, .max = 26 },
295 .m2 = { .min = 6, .max = 16 },
296 .p = { .min = 4, .max = 128 },
297 .p1 = { .min = 1, .max = 6 },
298 .p2 = { .dot_limit = 165000,
299 .p2_slow = 14, .p2_fast = 7 },
302 static const struct intel_limit intel_limits_i9xx_sdvo = {
303 .dot = { .min = 20000, .max = 400000 },
304 .vco = { .min = 1400000, .max = 2800000 },
305 .n = { .min = 1, .max = 6 },
306 .m = { .min = 70, .max = 120 },
307 .m1 = { .min = 8, .max = 18 },
308 .m2 = { .min = 3, .max = 7 },
309 .p = { .min = 5, .max = 80 },
310 .p1 = { .min = 1, .max = 8 },
311 .p2 = { .dot_limit = 200000,
312 .p2_slow = 10, .p2_fast = 5 },
315 static const struct intel_limit intel_limits_i9xx_lvds = {
316 .dot = { .min = 20000, .max = 400000 },
317 .vco = { .min = 1400000, .max = 2800000 },
318 .n = { .min = 1, .max = 6 },
319 .m = { .min = 70, .max = 120 },
320 .m1 = { .min = 8, .max = 18 },
321 .m2 = { .min = 3, .max = 7 },
322 .p = { .min = 7, .max = 98 },
323 .p1 = { .min = 1, .max = 8 },
324 .p2 = { .dot_limit = 112000,
325 .p2_slow = 14, .p2_fast = 7 },
329 static const struct intel_limit intel_limits_g4x_sdvo = {
330 .dot = { .min = 25000, .max = 270000 },
331 .vco = { .min = 1750000, .max = 3500000},
332 .n = { .min = 1, .max = 4 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 10, .max = 30 },
337 .p1 = { .min = 1, .max = 3},
338 .p2 = { .dot_limit = 270000,
344 static const struct intel_limit intel_limits_g4x_hdmi = {
345 .dot = { .min = 22000, .max = 400000 },
346 .vco = { .min = 1750000, .max = 3500000},
347 .n = { .min = 1, .max = 4 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 16, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 5, .max = 80 },
352 .p1 = { .min = 1, .max = 8},
353 .p2 = { .dot_limit = 165000,
354 .p2_slow = 10, .p2_fast = 5 },
357 static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
358 .dot = { .min = 20000, .max = 115000 },
359 .vco = { .min = 1750000, .max = 3500000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 104, .max = 138 },
362 .m1 = { .min = 17, .max = 23 },
363 .m2 = { .min = 5, .max = 11 },
364 .p = { .min = 28, .max = 112 },
365 .p1 = { .min = 2, .max = 8 },
366 .p2 = { .dot_limit = 0,
367 .p2_slow = 14, .p2_fast = 14
371 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
372 .dot = { .min = 80000, .max = 224000 },
373 .vco = { .min = 1750000, .max = 3500000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 104, .max = 138 },
376 .m1 = { .min = 17, .max = 23 },
377 .m2 = { .min = 5, .max = 11 },
378 .p = { .min = 14, .max = 42 },
379 .p1 = { .min = 2, .max = 6 },
380 .p2 = { .dot_limit = 0,
381 .p2_slow = 7, .p2_fast = 7
385 static const struct intel_limit intel_limits_pineview_sdvo = {
386 .dot = { .min = 20000, .max = 400000},
387 .vco = { .min = 1700000, .max = 3500000 },
388 /* Pineview's Ncounter is a ring counter */
389 .n = { .min = 3, .max = 6 },
390 .m = { .min = 2, .max = 256 },
391 /* Pineview only has one combined m divider, which we treat as m2. */
392 .m1 = { .min = 0, .max = 0 },
393 .m2 = { .min = 0, .max = 254 },
394 .p = { .min = 5, .max = 80 },
395 .p1 = { .min = 1, .max = 8 },
396 .p2 = { .dot_limit = 200000,
397 .p2_slow = 10, .p2_fast = 5 },
400 static const struct intel_limit intel_limits_pineview_lvds = {
401 .dot = { .min = 20000, .max = 400000 },
402 .vco = { .min = 1700000, .max = 3500000 },
403 .n = { .min = 3, .max = 6 },
404 .m = { .min = 2, .max = 256 },
405 .m1 = { .min = 0, .max = 0 },
406 .m2 = { .min = 0, .max = 254 },
407 .p = { .min = 7, .max = 112 },
408 .p1 = { .min = 1, .max = 8 },
409 .p2 = { .dot_limit = 112000,
410 .p2_slow = 14, .p2_fast = 14 },
413 /* Ironlake / Sandybridge
415 * We calculate clock using (register_value + 2) for N/M1/M2, so here
416 * the range value for them is (actual_value - 2).
418 static const struct intel_limit intel_limits_ironlake_dac = {
419 .dot = { .min = 25000, .max = 350000 },
420 .vco = { .min = 1760000, .max = 3510000 },
421 .n = { .min = 1, .max = 5 },
422 .m = { .min = 79, .max = 127 },
423 .m1 = { .min = 12, .max = 22 },
424 .m2 = { .min = 5, .max = 9 },
425 .p = { .min = 5, .max = 80 },
426 .p1 = { .min = 1, .max = 8 },
427 .p2 = { .dot_limit = 225000,
428 .p2_slow = 10, .p2_fast = 5 },
431 static const struct intel_limit intel_limits_ironlake_single_lvds = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 3 },
435 .m = { .min = 79, .max = 118 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
444 static const struct intel_limit intel_limits_ironlake_dual_lvds = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 127 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 56 },
452 .p1 = { .min = 2, .max = 8 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
457 /* LVDS 100mhz refclk limits. */
458 static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
459 .dot = { .min = 25000, .max = 350000 },
460 .vco = { .min = 1760000, .max = 3510000 },
461 .n = { .min = 1, .max = 2 },
462 .m = { .min = 79, .max = 126 },
463 .m1 = { .min = 12, .max = 22 },
464 .m2 = { .min = 5, .max = 9 },
465 .p = { .min = 28, .max = 112 },
466 .p1 = { .min = 2, .max = 8 },
467 .p2 = { .dot_limit = 225000,
468 .p2_slow = 14, .p2_fast = 14 },
471 static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
472 .dot = { .min = 25000, .max = 350000 },
473 .vco = { .min = 1760000, .max = 3510000 },
474 .n = { .min = 1, .max = 3 },
475 .m = { .min = 79, .max = 126 },
476 .m1 = { .min = 12, .max = 22 },
477 .m2 = { .min = 5, .max = 9 },
478 .p = { .min = 14, .max = 42 },
479 .p1 = { .min = 2, .max = 6 },
480 .p2 = { .dot_limit = 225000,
481 .p2_slow = 7, .p2_fast = 7 },
484 static const struct intel_limit intel_limits_vlv = {
486 * These are the data rate limits (measured in fast clocks)
487 * since those are the strictest limits we have. The fast
488 * clock and actual rate limits are more relaxed, so checking
489 * them would make no difference.
491 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
492 .vco = { .min = 4000000, .max = 6000000 },
493 .n = { .min = 1, .max = 7 },
494 .m1 = { .min = 2, .max = 3 },
495 .m2 = { .min = 11, .max = 156 },
496 .p1 = { .min = 2, .max = 3 },
497 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
500 static const struct intel_limit intel_limits_chv = {
502 * These are the data rate limits (measured in fast clocks)
503 * since those are the strictest limits we have. The fast
504 * clock and actual rate limits are more relaxed, so checking
505 * them would make no difference.
507 .dot = { .min = 25000 * 5, .max = 540000 * 5},
508 .vco = { .min = 4800000, .max = 6480000 },
509 .n = { .min = 1, .max = 1 },
510 .m1 = { .min = 2, .max = 2 },
511 .m2 = { .min = 24 << 22, .max = 175 << 22 },
512 .p1 = { .min = 2, .max = 4 },
513 .p2 = { .p2_slow = 1, .p2_fast = 14 },
516 static const struct intel_limit intel_limits_bxt = {
517 /* FIXME: find real dot limits */
518 .dot = { .min = 0, .max = INT_MAX },
519 .vco = { .min = 4800000, .max = 6700000 },
520 .n = { .min = 1, .max = 1 },
521 .m1 = { .min = 2, .max = 2 },
522 /* FIXME: find real m2 limits */
523 .m2 = { .min = 2 << 22, .max = 255 << 22 },
524 .p1 = { .min = 2, .max = 4 },
525 .p2 = { .p2_slow = 1, .p2_fast = 20 },
529 needs_modeset(struct drm_crtc_state *state)
531 return drm_atomic_crtc_needs_modeset(state);
535 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
536 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
537 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
538 * The helpers' return value is the rate of the clock that is fed to the
539 * display engine's pipe which can be the above fast dot clock rate or a
540 * divided-down version of it.
542 /* m1 is reserved as 0 in Pineview, n is a ring counter */
543 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
545 clock->m = clock->m2 + 2;
546 clock->p = clock->p1 * clock->p2;
547 if (WARN_ON(clock->n == 0 || clock->p == 0))
549 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
550 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
557 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
560 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
562 clock->m = i9xx_dpll_compute_m(clock);
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
572 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
574 clock->m = clock->m1 * clock->m2;
575 clock->p = clock->p1 * clock->p2;
576 if (WARN_ON(clock->n == 0 || clock->p == 0))
578 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
579 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
581 return clock->dot / 5;
584 int chv_calc_dpll_params(int refclk, struct dpll *clock)
586 clock->m = clock->m1 * clock->m2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594 return clock->dot / 5;
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
603 static bool intel_PLL_is_valid(struct drm_device *dev,
604 const struct intel_limit *limit,
605 const struct dpll *clock)
607 if (clock->n < limit->n.min || limit->n.max < clock->n)
608 INTELPllInvalid("n out of range\n");
609 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
614 INTELPllInvalid("m1 out of range\n");
616 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
617 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
621 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
629 INTELPllInvalid("vco out of range\n");
630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
634 INTELPllInvalid("dot out of range\n");
640 i9xx_select_p2_div(const struct intel_limit *limit,
641 const struct intel_crtc_state *crtc_state,
644 struct drm_device *dev = crtc_state->base.crtc->dev;
646 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
648 * For LVDS just rely on its current settings for dual-channel.
649 * We haven't figured out how to reliably set up different
650 * single/dual channel state, if we even can.
652 if (intel_is_dual_link_lvds(dev))
653 return limit->p2.p2_fast;
655 return limit->p2.p2_slow;
657 if (target < limit->p2.dot_limit)
658 return limit->p2.p2_slow;
660 return limit->p2.p2_fast;
665 * Returns a set of divisors for the desired target clock with the given
666 * refclk, or FALSE. The returned values represent the clock equation:
667 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
669 * Target and reference clocks are specified in kHz.
671 * If match_clock is provided, then best_clock P divider must match the P
672 * divider from @match_clock used for LVDS downclocking.
675 i9xx_find_best_dpll(const struct intel_limit *limit,
676 struct intel_crtc_state *crtc_state,
677 int target, int refclk, struct dpll *match_clock,
678 struct dpll *best_clock)
680 struct drm_device *dev = crtc_state->base.crtc->dev;
684 memset(best_clock, 0, sizeof(*best_clock));
686 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
688 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
690 for (clock.m2 = limit->m2.min;
691 clock.m2 <= limit->m2.max; clock.m2++) {
692 if (clock.m2 >= clock.m1)
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
700 i9xx_calc_dpll_params(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
705 clock.p != match_clock->p)
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
718 return (err != target);
722 * Returns a set of divisors for the desired target clock with the given
723 * refclk, or FALSE. The returned values represent the clock equation:
724 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
726 * Target and reference clocks are specified in kHz.
728 * If match_clock is provided, then best_clock P divider must match the P
729 * divider from @match_clock used for LVDS downclocking.
732 pnv_find_best_dpll(const struct intel_limit *limit,
733 struct intel_crtc_state *crtc_state,
734 int target, int refclk, struct dpll *match_clock,
735 struct dpll *best_clock)
737 struct drm_device *dev = crtc_state->base.crtc->dev;
741 memset(best_clock, 0, sizeof(*best_clock));
743 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
747 for (clock.m2 = limit->m2.min;
748 clock.m2 <= limit->m2.max; clock.m2++) {
749 for (clock.n = limit->n.min;
750 clock.n <= limit->n.max; clock.n++) {
751 for (clock.p1 = limit->p1.min;
752 clock.p1 <= limit->p1.max; clock.p1++) {
755 pnv_calc_dpll_params(refclk, &clock);
756 if (!intel_PLL_is_valid(dev, limit,
760 clock.p != match_clock->p)
763 this_err = abs(clock.dot - target);
764 if (this_err < err) {
773 return (err != target);
777 * Returns a set of divisors for the desired target clock with the given
778 * refclk, or FALSE. The returned values represent the clock equation:
779 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
781 * Target and reference clocks are specified in kHz.
783 * If match_clock is provided, then best_clock P divider must match the P
784 * divider from @match_clock used for LVDS downclocking.
787 g4x_find_best_dpll(const struct intel_limit *limit,
788 struct intel_crtc_state *crtc_state,
789 int target, int refclk, struct dpll *match_clock,
790 struct dpll *best_clock)
792 struct drm_device *dev = crtc_state->base.crtc->dev;
796 /* approximately equals target * 0.00585 */
797 int err_most = (target >> 8) + (target >> 9);
799 memset(best_clock, 0, sizeof(*best_clock));
801 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
803 max_n = limit->n.max;
804 /* based on hardware requirement, prefer smaller n to precision */
805 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
806 /* based on hardware requirement, prefere larger m1,m2 */
807 for (clock.m1 = limit->m1.max;
808 clock.m1 >= limit->m1.min; clock.m1--) {
809 for (clock.m2 = limit->m2.max;
810 clock.m2 >= limit->m2.min; clock.m2--) {
811 for (clock.p1 = limit->p1.max;
812 clock.p1 >= limit->p1.min; clock.p1--) {
815 i9xx_calc_dpll_params(refclk, &clock);
816 if (!intel_PLL_is_valid(dev, limit,
820 this_err = abs(clock.dot - target);
821 if (this_err < err_most) {
835 * Check if the calculated PLL configuration is more optimal compared to the
836 * best configuration and error found so far. Return the calculated error.
838 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
839 const struct dpll *calculated_clock,
840 const struct dpll *best_clock,
841 unsigned int best_error_ppm,
842 unsigned int *error_ppm)
845 * For CHV ignore the error and consider only the P value.
846 * Prefer a bigger P value based on HW requirements.
848 if (IS_CHERRYVIEW(dev)) {
851 return calculated_clock->p > best_clock->p;
854 if (WARN_ON_ONCE(!target_freq))
857 *error_ppm = div_u64(1000000ULL *
858 abs(target_freq - calculated_clock->dot),
861 * Prefer a better P value over a better (smaller) error if the error
862 * is small. Ensure this preference for future configurations too by
863 * setting the error to 0.
865 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
871 return *error_ppm + 10 < best_error_ppm;
875 * Returns a set of divisors for the desired target clock with the given
876 * refclk, or FALSE. The returned values represent the clock equation:
877 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
880 vlv_find_best_dpll(const struct intel_limit *limit,
881 struct intel_crtc_state *crtc_state,
882 int target, int refclk, struct dpll *match_clock,
883 struct dpll *best_clock)
885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
886 struct drm_device *dev = crtc->base.dev;
888 unsigned int bestppm = 1000000;
889 /* min update 19.2 MHz */
890 int max_n = min(limit->n.max, refclk / 19200);
893 target *= 5; /* fast clock */
895 memset(best_clock, 0, sizeof(*best_clock));
897 /* based on hardware requirement, prefer smaller n to precision */
898 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
899 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
900 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
901 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
902 clock.p = clock.p1 * clock.p2;
903 /* based on hardware requirement, prefer bigger m1,m2 values */
904 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
907 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
910 vlv_calc_dpll_params(refclk, &clock);
912 if (!intel_PLL_is_valid(dev, limit,
916 if (!vlv_PLL_is_optimal(dev, target,
934 * Returns a set of divisors for the desired target clock with the given
935 * refclk, or FALSE. The returned values represent the clock equation:
936 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
939 chv_find_best_dpll(const struct intel_limit *limit,
940 struct intel_crtc_state *crtc_state,
941 int target, int refclk, struct dpll *match_clock,
942 struct dpll *best_clock)
944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
945 struct drm_device *dev = crtc->base.dev;
946 unsigned int best_error_ppm;
951 memset(best_clock, 0, sizeof(*best_clock));
952 best_error_ppm = 1000000;
955 * Based on hardware doc, the n always set to 1, and m1 always
956 * set to 2. If requires to support 200Mhz refclk, we need to
957 * revisit this because n may not 1 anymore.
959 clock.n = 1, clock.m1 = 2;
960 target *= 5; /* fast clock */
962 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
963 for (clock.p2 = limit->p2.p2_fast;
964 clock.p2 >= limit->p2.p2_slow;
965 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
966 unsigned int error_ppm;
968 clock.p = clock.p1 * clock.p2;
970 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
971 clock.n) << 22, refclk * clock.m1);
973 if (m2 > INT_MAX/clock.m1)
978 chv_calc_dpll_params(refclk, &clock);
980 if (!intel_PLL_is_valid(dev, limit, &clock))
983 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
984 best_error_ppm, &error_ppm))
988 best_error_ppm = error_ppm;
996 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
997 struct dpll *best_clock)
1000 const struct intel_limit *limit = &intel_limits_bxt;
1002 return chv_find_best_dpll(limit, crtc_state,
1003 target_clock, refclk, NULL, best_clock);
1006 bool intel_crtc_active(struct drm_crtc *crtc)
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1010 /* Be paranoid as we can arrive here with only partial
1011 * state retrieved from the hardware during setup.
1013 * We can ditch the adjusted_mode.crtc_clock check as soon
1014 * as Haswell has gained clock readout/fastboot support.
1016 * We can ditch the crtc->primary->fb check as soon as we can
1017 * properly reconstruct framebuffers.
1019 * FIXME: The intel_crtc->active here should be switched to
1020 * crtc->state->active once we have proper CRTC states wired up
1023 return intel_crtc->active && crtc->primary->state->fb &&
1024 intel_crtc->config->base.adjusted_mode.crtc_clock;
1027 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1030 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1033 return intel_crtc->config->cpu_transcoder;
1036 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1038 struct drm_i915_private *dev_priv = to_i915(dev);
1039 i915_reg_t reg = PIPEDSL(pipe);
1044 line_mask = DSL_LINEMASK_GEN2;
1046 line_mask = DSL_LINEMASK_GEN3;
1048 line1 = I915_READ(reg) & line_mask;
1050 line2 = I915_READ(reg) & line_mask;
1052 return line1 == line2;
1056 * intel_wait_for_pipe_off - wait for pipe to turn off
1057 * @crtc: crtc whose pipe to wait for
1059 * After disabling a pipe, we can't wait for vblank in the usual way,
1060 * spinning on the vblank interrupt status bit, since we won't actually
1061 * see an interrupt when the pipe is disabled.
1063 * On Gen4 and above:
1064 * wait for the pipe register state bit to turn off
1067 * wait for the display line value to settle (it usually
1068 * ends up stopping at the start of the next frame).
1071 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1073 struct drm_device *dev = crtc->base.dev;
1074 struct drm_i915_private *dev_priv = to_i915(dev);
1075 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1076 enum pipe pipe = crtc->pipe;
1078 if (INTEL_INFO(dev)->gen >= 4) {
1079 i915_reg_t reg = PIPECONF(cpu_transcoder);
1081 /* Wait for the Pipe State to go off */
1082 if (intel_wait_for_register(dev_priv,
1083 reg, I965_PIPECONF_ACTIVE, 0,
1085 WARN(1, "pipe_off wait timed out\n");
1087 /* Wait for the display line to settle */
1088 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1089 WARN(1, "pipe_off wait timed out\n");
1093 /* Only for pre-ILK configs */
1094 void assert_pll(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, bool state)
1100 val = I915_READ(DPLL(pipe));
1101 cur_state = !!(val & DPLL_VCO_ENABLE);
1102 I915_STATE_WARN(cur_state != state,
1103 "PLL state assertion failure (expected %s, current %s)\n",
1104 onoff(state), onoff(cur_state));
1107 /* XXX: the dsi pll is shared between MIPI DSI ports */
1108 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1113 mutex_lock(&dev_priv->sb_lock);
1114 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1115 mutex_unlock(&dev_priv->sb_lock);
1117 cur_state = val & DSI_PLL_VCO_EN;
1118 I915_STATE_WARN(cur_state != state,
1119 "DSI PLL state assertion failure (expected %s, current %s)\n",
1120 onoff(state), onoff(cur_state));
1123 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1130 if (HAS_DDI(dev_priv)) {
1131 /* DDI does not have a specific FDI_TX register */
1132 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1133 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135 u32 val = I915_READ(FDI_TX_CTL(pipe));
1136 cur_state = !!(val & FDI_TX_ENABLE);
1138 I915_STATE_WARN(cur_state != state,
1139 "FDI TX state assertion failure (expected %s, current %s)\n",
1140 onoff(state), onoff(cur_state));
1142 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1143 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1145 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1146 enum pipe pipe, bool state)
1151 val = I915_READ(FDI_RX_CTL(pipe));
1152 cur_state = !!(val & FDI_RX_ENABLE);
1153 I915_STATE_WARN(cur_state != state,
1154 "FDI RX state assertion failure (expected %s, current %s)\n",
1155 onoff(state), onoff(cur_state));
1157 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1158 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1160 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1165 /* ILK FDI PLL is always enabled */
1166 if (IS_GEN5(dev_priv))
1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (HAS_DDI(dev_priv))
1173 val = I915_READ(FDI_TX_CTL(pipe));
1174 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1177 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1178 enum pipe pipe, bool state)
1183 val = I915_READ(FDI_RX_CTL(pipe));
1184 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1185 I915_STATE_WARN(cur_state != state,
1186 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1187 onoff(state), onoff(cur_state));
1190 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1193 struct drm_device *dev = &dev_priv->drm;
1196 enum pipe panel_pipe = PIPE_A;
1199 if (WARN_ON(HAS_DDI(dev)))
1202 if (HAS_PCH_SPLIT(dev)) {
1205 pp_reg = PP_CONTROL(0);
1206 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
1208 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1209 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211 /* XXX: else fix for eDP */
1212 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213 /* presumably write lock depends on pipe, not port select */
1214 pp_reg = PP_CONTROL(pipe);
1217 pp_reg = PP_CONTROL(0);
1218 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1219 panel_pipe = PIPE_B;
1222 val = I915_READ(pp_reg);
1223 if (!(val & PANEL_POWER_ON) ||
1224 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1227 I915_STATE_WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1232 static void assert_cursor(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1235 struct drm_device *dev = &dev_priv->drm;
1238 if (IS_845G(dev) || IS_I865G(dev))
1239 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1241 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1243 I915_STATE_WARN(cur_state != state,
1244 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1245 pipe_name(pipe), onoff(state), onoff(cur_state));
1247 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1248 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1250 void assert_pipe(struct drm_i915_private *dev_priv,
1251 enum pipe pipe, bool state)
1254 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1256 enum intel_display_power_domain power_domain;
1258 /* if we need the pipe quirk it must be always on */
1259 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1263 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1264 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1265 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1266 cur_state = !!(val & PIPECONF_ENABLE);
1268 intel_display_power_put(dev_priv, power_domain);
1273 I915_STATE_WARN(cur_state != state,
1274 "pipe %c assertion failure (expected %s, current %s)\n",
1275 pipe_name(pipe), onoff(state), onoff(cur_state));
1278 static void assert_plane(struct drm_i915_private *dev_priv,
1279 enum plane plane, bool state)
1284 val = I915_READ(DSPCNTR(plane));
1285 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1286 I915_STATE_WARN(cur_state != state,
1287 "plane %c assertion failure (expected %s, current %s)\n",
1288 plane_name(plane), onoff(state), onoff(cur_state));
1291 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1292 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1294 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1297 struct drm_device *dev = &dev_priv->drm;
1300 /* Primary planes are fixed to pipes on gen4+ */
1301 if (INTEL_INFO(dev)->gen >= 4) {
1302 u32 val = I915_READ(DSPCNTR(pipe));
1303 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1304 "plane %c assertion failure, should be disabled but not\n",
1309 /* Need to check both planes against the pipe */
1310 for_each_pipe(dev_priv, i) {
1311 u32 val = I915_READ(DSPCNTR(i));
1312 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1313 DISPPLANE_SEL_PIPE_SHIFT;
1314 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1315 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1316 plane_name(i), pipe_name(pipe));
1320 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1323 struct drm_device *dev = &dev_priv->drm;
1326 if (INTEL_INFO(dev)->gen >= 9) {
1327 for_each_sprite(dev_priv, pipe, sprite) {
1328 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1329 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1330 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1331 sprite, pipe_name(pipe));
1333 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1334 for_each_sprite(dev_priv, pipe, sprite) {
1335 u32 val = I915_READ(SPCNTR(pipe, sprite));
1336 I915_STATE_WARN(val & SP_ENABLE,
1337 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1338 sprite_name(pipe, sprite), pipe_name(pipe));
1340 } else if (INTEL_INFO(dev)->gen >= 7) {
1341 u32 val = I915_READ(SPRCTL(pipe));
1342 I915_STATE_WARN(val & SPRITE_ENABLE,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 plane_name(pipe), pipe_name(pipe));
1345 } else if (INTEL_INFO(dev)->gen >= 5) {
1346 u32 val = I915_READ(DVSCNTR(pipe));
1347 I915_STATE_WARN(val & DVS_ENABLE,
1348 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1349 plane_name(pipe), pipe_name(pipe));
1353 static void assert_vblank_disabled(struct drm_crtc *crtc)
1355 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1356 drm_crtc_vblank_put(crtc);
1359 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1365 val = I915_READ(PCH_TRANSCONF(pipe));
1366 enabled = !!(val & TRANS_ENABLE);
1367 I915_STATE_WARN(enabled,
1368 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1372 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1373 enum pipe pipe, u32 port_sel, u32 val)
1375 if ((val & DP_PORT_EN) == 0)
1378 if (HAS_PCH_CPT(dev_priv)) {
1379 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1380 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1382 } else if (IS_CHERRYVIEW(dev_priv)) {
1383 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1386 if ((val & DP_PIPE_MASK) != (pipe << 30))
1392 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1395 if ((val & SDVO_ENABLE) == 0)
1398 if (HAS_PCH_CPT(dev_priv)) {
1399 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1401 } else if (IS_CHERRYVIEW(dev_priv)) {
1402 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1405 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1411 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe, u32 val)
1414 if ((val & LVDS_PORT_EN) == 0)
1417 if (HAS_PCH_CPT(dev_priv)) {
1418 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1421 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1427 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1428 enum pipe pipe, u32 val)
1430 if ((val & ADPA_DAC_ENABLE) == 0)
1432 if (HAS_PCH_CPT(dev_priv)) {
1433 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1436 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1442 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1443 enum pipe pipe, i915_reg_t reg,
1446 u32 val = I915_READ(reg);
1447 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1448 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1449 i915_mmio_reg_offset(reg), pipe_name(pipe));
1451 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
1452 && (val & DP_PIPEB_SELECT),
1453 "IBX PCH dp port still using transcoder B\n");
1456 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1457 enum pipe pipe, i915_reg_t reg)
1459 u32 val = I915_READ(reg);
1460 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1461 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1462 i915_mmio_reg_offset(reg), pipe_name(pipe));
1464 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
1465 && (val & SDVO_PIPE_B_SELECT),
1466 "IBX PCH hdmi port still using transcoder B\n");
1469 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1476 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1478 val = I915_READ(PCH_ADPA);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1483 val = I915_READ(PCH_LVDS);
1484 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1485 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1493 static void _vlv_enable_pll(struct intel_crtc *crtc,
1494 const struct intel_crtc_state *pipe_config)
1496 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1497 enum pipe pipe = crtc->pipe;
1499 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1500 POSTING_READ(DPLL(pipe));
1503 if (intel_wait_for_register(dev_priv,
1508 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1511 static void vlv_enable_pll(struct intel_crtc *crtc,
1512 const struct intel_crtc_state *pipe_config)
1514 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1515 enum pipe pipe = crtc->pipe;
1517 assert_pipe_disabled(dev_priv, pipe);
1519 /* PLL is protected by panel, make sure we can write it */
1520 assert_panel_unlocked(dev_priv, pipe);
1522 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1523 _vlv_enable_pll(crtc, pipe_config);
1525 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1526 POSTING_READ(DPLL_MD(pipe));
1530 static void _chv_enable_pll(struct intel_crtc *crtc,
1531 const struct intel_crtc_state *pipe_config)
1533 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1534 enum pipe pipe = crtc->pipe;
1535 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1538 mutex_lock(&dev_priv->sb_lock);
1540 /* Enable back the 10bit clock to display controller */
1541 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1542 tmp |= DPIO_DCLKP_EN;
1543 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1545 mutex_unlock(&dev_priv->sb_lock);
1548 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1553 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1555 /* Check PLL is locked */
1556 if (intel_wait_for_register(dev_priv,
1557 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1559 DRM_ERROR("PLL %d failed to lock\n", pipe);
1562 static void chv_enable_pll(struct intel_crtc *crtc,
1563 const struct intel_crtc_state *pipe_config)
1565 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1566 enum pipe pipe = crtc->pipe;
1568 assert_pipe_disabled(dev_priv, pipe);
1570 /* PLL is protected by panel, make sure we can write it */
1571 assert_panel_unlocked(dev_priv, pipe);
1573 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1574 _chv_enable_pll(crtc, pipe_config);
1576 if (pipe != PIPE_A) {
1578 * WaPixelRepeatModeFixForC0:chv
1580 * DPLLCMD is AWOL. Use chicken bits to propagate
1581 * the value from DPLLBMD to either pipe B or C.
1583 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1584 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1585 I915_WRITE(CBR4_VLV, 0);
1586 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1589 * DPLLB VGA mode also seems to cause problems.
1590 * We should always have it disabled.
1592 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1594 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1595 POSTING_READ(DPLL_MD(pipe));
1599 static int intel_num_dvo_pipes(struct drm_device *dev)
1601 struct intel_crtc *crtc;
1604 for_each_intel_crtc(dev, crtc) {
1605 count += crtc->base.state->active &&
1606 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1614 struct drm_device *dev = crtc->base.dev;
1615 struct drm_i915_private *dev_priv = to_i915(dev);
1616 i915_reg_t reg = DPLL(crtc->pipe);
1617 u32 dpll = crtc->config->dpll_hw_state.dpll;
1619 assert_pipe_disabled(dev_priv, crtc->pipe);
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev) && !IS_I830(dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1625 /* Enable DVO 2x clock on both PLLs if necessary */
1626 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1628 * It appears to be important that we don't enable this
1629 * for the current pipe before otherwise configuring the
1630 * PLL. No idea how this should be handled if multiple
1631 * DVO outputs are enabled simultaneosly.
1633 dpll |= DPLL_DVO_2X_MODE;
1634 I915_WRITE(DPLL(!crtc->pipe),
1635 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1639 * Apparently we need to have VGA mode enabled prior to changing
1640 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1641 * dividers, even though the register value does change.
1645 I915_WRITE(reg, dpll);
1647 /* Wait for the clocks to stabilize. */
1651 if (INTEL_INFO(dev)->gen >= 4) {
1652 I915_WRITE(DPLL_MD(crtc->pipe),
1653 crtc->config->dpll_hw_state.dpll_md);
1655 /* The pixel multiplier can only be updated once the
1656 * DPLL is enabled and the clocks are stable.
1658 * So write it again.
1660 I915_WRITE(reg, dpll);
1663 /* We do this three times for luck */
1664 I915_WRITE(reg, dpll);
1666 udelay(150); /* wait for warmup */
1667 I915_WRITE(reg, dpll);
1669 udelay(150); /* wait for warmup */
1670 I915_WRITE(reg, dpll);
1672 udelay(150); /* wait for warmup */
1676 * i9xx_disable_pll - disable a PLL
1677 * @dev_priv: i915 private structure
1678 * @pipe: pipe PLL to disable
1680 * Disable the PLL for @pipe, making sure the pipe is off first.
1682 * Note! This is for pre-ILK only.
1684 static void i9xx_disable_pll(struct intel_crtc *crtc)
1686 struct drm_device *dev = crtc->base.dev;
1687 struct drm_i915_private *dev_priv = to_i915(dev);
1688 enum pipe pipe = crtc->pipe;
1690 /* Disable DVO 2x clock on both PLLs if necessary */
1692 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
1693 !intel_num_dvo_pipes(dev)) {
1694 I915_WRITE(DPLL(PIPE_B),
1695 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1696 I915_WRITE(DPLL(PIPE_A),
1697 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1700 /* Don't disable pipe or pipe PLLs if needed */
1701 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1702 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1705 /* Make sure the pipe isn't still relying on us */
1706 assert_pipe_disabled(dev_priv, pipe);
1708 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1709 POSTING_READ(DPLL(pipe));
1712 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1716 /* Make sure the pipe isn't still relying on us */
1717 assert_pipe_disabled(dev_priv, pipe);
1719 val = DPLL_INTEGRATED_REF_CLK_VLV |
1720 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1722 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1724 I915_WRITE(DPLL(pipe), val);
1725 POSTING_READ(DPLL(pipe));
1728 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1730 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1733 /* Make sure the pipe isn't still relying on us */
1734 assert_pipe_disabled(dev_priv, pipe);
1736 val = DPLL_SSC_REF_CLK_CHV |
1737 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1739 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1741 I915_WRITE(DPLL(pipe), val);
1742 POSTING_READ(DPLL(pipe));
1744 mutex_lock(&dev_priv->sb_lock);
1746 /* Disable 10bit clock to display controller */
1747 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1748 val &= ~DPIO_DCLKP_EN;
1749 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1751 mutex_unlock(&dev_priv->sb_lock);
1754 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1755 struct intel_digital_port *dport,
1756 unsigned int expected_mask)
1759 i915_reg_t dpll_reg;
1761 switch (dport->port) {
1763 port_mask = DPLL_PORTB_READY_MASK;
1767 port_mask = DPLL_PORTC_READY_MASK;
1769 expected_mask <<= 4;
1772 port_mask = DPLL_PORTD_READY_MASK;
1773 dpll_reg = DPIO_PHY_STATUS;
1779 if (intel_wait_for_register(dev_priv,
1780 dpll_reg, port_mask, expected_mask,
1782 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1783 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1786 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1789 struct drm_device *dev = &dev_priv->drm;
1790 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1793 uint32_t val, pipeconf_val;
1795 /* Make sure PCH DPLL is enabled */
1796 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1798 /* FDI must be feeding us bits for PCH ports */
1799 assert_fdi_tx_enabled(dev_priv, pipe);
1800 assert_fdi_rx_enabled(dev_priv, pipe);
1802 if (HAS_PCH_CPT(dev)) {
1803 /* Workaround: Set the timing override bit before enabling the
1804 * pch transcoder. */
1805 reg = TRANS_CHICKEN2(pipe);
1806 val = I915_READ(reg);
1807 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1808 I915_WRITE(reg, val);
1811 reg = PCH_TRANSCONF(pipe);
1812 val = I915_READ(reg);
1813 pipeconf_val = I915_READ(PIPECONF(pipe));
1815 if (HAS_PCH_IBX(dev_priv)) {
1817 * Make the BPC in transcoder be consistent with
1818 * that in pipeconf reg. For HDMI we must use 8bpc
1819 * here for both 8bpc and 12bpc.
1821 val &= ~PIPECONF_BPC_MASK;
1822 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
1823 val |= PIPECONF_8BPC;
1825 val |= pipeconf_val & PIPECONF_BPC_MASK;
1828 val &= ~TRANS_INTERLACE_MASK;
1829 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1830 if (HAS_PCH_IBX(dev_priv) &&
1831 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
1832 val |= TRANS_LEGACY_INTERLACED_ILK;
1834 val |= TRANS_INTERLACED;
1836 val |= TRANS_PROGRESSIVE;
1838 I915_WRITE(reg, val | TRANS_ENABLE);
1839 if (intel_wait_for_register(dev_priv,
1840 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1842 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1845 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1846 enum transcoder cpu_transcoder)
1848 u32 val, pipeconf_val;
1850 /* FDI must be feeding us bits for PCH ports */
1851 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1852 assert_fdi_rx_enabled(dev_priv, PIPE_A);
1854 /* Workaround: set timing override bit. */
1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1856 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1860 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1862 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1863 PIPECONF_INTERLACED_ILK)
1864 val |= TRANS_INTERLACED;
1866 val |= TRANS_PROGRESSIVE;
1868 I915_WRITE(LPT_TRANSCONF, val);
1869 if (intel_wait_for_register(dev_priv,
1874 DRM_ERROR("Failed to enable PCH transcoder\n");
1877 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1880 struct drm_device *dev = &dev_priv->drm;
1884 /* FDI relies on the transcoder */
1885 assert_fdi_tx_disabled(dev_priv, pipe);
1886 assert_fdi_rx_disabled(dev_priv, pipe);
1888 /* Ports must be off as well */
1889 assert_pch_ports_disabled(dev_priv, pipe);
1891 reg = PCH_TRANSCONF(pipe);
1892 val = I915_READ(reg);
1893 val &= ~TRANS_ENABLE;
1894 I915_WRITE(reg, val);
1895 /* wait for PCH transcoder off, transcoder state */
1896 if (intel_wait_for_register(dev_priv,
1897 reg, TRANS_STATE_ENABLE, 0,
1899 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1901 if (HAS_PCH_CPT(dev)) {
1902 /* Workaround: Clear the timing override chicken bit again. */
1903 reg = TRANS_CHICKEN2(pipe);
1904 val = I915_READ(reg);
1905 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1906 I915_WRITE(reg, val);
1910 void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1914 val = I915_READ(LPT_TRANSCONF);
1915 val &= ~TRANS_ENABLE;
1916 I915_WRITE(LPT_TRANSCONF, val);
1917 /* wait for PCH transcoder off, transcoder state */
1918 if (intel_wait_for_register(dev_priv,
1919 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1921 DRM_ERROR("Failed to disable PCH transcoder\n");
1923 /* Workaround: clear timing override bit. */
1924 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1925 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1926 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1930 * intel_enable_pipe - enable a pipe, asserting requirements
1931 * @crtc: crtc responsible for the pipe
1933 * Enable @crtc's pipe, making sure that various hardware specific requirements
1934 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1936 static void intel_enable_pipe(struct intel_crtc *crtc)
1938 struct drm_device *dev = crtc->base.dev;
1939 struct drm_i915_private *dev_priv = to_i915(dev);
1940 enum pipe pipe = crtc->pipe;
1941 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1942 enum pipe pch_transcoder;
1946 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1948 assert_planes_disabled(dev_priv, pipe);
1949 assert_cursor_disabled(dev_priv, pipe);
1950 assert_sprites_disabled(dev_priv, pipe);
1952 if (HAS_PCH_LPT(dev_priv))
1953 pch_transcoder = PIPE_A;
1955 pch_transcoder = pipe;
1958 * A pipe without a PLL won't actually be able to drive bits from
1959 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1962 if (HAS_GMCH_DISPLAY(dev_priv)) {
1963 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
1964 assert_dsi_pll_enabled(dev_priv);
1966 assert_pll_enabled(dev_priv, pipe);
1968 if (crtc->config->has_pch_encoder) {
1969 /* if driving the PCH, we need FDI enabled */
1970 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1971 assert_fdi_tx_pll_enabled(dev_priv,
1972 (enum pipe) cpu_transcoder);
1974 /* FIXME: assert CPU port conditions for SNB+ */
1977 reg = PIPECONF(cpu_transcoder);
1978 val = I915_READ(reg);
1979 if (val & PIPECONF_ENABLE) {
1980 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1981 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1985 I915_WRITE(reg, val | PIPECONF_ENABLE);
1989 * Until the pipe starts DSL will read as 0, which would cause
1990 * an apparent vblank timestamp jump, which messes up also the
1991 * frame count when it's derived from the timestamps. So let's
1992 * wait for the pipe to start properly before we call
1993 * drm_crtc_vblank_on()
1995 if (dev->max_vblank_count == 0 &&
1996 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1997 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2001 * intel_disable_pipe - disable a pipe, asserting requirements
2002 * @crtc: crtc whose pipes is to be disabled
2004 * Disable the pipe of @crtc, making sure that various hardware
2005 * specific requirements are met, if applicable, e.g. plane
2006 * disabled, panel fitter off, etc.
2008 * Will wait until the pipe has shut down before returning.
2010 static void intel_disable_pipe(struct intel_crtc *crtc)
2012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2013 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2014 enum pipe pipe = crtc->pipe;
2018 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2021 * Make sure planes won't keep trying to pump pixels to us,
2022 * or we might hang the display.
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2028 reg = PIPECONF(cpu_transcoder);
2029 val = I915_READ(reg);
2030 if ((val & PIPECONF_ENABLE) == 0)
2034 * Double wide has implications for planes
2035 * so best keep it disabled when not needed.
2037 if (crtc->config->double_wide)
2038 val &= ~PIPECONF_DOUBLE_WIDE;
2040 /* Don't disable pipe or pipe PLLs if needed */
2041 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2042 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2043 val &= ~PIPECONF_ENABLE;
2045 I915_WRITE(reg, val);
2046 if ((val & PIPECONF_ENABLE) == 0)
2047 intel_wait_for_pipe_off(crtc);
2050 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2052 return IS_GEN2(dev_priv) ? 2048 : 4096;
2055 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2056 uint64_t fb_modifier, unsigned int cpp)
2058 switch (fb_modifier) {
2059 case DRM_FORMAT_MOD_NONE:
2061 case I915_FORMAT_MOD_X_TILED:
2062 if (IS_GEN2(dev_priv))
2066 case I915_FORMAT_MOD_Y_TILED:
2067 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2071 case I915_FORMAT_MOD_Yf_TILED:
2087 MISSING_CASE(fb_modifier);
2092 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2093 uint64_t fb_modifier, unsigned int cpp)
2095 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2098 return intel_tile_size(dev_priv) /
2099 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2102 /* Return the tile dimensions in pixel units */
2103 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2104 unsigned int *tile_width,
2105 unsigned int *tile_height,
2106 uint64_t fb_modifier,
2109 unsigned int tile_width_bytes =
2110 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2112 *tile_width = tile_width_bytes / cpp;
2113 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2117 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2118 uint32_t pixel_format, uint64_t fb_modifier)
2120 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2121 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2123 return ALIGN(height, tile_height);
2126 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2128 unsigned int size = 0;
2131 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2132 size += rot_info->plane[i].width * rot_info->plane[i].height;
2138 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2139 const struct drm_framebuffer *fb,
2140 unsigned int rotation)
2142 if (intel_rotation_90_or_270(rotation)) {
2143 *view = i915_ggtt_view_rotated;
2144 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2146 *view = i915_ggtt_view_normal;
2150 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2152 if (INTEL_INFO(dev_priv)->gen >= 9)
2154 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2155 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2157 else if (INTEL_INFO(dev_priv)->gen >= 4)
2163 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2164 uint64_t fb_modifier)
2166 switch (fb_modifier) {
2167 case DRM_FORMAT_MOD_NONE:
2168 return intel_linear_alignment(dev_priv);
2169 case I915_FORMAT_MOD_X_TILED:
2170 if (INTEL_INFO(dev_priv)->gen >= 9)
2173 case I915_FORMAT_MOD_Y_TILED:
2174 case I915_FORMAT_MOD_Yf_TILED:
2175 return 1 * 1024 * 1024;
2177 MISSING_CASE(fb_modifier);
2183 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2185 struct drm_device *dev = fb->dev;
2186 struct drm_i915_private *dev_priv = to_i915(dev);
2187 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2188 struct i915_ggtt_view view;
2189 struct i915_vma *vma;
2192 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2194 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2196 intel_fill_fb_ggtt_view(&view, fb, rotation);
2198 /* Note that the w/a also requires 64 PTE of padding following the
2199 * bo. We currently fill all unused PTE with the shadow page and so
2200 * we should always have valid PTE following the scanout preventing
2203 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
2204 alignment = 256 * 1024;
2207 * Global gtt pte registers are special registers which actually forward
2208 * writes to a chunk of system memory. Which means that there is no risk
2209 * that the register values disappear as soon as we call
2210 * intel_runtime_pm_put(), so it is correct to wrap only the
2211 * pin/unpin/fence and not more.
2213 intel_runtime_pm_get(dev_priv);
2215 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
2219 if (i915_vma_is_map_and_fenceable(vma)) {
2220 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2221 * fence, whereas 965+ only requires a fence if using
2222 * framebuffer compression. For simplicity, we always, when
2223 * possible, install a fence as the cost is not that onerous.
2225 * If we fail to fence the tiled scanout, then either the
2226 * modeset will reject the change (which is highly unlikely as
2227 * the affected systems, all but one, do not have unmappable
2228 * space) or we will not be able to enable full powersaving
2229 * techniques (also likely not to apply due to various limits
2230 * FBC and the like impose on the size of the buffer, which
2231 * presumably we violated anyway with this unmappable buffer).
2232 * Anyway, it is presumably better to stumble onwards with
2233 * something and try to run the system in a "less than optimal"
2234 * mode that matches the user configuration.
2236 if (i915_vma_get_fence(vma) == 0)
2237 i915_vma_pin_fence(vma);
2241 intel_runtime_pm_put(dev_priv);
2245 void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2247 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2248 struct i915_ggtt_view view;
2249 struct i915_vma *vma;
2251 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2253 intel_fill_fb_ggtt_view(&view, fb, rotation);
2254 vma = i915_gem_object_to_ggtt(obj, &view);
2256 if (WARN_ON_ONCE(!vma))
2259 i915_vma_unpin_fence(vma);
2260 i915_gem_object_unpin_from_display_plane(vma);
2263 static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2264 unsigned int rotation)
2266 if (intel_rotation_90_or_270(rotation))
2267 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2269 return fb->pitches[plane];
2273 * Convert the x/y offsets into a linear offset.
2274 * Only valid with 0/180 degree rotation, which is fine since linear
2275 * offset is only used with linear buffers on pre-hsw and tiled buffers
2276 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2278 u32 intel_fb_xy_to_linear(int x, int y,
2279 const struct intel_plane_state *state,
2282 const struct drm_framebuffer *fb = state->base.fb;
2283 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2284 unsigned int pitch = fb->pitches[plane];
2286 return y * pitch + x * cpp;
2290 * Add the x/y offsets derived from fb->offsets[] to the user
2291 * specified plane src x/y offsets. The resulting x/y offsets
2292 * specify the start of scanout from the beginning of the gtt mapping.
2294 void intel_add_fb_offsets(int *x, int *y,
2295 const struct intel_plane_state *state,
2299 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2300 unsigned int rotation = state->base.rotation;
2302 if (intel_rotation_90_or_270(rotation)) {
2303 *x += intel_fb->rotated[plane].x;
2304 *y += intel_fb->rotated[plane].y;
2306 *x += intel_fb->normal[plane].x;
2307 *y += intel_fb->normal[plane].y;
2312 * Input tile dimensions and pitch must already be
2313 * rotated to match x and y, and in pixel units.
2315 static u32 _intel_adjust_tile_offset(int *x, int *y,
2316 unsigned int tile_width,
2317 unsigned int tile_height,
2318 unsigned int tile_size,
2319 unsigned int pitch_tiles,
2323 unsigned int pitch_pixels = pitch_tiles * tile_width;
2326 WARN_ON(old_offset & (tile_size - 1));
2327 WARN_ON(new_offset & (tile_size - 1));
2328 WARN_ON(new_offset > old_offset);
2330 tiles = (old_offset - new_offset) / tile_size;
2332 *y += tiles / pitch_tiles * tile_height;
2333 *x += tiles % pitch_tiles * tile_width;
2335 /* minimize x in case it got needlessly big */
2336 *y += *x / pitch_pixels * tile_height;
2343 * Adjust the tile offset by moving the difference into
2346 static u32 intel_adjust_tile_offset(int *x, int *y,
2347 const struct intel_plane_state *state, int plane,
2348 u32 old_offset, u32 new_offset)
2350 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2351 const struct drm_framebuffer *fb = state->base.fb;
2352 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2353 unsigned int rotation = state->base.rotation;
2354 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2356 WARN_ON(new_offset > old_offset);
2358 if (fb->modifier[plane] != DRM_FORMAT_MOD_NONE) {
2359 unsigned int tile_size, tile_width, tile_height;
2360 unsigned int pitch_tiles;
2362 tile_size = intel_tile_size(dev_priv);
2363 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2364 fb->modifier[plane], cpp);
2366 if (intel_rotation_90_or_270(rotation)) {
2367 pitch_tiles = pitch / tile_height;
2368 swap(tile_width, tile_height);
2370 pitch_tiles = pitch / (tile_width * cpp);
2373 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2374 tile_size, pitch_tiles,
2375 old_offset, new_offset);
2377 old_offset += *y * pitch + *x * cpp;
2379 *y = (old_offset - new_offset) / pitch;
2380 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2387 * Computes the linear offset to the base tile and adjusts
2388 * x, y. bytes per pixel is assumed to be a power-of-two.
2390 * In the 90/270 rotated case, x and y are assumed
2391 * to be already rotated to match the rotated GTT view, and
2392 * pitch is the tile_height aligned framebuffer height.
2394 * This function is used when computing the derived information
2395 * under intel_framebuffer, so using any of that information
2396 * here is not allowed. Anything under drm_framebuffer can be
2397 * used. This is why the user has to pass in the pitch since it
2398 * is specified in the rotated orientation.
2400 static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2402 const struct drm_framebuffer *fb, int plane,
2404 unsigned int rotation,
2407 uint64_t fb_modifier = fb->modifier[plane];
2408 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2409 u32 offset, offset_aligned;
2414 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2415 unsigned int tile_size, tile_width, tile_height;
2416 unsigned int tile_rows, tiles, pitch_tiles;
2418 tile_size = intel_tile_size(dev_priv);
2419 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2422 if (intel_rotation_90_or_270(rotation)) {
2423 pitch_tiles = pitch / tile_height;
2424 swap(tile_width, tile_height);
2426 pitch_tiles = pitch / (tile_width * cpp);
2429 tile_rows = *y / tile_height;
2432 tiles = *x / tile_width;
2435 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2436 offset_aligned = offset & ~alignment;
2438 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2439 tile_size, pitch_tiles,
2440 offset, offset_aligned);
2442 offset = *y * pitch + *x * cpp;
2443 offset_aligned = offset & ~alignment;
2445 *y = (offset & alignment) / pitch;
2446 *x = ((offset & alignment) - *y * pitch) / cpp;
2449 return offset_aligned;
2452 u32 intel_compute_tile_offset(int *x, int *y,
2453 const struct intel_plane_state *state,
2456 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2457 const struct drm_framebuffer *fb = state->base.fb;
2458 unsigned int rotation = state->base.rotation;
2459 int pitch = intel_fb_pitch(fb, plane, rotation);
2462 /* AUX_DIST needs only 4K alignment */
2463 if (fb->pixel_format == DRM_FORMAT_NV12 && plane == 1)
2466 alignment = intel_surf_alignment(dev_priv, fb->modifier[plane]);
2468 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2469 rotation, alignment);
2472 /* Convert the fb->offset[] linear offset into x/y offsets */
2473 static void intel_fb_offset_to_xy(int *x, int *y,
2474 const struct drm_framebuffer *fb, int plane)
2476 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2477 unsigned int pitch = fb->pitches[plane];
2478 u32 linear_offset = fb->offsets[plane];
2480 *y = linear_offset / pitch;
2481 *x = linear_offset % pitch / cpp;
2484 static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2486 switch (fb_modifier) {
2487 case I915_FORMAT_MOD_X_TILED:
2488 return I915_TILING_X;
2489 case I915_FORMAT_MOD_Y_TILED:
2490 return I915_TILING_Y;
2492 return I915_TILING_NONE;
2497 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2498 struct drm_framebuffer *fb)
2500 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2501 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2502 u32 gtt_offset_rotated = 0;
2503 unsigned int max_size = 0;
2504 uint32_t format = fb->pixel_format;
2505 int i, num_planes = drm_format_num_planes(format);
2506 unsigned int tile_size = intel_tile_size(dev_priv);
2508 for (i = 0; i < num_planes; i++) {
2509 unsigned int width, height;
2510 unsigned int cpp, size;
2514 cpp = drm_format_plane_cpp(format, i);
2515 width = drm_format_plane_width(fb->width, format, i);
2516 height = drm_format_plane_height(fb->height, format, i);
2518 intel_fb_offset_to_xy(&x, &y, fb, i);
2521 * The fence (if used) is aligned to the start of the object
2522 * so having the framebuffer wrap around across the edge of the
2523 * fenced region doesn't really work. We have no API to configure
2524 * the fence start offset within the object (nor could we probably
2525 * on gen2/3). So it's just easier if we just require that the
2526 * fb layout agrees with the fence layout. We already check that the
2527 * fb stride matches the fence stride elsewhere.
2529 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2530 (x + width) * cpp > fb->pitches[i]) {
2531 DRM_DEBUG("bad fb plane %d offset: 0x%x\n",
2537 * First pixel of the framebuffer from
2538 * the start of the normal gtt mapping.
2540 intel_fb->normal[i].x = x;
2541 intel_fb->normal[i].y = y;
2543 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
2544 fb, 0, fb->pitches[i],
2545 DRM_ROTATE_0, tile_size);
2546 offset /= tile_size;
2548 if (fb->modifier[i] != DRM_FORMAT_MOD_NONE) {
2549 unsigned int tile_width, tile_height;
2550 unsigned int pitch_tiles;
2553 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2554 fb->modifier[i], cpp);
2556 rot_info->plane[i].offset = offset;
2557 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2558 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2559 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2561 intel_fb->rotated[i].pitch =
2562 rot_info->plane[i].height * tile_height;
2564 /* how many tiles does this plane need */
2565 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2567 * If the plane isn't horizontally tile aligned,
2568 * we need one more tile.
2573 /* rotate the x/y offsets to match the GTT view */
2579 rot_info->plane[i].width * tile_width,
2580 rot_info->plane[i].height * tile_height,
2585 /* rotate the tile dimensions to match the GTT view */
2586 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2587 swap(tile_width, tile_height);
2590 * We only keep the x/y offsets, so push all of the
2591 * gtt offset into the x/y offsets.
2593 _intel_adjust_tile_offset(&x, &y,
2594 tile_width, tile_height,
2595 tile_size, pitch_tiles,
2596 gtt_offset_rotated * tile_size, 0);
2598 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2601 * First pixel of the framebuffer from
2602 * the start of the rotated gtt mapping.
2604 intel_fb->rotated[i].x = x;
2605 intel_fb->rotated[i].y = y;
2607 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2608 x * cpp, tile_size);
2611 /* how many tiles in total needed in the bo */
2612 max_size = max(max_size, offset + size);
2615 if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) {
2616 DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n",
2617 max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size);
2624 static int i9xx_format_to_fourcc(int format)
2627 case DISPPLANE_8BPP:
2628 return DRM_FORMAT_C8;
2629 case DISPPLANE_BGRX555:
2630 return DRM_FORMAT_XRGB1555;
2631 case DISPPLANE_BGRX565:
2632 return DRM_FORMAT_RGB565;
2634 case DISPPLANE_BGRX888:
2635 return DRM_FORMAT_XRGB8888;
2636 case DISPPLANE_RGBX888:
2637 return DRM_FORMAT_XBGR8888;
2638 case DISPPLANE_BGRX101010:
2639 return DRM_FORMAT_XRGB2101010;
2640 case DISPPLANE_RGBX101010:
2641 return DRM_FORMAT_XBGR2101010;
2645 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2648 case PLANE_CTL_FORMAT_RGB_565:
2649 return DRM_FORMAT_RGB565;
2651 case PLANE_CTL_FORMAT_XRGB_8888:
2654 return DRM_FORMAT_ABGR8888;
2656 return DRM_FORMAT_XBGR8888;
2659 return DRM_FORMAT_ARGB8888;
2661 return DRM_FORMAT_XRGB8888;
2663 case PLANE_CTL_FORMAT_XRGB_2101010:
2665 return DRM_FORMAT_XBGR2101010;
2667 return DRM_FORMAT_XRGB2101010;
2672 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2673 struct intel_initial_plane_config *plane_config)
2675 struct drm_device *dev = crtc->base.dev;
2676 struct drm_i915_private *dev_priv = to_i915(dev);
2677 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2678 struct drm_i915_gem_object *obj = NULL;
2679 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2680 struct drm_framebuffer *fb = &plane_config->fb->base;
2681 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2682 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2685 size_aligned -= base_aligned;
2687 if (plane_config->size == 0)
2690 /* If the FB is too big, just don't use it since fbdev is not very
2691 * important and we should probably use that space with FBC or other
2693 if (size_aligned * 2 > ggtt->stolen_usable_size)
2696 mutex_lock(&dev->struct_mutex);
2698 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2703 mutex_unlock(&dev->struct_mutex);
2707 if (plane_config->tiling == I915_TILING_X)
2708 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
2710 mode_cmd.pixel_format = fb->pixel_format;
2711 mode_cmd.width = fb->width;
2712 mode_cmd.height = fb->height;
2713 mode_cmd.pitches[0] = fb->pitches[0];
2714 mode_cmd.modifier[0] = fb->modifier[0];
2715 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2717 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2719 DRM_DEBUG_KMS("intel fb init failed\n");
2723 mutex_unlock(&dev->struct_mutex);
2725 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2729 i915_gem_object_put(obj);
2730 mutex_unlock(&dev->struct_mutex);
2734 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2736 update_state_fb(struct drm_plane *plane)
2738 if (plane->fb == plane->state->fb)
2741 if (plane->state->fb)
2742 drm_framebuffer_unreference(plane->state->fb);
2743 plane->state->fb = plane->fb;
2744 if (plane->state->fb)
2745 drm_framebuffer_reference(plane->state->fb);
2749 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2750 struct intel_initial_plane_config *plane_config)
2752 struct drm_device *dev = intel_crtc->base.dev;
2753 struct drm_i915_private *dev_priv = to_i915(dev);
2755 struct intel_crtc *i;
2756 struct drm_i915_gem_object *obj;
2757 struct drm_plane *primary = intel_crtc->base.primary;
2758 struct drm_plane_state *plane_state = primary->state;
2759 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2760 struct intel_plane *intel_plane = to_intel_plane(primary);
2761 struct intel_plane_state *intel_state =
2762 to_intel_plane_state(plane_state);
2763 struct drm_framebuffer *fb;
2765 if (!plane_config->fb)
2768 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2769 fb = &plane_config->fb->base;
2773 kfree(plane_config->fb);
2776 * Failed to alloc the obj, check to see if we should share
2777 * an fb with another CRTC instead
2779 for_each_crtc(dev, c) {
2780 i = to_intel_crtc(c);
2782 if (c == &intel_crtc->base)
2788 fb = c->primary->fb;
2792 obj = intel_fb_obj(fb);
2793 if (i915_gem_object_ggtt_offset(obj, NULL) == plane_config->base) {
2794 drm_framebuffer_reference(fb);
2800 * We've failed to reconstruct the BIOS FB. Current display state
2801 * indicates that the primary plane is visible, but has a NULL FB,
2802 * which will lead to problems later if we don't fix it up. The
2803 * simplest solution is to just disable the primary plane now and
2804 * pretend the BIOS never had it enabled.
2806 to_intel_plane_state(plane_state)->base.visible = false;
2807 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2808 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2809 intel_plane->disable_plane(primary, &intel_crtc->base);
2814 plane_state->src_x = 0;
2815 plane_state->src_y = 0;
2816 plane_state->src_w = fb->width << 16;
2817 plane_state->src_h = fb->height << 16;
2819 plane_state->crtc_x = 0;
2820 plane_state->crtc_y = 0;
2821 plane_state->crtc_w = fb->width;
2822 plane_state->crtc_h = fb->height;
2824 intel_state->base.src.x1 = plane_state->src_x;
2825 intel_state->base.src.y1 = plane_state->src_y;
2826 intel_state->base.src.x2 = plane_state->src_x + plane_state->src_w;
2827 intel_state->base.src.y2 = plane_state->src_y + plane_state->src_h;
2828 intel_state->base.dst.x1 = plane_state->crtc_x;
2829 intel_state->base.dst.y1 = plane_state->crtc_y;
2830 intel_state->base.dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2831 intel_state->base.dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2833 obj = intel_fb_obj(fb);
2834 if (i915_gem_object_is_tiled(obj))
2835 dev_priv->preserve_bios_swizzle = true;
2837 drm_framebuffer_reference(fb);
2838 primary->fb = primary->state->fb = fb;
2839 primary->crtc = primary->state->crtc = &intel_crtc->base;
2840 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2841 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2842 &obj->frontbuffer_bits);
2845 static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2846 unsigned int rotation)
2848 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2850 switch (fb->modifier[plane]) {
2851 case DRM_FORMAT_MOD_NONE:
2852 case I915_FORMAT_MOD_X_TILED:
2865 case I915_FORMAT_MOD_Y_TILED:
2866 case I915_FORMAT_MOD_Yf_TILED:
2881 MISSING_CASE(fb->modifier[plane]);
2887 static int skl_check_main_surface(struct intel_plane_state *plane_state)
2889 const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev);
2890 const struct drm_framebuffer *fb = plane_state->base.fb;
2891 unsigned int rotation = plane_state->base.rotation;
2892 int x = plane_state->base.src.x1 >> 16;
2893 int y = plane_state->base.src.y1 >> 16;
2894 int w = drm_rect_width(&plane_state->base.src) >> 16;
2895 int h = drm_rect_height(&plane_state->base.src) >> 16;
2896 int max_width = skl_max_plane_width(fb, 0, rotation);
2897 int max_height = 4096;
2898 u32 alignment, offset, aux_offset = plane_state->aux.offset;
2900 if (w > max_width || h > max_height) {
2901 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2902 w, h, max_width, max_height);
2906 intel_add_fb_offsets(&x, &y, plane_state, 0);
2907 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
2909 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2912 * AUX surface offset is specified as the distance from the
2913 * main surface offset, and it must be non-negative. Make
2914 * sure that is what we will get.
2916 if (offset > aux_offset)
2917 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2918 offset, aux_offset & ~(alignment - 1));
2921 * When using an X-tiled surface, the plane blows up
2922 * if the x offset + width exceed the stride.
2924 * TODO: linear and Y-tiled seem fine, Yf untested,
2926 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED) {
2927 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2929 while ((x + w) * cpp > fb->pitches[0]) {
2931 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2935 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2936 offset, offset - alignment);
2940 plane_state->main.offset = offset;
2941 plane_state->main.x = x;
2942 plane_state->main.y = y;
2947 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2949 const struct drm_framebuffer *fb = plane_state->base.fb;
2950 unsigned int rotation = plane_state->base.rotation;
2951 int max_width = skl_max_plane_width(fb, 1, rotation);
2952 int max_height = 4096;
2953 int x = plane_state->base.src.x1 >> 17;
2954 int y = plane_state->base.src.y1 >> 17;
2955 int w = drm_rect_width(&plane_state->base.src) >> 17;
2956 int h = drm_rect_height(&plane_state->base.src) >> 17;
2959 intel_add_fb_offsets(&x, &y, plane_state, 1);
2960 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2962 /* FIXME not quite sure how/if these apply to the chroma plane */
2963 if (w > max_width || h > max_height) {
2964 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2965 w, h, max_width, max_height);
2969 plane_state->aux.offset = offset;
2970 plane_state->aux.x = x;
2971 plane_state->aux.y = y;
2976 int skl_check_plane_surface(struct intel_plane_state *plane_state)
2978 const struct drm_framebuffer *fb = plane_state->base.fb;
2979 unsigned int rotation = plane_state->base.rotation;
2982 if (!plane_state->base.visible)
2985 /* Rotate src coordinates to match rotated GTT view */
2986 if (intel_rotation_90_or_270(rotation))
2987 drm_rect_rotate(&plane_state->base.src,
2988 fb->width << 16, fb->height << 16,
2992 * Handle the AUX surface first since
2993 * the main surface setup depends on it.
2995 if (fb->pixel_format == DRM_FORMAT_NV12) {
2996 ret = skl_check_nv12_aux_surface(plane_state);
3000 plane_state->aux.offset = ~0xfff;
3001 plane_state->aux.x = 0;
3002 plane_state->aux.y = 0;
3005 ret = skl_check_main_surface(plane_state);
3012 static void i9xx_update_primary_plane(struct drm_plane *primary,
3013 const struct intel_crtc_state *crtc_state,
3014 const struct intel_plane_state *plane_state)
3016 struct drm_device *dev = primary->dev;
3017 struct drm_i915_private *dev_priv = to_i915(dev);
3018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3019 struct drm_framebuffer *fb = plane_state->base.fb;
3020 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3021 int plane = intel_crtc->plane;
3024 i915_reg_t reg = DSPCNTR(plane);
3025 unsigned int rotation = plane_state->base.rotation;
3026 int x = plane_state->base.src.x1 >> 16;
3027 int y = plane_state->base.src.y1 >> 16;
3029 dspcntr = DISPPLANE_GAMMA_ENABLE;
3031 dspcntr |= DISPLAY_PLANE_ENABLE;
3033 if (INTEL_INFO(dev)->gen < 4) {
3034 if (intel_crtc->pipe == PIPE_B)
3035 dspcntr |= DISPPLANE_SEL_PIPE_B;
3037 /* pipesrc and dspsize control the size that is scaled from,
3038 * which should always be the user's requested size.
3040 I915_WRITE(DSPSIZE(plane),
3041 ((crtc_state->pipe_src_h - 1) << 16) |
3042 (crtc_state->pipe_src_w - 1));
3043 I915_WRITE(DSPPOS(plane), 0);
3044 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
3045 I915_WRITE(PRIMSIZE(plane),
3046 ((crtc_state->pipe_src_h - 1) << 16) |
3047 (crtc_state->pipe_src_w - 1));
3048 I915_WRITE(PRIMPOS(plane), 0);
3049 I915_WRITE(PRIMCNSTALPHA(plane), 0);
3052 switch (fb->pixel_format) {
3054 dspcntr |= DISPPLANE_8BPP;
3056 case DRM_FORMAT_XRGB1555:
3057 dspcntr |= DISPPLANE_BGRX555;
3059 case DRM_FORMAT_RGB565:
3060 dspcntr |= DISPPLANE_BGRX565;
3062 case DRM_FORMAT_XRGB8888:
3063 dspcntr |= DISPPLANE_BGRX888;
3065 case DRM_FORMAT_XBGR8888:
3066 dspcntr |= DISPPLANE_RGBX888;
3068 case DRM_FORMAT_XRGB2101010:
3069 dspcntr |= DISPPLANE_BGRX101010;
3071 case DRM_FORMAT_XBGR2101010:
3072 dspcntr |= DISPPLANE_RGBX101010;
3078 if (INTEL_GEN(dev_priv) >= 4 &&
3079 fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3080 dspcntr |= DISPPLANE_TILED;
3083 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3085 intel_add_fb_offsets(&x, &y, plane_state, 0);
3087 if (INTEL_INFO(dev)->gen >= 4)
3088 intel_crtc->dspaddr_offset =
3089 intel_compute_tile_offset(&x, &y, plane_state, 0);
3091 if (rotation == DRM_ROTATE_180) {
3092 dspcntr |= DISPPLANE_ROTATE_180;
3094 x += (crtc_state->pipe_src_w - 1);
3095 y += (crtc_state->pipe_src_h - 1);
3098 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3100 if (INTEL_INFO(dev)->gen < 4)
3101 intel_crtc->dspaddr_offset = linear_offset;
3103 intel_crtc->adjusted_x = x;
3104 intel_crtc->adjusted_y = y;
3106 I915_WRITE(reg, dspcntr);
3108 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3109 if (INTEL_INFO(dev)->gen >= 4) {
3110 I915_WRITE(DSPSURF(plane),
3111 intel_fb_gtt_offset(fb, rotation) +
3112 intel_crtc->dspaddr_offset);
3113 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3114 I915_WRITE(DSPLINOFF(plane), linear_offset);
3116 I915_WRITE(DSPADDR(plane), i915_gem_object_ggtt_offset(obj, NULL) + linear_offset);
3120 static void i9xx_disable_primary_plane(struct drm_plane *primary,
3121 struct drm_crtc *crtc)
3123 struct drm_device *dev = crtc->dev;
3124 struct drm_i915_private *dev_priv = to_i915(dev);
3125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3126 int plane = intel_crtc->plane;
3128 I915_WRITE(DSPCNTR(plane), 0);
3129 if (INTEL_INFO(dev_priv)->gen >= 4)
3130 I915_WRITE(DSPSURF(plane), 0);
3132 I915_WRITE(DSPADDR(plane), 0);
3133 POSTING_READ(DSPCNTR(plane));
3136 static void ironlake_update_primary_plane(struct drm_plane *primary,
3137 const struct intel_crtc_state *crtc_state,
3138 const struct intel_plane_state *plane_state)
3140 struct drm_device *dev = primary->dev;
3141 struct drm_i915_private *dev_priv = to_i915(dev);
3142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3143 struct drm_framebuffer *fb = plane_state->base.fb;
3144 int plane = intel_crtc->plane;
3147 i915_reg_t reg = DSPCNTR(plane);
3148 unsigned int rotation = plane_state->base.rotation;
3149 int x = plane_state->base.src.x1 >> 16;
3150 int y = plane_state->base.src.y1 >> 16;
3152 dspcntr = DISPPLANE_GAMMA_ENABLE;
3153 dspcntr |= DISPLAY_PLANE_ENABLE;
3155 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3156 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
3158 switch (fb->pixel_format) {
3160 dspcntr |= DISPPLANE_8BPP;
3162 case DRM_FORMAT_RGB565:
3163 dspcntr |= DISPPLANE_BGRX565;
3165 case DRM_FORMAT_XRGB8888:
3166 dspcntr |= DISPPLANE_BGRX888;
3168 case DRM_FORMAT_XBGR8888:
3169 dspcntr |= DISPPLANE_RGBX888;
3171 case DRM_FORMAT_XRGB2101010:
3172 dspcntr |= DISPPLANE_BGRX101010;
3174 case DRM_FORMAT_XBGR2101010:
3175 dspcntr |= DISPPLANE_RGBX101010;
3181 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
3182 dspcntr |= DISPPLANE_TILED;
3184 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
3185 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
3187 intel_add_fb_offsets(&x, &y, plane_state, 0);
3189 intel_crtc->dspaddr_offset =
3190 intel_compute_tile_offset(&x, &y, plane_state, 0);
3192 if (rotation == DRM_ROTATE_180) {
3193 dspcntr |= DISPPLANE_ROTATE_180;
3195 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
3196 x += (crtc_state->pipe_src_w - 1);
3197 y += (crtc_state->pipe_src_h - 1);
3201 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
3203 intel_crtc->adjusted_x = x;
3204 intel_crtc->adjusted_y = y;
3206 I915_WRITE(reg, dspcntr);
3208 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
3209 I915_WRITE(DSPSURF(plane),
3210 intel_fb_gtt_offset(fb, rotation) +
3211 intel_crtc->dspaddr_offset);
3212 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3213 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
3215 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
3216 I915_WRITE(DSPLINOFF(plane), linear_offset);
3221 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
3222 uint64_t fb_modifier, uint32_t pixel_format)
3224 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
3227 int cpp = drm_format_plane_cpp(pixel_format, 0);
3229 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
3233 u32 intel_fb_gtt_offset(struct drm_framebuffer *fb,
3234 unsigned int rotation)
3236 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3237 struct i915_ggtt_view view;
3238 struct i915_vma *vma;
3240 intel_fill_fb_ggtt_view(&view, fb, rotation);
3242 vma = i915_gem_object_to_ggtt(obj, &view);
3243 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
3247 return i915_ggtt_offset(vma);
3250 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3252 struct drm_device *dev = intel_crtc->base.dev;
3253 struct drm_i915_private *dev_priv = to_i915(dev);
3255 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3256 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3257 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3261 * This function detaches (aka. unbinds) unused scalers in hardware
3263 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3265 struct intel_crtc_scaler_state *scaler_state;
3268 scaler_state = &intel_crtc->config->scaler_state;
3270 /* loop through and disable scalers that aren't in use */
3271 for (i = 0; i < intel_crtc->num_scalers; i++) {
3272 if (!scaler_state->scalers[i].in_use)
3273 skl_detach_scaler(intel_crtc, i);
3277 u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3278 unsigned int rotation)
3280 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
3281 u32 stride = intel_fb_pitch(fb, plane, rotation);
3284 * The stride is either expressed as a multiple of 64 bytes chunks for
3285 * linear buffers or in number of tiles for tiled buffers.
3287 if (intel_rotation_90_or_270(rotation)) {
3288 int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
3290 stride /= intel_tile_height(dev_priv, fb->modifier[0], cpp);
3292 stride /= intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3299 u32 skl_plane_ctl_format(uint32_t pixel_format)
3301 switch (pixel_format) {
3303 return PLANE_CTL_FORMAT_INDEXED;
3304 case DRM_FORMAT_RGB565:
3305 return PLANE_CTL_FORMAT_RGB_565;
3306 case DRM_FORMAT_XBGR8888:
3307 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3308 case DRM_FORMAT_XRGB8888:
3309 return PLANE_CTL_FORMAT_XRGB_8888;
3311 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3312 * to be already pre-multiplied. We need to add a knob (or a different
3313 * DRM_FORMAT) for user-space to configure that.
3315 case DRM_FORMAT_ABGR8888:
3316 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3317 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3318 case DRM_FORMAT_ARGB8888:
3319 return PLANE_CTL_FORMAT_XRGB_8888 |
3320 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3321 case DRM_FORMAT_XRGB2101010:
3322 return PLANE_CTL_FORMAT_XRGB_2101010;
3323 case DRM_FORMAT_XBGR2101010:
3324 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3325 case DRM_FORMAT_YUYV:
3326 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3327 case DRM_FORMAT_YVYU:
3328 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3329 case DRM_FORMAT_UYVY:
3330 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3331 case DRM_FORMAT_VYUY:
3332 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3334 MISSING_CASE(pixel_format);
3340 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3342 switch (fb_modifier) {
3343 case DRM_FORMAT_MOD_NONE:
3345 case I915_FORMAT_MOD_X_TILED:
3346 return PLANE_CTL_TILED_X;
3347 case I915_FORMAT_MOD_Y_TILED:
3348 return PLANE_CTL_TILED_Y;
3349 case I915_FORMAT_MOD_Yf_TILED:
3350 return PLANE_CTL_TILED_YF;
3352 MISSING_CASE(fb_modifier);
3358 u32 skl_plane_ctl_rotation(unsigned int rotation)
3364 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3365 * while i915 HW rotation is clockwise, thats why this swapping.
3368 return PLANE_CTL_ROTATE_270;
3369 case DRM_ROTATE_180:
3370 return PLANE_CTL_ROTATE_180;
3371 case DRM_ROTATE_270:
3372 return PLANE_CTL_ROTATE_90;
3374 MISSING_CASE(rotation);
3380 static void skylake_update_primary_plane(struct drm_plane *plane,
3381 const struct intel_crtc_state *crtc_state,
3382 const struct intel_plane_state *plane_state)
3384 struct drm_device *dev = plane->dev;
3385 struct drm_i915_private *dev_priv = to_i915(dev);
3386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3387 struct drm_framebuffer *fb = plane_state->base.fb;
3388 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
3389 int pipe = intel_crtc->pipe;
3391 unsigned int rotation = plane_state->base.rotation;
3392 u32 stride = skl_plane_stride(fb, 0, rotation);
3393 u32 surf_addr = plane_state->main.offset;
3394 int scaler_id = plane_state->scaler_id;
3395 int src_x = plane_state->main.x;
3396 int src_y = plane_state->main.y;
3397 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3398 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3399 int dst_x = plane_state->base.dst.x1;
3400 int dst_y = plane_state->base.dst.y1;
3401 int dst_w = drm_rect_width(&plane_state->base.dst);
3402 int dst_h = drm_rect_height(&plane_state->base.dst);
3404 plane_ctl = PLANE_CTL_ENABLE |
3405 PLANE_CTL_PIPE_GAMMA_ENABLE |
3406 PLANE_CTL_PIPE_CSC_ENABLE;
3408 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3409 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3410 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3411 plane_ctl |= skl_plane_ctl_rotation(rotation);
3413 /* Sizes are 0 based */
3419 intel_crtc->dspaddr_offset = surf_addr;
3421 intel_crtc->adjusted_x = src_x;
3422 intel_crtc->adjusted_y = src_y;
3424 if (wm->dirty_pipes & drm_crtc_mask(&intel_crtc->base))
3425 skl_write_plane_wm(intel_crtc, wm, 0);
3427 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3428 I915_WRITE(PLANE_OFFSET(pipe, 0), (src_y << 16) | src_x);
3429 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3430 I915_WRITE(PLANE_SIZE(pipe, 0), (src_h << 16) | src_w);
3432 if (scaler_id >= 0) {
3433 uint32_t ps_ctrl = 0;
3435 WARN_ON(!dst_w || !dst_h);
3436 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3437 crtc_state->scaler_state.scalers[scaler_id].mode;
3438 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3439 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3440 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3441 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3442 I915_WRITE(PLANE_POS(pipe, 0), 0);
3444 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3447 I915_WRITE(PLANE_SURF(pipe, 0),
3448 intel_fb_gtt_offset(fb, rotation) + surf_addr);
3450 POSTING_READ(PLANE_SURF(pipe, 0));
3453 static void skylake_disable_primary_plane(struct drm_plane *primary,
3454 struct drm_crtc *crtc)
3456 struct drm_device *dev = crtc->dev;
3457 struct drm_i915_private *dev_priv = to_i915(dev);
3458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3459 int pipe = intel_crtc->pipe;
3462 * We only populate skl_results on watermark updates, and if the
3463 * plane's visiblity isn't actually changing neither is its watermarks.
3465 if (!crtc->primary->state->visible)
3466 skl_write_plane_wm(intel_crtc, &dev_priv->wm.skl_results, 0);
3468 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3469 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3470 POSTING_READ(PLANE_SURF(pipe, 0));
3473 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3475 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3476 int x, int y, enum mode_set_atomic state)
3478 /* Support for kgdboc is disabled, this needs a major rework. */
3479 DRM_ERROR("legacy panic handler not supported any more.\n");
3484 static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3486 struct intel_crtc *crtc;
3488 for_each_intel_crtc(&dev_priv->drm, crtc)
3489 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3492 static void intel_update_primary_planes(struct drm_device *dev)
3494 struct drm_crtc *crtc;
3496 for_each_crtc(dev, crtc) {
3497 struct intel_plane *plane = to_intel_plane(crtc->primary);
3498 struct intel_plane_state *plane_state =
3499 to_intel_plane_state(plane->base.state);
3501 if (plane_state->base.visible)
3502 plane->update_plane(&plane->base,
3503 to_intel_crtc_state(crtc->state),
3509 __intel_display_resume(struct drm_device *dev,
3510 struct drm_atomic_state *state)
3512 struct drm_crtc_state *crtc_state;
3513 struct drm_crtc *crtc;
3516 intel_modeset_setup_hw_state(dev);
3517 i915_redisable_vga(dev);
3522 for_each_crtc_in_state(state, crtc, crtc_state, i) {
3524 * Force recalculation even if we restore
3525 * current state. With fast modeset this may not result
3526 * in a modeset when the state is compatible.
3528 crtc_state->mode_changed = true;
3531 /* ignore any reset values/BIOS leftovers in the WM registers */
3532 to_intel_atomic_state(state)->skip_intermediate_wm = true;
3534 ret = drm_atomic_commit(state);
3536 WARN_ON(ret == -EDEADLK);
3540 static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3542 return intel_has_gpu_reset(dev_priv) &&
3543 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
3546 void intel_prepare_reset(struct drm_i915_private *dev_priv)
3548 struct drm_device *dev = &dev_priv->drm;
3549 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3550 struct drm_atomic_state *state;
3554 * Need mode_config.mutex so that we don't
3555 * trample ongoing ->detect() and whatnot.
3557 mutex_lock(&dev->mode_config.mutex);
3558 drm_modeset_acquire_init(ctx, 0);
3560 ret = drm_modeset_lock_all_ctx(dev, ctx);
3561 if (ret != -EDEADLK)
3564 drm_modeset_backoff(ctx);
3567 /* reset doesn't touch the display, but flips might get nuked anyway, */
3568 if (!i915.force_reset_modeset_test &&
3569 !gpu_reset_clobbers_display(dev_priv))
3573 * Disabling the crtcs gracefully seems nicer. Also the
3574 * g33 docs say we should at least disable all the planes.
3576 state = drm_atomic_helper_duplicate_state(dev, ctx);
3577 if (IS_ERR(state)) {
3578 ret = PTR_ERR(state);
3580 DRM_ERROR("Duplicating state failed with %i\n", ret);
3584 ret = drm_atomic_helper_disable_all(dev, ctx);
3586 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
3590 dev_priv->modeset_restore_state = state;
3591 state->acquire_ctx = ctx;
3595 drm_atomic_state_free(state);
3598 void intel_finish_reset(struct drm_i915_private *dev_priv)
3600 struct drm_device *dev = &dev_priv->drm;
3601 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3602 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3606 * Flips in the rings will be nuked by the reset,
3607 * so complete all pending flips so that user space
3608 * will get its events and not get stuck.
3610 intel_complete_page_flips(dev_priv);
3612 dev_priv->modeset_restore_state = NULL;
3614 dev_priv->modeset_restore_state = NULL;
3616 /* reset doesn't touch the display */
3617 if (!gpu_reset_clobbers_display(dev_priv)) {
3620 * Flips in the rings have been nuked by the reset,
3621 * so update the base address of all primary
3622 * planes to the the last fb to make sure we're
3623 * showing the correct fb after a reset.
3625 * FIXME: Atomic will make this obsolete since we won't schedule
3626 * CS-based flips (which might get lost in gpu resets) any more.
3628 intel_update_primary_planes(dev);
3630 ret = __intel_display_resume(dev, state);
3632 DRM_ERROR("Restoring old state failed with %i\n", ret);
3636 * The display has been reset as well,
3637 * so need a full re-initialization.
3639 intel_runtime_pm_disable_interrupts(dev_priv);
3640 intel_runtime_pm_enable_interrupts(dev_priv);
3642 intel_pps_unlock_regs_wa(dev_priv);
3643 intel_modeset_init_hw(dev);
3645 spin_lock_irq(&dev_priv->irq_lock);
3646 if (dev_priv->display.hpd_irq_setup)
3647 dev_priv->display.hpd_irq_setup(dev_priv);
3648 spin_unlock_irq(&dev_priv->irq_lock);
3650 ret = __intel_display_resume(dev, state);
3652 DRM_ERROR("Restoring old state failed with %i\n", ret);
3654 intel_hpd_init(dev_priv);
3657 drm_modeset_drop_locks(ctx);
3658 drm_modeset_acquire_fini(ctx);
3659 mutex_unlock(&dev->mode_config.mutex);
3662 static bool abort_flip_on_reset(struct intel_crtc *crtc)
3664 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3666 if (i915_reset_in_progress(error))
3669 if (crtc->reset_count != i915_reset_count(error))
3675 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3677 struct drm_device *dev = crtc->dev;
3678 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3681 if (abort_flip_on_reset(intel_crtc))
3684 spin_lock_irq(&dev->event_lock);
3685 pending = to_intel_crtc(crtc)->flip_work != NULL;
3686 spin_unlock_irq(&dev->event_lock);
3691 static void intel_update_pipe_config(struct intel_crtc *crtc,
3692 struct intel_crtc_state *old_crtc_state)
3694 struct drm_device *dev = crtc->base.dev;
3695 struct drm_i915_private *dev_priv = to_i915(dev);
3696 struct intel_crtc_state *pipe_config =
3697 to_intel_crtc_state(crtc->base.state);
3699 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3700 crtc->base.mode = crtc->base.state->mode;
3703 * Update pipe size and adjust fitter if needed: the reason for this is
3704 * that in compute_mode_changes we check the native mode (not the pfit
3705 * mode) to see if we can flip rather than do a full mode set. In the
3706 * fastboot case, we'll flip, but if we don't update the pipesrc and
3707 * pfit state, we'll end up with a big fb scanned out into the wrong
3711 I915_WRITE(PIPESRC(crtc->pipe),
3712 ((pipe_config->pipe_src_w - 1) << 16) |
3713 (pipe_config->pipe_src_h - 1));
3715 /* on skylake this is done by detaching scalers */
3716 if (INTEL_INFO(dev)->gen >= 9) {
3717 skl_detach_scalers(crtc);
3719 if (pipe_config->pch_pfit.enabled)
3720 skylake_pfit_enable(crtc);
3721 } else if (HAS_PCH_SPLIT(dev)) {
3722 if (pipe_config->pch_pfit.enabled)
3723 ironlake_pfit_enable(crtc);
3724 else if (old_crtc_state->pch_pfit.enabled)
3725 ironlake_pfit_disable(crtc, true);
3729 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3731 struct drm_device *dev = crtc->dev;
3732 struct drm_i915_private *dev_priv = to_i915(dev);
3733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3734 int pipe = intel_crtc->pipe;
3738 /* enable normal train */
3739 reg = FDI_TX_CTL(pipe);
3740 temp = I915_READ(reg);
3741 if (IS_IVYBRIDGE(dev)) {
3742 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3743 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3745 temp &= ~FDI_LINK_TRAIN_NONE;
3746 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3748 I915_WRITE(reg, temp);
3750 reg = FDI_RX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 if (HAS_PCH_CPT(dev)) {
3753 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3754 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3756 temp &= ~FDI_LINK_TRAIN_NONE;
3757 temp |= FDI_LINK_TRAIN_NONE;
3759 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3761 /* wait one idle pattern time */
3765 /* IVB wants error correction enabled */
3766 if (IS_IVYBRIDGE(dev))
3767 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3768 FDI_FE_ERRC_ENABLE);
3771 /* The FDI link training functions for ILK/Ibexpeak. */
3772 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3774 struct drm_device *dev = crtc->dev;
3775 struct drm_i915_private *dev_priv = to_i915(dev);
3776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3777 int pipe = intel_crtc->pipe;
3781 /* FDI needs bits from pipe first */
3782 assert_pipe_enabled(dev_priv, pipe);
3784 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3786 reg = FDI_RX_IMR(pipe);
3787 temp = I915_READ(reg);
3788 temp &= ~FDI_RX_SYMBOL_LOCK;
3789 temp &= ~FDI_RX_BIT_LOCK;
3790 I915_WRITE(reg, temp);
3794 /* enable CPU FDI TX and PCH FDI RX */
3795 reg = FDI_TX_CTL(pipe);
3796 temp = I915_READ(reg);
3797 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3798 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3799 temp &= ~FDI_LINK_TRAIN_NONE;
3800 temp |= FDI_LINK_TRAIN_PATTERN_1;
3801 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3803 reg = FDI_RX_CTL(pipe);
3804 temp = I915_READ(reg);
3805 temp &= ~FDI_LINK_TRAIN_NONE;
3806 temp |= FDI_LINK_TRAIN_PATTERN_1;
3807 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3812 /* Ironlake workaround, enable clock pointer after FDI enable*/
3813 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3814 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3815 FDI_RX_PHASE_SYNC_POINTER_EN);
3817 reg = FDI_RX_IIR(pipe);
3818 for (tries = 0; tries < 5; tries++) {
3819 temp = I915_READ(reg);
3820 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3822 if ((temp & FDI_RX_BIT_LOCK)) {
3823 DRM_DEBUG_KMS("FDI train 1 done.\n");
3824 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3829 DRM_ERROR("FDI train 1 fail!\n");
3832 reg = FDI_TX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_2;
3836 I915_WRITE(reg, temp);
3838 reg = FDI_RX_CTL(pipe);
3839 temp = I915_READ(reg);
3840 temp &= ~FDI_LINK_TRAIN_NONE;
3841 temp |= FDI_LINK_TRAIN_PATTERN_2;
3842 I915_WRITE(reg, temp);
3847 reg = FDI_RX_IIR(pipe);
3848 for (tries = 0; tries < 5; tries++) {
3849 temp = I915_READ(reg);
3850 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3852 if (temp & FDI_RX_SYMBOL_LOCK) {
3853 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3854 DRM_DEBUG_KMS("FDI train 2 done.\n");
3859 DRM_ERROR("FDI train 2 fail!\n");
3861 DRM_DEBUG_KMS("FDI train done\n");
3865 static const int snb_b_fdi_train_param[] = {
3866 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3867 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3868 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3869 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3872 /* The FDI link training functions for SNB/Cougarpoint. */
3873 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3875 struct drm_device *dev = crtc->dev;
3876 struct drm_i915_private *dev_priv = to_i915(dev);
3877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3878 int pipe = intel_crtc->pipe;
3882 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3884 reg = FDI_RX_IMR(pipe);
3885 temp = I915_READ(reg);
3886 temp &= ~FDI_RX_SYMBOL_LOCK;
3887 temp &= ~FDI_RX_BIT_LOCK;
3888 I915_WRITE(reg, temp);
3893 /* enable CPU FDI TX and PCH FDI RX */
3894 reg = FDI_TX_CTL(pipe);
3895 temp = I915_READ(reg);
3896 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3897 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3898 temp &= ~FDI_LINK_TRAIN_NONE;
3899 temp |= FDI_LINK_TRAIN_PATTERN_1;
3900 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3902 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3903 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3905 I915_WRITE(FDI_RX_MISC(pipe),
3906 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3908 reg = FDI_RX_CTL(pipe);
3909 temp = I915_READ(reg);
3910 if (HAS_PCH_CPT(dev)) {
3911 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3912 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3914 temp &= ~FDI_LINK_TRAIN_NONE;
3915 temp |= FDI_LINK_TRAIN_PATTERN_1;
3917 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3922 for (i = 0; i < 4; i++) {
3923 reg = FDI_TX_CTL(pipe);
3924 temp = I915_READ(reg);
3925 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3926 temp |= snb_b_fdi_train_param[i];
3927 I915_WRITE(reg, temp);
3932 for (retry = 0; retry < 5; retry++) {
3933 reg = FDI_RX_IIR(pipe);
3934 temp = I915_READ(reg);
3935 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3936 if (temp & FDI_RX_BIT_LOCK) {
3937 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3938 DRM_DEBUG_KMS("FDI train 1 done.\n");
3947 DRM_ERROR("FDI train 1 fail!\n");
3950 reg = FDI_TX_CTL(pipe);
3951 temp = I915_READ(reg);
3952 temp &= ~FDI_LINK_TRAIN_NONE;
3953 temp |= FDI_LINK_TRAIN_PATTERN_2;
3955 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3957 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3959 I915_WRITE(reg, temp);
3961 reg = FDI_RX_CTL(pipe);
3962 temp = I915_READ(reg);
3963 if (HAS_PCH_CPT(dev)) {
3964 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3965 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3967 temp &= ~FDI_LINK_TRAIN_NONE;
3968 temp |= FDI_LINK_TRAIN_PATTERN_2;
3970 I915_WRITE(reg, temp);
3975 for (i = 0; i < 4; i++) {
3976 reg = FDI_TX_CTL(pipe);
3977 temp = I915_READ(reg);
3978 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3979 temp |= snb_b_fdi_train_param[i];
3980 I915_WRITE(reg, temp);
3985 for (retry = 0; retry < 5; retry++) {
3986 reg = FDI_RX_IIR(pipe);
3987 temp = I915_READ(reg);
3988 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3989 if (temp & FDI_RX_SYMBOL_LOCK) {
3990 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3991 DRM_DEBUG_KMS("FDI train 2 done.\n");
4000 DRM_ERROR("FDI train 2 fail!\n");
4002 DRM_DEBUG_KMS("FDI train done.\n");
4005 /* Manual link training for Ivy Bridge A0 parts */
4006 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
4008 struct drm_device *dev = crtc->dev;
4009 struct drm_i915_private *dev_priv = to_i915(dev);
4010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4011 int pipe = intel_crtc->pipe;
4015 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
4017 reg = FDI_RX_IMR(pipe);
4018 temp = I915_READ(reg);
4019 temp &= ~FDI_RX_SYMBOL_LOCK;
4020 temp &= ~FDI_RX_BIT_LOCK;
4021 I915_WRITE(reg, temp);
4026 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
4027 I915_READ(FDI_RX_IIR(pipe)));
4029 /* Try each vswing and preemphasis setting twice before moving on */
4030 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
4031 /* disable first in case we need to retry */
4032 reg = FDI_TX_CTL(pipe);
4033 temp = I915_READ(reg);
4034 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
4035 temp &= ~FDI_TX_ENABLE;
4036 I915_WRITE(reg, temp);
4038 reg = FDI_RX_CTL(pipe);
4039 temp = I915_READ(reg);
4040 temp &= ~FDI_LINK_TRAIN_AUTO;
4041 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4042 temp &= ~FDI_RX_ENABLE;
4043 I915_WRITE(reg, temp);
4045 /* enable CPU FDI TX and PCH FDI RX */
4046 reg = FDI_TX_CTL(pipe);
4047 temp = I915_READ(reg);
4048 temp &= ~FDI_DP_PORT_WIDTH_MASK;
4049 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4050 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
4051 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
4052 temp |= snb_b_fdi_train_param[j/2];
4053 temp |= FDI_COMPOSITE_SYNC;
4054 I915_WRITE(reg, temp | FDI_TX_ENABLE);
4056 I915_WRITE(FDI_RX_MISC(pipe),
4057 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
4059 reg = FDI_RX_CTL(pipe);
4060 temp = I915_READ(reg);
4061 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4062 temp |= FDI_COMPOSITE_SYNC;
4063 I915_WRITE(reg, temp | FDI_RX_ENABLE);
4066 udelay(1); /* should be 0.5us */
4068 for (i = 0; i < 4; i++) {
4069 reg = FDI_RX_IIR(pipe);
4070 temp = I915_READ(reg);
4071 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4073 if (temp & FDI_RX_BIT_LOCK ||
4074 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4075 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4076 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4080 udelay(1); /* should be 0.5us */
4083 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4088 reg = FDI_TX_CTL(pipe);
4089 temp = I915_READ(reg);
4090 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4091 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4092 I915_WRITE(reg, temp);
4094 reg = FDI_RX_CTL(pipe);
4095 temp = I915_READ(reg);
4096 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4097 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
4098 I915_WRITE(reg, temp);
4101 udelay(2); /* should be 1.5us */
4103 for (i = 0; i < 4; i++) {
4104 reg = FDI_RX_IIR(pipe);
4105 temp = I915_READ(reg);
4106 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
4108 if (temp & FDI_RX_SYMBOL_LOCK ||
4109 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4110 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4111 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4115 udelay(2); /* should be 1.5us */
4118 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
4122 DRM_DEBUG_KMS("FDI train done.\n");
4125 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
4127 struct drm_device *dev = intel_crtc->base.dev;
4128 struct drm_i915_private *dev_priv = to_i915(dev);
4129 int pipe = intel_crtc->pipe;
4133 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
4134 reg = FDI_RX_CTL(pipe);
4135 temp = I915_READ(reg);
4136 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
4137 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
4138 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4139 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4144 /* Switch from Rawclk to PCDclk */
4145 temp = I915_READ(reg);
4146 I915_WRITE(reg, temp | FDI_PCDCLK);
4151 /* Enable CPU FDI TX PLL, always on for Ironlake */
4152 reg = FDI_TX_CTL(pipe);
4153 temp = I915_READ(reg);
4154 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4155 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4162 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4164 struct drm_device *dev = intel_crtc->base.dev;
4165 struct drm_i915_private *dev_priv = to_i915(dev);
4166 int pipe = intel_crtc->pipe;
4170 /* Switch from PCDclk to Rawclk */
4171 reg = FDI_RX_CTL(pipe);
4172 temp = I915_READ(reg);
4173 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4175 /* Disable CPU FDI TX PLL */
4176 reg = FDI_TX_CTL(pipe);
4177 temp = I915_READ(reg);
4178 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4183 reg = FDI_RX_CTL(pipe);
4184 temp = I915_READ(reg);
4185 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4187 /* Wait for the clocks to turn off. */
4192 static void ironlake_fdi_disable(struct drm_crtc *crtc)
4194 struct drm_device *dev = crtc->dev;
4195 struct drm_i915_private *dev_priv = to_i915(dev);
4196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4197 int pipe = intel_crtc->pipe;
4201 /* disable CPU FDI tx and PCH FDI rx */
4202 reg = FDI_TX_CTL(pipe);
4203 temp = I915_READ(reg);
4204 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4207 reg = FDI_RX_CTL(pipe);
4208 temp = I915_READ(reg);
4209 temp &= ~(0x7 << 16);
4210 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4211 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4216 /* Ironlake workaround, disable clock pointer after downing FDI */
4217 if (HAS_PCH_IBX(dev))
4218 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
4220 /* still set train pattern 1 */
4221 reg = FDI_TX_CTL(pipe);
4222 temp = I915_READ(reg);
4223 temp &= ~FDI_LINK_TRAIN_NONE;
4224 temp |= FDI_LINK_TRAIN_PATTERN_1;
4225 I915_WRITE(reg, temp);
4227 reg = FDI_RX_CTL(pipe);
4228 temp = I915_READ(reg);
4229 if (HAS_PCH_CPT(dev)) {
4230 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4231 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4233 temp &= ~FDI_LINK_TRAIN_NONE;
4234 temp |= FDI_LINK_TRAIN_PATTERN_1;
4236 /* BPC in FDI rx is consistent with that in PIPECONF */
4237 temp &= ~(0x07 << 16);
4238 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
4239 I915_WRITE(reg, temp);
4245 bool intel_has_pending_fb_unpin(struct drm_device *dev)
4247 struct intel_crtc *crtc;
4249 /* Note that we don't need to be called with mode_config.lock here
4250 * as our list of CRTC objects is static for the lifetime of the
4251 * device and so cannot disappear as we iterate. Similarly, we can
4252 * happily treat the predicates as racy, atomic checks as userspace
4253 * cannot claim and pin a new fb without at least acquring the
4254 * struct_mutex and so serialising with us.
4256 for_each_intel_crtc(dev, crtc) {
4257 if (atomic_read(&crtc->unpin_work_count) == 0)
4260 if (crtc->flip_work)
4261 intel_wait_for_vblank(dev, crtc->pipe);
4269 static void page_flip_completed(struct intel_crtc *intel_crtc)
4271 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
4272 struct intel_flip_work *work = intel_crtc->flip_work;
4274 intel_crtc->flip_work = NULL;
4277 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
4279 drm_crtc_vblank_put(&intel_crtc->base);
4281 wake_up_all(&dev_priv->pending_flip_queue);
4282 trace_i915_flip_complete(intel_crtc->plane,
4283 work->pending_flip_obj);
4285 queue_work(dev_priv->wq, &work->unpin_work);
4288 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
4290 struct drm_device *dev = crtc->dev;
4291 struct drm_i915_private *dev_priv = to_i915(dev);
4294 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
4296 ret = wait_event_interruptible_timeout(
4297 dev_priv->pending_flip_queue,
4298 !intel_crtc_has_pending_flip(crtc),
4305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4306 struct intel_flip_work *work;
4308 spin_lock_irq(&dev->event_lock);
4309 work = intel_crtc->flip_work;
4310 if (work && !is_mmio_work(work)) {
4311 WARN_ONCE(1, "Removing stuck page flip\n");
4312 page_flip_completed(intel_crtc);
4314 spin_unlock_irq(&dev->event_lock);
4320 void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
4324 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4326 mutex_lock(&dev_priv->sb_lock);
4328 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4329 temp |= SBI_SSCCTL_DISABLE;
4330 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4332 mutex_unlock(&dev_priv->sb_lock);
4335 /* Program iCLKIP clock to the desired frequency */
4336 static void lpt_program_iclkip(struct drm_crtc *crtc)
4338 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4339 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
4340 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4343 lpt_disable_iclkip(dev_priv);
4345 /* The iCLK virtual clock root frequency is in MHz,
4346 * but the adjusted_mode->crtc_clock in in KHz. To get the
4347 * divisors, it is necessary to divide one by another, so we
4348 * convert the virtual clock precision to KHz here for higher
4351 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
4352 u32 iclk_virtual_root_freq = 172800 * 1000;
4353 u32 iclk_pi_range = 64;
4354 u32 desired_divisor;
4356 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4358 divsel = (desired_divisor / iclk_pi_range) - 2;
4359 phaseinc = desired_divisor % iclk_pi_range;
4362 * Near 20MHz is a corner case which is
4363 * out of range for the 7-bit divisor
4369 /* This should not happen with any sane values */
4370 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4371 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4372 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4373 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4375 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4382 mutex_lock(&dev_priv->sb_lock);
4384 /* Program SSCDIVINTPHASE6 */
4385 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4386 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4387 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4388 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4389 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4390 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4391 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4392 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4394 /* Program SSCAUXDIV */
4395 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4396 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4397 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4398 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4400 /* Enable modulator and associated divider */
4401 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4402 temp &= ~SBI_SSCCTL_DISABLE;
4403 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4405 mutex_unlock(&dev_priv->sb_lock);
4407 /* Wait for initialization time */
4410 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4413 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4415 u32 divsel, phaseinc, auxdiv;
4416 u32 iclk_virtual_root_freq = 172800 * 1000;
4417 u32 iclk_pi_range = 64;
4418 u32 desired_divisor;
4421 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4424 mutex_lock(&dev_priv->sb_lock);
4426 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4427 if (temp & SBI_SSCCTL_DISABLE) {
4428 mutex_unlock(&dev_priv->sb_lock);
4432 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4433 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4434 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4435 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4436 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4438 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4439 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4440 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4442 mutex_unlock(&dev_priv->sb_lock);
4444 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4446 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4447 desired_divisor << auxdiv);
4450 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4451 enum pipe pch_transcoder)
4453 struct drm_device *dev = crtc->base.dev;
4454 struct drm_i915_private *dev_priv = to_i915(dev);
4455 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4457 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4458 I915_READ(HTOTAL(cpu_transcoder)));
4459 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4460 I915_READ(HBLANK(cpu_transcoder)));
4461 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4462 I915_READ(HSYNC(cpu_transcoder)));
4464 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4465 I915_READ(VTOTAL(cpu_transcoder)));
4466 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4467 I915_READ(VBLANK(cpu_transcoder)));
4468 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4469 I915_READ(VSYNC(cpu_transcoder)));
4470 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4471 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4474 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4476 struct drm_i915_private *dev_priv = to_i915(dev);
4479 temp = I915_READ(SOUTH_CHICKEN1);
4480 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4483 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4486 temp &= ~FDI_BC_BIFURCATION_SELECT;
4488 temp |= FDI_BC_BIFURCATION_SELECT;
4490 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4491 I915_WRITE(SOUTH_CHICKEN1, temp);
4492 POSTING_READ(SOUTH_CHICKEN1);
4495 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4497 struct drm_device *dev = intel_crtc->base.dev;
4499 switch (intel_crtc->pipe) {
4503 if (intel_crtc->config->fdi_lanes > 2)
4504 cpt_set_fdi_bc_bifurcation(dev, false);
4506 cpt_set_fdi_bc_bifurcation(dev, true);
4510 cpt_set_fdi_bc_bifurcation(dev, true);
4518 /* Return which DP Port should be selected for Transcoder DP control */
4520 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4522 struct drm_device *dev = crtc->dev;
4523 struct intel_encoder *encoder;
4525 for_each_encoder_on_crtc(dev, crtc, encoder) {
4526 if (encoder->type == INTEL_OUTPUT_DP ||
4527 encoder->type == INTEL_OUTPUT_EDP)
4528 return enc_to_dig_port(&encoder->base)->port;
4535 * Enable PCH resources required for PCH ports:
4537 * - FDI training & RX/TX
4538 * - update transcoder timings
4539 * - DP transcoding bits
4542 static void ironlake_pch_enable(struct drm_crtc *crtc)
4544 struct drm_device *dev = crtc->dev;
4545 struct drm_i915_private *dev_priv = to_i915(dev);
4546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4547 int pipe = intel_crtc->pipe;
4550 assert_pch_transcoder_disabled(dev_priv, pipe);
4552 if (IS_IVYBRIDGE(dev))
4553 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4555 /* Write the TU size bits before fdi link training, so that error
4556 * detection works. */
4557 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4558 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4560 /* For PCH output, training FDI link */
4561 dev_priv->display.fdi_link_train(crtc);
4563 /* We need to program the right clock selection before writing the pixel
4564 * mutliplier into the DPLL. */
4565 if (HAS_PCH_CPT(dev)) {
4568 temp = I915_READ(PCH_DPLL_SEL);
4569 temp |= TRANS_DPLL_ENABLE(pipe);
4570 sel = TRANS_DPLLB_SEL(pipe);
4571 if (intel_crtc->config->shared_dpll ==
4572 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4576 I915_WRITE(PCH_DPLL_SEL, temp);
4579 /* XXX: pch pll's can be enabled any time before we enable the PCH
4580 * transcoder, and we actually should do this to not upset any PCH
4581 * transcoder that already use the clock when we share it.
4583 * Note that enable_shared_dpll tries to do the right thing, but
4584 * get_shared_dpll unconditionally resets the pll - we need that to have
4585 * the right LVDS enable sequence. */
4586 intel_enable_shared_dpll(intel_crtc);
4588 /* set transcoder timing, panel must allow it */
4589 assert_panel_unlocked(dev_priv, pipe);
4590 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4592 intel_fdi_normal_train(crtc);
4594 /* For PCH DP, enable TRANS_DP_CTL */
4595 if (HAS_PCH_CPT(dev) && intel_crtc_has_dp_encoder(intel_crtc->config)) {
4596 const struct drm_display_mode *adjusted_mode =
4597 &intel_crtc->config->base.adjusted_mode;
4598 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4599 i915_reg_t reg = TRANS_DP_CTL(pipe);
4600 temp = I915_READ(reg);
4601 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4602 TRANS_DP_SYNC_MASK |
4604 temp |= TRANS_DP_OUTPUT_ENABLE;
4605 temp |= bpc << 9; /* same format but at 11:9 */
4607 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4608 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4609 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4610 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4612 switch (intel_trans_dp_port_sel(crtc)) {
4614 temp |= TRANS_DP_PORT_SEL_B;
4617 temp |= TRANS_DP_PORT_SEL_C;
4620 temp |= TRANS_DP_PORT_SEL_D;
4626 I915_WRITE(reg, temp);
4629 ironlake_enable_pch_transcoder(dev_priv, pipe);
4632 static void lpt_pch_enable(struct drm_crtc *crtc)
4634 struct drm_device *dev = crtc->dev;
4635 struct drm_i915_private *dev_priv = to_i915(dev);
4636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4637 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4639 assert_pch_transcoder_disabled(dev_priv, PIPE_A);
4641 lpt_program_iclkip(crtc);
4643 /* Set transcoder timing. */
4644 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4646 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4649 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4651 struct drm_i915_private *dev_priv = to_i915(dev);
4652 i915_reg_t dslreg = PIPEDSL(pipe);
4655 temp = I915_READ(dslreg);
4657 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4658 if (wait_for(I915_READ(dslreg) != temp, 5))
4659 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4664 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4665 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4666 int src_w, int src_h, int dst_w, int dst_h)
4668 struct intel_crtc_scaler_state *scaler_state =
4669 &crtc_state->scaler_state;
4670 struct intel_crtc *intel_crtc =
4671 to_intel_crtc(crtc_state->base.crtc);
4674 need_scaling = intel_rotation_90_or_270(rotation) ?
4675 (src_h != dst_w || src_w != dst_h):
4676 (src_w != dst_w || src_h != dst_h);
4679 * if plane is being disabled or scaler is no more required or force detach
4680 * - free scaler binded to this plane/crtc
4681 * - in order to do this, update crtc->scaler_usage
4683 * Here scaler state in crtc_state is set free so that
4684 * scaler can be assigned to other user. Actual register
4685 * update to free the scaler is done in plane/panel-fit programming.
4686 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4688 if (force_detach || !need_scaling) {
4689 if (*scaler_id >= 0) {
4690 scaler_state->scaler_users &= ~(1 << scaler_user);
4691 scaler_state->scalers[*scaler_id].in_use = 0;
4693 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4694 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4695 intel_crtc->pipe, scaler_user, *scaler_id,
4696 scaler_state->scaler_users);
4703 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4704 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4706 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4707 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4708 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4709 "size is out of scaler range\n",
4710 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4714 /* mark this plane as a scaler user in crtc_state */
4715 scaler_state->scaler_users |= (1 << scaler_user);
4716 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4717 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4718 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4719 scaler_state->scaler_users);
4725 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4727 * @state: crtc's scaler state
4730 * 0 - scaler_usage updated successfully
4731 * error - requested scaling cannot be supported or other error condition
4733 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4735 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4736 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4738 DRM_DEBUG_KMS("Updating scaler for [CRTC:%d:%s] scaler_user index %u.%u\n",
4739 intel_crtc->base.base.id, intel_crtc->base.name,
4740 intel_crtc->pipe, SKL_CRTC_INDEX);
4742 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4743 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4744 state->pipe_src_w, state->pipe_src_h,
4745 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4749 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4751 * @state: crtc's scaler state
4752 * @plane_state: atomic plane state to update
4755 * 0 - scaler_usage updated successfully
4756 * error - requested scaling cannot be supported or other error condition
4758 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4759 struct intel_plane_state *plane_state)
4762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4763 struct intel_plane *intel_plane =
4764 to_intel_plane(plane_state->base.plane);
4765 struct drm_framebuffer *fb = plane_state->base.fb;
4768 bool force_detach = !fb || !plane_state->base.visible;
4770 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d:%s] scaler_user index %u.%u\n",
4771 intel_plane->base.base.id, intel_plane->base.name,
4772 intel_crtc->pipe, drm_plane_index(&intel_plane->base));
4774 ret = skl_update_scaler(crtc_state, force_detach,
4775 drm_plane_index(&intel_plane->base),
4776 &plane_state->scaler_id,
4777 plane_state->base.rotation,
4778 drm_rect_width(&plane_state->base.src) >> 16,
4779 drm_rect_height(&plane_state->base.src) >> 16,
4780 drm_rect_width(&plane_state->base.dst),
4781 drm_rect_height(&plane_state->base.dst));
4783 if (ret || plane_state->scaler_id < 0)
4786 /* check colorkey */
4787 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4788 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4789 intel_plane->base.base.id,
4790 intel_plane->base.name);
4794 /* Check src format */
4795 switch (fb->pixel_format) {
4796 case DRM_FORMAT_RGB565:
4797 case DRM_FORMAT_XBGR8888:
4798 case DRM_FORMAT_XRGB8888:
4799 case DRM_FORMAT_ABGR8888:
4800 case DRM_FORMAT_ARGB8888:
4801 case DRM_FORMAT_XRGB2101010:
4802 case DRM_FORMAT_XBGR2101010:
4803 case DRM_FORMAT_YUYV:
4804 case DRM_FORMAT_YVYU:
4805 case DRM_FORMAT_UYVY:
4806 case DRM_FORMAT_VYUY:
4809 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4810 intel_plane->base.base.id, intel_plane->base.name,
4811 fb->base.id, fb->pixel_format);
4818 static void skylake_scaler_disable(struct intel_crtc *crtc)
4822 for (i = 0; i < crtc->num_scalers; i++)
4823 skl_detach_scaler(crtc, i);
4826 static void skylake_pfit_enable(struct intel_crtc *crtc)
4828 struct drm_device *dev = crtc->base.dev;
4829 struct drm_i915_private *dev_priv = to_i915(dev);
4830 int pipe = crtc->pipe;
4831 struct intel_crtc_scaler_state *scaler_state =
4832 &crtc->config->scaler_state;
4834 if (crtc->config->pch_pfit.enabled) {
4837 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
4840 id = scaler_state->scaler_id;
4841 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4842 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4843 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4844 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4848 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4850 struct drm_device *dev = crtc->base.dev;
4851 struct drm_i915_private *dev_priv = to_i915(dev);
4852 int pipe = crtc->pipe;
4854 if (crtc->config->pch_pfit.enabled) {
4855 /* Force use of hard-coded filter coefficients
4856 * as some pre-programmed values are broken,
4859 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4860 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4861 PF_PIPE_SEL_IVB(pipe));
4863 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4864 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4865 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4869 void hsw_enable_ips(struct intel_crtc *crtc)
4871 struct drm_device *dev = crtc->base.dev;
4872 struct drm_i915_private *dev_priv = to_i915(dev);
4874 if (!crtc->config->ips_enabled)
4878 * We can only enable IPS after we enable a plane and wait for a vblank
4879 * This function is called from post_plane_update, which is run after
4883 assert_plane_enabled(dev_priv, crtc->plane);
4884 if (IS_BROADWELL(dev)) {
4885 mutex_lock(&dev_priv->rps.hw_lock);
4886 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4887 mutex_unlock(&dev_priv->rps.hw_lock);
4888 /* Quoting Art Runyan: "its not safe to expect any particular
4889 * value in IPS_CTL bit 31 after enabling IPS through the
4890 * mailbox." Moreover, the mailbox may return a bogus state,
4891 * so we need to just enable it and continue on.
4894 I915_WRITE(IPS_CTL, IPS_ENABLE);
4895 /* The bit only becomes 1 in the next vblank, so this wait here
4896 * is essentially intel_wait_for_vblank. If we don't have this
4897 * and don't wait for vblanks until the end of crtc_enable, then
4898 * the HW state readout code will complain that the expected
4899 * IPS_CTL value is not the one we read. */
4900 if (intel_wait_for_register(dev_priv,
4901 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4903 DRM_ERROR("Timed out waiting for IPS enable\n");
4907 void hsw_disable_ips(struct intel_crtc *crtc)
4909 struct drm_device *dev = crtc->base.dev;
4910 struct drm_i915_private *dev_priv = to_i915(dev);
4912 if (!crtc->config->ips_enabled)
4915 assert_plane_enabled(dev_priv, crtc->plane);
4916 if (IS_BROADWELL(dev)) {
4917 mutex_lock(&dev_priv->rps.hw_lock);
4918 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4919 mutex_unlock(&dev_priv->rps.hw_lock);
4920 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4921 if (intel_wait_for_register(dev_priv,
4922 IPS_CTL, IPS_ENABLE, 0,
4924 DRM_ERROR("Timed out waiting for IPS disable\n");
4926 I915_WRITE(IPS_CTL, 0);
4927 POSTING_READ(IPS_CTL);
4930 /* We need to wait for a vblank before we can disable the plane. */
4931 intel_wait_for_vblank(dev, crtc->pipe);
4934 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4936 if (intel_crtc->overlay) {
4937 struct drm_device *dev = intel_crtc->base.dev;
4938 struct drm_i915_private *dev_priv = to_i915(dev);
4940 mutex_lock(&dev->struct_mutex);
4941 dev_priv->mm.interruptible = false;
4942 (void) intel_overlay_switch_off(intel_crtc->overlay);
4943 dev_priv->mm.interruptible = true;
4944 mutex_unlock(&dev->struct_mutex);
4947 /* Let userspace switch the overlay on again. In most cases userspace
4948 * has to recompute where to put it anyway.
4953 * intel_post_enable_primary - Perform operations after enabling primary plane
4954 * @crtc: the CRTC whose primary plane was just enabled
4956 * Performs potentially sleeping operations that must be done after the primary
4957 * plane is enabled, such as updating FBC and IPS. Note that this may be
4958 * called due to an explicit primary plane update, or due to an implicit
4959 * re-enable that is caused when a sprite plane is updated to no longer
4960 * completely hide the primary plane.
4963 intel_post_enable_primary(struct drm_crtc *crtc)
4965 struct drm_device *dev = crtc->dev;
4966 struct drm_i915_private *dev_priv = to_i915(dev);
4967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4968 int pipe = intel_crtc->pipe;
4971 * FIXME IPS should be fine as long as one plane is
4972 * enabled, but in practice it seems to have problems
4973 * when going from primary only to sprite only and vice
4976 hsw_enable_ips(intel_crtc);
4979 * Gen2 reports pipe underruns whenever all planes are disabled.
4980 * So don't enable underrun reporting before at least some planes
4982 * FIXME: Need to fix the logic to work when we turn off all planes
4983 * but leave the pipe running.
4986 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4988 /* Underruns don't always raise interrupts, so check manually. */
4989 intel_check_cpu_fifo_underruns(dev_priv);
4990 intel_check_pch_fifo_underruns(dev_priv);
4993 /* FIXME move all this to pre_plane_update() with proper state tracking */
4995 intel_pre_disable_primary(struct drm_crtc *crtc)
4997 struct drm_device *dev = crtc->dev;
4998 struct drm_i915_private *dev_priv = to_i915(dev);
4999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5000 int pipe = intel_crtc->pipe;
5003 * Gen2 reports pipe underruns whenever all planes are disabled.
5004 * So diasble underrun reporting before all the planes get disabled.
5005 * FIXME: Need to fix the logic to work when we turn off all planes
5006 * but leave the pipe running.
5009 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5012 * FIXME IPS should be fine as long as one plane is
5013 * enabled, but in practice it seems to have problems
5014 * when going from primary only to sprite only and vice
5017 hsw_disable_ips(intel_crtc);
5020 /* FIXME get rid of this and use pre_plane_update */
5022 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
5024 struct drm_device *dev = crtc->dev;
5025 struct drm_i915_private *dev_priv = to_i915(dev);
5026 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5027 int pipe = intel_crtc->pipe;
5029 intel_pre_disable_primary(crtc);
5032 * Vblank time updates from the shadow to live plane control register
5033 * are blocked if the memory self-refresh mode is active at that
5034 * moment. So to make sure the plane gets truly disabled, disable
5035 * first the self-refresh mode. The self-refresh enable bit in turn
5036 * will be checked/applied by the HW only at the next frame start
5037 * event which is after the vblank start event, so we need to have a
5038 * wait-for-vblank between disabling the plane and the pipe.
5040 if (HAS_GMCH_DISPLAY(dev)) {
5041 intel_set_memory_cxsr(dev_priv, false);
5042 dev_priv->wm.vlv.cxsr = false;
5043 intel_wait_for_vblank(dev, pipe);
5047 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
5049 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5050 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5051 struct intel_crtc_state *pipe_config =
5052 to_intel_crtc_state(crtc->base.state);
5053 struct drm_plane *primary = crtc->base.primary;
5054 struct drm_plane_state *old_pri_state =
5055 drm_atomic_get_existing_plane_state(old_state, primary);
5057 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5059 crtc->wm.cxsr_allowed = true;
5061 if (pipe_config->update_wm_post && pipe_config->base.active)
5062 intel_update_watermarks(&crtc->base);
5064 if (old_pri_state) {
5065 struct intel_plane_state *primary_state =
5066 to_intel_plane_state(primary->state);
5067 struct intel_plane_state *old_primary_state =
5068 to_intel_plane_state(old_pri_state);
5070 intel_fbc_post_update(crtc);
5072 if (primary_state->base.visible &&
5073 (needs_modeset(&pipe_config->base) ||
5074 !old_primary_state->base.visible))
5075 intel_post_enable_primary(&crtc->base);
5079 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
5081 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
5082 struct drm_device *dev = crtc->base.dev;
5083 struct drm_i915_private *dev_priv = to_i915(dev);
5084 struct intel_crtc_state *pipe_config =
5085 to_intel_crtc_state(crtc->base.state);
5086 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5087 struct drm_plane *primary = crtc->base.primary;
5088 struct drm_plane_state *old_pri_state =
5089 drm_atomic_get_existing_plane_state(old_state, primary);
5090 bool modeset = needs_modeset(&pipe_config->base);
5092 if (old_pri_state) {
5093 struct intel_plane_state *primary_state =
5094 to_intel_plane_state(primary->state);
5095 struct intel_plane_state *old_primary_state =
5096 to_intel_plane_state(old_pri_state);
5098 intel_fbc_pre_update(crtc, pipe_config, primary_state);
5100 if (old_primary_state->base.visible &&
5101 (modeset || !primary_state->base.visible))
5102 intel_pre_disable_primary(&crtc->base);
5105 if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev)) {
5106 crtc->wm.cxsr_allowed = false;
5109 * Vblank time updates from the shadow to live plane control register
5110 * are blocked if the memory self-refresh mode is active at that
5111 * moment. So to make sure the plane gets truly disabled, disable
5112 * first the self-refresh mode. The self-refresh enable bit in turn
5113 * will be checked/applied by the HW only at the next frame start
5114 * event which is after the vblank start event, so we need to have a
5115 * wait-for-vblank between disabling the plane and the pipe.
5117 if (old_crtc_state->base.active) {
5118 intel_set_memory_cxsr(dev_priv, false);
5119 dev_priv->wm.vlv.cxsr = false;
5120 intel_wait_for_vblank(dev, crtc->pipe);
5125 * IVB workaround: must disable low power watermarks for at least
5126 * one frame before enabling scaling. LP watermarks can be re-enabled
5127 * when scaling is disabled.
5129 * WaCxSRDisabledForSpriteScaling:ivb
5131 if (pipe_config->disable_lp_wm) {
5132 ilk_disable_lp_wm(dev);
5133 intel_wait_for_vblank(dev, crtc->pipe);
5137 * If we're doing a modeset, we're done. No need to do any pre-vblank
5138 * watermark programming here.
5140 if (needs_modeset(&pipe_config->base))
5144 * For platforms that support atomic watermarks, program the
5145 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5146 * will be the intermediate values that are safe for both pre- and
5147 * post- vblank; when vblank happens, the 'active' values will be set
5148 * to the final 'target' values and we'll do this again to get the
5149 * optimal watermarks. For gen9+ platforms, the values we program here
5150 * will be the final target values which will get automatically latched
5151 * at vblank time; no further programming will be necessary.
5153 * If a platform hasn't been transitioned to atomic watermarks yet,
5154 * we'll continue to update watermarks the old way, if flags tell
5157 if (dev_priv->display.initial_watermarks != NULL)
5158 dev_priv->display.initial_watermarks(pipe_config);
5159 else if (pipe_config->update_wm_pre)
5160 intel_update_watermarks(&crtc->base);
5163 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
5165 struct drm_device *dev = crtc->dev;
5166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5167 struct drm_plane *p;
5168 int pipe = intel_crtc->pipe;
5170 intel_crtc_dpms_overlay_disable(intel_crtc);
5172 drm_for_each_plane_mask(p, dev, plane_mask)
5173 to_intel_plane(p)->disable_plane(p, crtc);
5176 * FIXME: Once we grow proper nuclear flip support out of this we need
5177 * to compute the mask of flip planes precisely. For the time being
5178 * consider this a flip to a NULL plane.
5180 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
5183 static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
5184 struct intel_crtc_state *crtc_state,
5185 struct drm_atomic_state *old_state)
5187 struct drm_connector_state *old_conn_state;
5188 struct drm_connector *conn;
5191 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5192 struct drm_connector_state *conn_state = conn->state;
5193 struct intel_encoder *encoder =
5194 to_intel_encoder(conn_state->best_encoder);
5196 if (conn_state->crtc != crtc)
5199 if (encoder->pre_pll_enable)
5200 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
5204 static void intel_encoders_pre_enable(struct drm_crtc *crtc,
5205 struct intel_crtc_state *crtc_state,
5206 struct drm_atomic_state *old_state)
5208 struct drm_connector_state *old_conn_state;
5209 struct drm_connector *conn;
5212 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5213 struct drm_connector_state *conn_state = conn->state;
5214 struct intel_encoder *encoder =
5215 to_intel_encoder(conn_state->best_encoder);
5217 if (conn_state->crtc != crtc)
5220 if (encoder->pre_enable)
5221 encoder->pre_enable(encoder, crtc_state, conn_state);
5225 static void intel_encoders_enable(struct drm_crtc *crtc,
5226 struct intel_crtc_state *crtc_state,
5227 struct drm_atomic_state *old_state)
5229 struct drm_connector_state *old_conn_state;
5230 struct drm_connector *conn;
5233 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5234 struct drm_connector_state *conn_state = conn->state;
5235 struct intel_encoder *encoder =
5236 to_intel_encoder(conn_state->best_encoder);
5238 if (conn_state->crtc != crtc)
5241 encoder->enable(encoder, crtc_state, conn_state);
5242 intel_opregion_notify_encoder(encoder, true);
5246 static void intel_encoders_disable(struct drm_crtc *crtc,
5247 struct intel_crtc_state *old_crtc_state,
5248 struct drm_atomic_state *old_state)
5250 struct drm_connector_state *old_conn_state;
5251 struct drm_connector *conn;
5254 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5255 struct intel_encoder *encoder =
5256 to_intel_encoder(old_conn_state->best_encoder);
5258 if (old_conn_state->crtc != crtc)
5261 intel_opregion_notify_encoder(encoder, false);
5262 encoder->disable(encoder, old_crtc_state, old_conn_state);
5266 static void intel_encoders_post_disable(struct drm_crtc *crtc,
5267 struct intel_crtc_state *old_crtc_state,
5268 struct drm_atomic_state *old_state)
5270 struct drm_connector_state *old_conn_state;
5271 struct drm_connector *conn;
5274 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5275 struct intel_encoder *encoder =
5276 to_intel_encoder(old_conn_state->best_encoder);
5278 if (old_conn_state->crtc != crtc)
5281 if (encoder->post_disable)
5282 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
5286 static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
5287 struct intel_crtc_state *old_crtc_state,
5288 struct drm_atomic_state *old_state)
5290 struct drm_connector_state *old_conn_state;
5291 struct drm_connector *conn;
5294 for_each_connector_in_state(old_state, conn, old_conn_state, i) {
5295 struct intel_encoder *encoder =
5296 to_intel_encoder(old_conn_state->best_encoder);
5298 if (old_conn_state->crtc != crtc)
5301 if (encoder->post_pll_disable)
5302 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
5306 static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5307 struct drm_atomic_state *old_state)
5309 struct drm_crtc *crtc = pipe_config->base.crtc;
5310 struct drm_device *dev = crtc->dev;
5311 struct drm_i915_private *dev_priv = to_i915(dev);
5312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5313 int pipe = intel_crtc->pipe;
5315 if (WARN_ON(intel_crtc->active))
5319 * Sometimes spurious CPU pipe underruns happen during FDI
5320 * training, at least with VGA+HDMI cloning. Suppress them.
5322 * On ILK we get an occasional spurious CPU pipe underruns
5323 * between eDP port A enable and vdd enable. Also PCH port
5324 * enable seems to result in the occasional CPU pipe underrun.
5326 * Spurious PCH underruns also occur during PCH enabling.
5328 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5329 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5330 if (intel_crtc->config->has_pch_encoder)
5331 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5333 if (intel_crtc->config->has_pch_encoder)
5334 intel_prepare_shared_dpll(intel_crtc);
5336 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5337 intel_dp_set_m_n(intel_crtc, M1_N1);
5339 intel_set_pipe_timings(intel_crtc);
5340 intel_set_pipe_src_size(intel_crtc);
5342 if (intel_crtc->config->has_pch_encoder) {
5343 intel_cpu_transcoder_set_m_n(intel_crtc,
5344 &intel_crtc->config->fdi_m_n, NULL);
5347 ironlake_set_pipeconf(crtc);
5349 intel_crtc->active = true;
5351 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5353 if (intel_crtc->config->has_pch_encoder) {
5354 /* Note: FDI PLL enabling _must_ be done before we enable the
5355 * cpu pipes, hence this is separate from all the other fdi/pch
5357 ironlake_fdi_pll_enable(intel_crtc);
5359 assert_fdi_tx_disabled(dev_priv, pipe);
5360 assert_fdi_rx_disabled(dev_priv, pipe);
5363 ironlake_pfit_enable(intel_crtc);
5366 * On ILK+ LUT must be loaded before the pipe is running but with
5369 intel_color_load_luts(&pipe_config->base);
5371 if (dev_priv->display.initial_watermarks != NULL)
5372 dev_priv->display.initial_watermarks(intel_crtc->config);
5373 intel_enable_pipe(intel_crtc);
5375 if (intel_crtc->config->has_pch_encoder)
5376 ironlake_pch_enable(crtc);
5378 assert_vblank_disabled(crtc);
5379 drm_crtc_vblank_on(crtc);
5381 intel_encoders_enable(crtc, pipe_config, old_state);
5383 if (HAS_PCH_CPT(dev))
5384 cpt_verify_modeset(dev, intel_crtc->pipe);
5386 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5387 if (intel_crtc->config->has_pch_encoder)
5388 intel_wait_for_vblank(dev, pipe);
5389 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5390 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5393 /* IPS only exists on ULT machines and is tied to pipe A. */
5394 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5396 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5399 static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5400 struct drm_atomic_state *old_state)
5402 struct drm_crtc *crtc = pipe_config->base.crtc;
5403 struct drm_device *dev = crtc->dev;
5404 struct drm_i915_private *dev_priv = to_i915(dev);
5405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5406 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5407 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5409 if (WARN_ON(intel_crtc->active))
5412 if (intel_crtc->config->has_pch_encoder)
5413 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
5416 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5418 if (intel_crtc->config->shared_dpll)
5419 intel_enable_shared_dpll(intel_crtc);
5421 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5422 intel_dp_set_m_n(intel_crtc, M1_N1);
5424 if (!transcoder_is_dsi(cpu_transcoder))
5425 intel_set_pipe_timings(intel_crtc);
5427 intel_set_pipe_src_size(intel_crtc);
5429 if (cpu_transcoder != TRANSCODER_EDP &&
5430 !transcoder_is_dsi(cpu_transcoder)) {
5431 I915_WRITE(PIPE_MULT(cpu_transcoder),
5432 intel_crtc->config->pixel_multiplier - 1);
5435 if (intel_crtc->config->has_pch_encoder) {
5436 intel_cpu_transcoder_set_m_n(intel_crtc,
5437 &intel_crtc->config->fdi_m_n, NULL);
5440 if (!transcoder_is_dsi(cpu_transcoder))
5441 haswell_set_pipeconf(crtc);
5443 haswell_set_pipemisc(crtc);
5445 intel_color_set_csc(&pipe_config->base);
5447 intel_crtc->active = true;
5449 if (intel_crtc->config->has_pch_encoder)
5450 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5452 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5454 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5456 if (intel_crtc->config->has_pch_encoder)
5457 dev_priv->display.fdi_link_train(crtc);
5459 if (!transcoder_is_dsi(cpu_transcoder))
5460 intel_ddi_enable_pipe_clock(intel_crtc);
5462 if (INTEL_INFO(dev)->gen >= 9)
5463 skylake_pfit_enable(intel_crtc);
5465 ironlake_pfit_enable(intel_crtc);
5468 * On ILK+ LUT must be loaded before the pipe is running but with
5471 intel_color_load_luts(&pipe_config->base);
5473 intel_ddi_set_pipe_settings(crtc);
5474 if (!transcoder_is_dsi(cpu_transcoder))
5475 intel_ddi_enable_transcoder_func(crtc);
5477 if (dev_priv->display.initial_watermarks != NULL)
5478 dev_priv->display.initial_watermarks(pipe_config);
5480 intel_update_watermarks(crtc);
5482 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5483 if (!transcoder_is_dsi(cpu_transcoder))
5484 intel_enable_pipe(intel_crtc);
5486 if (intel_crtc->config->has_pch_encoder)
5487 lpt_pch_enable(crtc);
5489 if (intel_crtc->config->dp_encoder_is_mst)
5490 intel_ddi_set_vc_payload_alloc(crtc, true);
5492 assert_vblank_disabled(crtc);
5493 drm_crtc_vblank_on(crtc);
5495 intel_encoders_enable(crtc, pipe_config, old_state);
5497 if (intel_crtc->config->has_pch_encoder) {
5498 intel_wait_for_vblank(dev, pipe);
5499 intel_wait_for_vblank(dev, pipe);
5500 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5501 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
5505 /* If we change the relative order between pipe/planes enabling, we need
5506 * to change the workaround. */
5507 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5508 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5509 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5510 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5514 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5516 struct drm_device *dev = crtc->base.dev;
5517 struct drm_i915_private *dev_priv = to_i915(dev);
5518 int pipe = crtc->pipe;
5520 /* To avoid upsetting the power well on haswell only disable the pfit if
5521 * it's in use. The hw state code will make sure we get this right. */
5522 if (force || crtc->config->pch_pfit.enabled) {
5523 I915_WRITE(PF_CTL(pipe), 0);
5524 I915_WRITE(PF_WIN_POS(pipe), 0);
5525 I915_WRITE(PF_WIN_SZ(pipe), 0);
5529 static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5530 struct drm_atomic_state *old_state)
5532 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5533 struct drm_device *dev = crtc->dev;
5534 struct drm_i915_private *dev_priv = to_i915(dev);
5535 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5536 int pipe = intel_crtc->pipe;
5539 * Sometimes spurious CPU pipe underruns happen when the
5540 * pipe is already disabled, but FDI RX/TX is still enabled.
5541 * Happens at least with VGA+HDMI cloning. Suppress them.
5543 if (intel_crtc->config->has_pch_encoder) {
5544 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5545 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5548 intel_encoders_disable(crtc, old_crtc_state, old_state);
5550 drm_crtc_vblank_off(crtc);
5551 assert_vblank_disabled(crtc);
5553 intel_disable_pipe(intel_crtc);
5555 ironlake_pfit_disable(intel_crtc, false);
5557 if (intel_crtc->config->has_pch_encoder)
5558 ironlake_fdi_disable(crtc);
5560 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5562 if (intel_crtc->config->has_pch_encoder) {
5563 ironlake_disable_pch_transcoder(dev_priv, pipe);
5565 if (HAS_PCH_CPT(dev)) {
5569 /* disable TRANS_DP_CTL */
5570 reg = TRANS_DP_CTL(pipe);
5571 temp = I915_READ(reg);
5572 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5573 TRANS_DP_PORT_SEL_MASK);
5574 temp |= TRANS_DP_PORT_SEL_NONE;
5575 I915_WRITE(reg, temp);
5577 /* disable DPLL_SEL */
5578 temp = I915_READ(PCH_DPLL_SEL);
5579 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5580 I915_WRITE(PCH_DPLL_SEL, temp);
5583 ironlake_fdi_pll_disable(intel_crtc);
5586 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5587 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5590 static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5591 struct drm_atomic_state *old_state)
5593 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5594 struct drm_device *dev = crtc->dev;
5595 struct drm_i915_private *dev_priv = to_i915(dev);
5596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5597 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5599 if (intel_crtc->config->has_pch_encoder)
5600 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
5603 intel_encoders_disable(crtc, old_crtc_state, old_state);
5605 drm_crtc_vblank_off(crtc);
5606 assert_vblank_disabled(crtc);
5608 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5609 if (!transcoder_is_dsi(cpu_transcoder))
5610 intel_disable_pipe(intel_crtc);
5612 if (intel_crtc->config->dp_encoder_is_mst)
5613 intel_ddi_set_vc_payload_alloc(crtc, false);
5615 if (!transcoder_is_dsi(cpu_transcoder))
5616 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5618 if (INTEL_INFO(dev)->gen >= 9)
5619 skylake_scaler_disable(intel_crtc);
5621 ironlake_pfit_disable(intel_crtc, false);
5623 if (!transcoder_is_dsi(cpu_transcoder))
5624 intel_ddi_disable_pipe_clock(intel_crtc);
5626 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
5628 if (old_crtc_state->has_pch_encoder)
5629 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A,
5633 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5635 struct drm_device *dev = crtc->base.dev;
5636 struct drm_i915_private *dev_priv = to_i915(dev);
5637 struct intel_crtc_state *pipe_config = crtc->config;
5639 if (!pipe_config->gmch_pfit.control)
5643 * The panel fitter should only be adjusted whilst the pipe is disabled,
5644 * according to register description and PRM.
5646 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5647 assert_pipe_disabled(dev_priv, crtc->pipe);
5649 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5650 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5652 /* Border color in case we don't scale up to the full screen. Black by
5653 * default, change to something else for debugging. */
5654 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5657 static enum intel_display_power_domain port_to_power_domain(enum port port)
5661 return POWER_DOMAIN_PORT_DDI_A_LANES;
5663 return POWER_DOMAIN_PORT_DDI_B_LANES;
5665 return POWER_DOMAIN_PORT_DDI_C_LANES;
5667 return POWER_DOMAIN_PORT_DDI_D_LANES;
5669 return POWER_DOMAIN_PORT_DDI_E_LANES;
5672 return POWER_DOMAIN_PORT_OTHER;
5676 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5680 return POWER_DOMAIN_AUX_A;
5682 return POWER_DOMAIN_AUX_B;
5684 return POWER_DOMAIN_AUX_C;
5686 return POWER_DOMAIN_AUX_D;
5688 /* FIXME: Check VBT for actual wiring of PORT E */
5689 return POWER_DOMAIN_AUX_D;
5692 return POWER_DOMAIN_AUX_A;
5696 enum intel_display_power_domain
5697 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5699 struct drm_device *dev = intel_encoder->base.dev;
5700 struct intel_digital_port *intel_dig_port;
5702 switch (intel_encoder->type) {
5703 case INTEL_OUTPUT_UNKNOWN:
5704 /* Only DDI platforms should ever use this output type */
5705 WARN_ON_ONCE(!HAS_DDI(dev));
5706 case INTEL_OUTPUT_DP:
5707 case INTEL_OUTPUT_HDMI:
5708 case INTEL_OUTPUT_EDP:
5709 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5710 return port_to_power_domain(intel_dig_port->port);
5711 case INTEL_OUTPUT_DP_MST:
5712 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5713 return port_to_power_domain(intel_dig_port->port);
5714 case INTEL_OUTPUT_ANALOG:
5715 return POWER_DOMAIN_PORT_CRT;
5716 case INTEL_OUTPUT_DSI:
5717 return POWER_DOMAIN_PORT_DSI;
5719 return POWER_DOMAIN_PORT_OTHER;
5723 enum intel_display_power_domain
5724 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5726 struct drm_device *dev = intel_encoder->base.dev;
5727 struct intel_digital_port *intel_dig_port;
5729 switch (intel_encoder->type) {
5730 case INTEL_OUTPUT_UNKNOWN:
5731 case INTEL_OUTPUT_HDMI:
5733 * Only DDI platforms should ever use these output types.
5734 * We can get here after the HDMI detect code has already set
5735 * the type of the shared encoder. Since we can't be sure
5736 * what's the status of the given connectors, play safe and
5737 * run the DP detection too.
5739 WARN_ON_ONCE(!HAS_DDI(dev));
5740 case INTEL_OUTPUT_DP:
5741 case INTEL_OUTPUT_EDP:
5742 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5743 return port_to_aux_power_domain(intel_dig_port->port);
5744 case INTEL_OUTPUT_DP_MST:
5745 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5746 return port_to_aux_power_domain(intel_dig_port->port);
5748 MISSING_CASE(intel_encoder->type);
5749 return POWER_DOMAIN_AUX_A;
5753 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5754 struct intel_crtc_state *crtc_state)
5756 struct drm_device *dev = crtc->dev;
5757 struct drm_encoder *encoder;
5758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5759 enum pipe pipe = intel_crtc->pipe;
5761 enum transcoder transcoder = crtc_state->cpu_transcoder;
5763 if (!crtc_state->base.active)
5766 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5767 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5768 if (crtc_state->pch_pfit.enabled ||
5769 crtc_state->pch_pfit.force_thru)
5770 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5772 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5773 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5775 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5778 if (crtc_state->shared_dpll)
5779 mask |= BIT(POWER_DOMAIN_PLLS);
5784 static unsigned long
5785 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5786 struct intel_crtc_state *crtc_state)
5788 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5790 enum intel_display_power_domain domain;
5791 unsigned long domains, new_domains, old_domains;
5793 old_domains = intel_crtc->enabled_power_domains;
5794 intel_crtc->enabled_power_domains = new_domains =
5795 get_crtc_power_domains(crtc, crtc_state);
5797 domains = new_domains & ~old_domains;
5799 for_each_power_domain(domain, domains)
5800 intel_display_power_get(dev_priv, domain);
5802 return old_domains & ~new_domains;
5805 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5806 unsigned long domains)
5808 enum intel_display_power_domain domain;
5810 for_each_power_domain(domain, domains)
5811 intel_display_power_put(dev_priv, domain);
5814 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5816 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5818 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5819 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5820 return max_cdclk_freq;
5821 else if (IS_CHERRYVIEW(dev_priv))
5822 return max_cdclk_freq*95/100;
5823 else if (INTEL_INFO(dev_priv)->gen < 4)
5824 return 2*max_cdclk_freq*90/100;
5826 return max_cdclk_freq*90/100;
5829 static int skl_calc_cdclk(int max_pixclk, int vco);
5831 static void intel_update_max_cdclk(struct drm_device *dev)
5833 struct drm_i915_private *dev_priv = to_i915(dev);
5835 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5836 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5839 vco = dev_priv->skl_preferred_vco_freq;
5840 WARN_ON(vco != 8100000 && vco != 8640000);
5843 * Use the lower (vco 8640) cdclk values as a
5844 * first guess. skl_calc_cdclk() will correct it
5845 * if the preferred vco is 8100 instead.
5847 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5849 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5851 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5856 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
5857 } else if (IS_BROXTON(dev)) {
5858 dev_priv->max_cdclk_freq = 624000;
5859 } else if (IS_BROADWELL(dev)) {
5861 * FIXME with extra cooling we can allow
5862 * 540 MHz for ULX and 675 Mhz for ULT.
5863 * How can we know if extra cooling is
5864 * available? PCI ID, VTB, something else?
5866 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5867 dev_priv->max_cdclk_freq = 450000;
5868 else if (IS_BDW_ULX(dev))
5869 dev_priv->max_cdclk_freq = 450000;
5870 else if (IS_BDW_ULT(dev))
5871 dev_priv->max_cdclk_freq = 540000;
5873 dev_priv->max_cdclk_freq = 675000;
5874 } else if (IS_CHERRYVIEW(dev)) {
5875 dev_priv->max_cdclk_freq = 320000;
5876 } else if (IS_VALLEYVIEW(dev)) {
5877 dev_priv->max_cdclk_freq = 400000;
5879 /* otherwise assume cdclk is fixed */
5880 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5883 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5885 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5886 dev_priv->max_cdclk_freq);
5888 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5889 dev_priv->max_dotclk_freq);
5892 static void intel_update_cdclk(struct drm_device *dev)
5894 struct drm_i915_private *dev_priv = to_i915(dev);
5896 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5898 if (INTEL_GEN(dev_priv) >= 9)
5899 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
5900 dev_priv->cdclk_freq, dev_priv->cdclk_pll.vco,
5901 dev_priv->cdclk_pll.ref);
5903 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5904 dev_priv->cdclk_freq);
5907 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
5908 * Programmng [sic] note: bit[9:2] should be programmed to the number
5909 * of cdclk that generates 4MHz reference clock freq which is used to
5910 * generate GMBus clock. This will vary with the cdclk freq.
5912 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5913 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5916 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5917 static int skl_cdclk_decimal(int cdclk)
5919 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
5922 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
5926 if (cdclk == dev_priv->cdclk_pll.ref)
5931 MISSING_CASE(cdclk);
5943 return dev_priv->cdclk_pll.ref * ratio;
5946 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
5948 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
5951 if (intel_wait_for_register(dev_priv,
5952 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
5954 DRM_ERROR("timeout waiting for DE PLL unlock\n");
5956 dev_priv->cdclk_pll.vco = 0;
5959 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
5961 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk_pll.ref);
5964 val = I915_READ(BXT_DE_PLL_CTL);
5965 val &= ~BXT_DE_PLL_RATIO_MASK;
5966 val |= BXT_DE_PLL_RATIO(ratio);
5967 I915_WRITE(BXT_DE_PLL_CTL, val);
5969 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5972 if (intel_wait_for_register(dev_priv,
5977 DRM_ERROR("timeout waiting for DE PLL lock\n");
5979 dev_priv->cdclk_pll.vco = vco;
5982 static void bxt_set_cdclk(struct drm_i915_private *dev_priv, int cdclk)
5987 vco = bxt_de_pll_vco(dev_priv, cdclk);
5989 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
5991 /* cdclk = vco / 2 / div{1,1.5,2,4} */
5992 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
5994 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5997 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
6000 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
6003 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6006 WARN_ON(cdclk != dev_priv->cdclk_pll.ref);
6009 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
6013 /* Inform power controller of upcoming frequency change */
6014 mutex_lock(&dev_priv->rps.hw_lock);
6015 ret = sandybridge_pcode_write_timeout(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
6017 mutex_unlock(&dev_priv->rps.hw_lock);
6020 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
6025 if (dev_priv->cdclk_pll.vco != 0 &&
6026 dev_priv->cdclk_pll.vco != vco)
6027 bxt_de_pll_disable(dev_priv);
6029 if (dev_priv->cdclk_pll.vco != vco)
6030 bxt_de_pll_enable(dev_priv, vco);
6032 val = divider | skl_cdclk_decimal(cdclk);
6034 * FIXME if only the cd2x divider needs changing, it could be done
6035 * without shutting off the pipe (if only one pipe is active).
6037 val |= BXT_CDCLK_CD2X_PIPE_NONE;
6039 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6042 if (cdclk >= 500000)
6043 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6044 I915_WRITE(CDCLK_CTL, val);
6046 mutex_lock(&dev_priv->rps.hw_lock);
6047 ret = sandybridge_pcode_write_timeout(dev_priv,
6048 HSW_PCODE_DE_WRITE_FREQ_REQ,
6049 DIV_ROUND_UP(cdclk, 25000), 2000);
6050 mutex_unlock(&dev_priv->rps.hw_lock);
6053 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
6058 intel_update_cdclk(&dev_priv->drm);
6061 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
6063 u32 cdctl, expected;
6065 intel_update_cdclk(&dev_priv->drm);
6067 if (dev_priv->cdclk_pll.vco == 0 ||
6068 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6071 /* DPLL okay; verify the cdclock
6073 * Some BIOS versions leave an incorrect decimal frequency value and
6074 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
6075 * so sanitize this register.
6077 cdctl = I915_READ(CDCLK_CTL);
6079 * Let's ignore the pipe field, since BIOS could have configured the
6080 * dividers both synching to an active pipe, or asynchronously
6083 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
6085 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
6086 skl_cdclk_decimal(dev_priv->cdclk_freq);
6088 * Disable SSA Precharge when CD clock frequency < 500 MHz,
6091 if (dev_priv->cdclk_freq >= 500000)
6092 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
6094 if (cdctl == expected)
6095 /* All well; nothing to sanitize */
6099 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6101 /* force cdclk programming */
6102 dev_priv->cdclk_freq = 0;
6104 /* force full PLL disable + enable */
6105 dev_priv->cdclk_pll.vco = -1;
6108 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
6110 bxt_sanitize_cdclk(dev_priv);
6112 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0)
6117 * - The initial CDCLK needs to be read from VBT.
6118 * Need to make this change after VBT has changes for BXT.
6120 bxt_set_cdclk(dev_priv, bxt_calc_cdclk(0));
6123 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
6125 bxt_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref);
6128 static int skl_calc_cdclk(int max_pixclk, int vco)
6130 if (vco == 8640000) {
6131 if (max_pixclk > 540000)
6133 else if (max_pixclk > 432000)
6135 else if (max_pixclk > 308571)
6140 if (max_pixclk > 540000)
6142 else if (max_pixclk > 450000)
6144 else if (max_pixclk > 337500)
6152 skl_dpll0_update(struct drm_i915_private *dev_priv)
6156 dev_priv->cdclk_pll.ref = 24000;
6157 dev_priv->cdclk_pll.vco = 0;
6159 val = I915_READ(LCPLL1_CTL);
6160 if ((val & LCPLL_PLL_ENABLE) == 0)
6163 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
6166 val = I915_READ(DPLL_CTRL1);
6168 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
6169 DPLL_CTRL1_SSC(SKL_DPLL0) |
6170 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
6171 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
6174 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
6175 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
6176 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
6177 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
6178 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
6179 dev_priv->cdclk_pll.vco = 8100000;
6181 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
6182 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
6183 dev_priv->cdclk_pll.vco = 8640000;
6186 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6191 void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, int vco)
6193 bool changed = dev_priv->skl_preferred_vco_freq != vco;
6195 dev_priv->skl_preferred_vco_freq = vco;
6198 intel_update_max_cdclk(&dev_priv->drm);
6202 skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
6204 int min_cdclk = skl_calc_cdclk(0, vco);
6207 WARN_ON(vco != 8100000 && vco != 8640000);
6209 /* select the minimum CDCLK before enabling DPLL 0 */
6210 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
6211 I915_WRITE(CDCLK_CTL, val);
6212 POSTING_READ(CDCLK_CTL);
6215 * We always enable DPLL0 with the lowest link rate possible, but still
6216 * taking into account the VCO required to operate the eDP panel at the
6217 * desired frequency. The usual DP link rates operate with a VCO of
6218 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
6219 * The modeset code is responsible for the selection of the exact link
6220 * rate later on, with the constraint of choosing a frequency that
6223 val = I915_READ(DPLL_CTRL1);
6225 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
6226 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
6227 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
6229 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
6232 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
6235 I915_WRITE(DPLL_CTRL1, val);
6236 POSTING_READ(DPLL_CTRL1);
6238 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
6240 if (intel_wait_for_register(dev_priv,
6241 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
6243 DRM_ERROR("DPLL0 not locked\n");
6245 dev_priv->cdclk_pll.vco = vco;
6247 /* We'll want to keep using the current vco from now on. */
6248 skl_set_preferred_cdclk_vco(dev_priv, vco);
6252 skl_dpll0_disable(struct drm_i915_private *dev_priv)
6254 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
6255 if (intel_wait_for_register(dev_priv,
6256 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
6258 DRM_ERROR("Couldn't disable DPLL0\n");
6260 dev_priv->cdclk_pll.vco = 0;
6263 static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk, int vco)
6265 struct drm_device *dev = &dev_priv->drm;
6266 u32 freq_select, pcu_ack;
6269 WARN_ON((cdclk == 24000) != (vco == 0));
6271 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz (VCO %d kHz)\n", cdclk, vco);
6273 mutex_lock(&dev_priv->rps.hw_lock);
6274 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
6275 SKL_CDCLK_PREPARE_FOR_CHANGE,
6276 SKL_CDCLK_READY_FOR_CHANGE,
6277 SKL_CDCLK_READY_FOR_CHANGE, 3);
6278 mutex_unlock(&dev_priv->rps.hw_lock);
6280 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
6289 freq_select = CDCLK_FREQ_450_432;
6293 freq_select = CDCLK_FREQ_540;
6299 freq_select = CDCLK_FREQ_337_308;
6304 freq_select = CDCLK_FREQ_675_617;
6309 if (dev_priv->cdclk_pll.vco != 0 &&
6310 dev_priv->cdclk_pll.vco != vco)
6311 skl_dpll0_disable(dev_priv);
6313 if (dev_priv->cdclk_pll.vco != vco)
6314 skl_dpll0_enable(dev_priv, vco);
6316 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
6317 POSTING_READ(CDCLK_CTL);
6319 /* inform PCU of the change */
6320 mutex_lock(&dev_priv->rps.hw_lock);
6321 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
6322 mutex_unlock(&dev_priv->rps.hw_lock);
6324 intel_update_cdclk(dev);
6327 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv);
6329 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
6331 skl_set_cdclk(dev_priv, dev_priv->cdclk_pll.ref, 0);
6334 void skl_init_cdclk(struct drm_i915_private *dev_priv)
6338 skl_sanitize_cdclk(dev_priv);
6340 if (dev_priv->cdclk_freq != 0 && dev_priv->cdclk_pll.vco != 0) {
6342 * Use the current vco as our initial
6343 * guess as to what the preferred vco is.
6345 if (dev_priv->skl_preferred_vco_freq == 0)
6346 skl_set_preferred_cdclk_vco(dev_priv,
6347 dev_priv->cdclk_pll.vco);
6351 vco = dev_priv->skl_preferred_vco_freq;
6354 cdclk = skl_calc_cdclk(0, vco);
6356 skl_set_cdclk(dev_priv, cdclk, vco);
6359 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
6361 uint32_t cdctl, expected;
6364 * check if the pre-os intialized the display
6365 * There is SWF18 scratchpad register defined which is set by the
6366 * pre-os which can be used by the OS drivers to check the status
6368 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
6371 intel_update_cdclk(&dev_priv->drm);
6372 /* Is PLL enabled and locked ? */
6373 if (dev_priv->cdclk_pll.vco == 0 ||
6374 dev_priv->cdclk_freq == dev_priv->cdclk_pll.ref)
6377 /* DPLL okay; verify the cdclock
6379 * Noticed in some instances that the freq selection is correct but
6380 * decimal part is programmed wrong from BIOS where pre-os does not
6381 * enable display. Verify the same as well.
6383 cdctl = I915_READ(CDCLK_CTL);
6384 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
6385 skl_cdclk_decimal(dev_priv->cdclk_freq);
6386 if (cdctl == expected)
6387 /* All well; nothing to sanitize */
6391 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
6393 /* force cdclk programming */
6394 dev_priv->cdclk_freq = 0;
6395 /* force full PLL disable + enable */
6396 dev_priv->cdclk_pll.vco = -1;
6399 /* Adjust CDclk dividers to allow high res or save power if possible */
6400 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
6402 struct drm_i915_private *dev_priv = to_i915(dev);
6405 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6406 != dev_priv->cdclk_freq);
6408 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
6410 else if (cdclk == 266667)
6415 mutex_lock(&dev_priv->rps.hw_lock);
6416 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6417 val &= ~DSPFREQGUAR_MASK;
6418 val |= (cmd << DSPFREQGUAR_SHIFT);
6419 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6420 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6421 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
6423 DRM_ERROR("timed out waiting for CDclk change\n");
6425 mutex_unlock(&dev_priv->rps.hw_lock);
6427 mutex_lock(&dev_priv->sb_lock);
6429 if (cdclk == 400000) {
6432 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6434 /* adjust cdclk divider */
6435 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6436 val &= ~CCK_FREQUENCY_VALUES;
6438 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
6440 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
6441 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
6443 DRM_ERROR("timed out waiting for CDclk change\n");
6446 /* adjust self-refresh exit latency value */
6447 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6451 * For high bandwidth configs, we set a higher latency in the bunit
6452 * so that the core display fetch happens in time to avoid underruns.
6454 if (cdclk == 400000)
6455 val |= 4500 / 250; /* 4.5 usec */
6457 val |= 3000 / 250; /* 3.0 usec */
6458 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6460 mutex_unlock(&dev_priv->sb_lock);
6462 intel_update_cdclk(dev);
6465 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6467 struct drm_i915_private *dev_priv = to_i915(dev);
6470 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6471 != dev_priv->cdclk_freq);
6480 MISSING_CASE(cdclk);
6485 * Specs are full of misinformation, but testing on actual
6486 * hardware has shown that we just need to write the desired
6487 * CCK divider into the Punit register.
6489 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6491 mutex_lock(&dev_priv->rps.hw_lock);
6492 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6493 val &= ~DSPFREQGUAR_MASK_CHV;
6494 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6495 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6496 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6497 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6499 DRM_ERROR("timed out waiting for CDclk change\n");
6501 mutex_unlock(&dev_priv->rps.hw_lock);
6503 intel_update_cdclk(dev);
6506 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6509 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6510 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6513 * Really only a few cases to deal with, as only 4 CDclks are supported:
6516 * 320/333MHz (depends on HPLL freq)
6518 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6519 * of the lower bin and adjust if needed.
6521 * We seem to get an unstable or solid color picture at 200MHz.
6522 * Not sure what's wrong. For now use 200MHz only when all pipes
6525 if (!IS_CHERRYVIEW(dev_priv) &&
6526 max_pixclk > freq_320*limit/100)
6528 else if (max_pixclk > 266667*limit/100)
6530 else if (max_pixclk > 0)
6536 static int bxt_calc_cdclk(int max_pixclk)
6538 if (max_pixclk > 576000)
6540 else if (max_pixclk > 384000)
6542 else if (max_pixclk > 288000)
6544 else if (max_pixclk > 144000)
6550 /* Compute the max pixel clock for new configuration. */
6551 static int intel_mode_max_pixclk(struct drm_device *dev,
6552 struct drm_atomic_state *state)
6554 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6555 struct drm_i915_private *dev_priv = to_i915(dev);
6556 struct drm_crtc *crtc;
6557 struct drm_crtc_state *crtc_state;
6558 unsigned max_pixclk = 0, i;
6561 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6562 sizeof(intel_state->min_pixclk));
6564 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6567 if (crtc_state->enable)
6568 pixclk = crtc_state->adjusted_mode.crtc_clock;
6570 intel_state->min_pixclk[i] = pixclk;
6573 for_each_pipe(dev_priv, pipe)
6574 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6579 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6581 struct drm_device *dev = state->dev;
6582 struct drm_i915_private *dev_priv = to_i915(dev);
6583 int max_pixclk = intel_mode_max_pixclk(dev, state);
6584 struct intel_atomic_state *intel_state =
6585 to_intel_atomic_state(state);
6587 intel_state->cdclk = intel_state->dev_cdclk =
6588 valleyview_calc_cdclk(dev_priv, max_pixclk);
6590 if (!intel_state->active_crtcs)
6591 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6596 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
6598 int max_pixclk = ilk_max_pixel_rate(state);
6599 struct intel_atomic_state *intel_state =
6600 to_intel_atomic_state(state);
6602 intel_state->cdclk = intel_state->dev_cdclk =
6603 bxt_calc_cdclk(max_pixclk);
6605 if (!intel_state->active_crtcs)
6606 intel_state->dev_cdclk = bxt_calc_cdclk(0);
6611 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6613 unsigned int credits, default_credits;
6615 if (IS_CHERRYVIEW(dev_priv))
6616 default_credits = PFI_CREDIT(12);
6618 default_credits = PFI_CREDIT(8);
6620 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6621 /* CHV suggested value is 31 or 63 */
6622 if (IS_CHERRYVIEW(dev_priv))
6623 credits = PFI_CREDIT_63;
6625 credits = PFI_CREDIT(15);
6627 credits = default_credits;
6631 * WA - write default credits before re-programming
6632 * FIXME: should we also set the resend bit here?
6634 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6637 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6638 credits | PFI_CREDIT_RESEND);
6641 * FIXME is this guaranteed to clear
6642 * immediately or should we poll for it?
6644 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6647 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6649 struct drm_device *dev = old_state->dev;
6650 struct drm_i915_private *dev_priv = to_i915(dev);
6651 struct intel_atomic_state *old_intel_state =
6652 to_intel_atomic_state(old_state);
6653 unsigned req_cdclk = old_intel_state->dev_cdclk;
6656 * FIXME: We can end up here with all power domains off, yet
6657 * with a CDCLK frequency other than the minimum. To account
6658 * for this take the PIPE-A power domain, which covers the HW
6659 * blocks needed for the following programming. This can be
6660 * removed once it's guaranteed that we get here either with
6661 * the minimum CDCLK set, or the required power domains
6664 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6666 if (IS_CHERRYVIEW(dev))
6667 cherryview_set_cdclk(dev, req_cdclk);
6669 valleyview_set_cdclk(dev, req_cdclk);
6671 vlv_program_pfi_credits(dev_priv);
6673 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6676 static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
6677 struct drm_atomic_state *old_state)
6679 struct drm_crtc *crtc = pipe_config->base.crtc;
6680 struct drm_device *dev = crtc->dev;
6681 struct drm_i915_private *dev_priv = to_i915(dev);
6682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6683 int pipe = intel_crtc->pipe;
6685 if (WARN_ON(intel_crtc->active))
6688 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6689 intel_dp_set_m_n(intel_crtc, M1_N1);
6691 intel_set_pipe_timings(intel_crtc);
6692 intel_set_pipe_src_size(intel_crtc);
6694 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6695 struct drm_i915_private *dev_priv = to_i915(dev);
6697 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6698 I915_WRITE(CHV_CANVAS(pipe), 0);
6701 i9xx_set_pipeconf(intel_crtc);
6703 intel_crtc->active = true;
6705 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6707 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
6709 if (IS_CHERRYVIEW(dev)) {
6710 chv_prepare_pll(intel_crtc, intel_crtc->config);
6711 chv_enable_pll(intel_crtc, intel_crtc->config);
6713 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6714 vlv_enable_pll(intel_crtc, intel_crtc->config);
6717 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6719 i9xx_pfit_enable(intel_crtc);
6721 intel_color_load_luts(&pipe_config->base);
6723 intel_update_watermarks(crtc);
6724 intel_enable_pipe(intel_crtc);
6726 assert_vblank_disabled(crtc);
6727 drm_crtc_vblank_on(crtc);
6729 intel_encoders_enable(crtc, pipe_config, old_state);
6732 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6734 struct drm_device *dev = crtc->base.dev;
6735 struct drm_i915_private *dev_priv = to_i915(dev);
6737 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6738 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6741 static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
6742 struct drm_atomic_state *old_state)
6744 struct drm_crtc *crtc = pipe_config->base.crtc;
6745 struct drm_device *dev = crtc->dev;
6746 struct drm_i915_private *dev_priv = to_i915(dev);
6747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6748 enum pipe pipe = intel_crtc->pipe;
6750 if (WARN_ON(intel_crtc->active))
6753 i9xx_set_pll_dividers(intel_crtc);
6755 if (intel_crtc_has_dp_encoder(intel_crtc->config))
6756 intel_dp_set_m_n(intel_crtc, M1_N1);
6758 intel_set_pipe_timings(intel_crtc);
6759 intel_set_pipe_src_size(intel_crtc);
6761 i9xx_set_pipeconf(intel_crtc);
6763 intel_crtc->active = true;
6766 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6768 intel_encoders_pre_enable(crtc, pipe_config, old_state);
6770 i9xx_enable_pll(intel_crtc);
6772 i9xx_pfit_enable(intel_crtc);
6774 intel_color_load_luts(&pipe_config->base);
6776 intel_update_watermarks(crtc);
6777 intel_enable_pipe(intel_crtc);
6779 assert_vblank_disabled(crtc);
6780 drm_crtc_vblank_on(crtc);
6782 intel_encoders_enable(crtc, pipe_config, old_state);
6785 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6787 struct drm_device *dev = crtc->base.dev;
6788 struct drm_i915_private *dev_priv = to_i915(dev);
6790 if (!crtc->config->gmch_pfit.control)
6793 assert_pipe_disabled(dev_priv, crtc->pipe);
6795 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6796 I915_READ(PFIT_CONTROL));
6797 I915_WRITE(PFIT_CONTROL, 0);
6800 static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
6801 struct drm_atomic_state *old_state)
6803 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6804 struct drm_device *dev = crtc->dev;
6805 struct drm_i915_private *dev_priv = to_i915(dev);
6806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6807 int pipe = intel_crtc->pipe;
6810 * On gen2 planes are double buffered but the pipe isn't, so we must
6811 * wait for planes to fully turn off before disabling the pipe.
6814 intel_wait_for_vblank(dev, pipe);
6816 intel_encoders_disable(crtc, old_crtc_state, old_state);
6818 drm_crtc_vblank_off(crtc);
6819 assert_vblank_disabled(crtc);
6821 intel_disable_pipe(intel_crtc);
6823 i9xx_pfit_disable(intel_crtc);
6825 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
6827 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
6828 if (IS_CHERRYVIEW(dev))
6829 chv_disable_pll(dev_priv, pipe);
6830 else if (IS_VALLEYVIEW(dev))
6831 vlv_disable_pll(dev_priv, pipe);
6833 i9xx_disable_pll(intel_crtc);
6836 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
6839 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6842 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6844 struct intel_encoder *encoder;
6845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6846 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6847 enum intel_display_power_domain domain;
6848 unsigned long domains;
6849 struct drm_atomic_state *state;
6850 struct intel_crtc_state *crtc_state;
6853 if (!intel_crtc->active)
6856 if (to_intel_plane_state(crtc->primary->state)->base.visible) {
6857 WARN_ON(intel_crtc->flip_work);
6859 intel_pre_disable_primary_noatomic(crtc);
6861 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6862 to_intel_plane_state(crtc->primary->state)->base.visible = false;
6865 state = drm_atomic_state_alloc(crtc->dev);
6867 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
6868 crtc->base.id, crtc->name);
6872 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
6874 /* Everything's already locked, -EDEADLK can't happen. */
6875 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6876 ret = drm_atomic_add_affected_connectors(state, crtc);
6878 WARN_ON(IS_ERR(crtc_state) || ret);
6880 dev_priv->display.crtc_disable(crtc_state, state);
6882 drm_atomic_state_free(state);
6884 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
6885 crtc->base.id, crtc->name);
6887 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6888 crtc->state->active = false;
6889 intel_crtc->active = false;
6890 crtc->enabled = false;
6891 crtc->state->connector_mask = 0;
6892 crtc->state->encoder_mask = 0;
6894 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6895 encoder->base.crtc = NULL;
6897 intel_fbc_disable(intel_crtc);
6898 intel_update_watermarks(crtc);
6899 intel_disable_shared_dpll(intel_crtc);
6901 domains = intel_crtc->enabled_power_domains;
6902 for_each_power_domain(domain, domains)
6903 intel_display_power_put(dev_priv, domain);
6904 intel_crtc->enabled_power_domains = 0;
6906 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6907 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6911 * turn all crtc's off, but do not adjust state
6912 * This has to be paired with a call to intel_modeset_setup_hw_state.
6914 int intel_display_suspend(struct drm_device *dev)
6916 struct drm_i915_private *dev_priv = to_i915(dev);
6917 struct drm_atomic_state *state;
6920 state = drm_atomic_helper_suspend(dev);
6921 ret = PTR_ERR_OR_ZERO(state);
6923 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6925 dev_priv->modeset_restore_state = state;
6929 void intel_encoder_destroy(struct drm_encoder *encoder)
6931 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6933 drm_encoder_cleanup(encoder);
6934 kfree(intel_encoder);
6937 /* Cross check the actual hw state with our own modeset state tracking (and it's
6938 * internal consistency). */
6939 static void intel_connector_verify_state(struct intel_connector *connector)
6941 struct drm_crtc *crtc = connector->base.state->crtc;
6943 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6944 connector->base.base.id,
6945 connector->base.name);
6947 if (connector->get_hw_state(connector)) {
6948 struct intel_encoder *encoder = connector->encoder;
6949 struct drm_connector_state *conn_state = connector->base.state;
6951 I915_STATE_WARN(!crtc,
6952 "connector enabled without attached crtc\n");
6957 I915_STATE_WARN(!crtc->state->active,
6958 "connector is active, but attached crtc isn't\n");
6960 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6963 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6964 "atomic encoder doesn't match attached encoder\n");
6966 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6967 "attached encoder crtc differs from connector crtc\n");
6969 I915_STATE_WARN(crtc && crtc->state->active,
6970 "attached crtc is active, but connector isn't\n");
6971 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6972 "best encoder set without crtc!\n");
6976 int intel_connector_init(struct intel_connector *connector)
6978 drm_atomic_helper_connector_reset(&connector->base);
6980 if (!connector->base.state)
6986 struct intel_connector *intel_connector_alloc(void)
6988 struct intel_connector *connector;
6990 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6994 if (intel_connector_init(connector) < 0) {
7002 /* Simple connector->get_hw_state implementation for encoders that support only
7003 * one connector and no cloning and hence the encoder state determines the state
7004 * of the connector. */
7005 bool intel_connector_get_hw_state(struct intel_connector *connector)
7008 struct intel_encoder *encoder = connector->encoder;
7010 return encoder->get_hw_state(encoder, &pipe);
7013 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
7015 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
7016 return crtc_state->fdi_lanes;
7021 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
7022 struct intel_crtc_state *pipe_config)
7024 struct drm_atomic_state *state = pipe_config->base.state;
7025 struct intel_crtc *other_crtc;
7026 struct intel_crtc_state *other_crtc_state;
7028 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
7029 pipe_name(pipe), pipe_config->fdi_lanes);
7030 if (pipe_config->fdi_lanes > 4) {
7031 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
7032 pipe_name(pipe), pipe_config->fdi_lanes);
7036 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7037 if (pipe_config->fdi_lanes > 2) {
7038 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
7039 pipe_config->fdi_lanes);
7046 if (INTEL_INFO(dev)->num_pipes == 2)
7049 /* Ivybridge 3 pipe is really complicated */
7054 if (pipe_config->fdi_lanes <= 2)
7057 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
7059 intel_atomic_get_crtc_state(state, other_crtc);
7060 if (IS_ERR(other_crtc_state))
7061 return PTR_ERR(other_crtc_state);
7063 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
7064 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
7065 pipe_name(pipe), pipe_config->fdi_lanes);
7070 if (pipe_config->fdi_lanes > 2) {
7071 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
7072 pipe_name(pipe), pipe_config->fdi_lanes);
7076 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
7078 intel_atomic_get_crtc_state(state, other_crtc);
7079 if (IS_ERR(other_crtc_state))
7080 return PTR_ERR(other_crtc_state);
7082 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
7083 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
7093 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
7094 struct intel_crtc_state *pipe_config)
7096 struct drm_device *dev = intel_crtc->base.dev;
7097 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7098 int lane, link_bw, fdi_dotclock, ret;
7099 bool needs_recompute = false;
7102 /* FDI is a binary signal running at ~2.7GHz, encoding
7103 * each output octet as 10 bits. The actual frequency
7104 * is stored as a divider into a 100MHz clock, and the
7105 * mode pixel clock is stored in units of 1KHz.
7106 * Hence the bw of each lane in terms of the mode signal
7109 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
7111 fdi_dotclock = adjusted_mode->crtc_clock;
7113 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
7114 pipe_config->pipe_bpp);
7116 pipe_config->fdi_lanes = lane;
7118 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
7119 link_bw, &pipe_config->fdi_m_n);
7121 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
7122 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
7123 pipe_config->pipe_bpp -= 2*3;
7124 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
7125 pipe_config->pipe_bpp);
7126 needs_recompute = true;
7127 pipe_config->bw_constrained = true;
7132 if (needs_recompute)
7138 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
7139 struct intel_crtc_state *pipe_config)
7141 if (pipe_config->pipe_bpp > 24)
7144 /* HSW can handle pixel rate up to cdclk? */
7145 if (IS_HASWELL(dev_priv))
7149 * We compare against max which means we must take
7150 * the increased cdclk requirement into account when
7151 * calculating the new cdclk.
7153 * Should measure whether using a lower cdclk w/o IPS
7155 return ilk_pipe_pixel_rate(pipe_config) <=
7156 dev_priv->max_cdclk_freq * 95 / 100;
7159 static void hsw_compute_ips_config(struct intel_crtc *crtc,
7160 struct intel_crtc_state *pipe_config)
7162 struct drm_device *dev = crtc->base.dev;
7163 struct drm_i915_private *dev_priv = to_i915(dev);
7165 pipe_config->ips_enabled = i915.enable_ips &&
7166 hsw_crtc_supports_ips(crtc) &&
7167 pipe_config_supports_ips(dev_priv, pipe_config);
7170 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
7172 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
7174 /* GDG double wide on either pipe, otherwise pipe A only */
7175 return INTEL_INFO(dev_priv)->gen < 4 &&
7176 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
7179 static int intel_crtc_compute_config(struct intel_crtc *crtc,
7180 struct intel_crtc_state *pipe_config)
7182 struct drm_device *dev = crtc->base.dev;
7183 struct drm_i915_private *dev_priv = to_i915(dev);
7184 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
7185 int clock_limit = dev_priv->max_dotclk_freq;
7187 if (INTEL_INFO(dev)->gen < 4) {
7188 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
7191 * Enable double wide mode when the dot clock
7192 * is > 90% of the (display) core speed.
7194 if (intel_crtc_supports_double_wide(crtc) &&
7195 adjusted_mode->crtc_clock > clock_limit) {
7196 clock_limit = dev_priv->max_dotclk_freq;
7197 pipe_config->double_wide = true;
7201 if (adjusted_mode->crtc_clock > clock_limit) {
7202 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
7203 adjusted_mode->crtc_clock, clock_limit,
7204 yesno(pipe_config->double_wide));
7209 * Pipe horizontal size must be even in:
7211 * - LVDS dual channel mode
7212 * - Double wide pipe
7214 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
7215 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
7216 pipe_config->pipe_src_w &= ~1;
7218 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
7219 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7221 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
7222 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
7226 hsw_compute_ips_config(crtc, pipe_config);
7228 if (pipe_config->has_pch_encoder)
7229 return ironlake_fdi_compute_config(crtc, pipe_config);
7234 static int skylake_get_display_clock_speed(struct drm_device *dev)
7236 struct drm_i915_private *dev_priv = to_i915(dev);
7239 skl_dpll0_update(dev_priv);
7241 if (dev_priv->cdclk_pll.vco == 0)
7242 return dev_priv->cdclk_pll.ref;
7244 cdctl = I915_READ(CDCLK_CTL);
7246 if (dev_priv->cdclk_pll.vco == 8640000) {
7247 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7248 case CDCLK_FREQ_450_432:
7250 case CDCLK_FREQ_337_308:
7252 case CDCLK_FREQ_540:
7254 case CDCLK_FREQ_675_617:
7257 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7260 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
7261 case CDCLK_FREQ_450_432:
7263 case CDCLK_FREQ_337_308:
7265 case CDCLK_FREQ_540:
7267 case CDCLK_FREQ_675_617:
7270 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
7274 return dev_priv->cdclk_pll.ref;
7277 static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
7281 dev_priv->cdclk_pll.ref = 19200;
7282 dev_priv->cdclk_pll.vco = 0;
7284 val = I915_READ(BXT_DE_PLL_ENABLE);
7285 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
7288 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
7291 val = I915_READ(BXT_DE_PLL_CTL);
7292 dev_priv->cdclk_pll.vco = (val & BXT_DE_PLL_RATIO_MASK) *
7293 dev_priv->cdclk_pll.ref;
7296 static int broxton_get_display_clock_speed(struct drm_device *dev)
7298 struct drm_i915_private *dev_priv = to_i915(dev);
7302 bxt_de_pll_update(dev_priv);
7304 vco = dev_priv->cdclk_pll.vco;
7306 return dev_priv->cdclk_pll.ref;
7308 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
7311 case BXT_CDCLK_CD2X_DIV_SEL_1:
7314 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
7317 case BXT_CDCLK_CD2X_DIV_SEL_2:
7320 case BXT_CDCLK_CD2X_DIV_SEL_4:
7324 MISSING_CASE(divider);
7325 return dev_priv->cdclk_pll.ref;
7328 return DIV_ROUND_CLOSEST(vco, div);
7331 static int broadwell_get_display_clock_speed(struct drm_device *dev)
7333 struct drm_i915_private *dev_priv = to_i915(dev);
7334 uint32_t lcpll = I915_READ(LCPLL_CTL);
7335 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7337 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7339 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7341 else if (freq == LCPLL_CLK_FREQ_450)
7343 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
7345 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
7351 static int haswell_get_display_clock_speed(struct drm_device *dev)
7353 struct drm_i915_private *dev_priv = to_i915(dev);
7354 uint32_t lcpll = I915_READ(LCPLL_CTL);
7355 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
7357 if (lcpll & LCPLL_CD_SOURCE_FCLK)
7359 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
7361 else if (freq == LCPLL_CLK_FREQ_450)
7363 else if (IS_HSW_ULT(dev))
7369 static int valleyview_get_display_clock_speed(struct drm_device *dev)
7371 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
7372 CCK_DISPLAY_CLOCK_CONTROL);
7375 static int ilk_get_display_clock_speed(struct drm_device *dev)
7380 static int i945_get_display_clock_speed(struct drm_device *dev)
7385 static int i915_get_display_clock_speed(struct drm_device *dev)
7390 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
7395 static int pnv_get_display_clock_speed(struct drm_device *dev)
7397 struct pci_dev *pdev = dev->pdev;
7400 pci_read_config_word(pdev, GCFGC, &gcfgc);
7402 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7403 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
7405 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
7407 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
7409 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
7412 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
7413 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
7415 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
7420 static int i915gm_get_display_clock_speed(struct drm_device *dev)
7422 struct pci_dev *pdev = dev->pdev;
7425 pci_read_config_word(pdev, GCFGC, &gcfgc);
7427 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
7430 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
7431 case GC_DISPLAY_CLOCK_333_MHZ:
7434 case GC_DISPLAY_CLOCK_190_200_MHZ:
7440 static int i865_get_display_clock_speed(struct drm_device *dev)
7445 static int i85x_get_display_clock_speed(struct drm_device *dev)
7447 struct pci_dev *pdev = dev->pdev;
7451 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7452 * encoding is different :(
7453 * FIXME is this the right way to detect 852GM/852GMV?
7455 if (pdev->revision == 0x1)
7458 pci_bus_read_config_word(pdev->bus,
7459 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7461 /* Assume that the hardware is in the high speed state. This
7462 * should be the default.
7464 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7465 case GC_CLOCK_133_200:
7466 case GC_CLOCK_133_200_2:
7467 case GC_CLOCK_100_200:
7469 case GC_CLOCK_166_250:
7471 case GC_CLOCK_100_133:
7473 case GC_CLOCK_133_266:
7474 case GC_CLOCK_133_266_2:
7475 case GC_CLOCK_166_266:
7479 /* Shouldn't happen */
7483 static int i830_get_display_clock_speed(struct drm_device *dev)
7488 static unsigned int intel_hpll_vco(struct drm_device *dev)
7490 struct drm_i915_private *dev_priv = to_i915(dev);
7491 static const unsigned int blb_vco[8] = {
7498 static const unsigned int pnv_vco[8] = {
7505 static const unsigned int cl_vco[8] = {
7514 static const unsigned int elk_vco[8] = {
7520 static const unsigned int ctg_vco[8] = {
7528 const unsigned int *vco_table;
7532 /* FIXME other chipsets? */
7534 vco_table = ctg_vco;
7535 else if (IS_G4X(dev))
7536 vco_table = elk_vco;
7537 else if (IS_CRESTLINE(dev))
7539 else if (IS_PINEVIEW(dev))
7540 vco_table = pnv_vco;
7541 else if (IS_G33(dev))
7542 vco_table = blb_vco;
7546 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7548 vco = vco_table[tmp & 0x7];
7550 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7552 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7557 static int gm45_get_display_clock_speed(struct drm_device *dev)
7559 struct pci_dev *pdev = dev->pdev;
7560 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7563 pci_read_config_word(pdev, GCFGC, &tmp);
7565 cdclk_sel = (tmp >> 12) & 0x1;
7571 return cdclk_sel ? 333333 : 222222;
7573 return cdclk_sel ? 320000 : 228571;
7575 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7580 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7582 struct pci_dev *pdev = dev->pdev;
7583 static const uint8_t div_3200[] = { 16, 10, 8 };
7584 static const uint8_t div_4000[] = { 20, 12, 10 };
7585 static const uint8_t div_5333[] = { 24, 16, 14 };
7586 const uint8_t *div_table;
7587 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7590 pci_read_config_word(pdev, GCFGC, &tmp);
7592 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7594 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7599 div_table = div_3200;
7602 div_table = div_4000;
7605 div_table = div_5333;
7611 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7614 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7618 static int g33_get_display_clock_speed(struct drm_device *dev)
7620 struct pci_dev *pdev = dev->pdev;
7621 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7622 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7623 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7624 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7625 const uint8_t *div_table;
7626 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7629 pci_read_config_word(pdev, GCFGC, &tmp);
7631 cdclk_sel = (tmp >> 4) & 0x7;
7633 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7638 div_table = div_3200;
7641 div_table = div_4000;
7644 div_table = div_4800;
7647 div_table = div_5333;
7653 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7656 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7661 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7663 while (*num > DATA_LINK_M_N_MASK ||
7664 *den > DATA_LINK_M_N_MASK) {
7670 static void compute_m_n(unsigned int m, unsigned int n,
7671 uint32_t *ret_m, uint32_t *ret_n)
7673 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7674 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7675 intel_reduce_m_n_ratio(ret_m, ret_n);
7679 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7680 int pixel_clock, int link_clock,
7681 struct intel_link_m_n *m_n)
7685 compute_m_n(bits_per_pixel * pixel_clock,
7686 link_clock * nlanes * 8,
7687 &m_n->gmch_m, &m_n->gmch_n);
7689 compute_m_n(pixel_clock, link_clock,
7690 &m_n->link_m, &m_n->link_n);
7693 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7695 if (i915.panel_use_ssc >= 0)
7696 return i915.panel_use_ssc != 0;
7697 return dev_priv->vbt.lvds_use_ssc
7698 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7701 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7703 return (1 << dpll->n) << 16 | dpll->m2;
7706 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7708 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7711 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7712 struct intel_crtc_state *crtc_state,
7713 struct dpll *reduced_clock)
7715 struct drm_device *dev = crtc->base.dev;
7718 if (IS_PINEVIEW(dev)) {
7719 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7721 fp2 = pnv_dpll_compute_fp(reduced_clock);
7723 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7725 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7728 crtc_state->dpll_hw_state.fp0 = fp;
7730 crtc->lowfreq_avail = false;
7731 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7733 crtc_state->dpll_hw_state.fp1 = fp2;
7734 crtc->lowfreq_avail = true;
7736 crtc_state->dpll_hw_state.fp1 = fp;
7740 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7746 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7747 * and set it to a reasonable value instead.
7749 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7750 reg_val &= 0xffffff00;
7751 reg_val |= 0x00000030;
7752 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7754 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7755 reg_val &= 0x8cffffff;
7756 reg_val = 0x8c000000;
7757 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7759 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7760 reg_val &= 0xffffff00;
7761 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7763 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7764 reg_val &= 0x00ffffff;
7765 reg_val |= 0xb0000000;
7766 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7769 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7770 struct intel_link_m_n *m_n)
7772 struct drm_device *dev = crtc->base.dev;
7773 struct drm_i915_private *dev_priv = to_i915(dev);
7774 int pipe = crtc->pipe;
7776 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7777 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7778 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7779 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7782 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7783 struct intel_link_m_n *m_n,
7784 struct intel_link_m_n *m2_n2)
7786 struct drm_device *dev = crtc->base.dev;
7787 struct drm_i915_private *dev_priv = to_i915(dev);
7788 int pipe = crtc->pipe;
7789 enum transcoder transcoder = crtc->config->cpu_transcoder;
7791 if (INTEL_INFO(dev)->gen >= 5) {
7792 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7793 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7794 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7795 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7796 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7797 * for gen < 8) and if DRRS is supported (to make sure the
7798 * registers are not unnecessarily accessed).
7800 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7801 crtc->config->has_drrs) {
7802 I915_WRITE(PIPE_DATA_M2(transcoder),
7803 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7804 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7805 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7806 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7809 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7810 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7811 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7812 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7816 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7818 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7821 dp_m_n = &crtc->config->dp_m_n;
7822 dp_m2_n2 = &crtc->config->dp_m2_n2;
7823 } else if (m_n == M2_N2) {
7826 * M2_N2 registers are not supported. Hence m2_n2 divider value
7827 * needs to be programmed into M1_N1.
7829 dp_m_n = &crtc->config->dp_m2_n2;
7831 DRM_ERROR("Unsupported divider value\n");
7835 if (crtc->config->has_pch_encoder)
7836 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7838 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7841 static void vlv_compute_dpll(struct intel_crtc *crtc,
7842 struct intel_crtc_state *pipe_config)
7844 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7845 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7846 if (crtc->pipe != PIPE_A)
7847 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7849 /* DPLL not used with DSI, but still need the rest set up */
7850 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7851 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
7852 DPLL_EXT_BUFFER_ENABLE_VLV;
7854 pipe_config->dpll_hw_state.dpll_md =
7855 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7858 static void chv_compute_dpll(struct intel_crtc *crtc,
7859 struct intel_crtc_state *pipe_config)
7861 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7862 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
7863 if (crtc->pipe != PIPE_A)
7864 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7866 /* DPLL not used with DSI, but still need the rest set up */
7867 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
7868 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
7870 pipe_config->dpll_hw_state.dpll_md =
7871 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7874 static void vlv_prepare_pll(struct intel_crtc *crtc,
7875 const struct intel_crtc_state *pipe_config)
7877 struct drm_device *dev = crtc->base.dev;
7878 struct drm_i915_private *dev_priv = to_i915(dev);
7879 enum pipe pipe = crtc->pipe;
7881 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7882 u32 coreclk, reg_val;
7885 I915_WRITE(DPLL(pipe),
7886 pipe_config->dpll_hw_state.dpll &
7887 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
7889 /* No need to actually set up the DPLL with DSI */
7890 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7893 mutex_lock(&dev_priv->sb_lock);
7895 bestn = pipe_config->dpll.n;
7896 bestm1 = pipe_config->dpll.m1;
7897 bestm2 = pipe_config->dpll.m2;
7898 bestp1 = pipe_config->dpll.p1;
7899 bestp2 = pipe_config->dpll.p2;
7901 /* See eDP HDMI DPIO driver vbios notes doc */
7903 /* PLL B needs special handling */
7905 vlv_pllb_recal_opamp(dev_priv, pipe);
7907 /* Set up Tx target for periodic Rcomp update */
7908 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7910 /* Disable target IRef on PLL */
7911 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7912 reg_val &= 0x00ffffff;
7913 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7915 /* Disable fast lock */
7916 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7918 /* Set idtafcrecal before PLL is enabled */
7919 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7920 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7921 mdiv |= ((bestn << DPIO_N_SHIFT));
7922 mdiv |= (1 << DPIO_K_SHIFT);
7925 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7926 * but we don't support that).
7927 * Note: don't use the DAC post divider as it seems unstable.
7929 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7930 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7932 mdiv |= DPIO_ENABLE_CALIBRATION;
7933 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7935 /* Set HBR and RBR LPF coefficients */
7936 if (pipe_config->port_clock == 162000 ||
7937 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
7938 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
7939 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7942 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7945 if (intel_crtc_has_dp_encoder(pipe_config)) {
7946 /* Use SSC source */
7948 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7953 } else { /* HDMI or VGA */
7954 /* Use bend source */
7956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7963 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7964 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7965 if (intel_crtc_has_dp_encoder(crtc->config))
7966 coreclk |= 0x01000000;
7967 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7969 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7970 mutex_unlock(&dev_priv->sb_lock);
7973 static void chv_prepare_pll(struct intel_crtc *crtc,
7974 const struct intel_crtc_state *pipe_config)
7976 struct drm_device *dev = crtc->base.dev;
7977 struct drm_i915_private *dev_priv = to_i915(dev);
7978 enum pipe pipe = crtc->pipe;
7979 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7980 u32 loopfilter, tribuf_calcntr;
7981 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7985 /* Enable Refclk and SSC */
7986 I915_WRITE(DPLL(pipe),
7987 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7989 /* No need to actually set up the DPLL with DSI */
7990 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7993 bestn = pipe_config->dpll.n;
7994 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7995 bestm1 = pipe_config->dpll.m1;
7996 bestm2 = pipe_config->dpll.m2 >> 22;
7997 bestp1 = pipe_config->dpll.p1;
7998 bestp2 = pipe_config->dpll.p2;
7999 vco = pipe_config->dpll.vco;
8003 mutex_lock(&dev_priv->sb_lock);
8005 /* p1 and p2 divider */
8006 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
8007 5 << DPIO_CHV_S1_DIV_SHIFT |
8008 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
8009 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
8010 1 << DPIO_CHV_K_DIV_SHIFT);
8012 /* Feedback post-divider - m2 */
8013 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
8015 /* Feedback refclk divider - n and m1 */
8016 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
8017 DPIO_CHV_M1_DIV_BY_2 |
8018 1 << DPIO_CHV_N_DIV_SHIFT);
8020 /* M2 fraction division */
8021 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
8023 /* M2 fraction division enable */
8024 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8025 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
8026 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
8028 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
8029 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
8031 /* Program digital lock detect threshold */
8032 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
8033 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
8034 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
8035 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
8037 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
8038 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
8041 if (vco == 5400000) {
8042 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
8043 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
8044 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
8045 tribuf_calcntr = 0x9;
8046 } else if (vco <= 6200000) {
8047 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
8048 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
8049 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8050 tribuf_calcntr = 0x9;
8051 } else if (vco <= 6480000) {
8052 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8053 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8054 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8055 tribuf_calcntr = 0x8;
8057 /* Not supported. Apply the same limits as in the max case */
8058 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
8059 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
8060 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
8063 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
8065 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
8066 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
8067 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
8068 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
8071 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
8072 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
8075 mutex_unlock(&dev_priv->sb_lock);
8079 * vlv_force_pll_on - forcibly enable just the PLL
8080 * @dev_priv: i915 private structure
8081 * @pipe: pipe PLL to enable
8082 * @dpll: PLL configuration
8084 * Enable the PLL for @pipe using the supplied @dpll config. To be used
8085 * in cases where we need the PLL enabled even when @pipe is not going to
8088 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
8089 const struct dpll *dpll)
8091 struct intel_crtc *crtc =
8092 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
8093 struct intel_crtc_state *pipe_config;
8095 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8099 pipe_config->base.crtc = &crtc->base;
8100 pipe_config->pixel_multiplier = 1;
8101 pipe_config->dpll = *dpll;
8103 if (IS_CHERRYVIEW(dev)) {
8104 chv_compute_dpll(crtc, pipe_config);
8105 chv_prepare_pll(crtc, pipe_config);
8106 chv_enable_pll(crtc, pipe_config);
8108 vlv_compute_dpll(crtc, pipe_config);
8109 vlv_prepare_pll(crtc, pipe_config);
8110 vlv_enable_pll(crtc, pipe_config);
8119 * vlv_force_pll_off - forcibly disable just the PLL
8120 * @dev_priv: i915 private structure
8121 * @pipe: pipe PLL to disable
8123 * Disable the PLL for @pipe. To be used in cases where we need
8124 * the PLL enabled even when @pipe is not going to be enabled.
8126 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
8128 if (IS_CHERRYVIEW(dev))
8129 chv_disable_pll(to_i915(dev), pipe);
8131 vlv_disable_pll(to_i915(dev), pipe);
8134 static void i9xx_compute_dpll(struct intel_crtc *crtc,
8135 struct intel_crtc_state *crtc_state,
8136 struct dpll *reduced_clock)
8138 struct drm_device *dev = crtc->base.dev;
8139 struct drm_i915_private *dev_priv = to_i915(dev);
8141 struct dpll *clock = &crtc_state->dpll;
8143 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8145 dpll = DPLL_VGA_MODE_DIS;
8147 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
8148 dpll |= DPLLB_MODE_LVDS;
8150 dpll |= DPLLB_MODE_DAC_SERIAL;
8152 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8153 dpll |= (crtc_state->pixel_multiplier - 1)
8154 << SDVO_MULTIPLIER_SHIFT_HIRES;
8157 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8158 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
8159 dpll |= DPLL_SDVO_HIGH_SPEED;
8161 if (intel_crtc_has_dp_encoder(crtc_state))
8162 dpll |= DPLL_SDVO_HIGH_SPEED;
8164 /* compute bitmask from p1 value */
8165 if (IS_PINEVIEW(dev))
8166 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
8168 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8169 if (IS_G4X(dev) && reduced_clock)
8170 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8172 switch (clock->p2) {
8174 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8177 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8180 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8183 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8186 if (INTEL_INFO(dev)->gen >= 4)
8187 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
8189 if (crtc_state->sdvo_tv_clock)
8190 dpll |= PLL_REF_INPUT_TVCLKINBC;
8191 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8192 intel_panel_use_ssc(dev_priv))
8193 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8195 dpll |= PLL_REF_INPUT_DREFCLK;
8197 dpll |= DPLL_VCO_ENABLE;
8198 crtc_state->dpll_hw_state.dpll = dpll;
8200 if (INTEL_INFO(dev)->gen >= 4) {
8201 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
8202 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8203 crtc_state->dpll_hw_state.dpll_md = dpll_md;
8207 static void i8xx_compute_dpll(struct intel_crtc *crtc,
8208 struct intel_crtc_state *crtc_state,
8209 struct dpll *reduced_clock)
8211 struct drm_device *dev = crtc->base.dev;
8212 struct drm_i915_private *dev_priv = to_i915(dev);
8214 struct dpll *clock = &crtc_state->dpll;
8216 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
8218 dpll = DPLL_VGA_MODE_DIS;
8220 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8221 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8224 dpll |= PLL_P1_DIVIDE_BY_TWO;
8226 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8228 dpll |= PLL_P2_DIVIDE_BY_4;
8231 if (!IS_I830(dev) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
8232 dpll |= DPLL_DVO_2X_MODE;
8234 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8235 intel_panel_use_ssc(dev_priv))
8236 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8238 dpll |= PLL_REF_INPUT_DREFCLK;
8240 dpll |= DPLL_VCO_ENABLE;
8241 crtc_state->dpll_hw_state.dpll = dpll;
8244 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
8246 struct drm_device *dev = intel_crtc->base.dev;
8247 struct drm_i915_private *dev_priv = to_i915(dev);
8248 enum pipe pipe = intel_crtc->pipe;
8249 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8250 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
8251 uint32_t crtc_vtotal, crtc_vblank_end;
8254 /* We need to be careful not to changed the adjusted mode, for otherwise
8255 * the hw state checker will get angry at the mismatch. */
8256 crtc_vtotal = adjusted_mode->crtc_vtotal;
8257 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
8259 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
8260 /* the chip adds 2 halflines automatically */
8262 crtc_vblank_end -= 1;
8264 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8265 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
8267 vsyncshift = adjusted_mode->crtc_hsync_start -
8268 adjusted_mode->crtc_htotal / 2;
8270 vsyncshift += adjusted_mode->crtc_htotal;
8273 if (INTEL_INFO(dev)->gen > 3)
8274 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
8276 I915_WRITE(HTOTAL(cpu_transcoder),
8277 (adjusted_mode->crtc_hdisplay - 1) |
8278 ((adjusted_mode->crtc_htotal - 1) << 16));
8279 I915_WRITE(HBLANK(cpu_transcoder),
8280 (adjusted_mode->crtc_hblank_start - 1) |
8281 ((adjusted_mode->crtc_hblank_end - 1) << 16));
8282 I915_WRITE(HSYNC(cpu_transcoder),
8283 (adjusted_mode->crtc_hsync_start - 1) |
8284 ((adjusted_mode->crtc_hsync_end - 1) << 16));
8286 I915_WRITE(VTOTAL(cpu_transcoder),
8287 (adjusted_mode->crtc_vdisplay - 1) |
8288 ((crtc_vtotal - 1) << 16));
8289 I915_WRITE(VBLANK(cpu_transcoder),
8290 (adjusted_mode->crtc_vblank_start - 1) |
8291 ((crtc_vblank_end - 1) << 16));
8292 I915_WRITE(VSYNC(cpu_transcoder),
8293 (adjusted_mode->crtc_vsync_start - 1) |
8294 ((adjusted_mode->crtc_vsync_end - 1) << 16));
8296 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
8297 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
8298 * documented on the DDI_FUNC_CTL register description, EDP Input Select
8300 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
8301 (pipe == PIPE_B || pipe == PIPE_C))
8302 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
8306 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
8308 struct drm_device *dev = intel_crtc->base.dev;
8309 struct drm_i915_private *dev_priv = to_i915(dev);
8310 enum pipe pipe = intel_crtc->pipe;
8312 /* pipesrc controls the size that is scaled from, which should
8313 * always be the user's requested size.
8315 I915_WRITE(PIPESRC(pipe),
8316 ((intel_crtc->config->pipe_src_w - 1) << 16) |
8317 (intel_crtc->config->pipe_src_h - 1));
8320 static void intel_get_pipe_timings(struct intel_crtc *crtc,
8321 struct intel_crtc_state *pipe_config)
8323 struct drm_device *dev = crtc->base.dev;
8324 struct drm_i915_private *dev_priv = to_i915(dev);
8325 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
8328 tmp = I915_READ(HTOTAL(cpu_transcoder));
8329 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
8330 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
8331 tmp = I915_READ(HBLANK(cpu_transcoder));
8332 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
8333 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
8334 tmp = I915_READ(HSYNC(cpu_transcoder));
8335 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
8336 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
8338 tmp = I915_READ(VTOTAL(cpu_transcoder));
8339 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
8340 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
8341 tmp = I915_READ(VBLANK(cpu_transcoder));
8342 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
8343 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
8344 tmp = I915_READ(VSYNC(cpu_transcoder));
8345 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
8346 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
8348 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
8349 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
8350 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
8351 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
8355 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
8356 struct intel_crtc_state *pipe_config)
8358 struct drm_device *dev = crtc->base.dev;
8359 struct drm_i915_private *dev_priv = to_i915(dev);
8362 tmp = I915_READ(PIPESRC(crtc->pipe));
8363 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
8364 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
8366 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
8367 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
8370 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
8371 struct intel_crtc_state *pipe_config)
8373 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
8374 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
8375 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
8376 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
8378 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
8379 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
8380 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
8381 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
8383 mode->flags = pipe_config->base.adjusted_mode.flags;
8384 mode->type = DRM_MODE_TYPE_DRIVER;
8386 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
8387 mode->flags |= pipe_config->base.adjusted_mode.flags;
8389 mode->hsync = drm_mode_hsync(mode);
8390 mode->vrefresh = drm_mode_vrefresh(mode);
8391 drm_mode_set_name(mode);
8394 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
8396 struct drm_device *dev = intel_crtc->base.dev;
8397 struct drm_i915_private *dev_priv = to_i915(dev);
8402 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
8403 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8404 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
8406 if (intel_crtc->config->double_wide)
8407 pipeconf |= PIPECONF_DOUBLE_WIDE;
8409 /* only g4x and later have fancy bpc/dither controls */
8410 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8411 /* Bspec claims that we can't use dithering for 30bpp pipes. */
8412 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
8413 pipeconf |= PIPECONF_DITHER_EN |
8414 PIPECONF_DITHER_TYPE_SP;
8416 switch (intel_crtc->config->pipe_bpp) {
8418 pipeconf |= PIPECONF_6BPC;
8421 pipeconf |= PIPECONF_8BPC;
8424 pipeconf |= PIPECONF_10BPC;
8427 /* Case prevented by intel_choose_pipe_bpp_dither. */
8432 if (HAS_PIPE_CXSR(dev)) {
8433 if (intel_crtc->lowfreq_avail) {
8434 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
8435 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
8437 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8441 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8442 if (INTEL_INFO(dev)->gen < 4 ||
8443 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
8444 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8446 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8448 pipeconf |= PIPECONF_PROGRESSIVE;
8450 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8451 intel_crtc->config->limited_color_range)
8452 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8454 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8455 POSTING_READ(PIPECONF(intel_crtc->pipe));
8458 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
8459 struct intel_crtc_state *crtc_state)
8461 struct drm_device *dev = crtc->base.dev;
8462 struct drm_i915_private *dev_priv = to_i915(dev);
8463 const struct intel_limit *limit;
8466 memset(&crtc_state->dpll_hw_state, 0,
8467 sizeof(crtc_state->dpll_hw_state));
8469 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8470 if (intel_panel_use_ssc(dev_priv)) {
8471 refclk = dev_priv->vbt.lvds_ssc_freq;
8472 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8475 limit = &intel_limits_i8xx_lvds;
8476 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
8477 limit = &intel_limits_i8xx_dvo;
8479 limit = &intel_limits_i8xx_dac;
8482 if (!crtc_state->clock_set &&
8483 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8484 refclk, NULL, &crtc_state->dpll)) {
8485 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8489 i8xx_compute_dpll(crtc, crtc_state, NULL);
8494 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
8495 struct intel_crtc_state *crtc_state)
8497 struct drm_device *dev = crtc->base.dev;
8498 struct drm_i915_private *dev_priv = to_i915(dev);
8499 const struct intel_limit *limit;
8502 memset(&crtc_state->dpll_hw_state, 0,
8503 sizeof(crtc_state->dpll_hw_state));
8505 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8506 if (intel_panel_use_ssc(dev_priv)) {
8507 refclk = dev_priv->vbt.lvds_ssc_freq;
8508 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8511 if (intel_is_dual_link_lvds(dev))
8512 limit = &intel_limits_g4x_dual_channel_lvds;
8514 limit = &intel_limits_g4x_single_channel_lvds;
8515 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
8516 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
8517 limit = &intel_limits_g4x_hdmi;
8518 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
8519 limit = &intel_limits_g4x_sdvo;
8521 /* The option is for other outputs */
8522 limit = &intel_limits_i9xx_sdvo;
8525 if (!crtc_state->clock_set &&
8526 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8527 refclk, NULL, &crtc_state->dpll)) {
8528 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8532 i9xx_compute_dpll(crtc, crtc_state, NULL);
8537 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
8538 struct intel_crtc_state *crtc_state)
8540 struct drm_device *dev = crtc->base.dev;
8541 struct drm_i915_private *dev_priv = to_i915(dev);
8542 const struct intel_limit *limit;
8545 memset(&crtc_state->dpll_hw_state, 0,
8546 sizeof(crtc_state->dpll_hw_state));
8548 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8549 if (intel_panel_use_ssc(dev_priv)) {
8550 refclk = dev_priv->vbt.lvds_ssc_freq;
8551 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8554 limit = &intel_limits_pineview_lvds;
8556 limit = &intel_limits_pineview_sdvo;
8559 if (!crtc_state->clock_set &&
8560 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8561 refclk, NULL, &crtc_state->dpll)) {
8562 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8566 i9xx_compute_dpll(crtc, crtc_state, NULL);
8571 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8572 struct intel_crtc_state *crtc_state)
8574 struct drm_device *dev = crtc->base.dev;
8575 struct drm_i915_private *dev_priv = to_i915(dev);
8576 const struct intel_limit *limit;
8579 memset(&crtc_state->dpll_hw_state, 0,
8580 sizeof(crtc_state->dpll_hw_state));
8582 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8583 if (intel_panel_use_ssc(dev_priv)) {
8584 refclk = dev_priv->vbt.lvds_ssc_freq;
8585 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
8588 limit = &intel_limits_i9xx_lvds;
8590 limit = &intel_limits_i9xx_sdvo;
8593 if (!crtc_state->clock_set &&
8594 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8595 refclk, NULL, &crtc_state->dpll)) {
8596 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8600 i9xx_compute_dpll(crtc, crtc_state, NULL);
8605 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
8606 struct intel_crtc_state *crtc_state)
8608 int refclk = 100000;
8609 const struct intel_limit *limit = &intel_limits_chv;
8611 memset(&crtc_state->dpll_hw_state, 0,
8612 sizeof(crtc_state->dpll_hw_state));
8614 if (!crtc_state->clock_set &&
8615 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8616 refclk, NULL, &crtc_state->dpll)) {
8617 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8621 chv_compute_dpll(crtc, crtc_state);
8626 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
8627 struct intel_crtc_state *crtc_state)
8629 int refclk = 100000;
8630 const struct intel_limit *limit = &intel_limits_vlv;
8632 memset(&crtc_state->dpll_hw_state, 0,
8633 sizeof(crtc_state->dpll_hw_state));
8635 if (!crtc_state->clock_set &&
8636 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8637 refclk, NULL, &crtc_state->dpll)) {
8638 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8642 vlv_compute_dpll(crtc, crtc_state);
8647 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8648 struct intel_crtc_state *pipe_config)
8650 struct drm_device *dev = crtc->base.dev;
8651 struct drm_i915_private *dev_priv = to_i915(dev);
8654 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8657 tmp = I915_READ(PFIT_CONTROL);
8658 if (!(tmp & PFIT_ENABLE))
8661 /* Check whether the pfit is attached to our pipe. */
8662 if (INTEL_INFO(dev)->gen < 4) {
8663 if (crtc->pipe != PIPE_B)
8666 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8670 pipe_config->gmch_pfit.control = tmp;
8671 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8674 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8675 struct intel_crtc_state *pipe_config)
8677 struct drm_device *dev = crtc->base.dev;
8678 struct drm_i915_private *dev_priv = to_i915(dev);
8679 int pipe = pipe_config->cpu_transcoder;
8682 int refclk = 100000;
8684 /* In case of DSI, DPLL will not be used */
8685 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8688 mutex_lock(&dev_priv->sb_lock);
8689 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8690 mutex_unlock(&dev_priv->sb_lock);
8692 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8693 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8694 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8695 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8696 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8698 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8702 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8703 struct intel_initial_plane_config *plane_config)
8705 struct drm_device *dev = crtc->base.dev;
8706 struct drm_i915_private *dev_priv = to_i915(dev);
8707 u32 val, base, offset;
8708 int pipe = crtc->pipe, plane = crtc->plane;
8709 int fourcc, pixel_format;
8710 unsigned int aligned_height;
8711 struct drm_framebuffer *fb;
8712 struct intel_framebuffer *intel_fb;
8714 val = I915_READ(DSPCNTR(plane));
8715 if (!(val & DISPLAY_PLANE_ENABLE))
8718 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8720 DRM_DEBUG_KMS("failed to alloc fb\n");
8724 fb = &intel_fb->base;
8726 if (INTEL_INFO(dev)->gen >= 4) {
8727 if (val & DISPPLANE_TILED) {
8728 plane_config->tiling = I915_TILING_X;
8729 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8733 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8734 fourcc = i9xx_format_to_fourcc(pixel_format);
8735 fb->pixel_format = fourcc;
8736 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8738 if (INTEL_INFO(dev)->gen >= 4) {
8739 if (plane_config->tiling)
8740 offset = I915_READ(DSPTILEOFF(plane));
8742 offset = I915_READ(DSPLINOFF(plane));
8743 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8745 base = I915_READ(DSPADDR(plane));
8747 plane_config->base = base;
8749 val = I915_READ(PIPESRC(pipe));
8750 fb->width = ((val >> 16) & 0xfff) + 1;
8751 fb->height = ((val >> 0) & 0xfff) + 1;
8753 val = I915_READ(DSPSTRIDE(pipe));
8754 fb->pitches[0] = val & 0xffffffc0;
8756 aligned_height = intel_fb_align_height(dev, fb->height,
8760 plane_config->size = fb->pitches[0] * aligned_height;
8762 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8763 pipe_name(pipe), plane, fb->width, fb->height,
8764 fb->bits_per_pixel, base, fb->pitches[0],
8765 plane_config->size);
8767 plane_config->fb = intel_fb;
8770 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8771 struct intel_crtc_state *pipe_config)
8773 struct drm_device *dev = crtc->base.dev;
8774 struct drm_i915_private *dev_priv = to_i915(dev);
8775 int pipe = pipe_config->cpu_transcoder;
8776 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8778 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8779 int refclk = 100000;
8781 /* In case of DSI, DPLL will not be used */
8782 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
8785 mutex_lock(&dev_priv->sb_lock);
8786 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8787 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8788 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8789 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8790 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8791 mutex_unlock(&dev_priv->sb_lock);
8793 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8794 clock.m2 = (pll_dw0 & 0xff) << 22;
8795 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8796 clock.m2 |= pll_dw2 & 0x3fffff;
8797 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8798 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8799 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8801 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8804 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8805 struct intel_crtc_state *pipe_config)
8807 struct drm_device *dev = crtc->base.dev;
8808 struct drm_i915_private *dev_priv = to_i915(dev);
8809 enum intel_display_power_domain power_domain;
8813 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8814 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8817 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8818 pipe_config->shared_dpll = NULL;
8822 tmp = I915_READ(PIPECONF(crtc->pipe));
8823 if (!(tmp & PIPECONF_ENABLE))
8826 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8827 switch (tmp & PIPECONF_BPC_MASK) {
8829 pipe_config->pipe_bpp = 18;
8832 pipe_config->pipe_bpp = 24;
8834 case PIPECONF_10BPC:
8835 pipe_config->pipe_bpp = 30;
8842 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8843 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8844 pipe_config->limited_color_range = true;
8846 if (INTEL_INFO(dev)->gen < 4)
8847 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8849 intel_get_pipe_timings(crtc, pipe_config);
8850 intel_get_pipe_src_size(crtc, pipe_config);
8852 i9xx_get_pfit_config(crtc, pipe_config);
8854 if (INTEL_INFO(dev)->gen >= 4) {
8855 /* No way to read it out on pipes B and C */
8856 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8857 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8859 tmp = I915_READ(DPLL_MD(crtc->pipe));
8860 pipe_config->pixel_multiplier =
8861 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8862 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8863 pipe_config->dpll_hw_state.dpll_md = tmp;
8864 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8865 tmp = I915_READ(DPLL(crtc->pipe));
8866 pipe_config->pixel_multiplier =
8867 ((tmp & SDVO_MULTIPLIER_MASK)
8868 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8870 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8871 * port and will be fixed up in the encoder->get_config
8873 pipe_config->pixel_multiplier = 1;
8875 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8876 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8878 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8879 * on 830. Filter it out here so that we don't
8880 * report errors due to that.
8883 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8885 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8886 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8888 /* Mask out read-only status bits. */
8889 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8890 DPLL_PORTC_READY_MASK |
8891 DPLL_PORTB_READY_MASK);
8894 if (IS_CHERRYVIEW(dev))
8895 chv_crtc_clock_get(crtc, pipe_config);
8896 else if (IS_VALLEYVIEW(dev))
8897 vlv_crtc_clock_get(crtc, pipe_config);
8899 i9xx_crtc_clock_get(crtc, pipe_config);
8902 * Normally the dotclock is filled in by the encoder .get_config()
8903 * but in case the pipe is enabled w/o any ports we need a sane
8906 pipe_config->base.adjusted_mode.crtc_clock =
8907 pipe_config->port_clock / pipe_config->pixel_multiplier;
8912 intel_display_power_put(dev_priv, power_domain);
8917 static void ironlake_init_pch_refclk(struct drm_device *dev)
8919 struct drm_i915_private *dev_priv = to_i915(dev);
8920 struct intel_encoder *encoder;
8923 bool has_lvds = false;
8924 bool has_cpu_edp = false;
8925 bool has_panel = false;
8926 bool has_ck505 = false;
8927 bool can_ssc = false;
8928 bool using_ssc_source = false;
8930 /* We need to take the global config into account */
8931 for_each_intel_encoder(dev, encoder) {
8932 switch (encoder->type) {
8933 case INTEL_OUTPUT_LVDS:
8937 case INTEL_OUTPUT_EDP:
8939 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8947 if (HAS_PCH_IBX(dev)) {
8948 has_ck505 = dev_priv->vbt.display_clock_mode;
8949 can_ssc = has_ck505;
8955 /* Check if any DPLLs are using the SSC source */
8956 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8957 u32 temp = I915_READ(PCH_DPLL(i));
8959 if (!(temp & DPLL_VCO_ENABLE))
8962 if ((temp & PLL_REF_INPUT_MASK) ==
8963 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
8964 using_ssc_source = true;
8969 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
8970 has_panel, has_lvds, has_ck505, using_ssc_source);
8972 /* Ironlake: try to setup display ref clock before DPLL
8973 * enabling. This is only under driver's control after
8974 * PCH B stepping, previous chipset stepping should be
8975 * ignoring this setting.
8977 val = I915_READ(PCH_DREF_CONTROL);
8979 /* As we must carefully and slowly disable/enable each source in turn,
8980 * compute the final state we want first and check if we need to
8981 * make any changes at all.
8984 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8986 final |= DREF_NONSPREAD_CK505_ENABLE;
8988 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8990 final &= ~DREF_SSC_SOURCE_MASK;
8991 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8992 final &= ~DREF_SSC1_ENABLE;
8995 final |= DREF_SSC_SOURCE_ENABLE;
8997 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8998 final |= DREF_SSC1_ENABLE;
9001 if (intel_panel_use_ssc(dev_priv) && can_ssc)
9002 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9004 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9006 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9007 } else if (using_ssc_source) {
9008 final |= DREF_SSC_SOURCE_ENABLE;
9009 final |= DREF_SSC1_ENABLE;
9015 /* Always enable nonspread source */
9016 val &= ~DREF_NONSPREAD_SOURCE_MASK;
9019 val |= DREF_NONSPREAD_CK505_ENABLE;
9021 val |= DREF_NONSPREAD_SOURCE_ENABLE;
9024 val &= ~DREF_SSC_SOURCE_MASK;
9025 val |= DREF_SSC_SOURCE_ENABLE;
9027 /* SSC must be turned on before enabling the CPU output */
9028 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9029 DRM_DEBUG_KMS("Using SSC on panel\n");
9030 val |= DREF_SSC1_ENABLE;
9032 val &= ~DREF_SSC1_ENABLE;
9034 /* Get SSC going before enabling the outputs */
9035 I915_WRITE(PCH_DREF_CONTROL, val);
9036 POSTING_READ(PCH_DREF_CONTROL);
9039 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9041 /* Enable CPU source on CPU attached eDP */
9043 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
9044 DRM_DEBUG_KMS("Using SSC on eDP\n");
9045 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
9047 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
9049 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9051 I915_WRITE(PCH_DREF_CONTROL, val);
9052 POSTING_READ(PCH_DREF_CONTROL);
9055 DRM_DEBUG_KMS("Disabling CPU source output\n");
9057 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
9059 /* Turn off CPU output */
9060 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
9062 I915_WRITE(PCH_DREF_CONTROL, val);
9063 POSTING_READ(PCH_DREF_CONTROL);
9066 if (!using_ssc_source) {
9067 DRM_DEBUG_KMS("Disabling SSC source\n");
9069 /* Turn off the SSC source */
9070 val &= ~DREF_SSC_SOURCE_MASK;
9071 val |= DREF_SSC_SOURCE_DISABLE;
9074 val &= ~DREF_SSC1_ENABLE;
9076 I915_WRITE(PCH_DREF_CONTROL, val);
9077 POSTING_READ(PCH_DREF_CONTROL);
9082 BUG_ON(val != final);
9085 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
9089 tmp = I915_READ(SOUTH_CHICKEN2);
9090 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
9091 I915_WRITE(SOUTH_CHICKEN2, tmp);
9093 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
9094 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
9095 DRM_ERROR("FDI mPHY reset assert timeout\n");
9097 tmp = I915_READ(SOUTH_CHICKEN2);
9098 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
9099 I915_WRITE(SOUTH_CHICKEN2, tmp);
9101 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
9102 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
9103 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
9106 /* WaMPhyProgramming:hsw */
9107 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
9111 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
9112 tmp &= ~(0xFF << 24);
9113 tmp |= (0x12 << 24);
9114 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
9116 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
9118 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
9120 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
9122 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
9124 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
9125 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9126 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
9128 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
9129 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
9130 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
9132 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
9135 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
9137 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
9140 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
9142 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
9145 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
9147 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
9150 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
9152 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
9153 tmp &= ~(0xFF << 16);
9154 tmp |= (0x1C << 16);
9155 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
9157 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
9158 tmp &= ~(0xFF << 16);
9159 tmp |= (0x1C << 16);
9160 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
9162 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
9164 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
9166 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
9168 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
9170 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
9171 tmp &= ~(0xF << 28);
9173 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
9175 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
9176 tmp &= ~(0xF << 28);
9178 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
9181 /* Implements 3 different sequences from BSpec chapter "Display iCLK
9182 * Programming" based on the parameters passed:
9183 * - Sequence to enable CLKOUT_DP
9184 * - Sequence to enable CLKOUT_DP without spread
9185 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
9187 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
9190 struct drm_i915_private *dev_priv = to_i915(dev);
9193 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
9195 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
9198 mutex_lock(&dev_priv->sb_lock);
9200 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9201 tmp &= ~SBI_SSCCTL_DISABLE;
9202 tmp |= SBI_SSCCTL_PATHALT;
9203 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9208 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9209 tmp &= ~SBI_SSCCTL_PATHALT;
9210 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9213 lpt_reset_fdi_mphy(dev_priv);
9214 lpt_program_fdi_mphy(dev_priv);
9218 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9219 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9220 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9221 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9223 mutex_unlock(&dev_priv->sb_lock);
9226 /* Sequence to disable CLKOUT_DP */
9227 static void lpt_disable_clkout_dp(struct drm_device *dev)
9229 struct drm_i915_private *dev_priv = to_i915(dev);
9232 mutex_lock(&dev_priv->sb_lock);
9234 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
9235 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
9236 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
9237 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
9239 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
9240 if (!(tmp & SBI_SSCCTL_DISABLE)) {
9241 if (!(tmp & SBI_SSCCTL_PATHALT)) {
9242 tmp |= SBI_SSCCTL_PATHALT;
9243 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9246 tmp |= SBI_SSCCTL_DISABLE;
9247 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
9250 mutex_unlock(&dev_priv->sb_lock);
9253 #define BEND_IDX(steps) ((50 + (steps)) / 5)
9255 static const uint16_t sscdivintphase[] = {
9256 [BEND_IDX( 50)] = 0x3B23,
9257 [BEND_IDX( 45)] = 0x3B23,
9258 [BEND_IDX( 40)] = 0x3C23,
9259 [BEND_IDX( 35)] = 0x3C23,
9260 [BEND_IDX( 30)] = 0x3D23,
9261 [BEND_IDX( 25)] = 0x3D23,
9262 [BEND_IDX( 20)] = 0x3E23,
9263 [BEND_IDX( 15)] = 0x3E23,
9264 [BEND_IDX( 10)] = 0x3F23,
9265 [BEND_IDX( 5)] = 0x3F23,
9266 [BEND_IDX( 0)] = 0x0025,
9267 [BEND_IDX( -5)] = 0x0025,
9268 [BEND_IDX(-10)] = 0x0125,
9269 [BEND_IDX(-15)] = 0x0125,
9270 [BEND_IDX(-20)] = 0x0225,
9271 [BEND_IDX(-25)] = 0x0225,
9272 [BEND_IDX(-30)] = 0x0325,
9273 [BEND_IDX(-35)] = 0x0325,
9274 [BEND_IDX(-40)] = 0x0425,
9275 [BEND_IDX(-45)] = 0x0425,
9276 [BEND_IDX(-50)] = 0x0525,
9281 * steps -50 to 50 inclusive, in steps of 5
9282 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
9283 * change in clock period = -(steps / 10) * 5.787 ps
9285 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
9288 int idx = BEND_IDX(steps);
9290 if (WARN_ON(steps % 5 != 0))
9293 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
9296 mutex_lock(&dev_priv->sb_lock);
9298 if (steps % 10 != 0)
9302 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
9304 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
9306 tmp |= sscdivintphase[idx];
9307 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
9309 mutex_unlock(&dev_priv->sb_lock);
9314 static void lpt_init_pch_refclk(struct drm_device *dev)
9316 struct intel_encoder *encoder;
9317 bool has_vga = false;
9319 for_each_intel_encoder(dev, encoder) {
9320 switch (encoder->type) {
9321 case INTEL_OUTPUT_ANALOG:
9330 lpt_bend_clkout_dp(to_i915(dev), 0);
9331 lpt_enable_clkout_dp(dev, true, true);
9333 lpt_disable_clkout_dp(dev);
9338 * Initialize reference clocks when the driver loads
9340 void intel_init_pch_refclk(struct drm_device *dev)
9342 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9343 ironlake_init_pch_refclk(dev);
9344 else if (HAS_PCH_LPT(dev))
9345 lpt_init_pch_refclk(dev);
9348 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
9350 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9352 int pipe = intel_crtc->pipe;
9357 switch (intel_crtc->config->pipe_bpp) {
9359 val |= PIPECONF_6BPC;
9362 val |= PIPECONF_8BPC;
9365 val |= PIPECONF_10BPC;
9368 val |= PIPECONF_12BPC;
9371 /* Case prevented by intel_choose_pipe_bpp_dither. */
9375 if (intel_crtc->config->dither)
9376 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9378 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9379 val |= PIPECONF_INTERLACED_ILK;
9381 val |= PIPECONF_PROGRESSIVE;
9383 if (intel_crtc->config->limited_color_range)
9384 val |= PIPECONF_COLOR_RANGE_SELECT;
9386 I915_WRITE(PIPECONF(pipe), val);
9387 POSTING_READ(PIPECONF(pipe));
9390 static void haswell_set_pipeconf(struct drm_crtc *crtc)
9392 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9394 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9397 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
9398 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
9400 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
9401 val |= PIPECONF_INTERLACED_ILK;
9403 val |= PIPECONF_PROGRESSIVE;
9405 I915_WRITE(PIPECONF(cpu_transcoder), val);
9406 POSTING_READ(PIPECONF(cpu_transcoder));
9409 static void haswell_set_pipemisc(struct drm_crtc *crtc)
9411 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
9412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9414 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
9417 switch (intel_crtc->config->pipe_bpp) {
9419 val |= PIPEMISC_DITHER_6_BPC;
9422 val |= PIPEMISC_DITHER_8_BPC;
9425 val |= PIPEMISC_DITHER_10_BPC;
9428 val |= PIPEMISC_DITHER_12_BPC;
9431 /* Case prevented by pipe_config_set_bpp. */
9435 if (intel_crtc->config->dither)
9436 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
9438 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
9442 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
9445 * Account for spread spectrum to avoid
9446 * oversubscribing the link. Max center spread
9447 * is 2.5%; use 5% for safety's sake.
9449 u32 bps = target_clock * bpp * 21 / 20;
9450 return DIV_ROUND_UP(bps, link_bw * 8);
9453 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
9455 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
9458 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
9459 struct intel_crtc_state *crtc_state,
9460 struct dpll *reduced_clock)
9462 struct drm_crtc *crtc = &intel_crtc->base;
9463 struct drm_device *dev = crtc->dev;
9464 struct drm_i915_private *dev_priv = to_i915(dev);
9468 /* Enable autotuning of the PLL clock (if permissible) */
9470 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9471 if ((intel_panel_use_ssc(dev_priv) &&
9472 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9473 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9475 } else if (crtc_state->sdvo_tv_clock)
9478 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9480 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9483 if (reduced_clock) {
9484 fp2 = i9xx_dpll_compute_fp(reduced_clock);
9486 if (reduced_clock->m < factor * reduced_clock->n)
9494 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
9495 dpll |= DPLLB_MODE_LVDS;
9497 dpll |= DPLLB_MODE_DAC_SERIAL;
9499 dpll |= (crtc_state->pixel_multiplier - 1)
9500 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9502 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
9503 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
9504 dpll |= DPLL_SDVO_HIGH_SPEED;
9506 if (intel_crtc_has_dp_encoder(crtc_state))
9507 dpll |= DPLL_SDVO_HIGH_SPEED;
9510 * The high speed IO clock is only really required for
9511 * SDVO/HDMI/DP, but we also enable it for CRT to make it
9512 * possible to share the DPLL between CRT and HDMI. Enabling
9513 * the clock needlessly does no real harm, except use up a
9514 * bit of power potentially.
9516 * We'll limit this to IVB with 3 pipes, since it has only two
9517 * DPLLs and so DPLL sharing is the only way to get three pipes
9518 * driving PCH ports at the same time. On SNB we could do this,
9519 * and potentially avoid enabling the second DPLL, but it's not
9520 * clear if it''s a win or loss power wise. No point in doing
9521 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
9523 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
9524 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
9525 dpll |= DPLL_SDVO_HIGH_SPEED;
9527 /* compute bitmask from p1 value */
9528 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9530 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9532 switch (crtc_state->dpll.p2) {
9534 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9537 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9540 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9543 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9547 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9548 intel_panel_use_ssc(dev_priv))
9549 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9551 dpll |= PLL_REF_INPUT_DREFCLK;
9553 dpll |= DPLL_VCO_ENABLE;
9555 crtc_state->dpll_hw_state.dpll = dpll;
9556 crtc_state->dpll_hw_state.fp0 = fp;
9557 crtc_state->dpll_hw_state.fp1 = fp2;
9560 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9561 struct intel_crtc_state *crtc_state)
9563 struct drm_device *dev = crtc->base.dev;
9564 struct drm_i915_private *dev_priv = to_i915(dev);
9565 struct dpll reduced_clock;
9566 bool has_reduced_clock = false;
9567 struct intel_shared_dpll *pll;
9568 const struct intel_limit *limit;
9569 int refclk = 120000;
9571 memset(&crtc_state->dpll_hw_state, 0,
9572 sizeof(crtc_state->dpll_hw_state));
9574 crtc->lowfreq_avail = false;
9576 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9577 if (!crtc_state->has_pch_encoder)
9580 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
9581 if (intel_panel_use_ssc(dev_priv)) {
9582 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
9583 dev_priv->vbt.lvds_ssc_freq);
9584 refclk = dev_priv->vbt.lvds_ssc_freq;
9587 if (intel_is_dual_link_lvds(dev)) {
9588 if (refclk == 100000)
9589 limit = &intel_limits_ironlake_dual_lvds_100m;
9591 limit = &intel_limits_ironlake_dual_lvds;
9593 if (refclk == 100000)
9594 limit = &intel_limits_ironlake_single_lvds_100m;
9596 limit = &intel_limits_ironlake_single_lvds;
9599 limit = &intel_limits_ironlake_dac;
9602 if (!crtc_state->clock_set &&
9603 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
9604 refclk, NULL, &crtc_state->dpll)) {
9605 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9609 ironlake_compute_dpll(crtc, crtc_state,
9610 has_reduced_clock ? &reduced_clock : NULL);
9612 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
9614 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9615 pipe_name(crtc->pipe));
9619 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
9621 crtc->lowfreq_avail = true;
9626 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9627 struct intel_link_m_n *m_n)
9629 struct drm_device *dev = crtc->base.dev;
9630 struct drm_i915_private *dev_priv = to_i915(dev);
9631 enum pipe pipe = crtc->pipe;
9633 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9634 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9635 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9637 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9638 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9639 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9642 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9643 enum transcoder transcoder,
9644 struct intel_link_m_n *m_n,
9645 struct intel_link_m_n *m2_n2)
9647 struct drm_device *dev = crtc->base.dev;
9648 struct drm_i915_private *dev_priv = to_i915(dev);
9649 enum pipe pipe = crtc->pipe;
9651 if (INTEL_INFO(dev)->gen >= 5) {
9652 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9653 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9654 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9656 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9657 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9658 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9659 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9660 * gen < 8) and if DRRS is supported (to make sure the
9661 * registers are not unnecessarily read).
9663 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9664 crtc->config->has_drrs) {
9665 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9666 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9667 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9669 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9670 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9671 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9674 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9675 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9676 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9678 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9679 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9680 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9684 void intel_dp_get_m_n(struct intel_crtc *crtc,
9685 struct intel_crtc_state *pipe_config)
9687 if (pipe_config->has_pch_encoder)
9688 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9690 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9691 &pipe_config->dp_m_n,
9692 &pipe_config->dp_m2_n2);
9695 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9696 struct intel_crtc_state *pipe_config)
9698 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9699 &pipe_config->fdi_m_n, NULL);
9702 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9703 struct intel_crtc_state *pipe_config)
9705 struct drm_device *dev = crtc->base.dev;
9706 struct drm_i915_private *dev_priv = to_i915(dev);
9707 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9708 uint32_t ps_ctrl = 0;
9712 /* find scaler attached to this pipe */
9713 for (i = 0; i < crtc->num_scalers; i++) {
9714 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9715 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9717 pipe_config->pch_pfit.enabled = true;
9718 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9719 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9724 scaler_state->scaler_id = id;
9726 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9728 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9733 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9734 struct intel_initial_plane_config *plane_config)
9736 struct drm_device *dev = crtc->base.dev;
9737 struct drm_i915_private *dev_priv = to_i915(dev);
9738 u32 val, base, offset, stride_mult, tiling;
9739 int pipe = crtc->pipe;
9740 int fourcc, pixel_format;
9741 unsigned int aligned_height;
9742 struct drm_framebuffer *fb;
9743 struct intel_framebuffer *intel_fb;
9745 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9747 DRM_DEBUG_KMS("failed to alloc fb\n");
9751 fb = &intel_fb->base;
9753 val = I915_READ(PLANE_CTL(pipe, 0));
9754 if (!(val & PLANE_CTL_ENABLE))
9757 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9758 fourcc = skl_format_to_fourcc(pixel_format,
9759 val & PLANE_CTL_ORDER_RGBX,
9760 val & PLANE_CTL_ALPHA_MASK);
9761 fb->pixel_format = fourcc;
9762 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9764 tiling = val & PLANE_CTL_TILED_MASK;
9766 case PLANE_CTL_TILED_LINEAR:
9767 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9769 case PLANE_CTL_TILED_X:
9770 plane_config->tiling = I915_TILING_X;
9771 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9773 case PLANE_CTL_TILED_Y:
9774 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9776 case PLANE_CTL_TILED_YF:
9777 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9780 MISSING_CASE(tiling);
9784 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9785 plane_config->base = base;
9787 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9789 val = I915_READ(PLANE_SIZE(pipe, 0));
9790 fb->height = ((val >> 16) & 0xfff) + 1;
9791 fb->width = ((val >> 0) & 0x1fff) + 1;
9793 val = I915_READ(PLANE_STRIDE(pipe, 0));
9794 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9796 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9798 aligned_height = intel_fb_align_height(dev, fb->height,
9802 plane_config->size = fb->pitches[0] * aligned_height;
9804 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9805 pipe_name(pipe), fb->width, fb->height,
9806 fb->bits_per_pixel, base, fb->pitches[0],
9807 plane_config->size);
9809 plane_config->fb = intel_fb;
9816 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9817 struct intel_crtc_state *pipe_config)
9819 struct drm_device *dev = crtc->base.dev;
9820 struct drm_i915_private *dev_priv = to_i915(dev);
9823 tmp = I915_READ(PF_CTL(crtc->pipe));
9825 if (tmp & PF_ENABLE) {
9826 pipe_config->pch_pfit.enabled = true;
9827 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9828 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9830 /* We currently do not free assignements of panel fitters on
9831 * ivb/hsw (since we don't use the higher upscaling modes which
9832 * differentiates them) so just WARN about this case for now. */
9834 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9835 PF_PIPE_SEL_IVB(crtc->pipe));
9841 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9842 struct intel_initial_plane_config *plane_config)
9844 struct drm_device *dev = crtc->base.dev;
9845 struct drm_i915_private *dev_priv = to_i915(dev);
9846 u32 val, base, offset;
9847 int pipe = crtc->pipe;
9848 int fourcc, pixel_format;
9849 unsigned int aligned_height;
9850 struct drm_framebuffer *fb;
9851 struct intel_framebuffer *intel_fb;
9853 val = I915_READ(DSPCNTR(pipe));
9854 if (!(val & DISPLAY_PLANE_ENABLE))
9857 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9859 DRM_DEBUG_KMS("failed to alloc fb\n");
9863 fb = &intel_fb->base;
9865 if (INTEL_INFO(dev)->gen >= 4) {
9866 if (val & DISPPLANE_TILED) {
9867 plane_config->tiling = I915_TILING_X;
9868 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9872 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9873 fourcc = i9xx_format_to_fourcc(pixel_format);
9874 fb->pixel_format = fourcc;
9875 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9877 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9878 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9879 offset = I915_READ(DSPOFFSET(pipe));
9881 if (plane_config->tiling)
9882 offset = I915_READ(DSPTILEOFF(pipe));
9884 offset = I915_READ(DSPLINOFF(pipe));
9886 plane_config->base = base;
9888 val = I915_READ(PIPESRC(pipe));
9889 fb->width = ((val >> 16) & 0xfff) + 1;
9890 fb->height = ((val >> 0) & 0xfff) + 1;
9892 val = I915_READ(DSPSTRIDE(pipe));
9893 fb->pitches[0] = val & 0xffffffc0;
9895 aligned_height = intel_fb_align_height(dev, fb->height,
9899 plane_config->size = fb->pitches[0] * aligned_height;
9901 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9902 pipe_name(pipe), fb->width, fb->height,
9903 fb->bits_per_pixel, base, fb->pitches[0],
9904 plane_config->size);
9906 plane_config->fb = intel_fb;
9909 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9910 struct intel_crtc_state *pipe_config)
9912 struct drm_device *dev = crtc->base.dev;
9913 struct drm_i915_private *dev_priv = to_i915(dev);
9914 enum intel_display_power_domain power_domain;
9918 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9919 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9922 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9923 pipe_config->shared_dpll = NULL;
9926 tmp = I915_READ(PIPECONF(crtc->pipe));
9927 if (!(tmp & PIPECONF_ENABLE))
9930 switch (tmp & PIPECONF_BPC_MASK) {
9932 pipe_config->pipe_bpp = 18;
9935 pipe_config->pipe_bpp = 24;
9937 case PIPECONF_10BPC:
9938 pipe_config->pipe_bpp = 30;
9940 case PIPECONF_12BPC:
9941 pipe_config->pipe_bpp = 36;
9947 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9948 pipe_config->limited_color_range = true;
9950 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9951 struct intel_shared_dpll *pll;
9952 enum intel_dpll_id pll_id;
9954 pipe_config->has_pch_encoder = true;
9956 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9957 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9958 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9960 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9962 if (HAS_PCH_IBX(dev_priv)) {
9964 * The pipe->pch transcoder and pch transcoder->pll
9967 pll_id = (enum intel_dpll_id) crtc->pipe;
9969 tmp = I915_READ(PCH_DPLL_SEL);
9970 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9971 pll_id = DPLL_ID_PCH_PLL_B;
9973 pll_id= DPLL_ID_PCH_PLL_A;
9976 pipe_config->shared_dpll =
9977 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9978 pll = pipe_config->shared_dpll;
9980 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9981 &pipe_config->dpll_hw_state));
9983 tmp = pipe_config->dpll_hw_state.dpll;
9984 pipe_config->pixel_multiplier =
9985 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9986 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9988 ironlake_pch_clock_get(crtc, pipe_config);
9990 pipe_config->pixel_multiplier = 1;
9993 intel_get_pipe_timings(crtc, pipe_config);
9994 intel_get_pipe_src_size(crtc, pipe_config);
9996 ironlake_get_pfit_config(crtc, pipe_config);
10001 intel_display_power_put(dev_priv, power_domain);
10006 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
10008 struct drm_device *dev = &dev_priv->drm;
10009 struct intel_crtc *crtc;
10011 for_each_intel_crtc(dev, crtc)
10012 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
10013 pipe_name(crtc->pipe));
10015 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
10016 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
10017 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
10018 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
10019 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
10020 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
10021 "CPU PWM1 enabled\n");
10022 if (IS_HASWELL(dev))
10023 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
10024 "CPU PWM2 enabled\n");
10025 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
10026 "PCH PWM1 enabled\n");
10027 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
10028 "Utility pin enabled\n");
10029 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
10032 * In theory we can still leave IRQs enabled, as long as only the HPD
10033 * interrupts remain enabled. We used to check for that, but since it's
10034 * gen-specific and since we only disable LCPLL after we fully disable
10035 * the interrupts, the check below should be enough.
10037 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
10040 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
10042 struct drm_device *dev = &dev_priv->drm;
10044 if (IS_HASWELL(dev))
10045 return I915_READ(D_COMP_HSW);
10047 return I915_READ(D_COMP_BDW);
10050 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
10052 struct drm_device *dev = &dev_priv->drm;
10054 if (IS_HASWELL(dev)) {
10055 mutex_lock(&dev_priv->rps.hw_lock);
10056 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
10058 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
10059 mutex_unlock(&dev_priv->rps.hw_lock);
10061 I915_WRITE(D_COMP_BDW, val);
10062 POSTING_READ(D_COMP_BDW);
10067 * This function implements pieces of two sequences from BSpec:
10068 * - Sequence for display software to disable LCPLL
10069 * - Sequence for display software to allow package C8+
10070 * The steps implemented here are just the steps that actually touch the LCPLL
10071 * register. Callers should take care of disabling all the display engine
10072 * functions, doing the mode unset, fixing interrupts, etc.
10074 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
10075 bool switch_to_fclk, bool allow_power_down)
10079 assert_can_disable_lcpll(dev_priv);
10081 val = I915_READ(LCPLL_CTL);
10083 if (switch_to_fclk) {
10084 val |= LCPLL_CD_SOURCE_FCLK;
10085 I915_WRITE(LCPLL_CTL, val);
10087 if (wait_for_us(I915_READ(LCPLL_CTL) &
10088 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10089 DRM_ERROR("Switching to FCLK failed\n");
10091 val = I915_READ(LCPLL_CTL);
10094 val |= LCPLL_PLL_DISABLE;
10095 I915_WRITE(LCPLL_CTL, val);
10096 POSTING_READ(LCPLL_CTL);
10098 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
10099 DRM_ERROR("LCPLL still locked\n");
10101 val = hsw_read_dcomp(dev_priv);
10102 val |= D_COMP_COMP_DISABLE;
10103 hsw_write_dcomp(dev_priv, val);
10106 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
10108 DRM_ERROR("D_COMP RCOMP still in progress\n");
10110 if (allow_power_down) {
10111 val = I915_READ(LCPLL_CTL);
10112 val |= LCPLL_POWER_DOWN_ALLOW;
10113 I915_WRITE(LCPLL_CTL, val);
10114 POSTING_READ(LCPLL_CTL);
10119 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
10122 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
10126 val = I915_READ(LCPLL_CTL);
10128 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
10129 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
10133 * Make sure we're not on PC8 state before disabling PC8, otherwise
10134 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
10136 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
10138 if (val & LCPLL_POWER_DOWN_ALLOW) {
10139 val &= ~LCPLL_POWER_DOWN_ALLOW;
10140 I915_WRITE(LCPLL_CTL, val);
10141 POSTING_READ(LCPLL_CTL);
10144 val = hsw_read_dcomp(dev_priv);
10145 val |= D_COMP_COMP_FORCE;
10146 val &= ~D_COMP_COMP_DISABLE;
10147 hsw_write_dcomp(dev_priv, val);
10149 val = I915_READ(LCPLL_CTL);
10150 val &= ~LCPLL_PLL_DISABLE;
10151 I915_WRITE(LCPLL_CTL, val);
10153 if (intel_wait_for_register(dev_priv,
10154 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
10156 DRM_ERROR("LCPLL not locked yet\n");
10158 if (val & LCPLL_CD_SOURCE_FCLK) {
10159 val = I915_READ(LCPLL_CTL);
10160 val &= ~LCPLL_CD_SOURCE_FCLK;
10161 I915_WRITE(LCPLL_CTL, val);
10163 if (wait_for_us((I915_READ(LCPLL_CTL) &
10164 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10165 DRM_ERROR("Switching back to LCPLL failed\n");
10168 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
10169 intel_update_cdclk(&dev_priv->drm);
10173 * Package states C8 and deeper are really deep PC states that can only be
10174 * reached when all the devices on the system allow it, so even if the graphics
10175 * device allows PC8+, it doesn't mean the system will actually get to these
10176 * states. Our driver only allows PC8+ when going into runtime PM.
10178 * The requirements for PC8+ are that all the outputs are disabled, the power
10179 * well is disabled and most interrupts are disabled, and these are also
10180 * requirements for runtime PM. When these conditions are met, we manually do
10181 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
10182 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
10183 * hang the machine.
10185 * When we really reach PC8 or deeper states (not just when we allow it) we lose
10186 * the state of some registers, so when we come back from PC8+ we need to
10187 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
10188 * need to take care of the registers kept by RC6. Notice that this happens even
10189 * if we don't put the device in PCI D3 state (which is what currently happens
10190 * because of the runtime PM support).
10192 * For more, read "Display Sequences for Package C8" on the hardware
10195 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
10197 struct drm_device *dev = &dev_priv->drm;
10200 DRM_DEBUG_KMS("Enabling package C8+\n");
10202 if (HAS_PCH_LPT_LP(dev)) {
10203 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10204 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
10205 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10208 lpt_disable_clkout_dp(dev);
10209 hsw_disable_lcpll(dev_priv, true, true);
10212 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
10214 struct drm_device *dev = &dev_priv->drm;
10217 DRM_DEBUG_KMS("Disabling package C8+\n");
10219 hsw_restore_lcpll(dev_priv);
10220 lpt_init_pch_refclk(dev);
10222 if (HAS_PCH_LPT_LP(dev)) {
10223 val = I915_READ(SOUTH_DSPCLK_GATE_D);
10224 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
10225 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
10229 static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10231 struct drm_device *dev = old_state->dev;
10232 struct intel_atomic_state *old_intel_state =
10233 to_intel_atomic_state(old_state);
10234 unsigned int req_cdclk = old_intel_state->dev_cdclk;
10236 bxt_set_cdclk(to_i915(dev), req_cdclk);
10239 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
10242 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
10244 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
10245 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
10246 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
10248 /* BSpec says "Do not use DisplayPort with CDCLK less than
10249 * 432 MHz, audio enabled, port width x4, and link rate
10250 * HBR2 (5.4 GHz), or else there may be audio corruption or
10251 * screen corruption."
10253 if (intel_crtc_has_dp_encoder(crtc_state) &&
10254 crtc_state->has_audio &&
10255 crtc_state->port_clock >= 540000 &&
10256 crtc_state->lane_count == 4)
10257 pixel_rate = max(432000, pixel_rate);
10262 /* compute the max rate for new configuration */
10263 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
10265 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10266 struct drm_i915_private *dev_priv = to_i915(state->dev);
10267 struct drm_crtc *crtc;
10268 struct drm_crtc_state *cstate;
10269 struct intel_crtc_state *crtc_state;
10270 unsigned max_pixel_rate = 0, i;
10273 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
10274 sizeof(intel_state->min_pixclk));
10276 for_each_crtc_in_state(state, crtc, cstate, i) {
10279 crtc_state = to_intel_crtc_state(cstate);
10280 if (!crtc_state->base.enable) {
10281 intel_state->min_pixclk[i] = 0;
10285 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
10287 if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
10288 pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
10291 intel_state->min_pixclk[i] = pixel_rate;
10294 for_each_pipe(dev_priv, pipe)
10295 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
10297 return max_pixel_rate;
10300 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
10302 struct drm_i915_private *dev_priv = to_i915(dev);
10303 uint32_t val, data;
10306 if (WARN((I915_READ(LCPLL_CTL) &
10307 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
10308 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
10309 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
10310 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
10311 "trying to change cdclk frequency with cdclk not enabled\n"))
10314 mutex_lock(&dev_priv->rps.hw_lock);
10315 ret = sandybridge_pcode_write(dev_priv,
10316 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
10317 mutex_unlock(&dev_priv->rps.hw_lock);
10319 DRM_ERROR("failed to inform pcode about cdclk change\n");
10323 val = I915_READ(LCPLL_CTL);
10324 val |= LCPLL_CD_SOURCE_FCLK;
10325 I915_WRITE(LCPLL_CTL, val);
10327 if (wait_for_us(I915_READ(LCPLL_CTL) &
10328 LCPLL_CD_SOURCE_FCLK_DONE, 1))
10329 DRM_ERROR("Switching to FCLK failed\n");
10331 val = I915_READ(LCPLL_CTL);
10332 val &= ~LCPLL_CLK_FREQ_MASK;
10336 val |= LCPLL_CLK_FREQ_450;
10340 val |= LCPLL_CLK_FREQ_54O_BDW;
10344 val |= LCPLL_CLK_FREQ_337_5_BDW;
10348 val |= LCPLL_CLK_FREQ_675_BDW;
10352 WARN(1, "invalid cdclk frequency\n");
10356 I915_WRITE(LCPLL_CTL, val);
10358 val = I915_READ(LCPLL_CTL);
10359 val &= ~LCPLL_CD_SOURCE_FCLK;
10360 I915_WRITE(LCPLL_CTL, val);
10362 if (wait_for_us((I915_READ(LCPLL_CTL) &
10363 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
10364 DRM_ERROR("Switching back to LCPLL failed\n");
10366 mutex_lock(&dev_priv->rps.hw_lock);
10367 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
10368 mutex_unlock(&dev_priv->rps.hw_lock);
10370 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
10372 intel_update_cdclk(dev);
10374 WARN(cdclk != dev_priv->cdclk_freq,
10375 "cdclk requested %d kHz but got %d kHz\n",
10376 cdclk, dev_priv->cdclk_freq);
10379 static int broadwell_calc_cdclk(int max_pixclk)
10381 if (max_pixclk > 540000)
10383 else if (max_pixclk > 450000)
10385 else if (max_pixclk > 337500)
10391 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
10393 struct drm_i915_private *dev_priv = to_i915(state->dev);
10394 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10395 int max_pixclk = ilk_max_pixel_rate(state);
10399 * FIXME should also account for plane ratio
10400 * once 64bpp pixel formats are supported.
10402 cdclk = broadwell_calc_cdclk(max_pixclk);
10404 if (cdclk > dev_priv->max_cdclk_freq) {
10405 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10406 cdclk, dev_priv->max_cdclk_freq);
10410 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10411 if (!intel_state->active_crtcs)
10412 intel_state->dev_cdclk = broadwell_calc_cdclk(0);
10417 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10419 struct drm_device *dev = old_state->dev;
10420 struct intel_atomic_state *old_intel_state =
10421 to_intel_atomic_state(old_state);
10422 unsigned req_cdclk = old_intel_state->dev_cdclk;
10424 broadwell_set_cdclk(dev, req_cdclk);
10427 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
10429 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
10430 struct drm_i915_private *dev_priv = to_i915(state->dev);
10431 const int max_pixclk = ilk_max_pixel_rate(state);
10432 int vco = intel_state->cdclk_pll_vco;
10436 * FIXME should also account for plane ratio
10437 * once 64bpp pixel formats are supported.
10439 cdclk = skl_calc_cdclk(max_pixclk, vco);
10442 * FIXME move the cdclk caclulation to
10443 * compute_config() so we can fail gracegully.
10445 if (cdclk > dev_priv->max_cdclk_freq) {
10446 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
10447 cdclk, dev_priv->max_cdclk_freq);
10448 cdclk = dev_priv->max_cdclk_freq;
10451 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
10452 if (!intel_state->active_crtcs)
10453 intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
10458 static void skl_modeset_commit_cdclk(struct drm_atomic_state *old_state)
10460 struct drm_i915_private *dev_priv = to_i915(old_state->dev);
10461 struct intel_atomic_state *intel_state = to_intel_atomic_state(old_state);
10462 unsigned int req_cdclk = intel_state->dev_cdclk;
10463 unsigned int req_vco = intel_state->cdclk_pll_vco;
10465 skl_set_cdclk(dev_priv, req_cdclk, req_vco);
10468 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
10469 struct intel_crtc_state *crtc_state)
10471 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
10472 if (!intel_ddi_pll_select(crtc, crtc_state))
10476 crtc->lowfreq_avail = false;
10481 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
10483 struct intel_crtc_state *pipe_config)
10485 enum intel_dpll_id id;
10489 id = DPLL_ID_SKL_DPLL0;
10492 id = DPLL_ID_SKL_DPLL1;
10495 id = DPLL_ID_SKL_DPLL2;
10498 DRM_ERROR("Incorrect port type\n");
10502 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10505 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
10507 struct intel_crtc_state *pipe_config)
10509 enum intel_dpll_id id;
10512 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
10513 id = temp >> (port * 3 + 1);
10515 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
10518 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10521 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
10523 struct intel_crtc_state *pipe_config)
10525 enum intel_dpll_id id;
10526 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
10528 switch (ddi_pll_sel) {
10529 case PORT_CLK_SEL_WRPLL1:
10530 id = DPLL_ID_WRPLL1;
10532 case PORT_CLK_SEL_WRPLL2:
10533 id = DPLL_ID_WRPLL2;
10535 case PORT_CLK_SEL_SPLL:
10538 case PORT_CLK_SEL_LCPLL_810:
10539 id = DPLL_ID_LCPLL_810;
10541 case PORT_CLK_SEL_LCPLL_1350:
10542 id = DPLL_ID_LCPLL_1350;
10544 case PORT_CLK_SEL_LCPLL_2700:
10545 id = DPLL_ID_LCPLL_2700;
10548 MISSING_CASE(ddi_pll_sel);
10550 case PORT_CLK_SEL_NONE:
10554 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
10557 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
10558 struct intel_crtc_state *pipe_config,
10559 unsigned long *power_domain_mask)
10561 struct drm_device *dev = crtc->base.dev;
10562 struct drm_i915_private *dev_priv = to_i915(dev);
10563 enum intel_display_power_domain power_domain;
10567 * The pipe->transcoder mapping is fixed with the exception of the eDP
10568 * transcoder handled below.
10570 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10573 * XXX: Do intel_display_power_get_if_enabled before reading this (for
10574 * consistency and less surprising code; it's in always on power).
10576 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10577 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10578 enum pipe trans_edp_pipe;
10579 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10581 WARN(1, "unknown pipe linked to edp transcoder\n");
10582 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10583 case TRANS_DDI_EDP_INPUT_A_ON:
10584 trans_edp_pipe = PIPE_A;
10586 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10587 trans_edp_pipe = PIPE_B;
10589 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10590 trans_edp_pipe = PIPE_C;
10594 if (trans_edp_pipe == crtc->pipe)
10595 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10598 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
10599 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10601 *power_domain_mask |= BIT(power_domain);
10603 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10605 return tmp & PIPECONF_ENABLE;
10608 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
10609 struct intel_crtc_state *pipe_config,
10610 unsigned long *power_domain_mask)
10612 struct drm_device *dev = crtc->base.dev;
10613 struct drm_i915_private *dev_priv = to_i915(dev);
10614 enum intel_display_power_domain power_domain;
10616 enum transcoder cpu_transcoder;
10619 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
10620 if (port == PORT_A)
10621 cpu_transcoder = TRANSCODER_DSI_A;
10623 cpu_transcoder = TRANSCODER_DSI_C;
10625 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
10626 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10628 *power_domain_mask |= BIT(power_domain);
10631 * The PLL needs to be enabled with a valid divider
10632 * configuration, otherwise accessing DSI registers will hang
10633 * the machine. See BSpec North Display Engine
10634 * registers/MIPI[BXT]. We can break out here early, since we
10635 * need the same DSI PLL to be enabled for both DSI ports.
10637 if (!intel_dsi_pll_is_enabled(dev_priv))
10640 /* XXX: this works for video mode only */
10641 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
10642 if (!(tmp & DPI_ENABLE))
10645 tmp = I915_READ(MIPI_CTRL(port));
10646 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
10649 pipe_config->cpu_transcoder = cpu_transcoder;
10653 return transcoder_is_dsi(pipe_config->cpu_transcoder);
10656 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
10657 struct intel_crtc_state *pipe_config)
10659 struct drm_device *dev = crtc->base.dev;
10660 struct drm_i915_private *dev_priv = to_i915(dev);
10661 struct intel_shared_dpll *pll;
10665 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10667 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10669 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10670 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10671 else if (IS_BROXTON(dev))
10672 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10674 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10676 pll = pipe_config->shared_dpll;
10678 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
10679 &pipe_config->dpll_hw_state));
10683 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10684 * DDI E. So just check whether this pipe is wired to DDI E and whether
10685 * the PCH transcoder is on.
10687 if (INTEL_INFO(dev)->gen < 9 &&
10688 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10689 pipe_config->has_pch_encoder = true;
10691 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10692 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10693 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10695 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10699 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10700 struct intel_crtc_state *pipe_config)
10702 struct drm_device *dev = crtc->base.dev;
10703 struct drm_i915_private *dev_priv = to_i915(dev);
10704 enum intel_display_power_domain power_domain;
10705 unsigned long power_domain_mask;
10708 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
10709 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
10711 power_domain_mask = BIT(power_domain);
10713 pipe_config->shared_dpll = NULL;
10715 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
10717 if (IS_BROXTON(dev_priv) &&
10718 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
10726 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10727 haswell_get_ddi_port_state(crtc, pipe_config);
10728 intel_get_pipe_timings(crtc, pipe_config);
10731 intel_get_pipe_src_size(crtc, pipe_config);
10733 pipe_config->gamma_mode =
10734 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
10736 if (INTEL_INFO(dev)->gen >= 9) {
10737 skl_init_scalers(dev, crtc, pipe_config);
10740 if (INTEL_INFO(dev)->gen >= 9) {
10741 pipe_config->scaler_state.scaler_id = -1;
10742 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10745 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10746 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
10747 power_domain_mask |= BIT(power_domain);
10748 if (INTEL_INFO(dev)->gen >= 9)
10749 skylake_get_pfit_config(crtc, pipe_config);
10751 ironlake_get_pfit_config(crtc, pipe_config);
10754 if (IS_HASWELL(dev))
10755 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10756 (I915_READ(IPS_CTL) & IPS_ENABLE);
10758 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10759 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10760 pipe_config->pixel_multiplier =
10761 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10763 pipe_config->pixel_multiplier = 1;
10767 for_each_power_domain(power_domain, power_domain_mask)
10768 intel_display_power_put(dev_priv, power_domain);
10773 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10774 const struct intel_plane_state *plane_state)
10776 struct drm_device *dev = crtc->dev;
10777 struct drm_i915_private *dev_priv = to_i915(dev);
10778 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10779 uint32_t cntl = 0, size = 0;
10781 if (plane_state && plane_state->base.visible) {
10782 unsigned int width = plane_state->base.crtc_w;
10783 unsigned int height = plane_state->base.crtc_h;
10784 unsigned int stride = roundup_pow_of_two(width) * 4;
10788 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10799 cntl |= CURSOR_ENABLE |
10800 CURSOR_GAMMA_ENABLE |
10801 CURSOR_FORMAT_ARGB |
10802 CURSOR_STRIDE(stride);
10804 size = (height << 12) | width;
10807 if (intel_crtc->cursor_cntl != 0 &&
10808 (intel_crtc->cursor_base != base ||
10809 intel_crtc->cursor_size != size ||
10810 intel_crtc->cursor_cntl != cntl)) {
10811 /* On these chipsets we can only modify the base/size/stride
10812 * whilst the cursor is disabled.
10814 I915_WRITE(CURCNTR(PIPE_A), 0);
10815 POSTING_READ(CURCNTR(PIPE_A));
10816 intel_crtc->cursor_cntl = 0;
10819 if (intel_crtc->cursor_base != base) {
10820 I915_WRITE(CURBASE(PIPE_A), base);
10821 intel_crtc->cursor_base = base;
10824 if (intel_crtc->cursor_size != size) {
10825 I915_WRITE(CURSIZE, size);
10826 intel_crtc->cursor_size = size;
10829 if (intel_crtc->cursor_cntl != cntl) {
10830 I915_WRITE(CURCNTR(PIPE_A), cntl);
10831 POSTING_READ(CURCNTR(PIPE_A));
10832 intel_crtc->cursor_cntl = cntl;
10836 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10837 const struct intel_plane_state *plane_state)
10839 struct drm_device *dev = crtc->dev;
10840 struct drm_i915_private *dev_priv = to_i915(dev);
10841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10842 const struct skl_wm_values *wm = &dev_priv->wm.skl_results;
10843 int pipe = intel_crtc->pipe;
10846 if (INTEL_GEN(dev_priv) >= 9 && wm->dirty_pipes & drm_crtc_mask(crtc))
10847 skl_write_cursor_wm(intel_crtc, wm);
10849 if (plane_state && plane_state->base.visible) {
10850 cntl = MCURSOR_GAMMA_ENABLE;
10851 switch (plane_state->base.crtc_w) {
10853 cntl |= CURSOR_MODE_64_ARGB_AX;
10856 cntl |= CURSOR_MODE_128_ARGB_AX;
10859 cntl |= CURSOR_MODE_256_ARGB_AX;
10862 MISSING_CASE(plane_state->base.crtc_w);
10865 cntl |= pipe << 28; /* Connect to correct pipe */
10868 cntl |= CURSOR_PIPE_CSC_ENABLE;
10870 if (plane_state->base.rotation == DRM_ROTATE_180)
10871 cntl |= CURSOR_ROTATE_180;
10874 if (intel_crtc->cursor_cntl != cntl) {
10875 I915_WRITE(CURCNTR(pipe), cntl);
10876 POSTING_READ(CURCNTR(pipe));
10877 intel_crtc->cursor_cntl = cntl;
10880 /* and commit changes on next vblank */
10881 I915_WRITE(CURBASE(pipe), base);
10882 POSTING_READ(CURBASE(pipe));
10884 intel_crtc->cursor_base = base;
10887 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10888 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10889 const struct intel_plane_state *plane_state)
10891 struct drm_device *dev = crtc->dev;
10892 struct drm_i915_private *dev_priv = to_i915(dev);
10893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10894 int pipe = intel_crtc->pipe;
10895 u32 base = intel_crtc->cursor_addr;
10899 int x = plane_state->base.crtc_x;
10900 int y = plane_state->base.crtc_y;
10903 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10906 pos |= x << CURSOR_X_SHIFT;
10909 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10912 pos |= y << CURSOR_Y_SHIFT;
10914 /* ILK+ do this automagically */
10915 if (HAS_GMCH_DISPLAY(dev) &&
10916 plane_state->base.rotation == DRM_ROTATE_180) {
10917 base += (plane_state->base.crtc_h *
10918 plane_state->base.crtc_w - 1) * 4;
10922 I915_WRITE(CURPOS(pipe), pos);
10924 if (IS_845G(dev) || IS_I865G(dev))
10925 i845_update_cursor(crtc, base, plane_state);
10927 i9xx_update_cursor(crtc, base, plane_state);
10930 static bool cursor_size_ok(struct drm_device *dev,
10931 uint32_t width, uint32_t height)
10933 if (width == 0 || height == 0)
10937 * 845g/865g are special in that they are only limited by
10938 * the width of their cursors, the height is arbitrary up to
10939 * the precision of the register. Everything else requires
10940 * square cursors, limited to a few power-of-two sizes.
10942 if (IS_845G(dev) || IS_I865G(dev)) {
10943 if ((width & 63) != 0)
10946 if (width > (IS_845G(dev) ? 64 : 512))
10952 switch (width | height) {
10967 /* VESA 640x480x72Hz mode to set on the pipe */
10968 static struct drm_display_mode load_detect_mode = {
10969 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10970 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10973 struct drm_framebuffer *
10974 __intel_framebuffer_create(struct drm_device *dev,
10975 struct drm_mode_fb_cmd2 *mode_cmd,
10976 struct drm_i915_gem_object *obj)
10978 struct intel_framebuffer *intel_fb;
10981 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10983 return ERR_PTR(-ENOMEM);
10985 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10989 return &intel_fb->base;
10993 return ERR_PTR(ret);
10996 static struct drm_framebuffer *
10997 intel_framebuffer_create(struct drm_device *dev,
10998 struct drm_mode_fb_cmd2 *mode_cmd,
10999 struct drm_i915_gem_object *obj)
11001 struct drm_framebuffer *fb;
11004 ret = i915_mutex_lock_interruptible(dev);
11006 return ERR_PTR(ret);
11007 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
11008 mutex_unlock(&dev->struct_mutex);
11014 intel_framebuffer_pitch_for_width(int width, int bpp)
11016 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
11017 return ALIGN(pitch, 64);
11021 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
11023 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
11024 return PAGE_ALIGN(pitch * mode->vdisplay);
11027 static struct drm_framebuffer *
11028 intel_framebuffer_create_for_mode(struct drm_device *dev,
11029 struct drm_display_mode *mode,
11030 int depth, int bpp)
11032 struct drm_framebuffer *fb;
11033 struct drm_i915_gem_object *obj;
11034 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
11036 obj = i915_gem_object_create(dev,
11037 intel_framebuffer_size_for_mode(mode, bpp));
11039 return ERR_CAST(obj);
11041 mode_cmd.width = mode->hdisplay;
11042 mode_cmd.height = mode->vdisplay;
11043 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
11045 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
11047 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
11049 i915_gem_object_put_unlocked(obj);
11054 static struct drm_framebuffer *
11055 mode_fits_in_fbdev(struct drm_device *dev,
11056 struct drm_display_mode *mode)
11058 #ifdef CONFIG_DRM_FBDEV_EMULATION
11059 struct drm_i915_private *dev_priv = to_i915(dev);
11060 struct drm_i915_gem_object *obj;
11061 struct drm_framebuffer *fb;
11063 if (!dev_priv->fbdev)
11066 if (!dev_priv->fbdev->fb)
11069 obj = dev_priv->fbdev->fb->obj;
11072 fb = &dev_priv->fbdev->fb->base;
11073 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
11074 fb->bits_per_pixel))
11077 if (obj->base.size < mode->vdisplay * fb->pitches[0])
11080 drm_framebuffer_reference(fb);
11087 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
11088 struct drm_crtc *crtc,
11089 struct drm_display_mode *mode,
11090 struct drm_framebuffer *fb,
11093 struct drm_plane_state *plane_state;
11094 int hdisplay, vdisplay;
11097 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
11098 if (IS_ERR(plane_state))
11099 return PTR_ERR(plane_state);
11102 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11104 hdisplay = vdisplay = 0;
11106 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
11109 drm_atomic_set_fb_for_plane(plane_state, fb);
11110 plane_state->crtc_x = 0;
11111 plane_state->crtc_y = 0;
11112 plane_state->crtc_w = hdisplay;
11113 plane_state->crtc_h = vdisplay;
11114 plane_state->src_x = x << 16;
11115 plane_state->src_y = y << 16;
11116 plane_state->src_w = hdisplay << 16;
11117 plane_state->src_h = vdisplay << 16;
11122 bool intel_get_load_detect_pipe(struct drm_connector *connector,
11123 struct drm_display_mode *mode,
11124 struct intel_load_detect_pipe *old,
11125 struct drm_modeset_acquire_ctx *ctx)
11127 struct intel_crtc *intel_crtc;
11128 struct intel_encoder *intel_encoder =
11129 intel_attached_encoder(connector);
11130 struct drm_crtc *possible_crtc;
11131 struct drm_encoder *encoder = &intel_encoder->base;
11132 struct drm_crtc *crtc = NULL;
11133 struct drm_device *dev = encoder->dev;
11134 struct drm_framebuffer *fb;
11135 struct drm_mode_config *config = &dev->mode_config;
11136 struct drm_atomic_state *state = NULL, *restore_state = NULL;
11137 struct drm_connector_state *connector_state;
11138 struct intel_crtc_state *crtc_state;
11141 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11142 connector->base.id, connector->name,
11143 encoder->base.id, encoder->name);
11145 old->restore_state = NULL;
11148 ret = drm_modeset_lock(&config->connection_mutex, ctx);
11153 * Algorithm gets a little messy:
11155 * - if the connector already has an assigned crtc, use it (but make
11156 * sure it's on first)
11158 * - try to find the first unused crtc that can drive this connector,
11159 * and use that if we find one
11162 /* See if we already have a CRTC for this connector */
11163 if (connector->state->crtc) {
11164 crtc = connector->state->crtc;
11166 ret = drm_modeset_lock(&crtc->mutex, ctx);
11170 /* Make sure the crtc and connector are running */
11174 /* Find an unused one (if possible) */
11175 for_each_crtc(dev, possible_crtc) {
11177 if (!(encoder->possible_crtcs & (1 << i)))
11180 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
11184 if (possible_crtc->state->enable) {
11185 drm_modeset_unlock(&possible_crtc->mutex);
11189 crtc = possible_crtc;
11194 * If we didn't find an unused CRTC, don't use any.
11197 DRM_DEBUG_KMS("no pipe available for load-detect\n");
11202 intel_crtc = to_intel_crtc(crtc);
11204 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
11208 state = drm_atomic_state_alloc(dev);
11209 restore_state = drm_atomic_state_alloc(dev);
11210 if (!state || !restore_state) {
11215 state->acquire_ctx = ctx;
11216 restore_state->acquire_ctx = ctx;
11218 connector_state = drm_atomic_get_connector_state(state, connector);
11219 if (IS_ERR(connector_state)) {
11220 ret = PTR_ERR(connector_state);
11224 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
11228 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
11229 if (IS_ERR(crtc_state)) {
11230 ret = PTR_ERR(crtc_state);
11234 crtc_state->base.active = crtc_state->base.enable = true;
11237 mode = &load_detect_mode;
11239 /* We need a framebuffer large enough to accommodate all accesses
11240 * that the plane may generate whilst we perform load detection.
11241 * We can not rely on the fbcon either being present (we get called
11242 * during its initialisation to detect all boot displays, or it may
11243 * not even exist) or that it is large enough to satisfy the
11246 fb = mode_fits_in_fbdev(dev, mode);
11248 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
11249 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
11251 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
11253 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
11257 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
11261 drm_framebuffer_unreference(fb);
11263 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
11267 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
11269 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
11271 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
11273 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
11277 ret = drm_atomic_commit(state);
11279 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
11283 old->restore_state = restore_state;
11285 /* let the connector get through one full cycle before testing */
11286 intel_wait_for_vblank(dev, intel_crtc->pipe);
11290 drm_atomic_state_free(state);
11291 drm_atomic_state_free(restore_state);
11292 restore_state = state = NULL;
11294 if (ret == -EDEADLK) {
11295 drm_modeset_backoff(ctx);
11302 void intel_release_load_detect_pipe(struct drm_connector *connector,
11303 struct intel_load_detect_pipe *old,
11304 struct drm_modeset_acquire_ctx *ctx)
11306 struct intel_encoder *intel_encoder =
11307 intel_attached_encoder(connector);
11308 struct drm_encoder *encoder = &intel_encoder->base;
11309 struct drm_atomic_state *state = old->restore_state;
11312 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
11313 connector->base.id, connector->name,
11314 encoder->base.id, encoder->name);
11319 ret = drm_atomic_commit(state);
11321 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
11322 drm_atomic_state_free(state);
11326 static int i9xx_pll_refclk(struct drm_device *dev,
11327 const struct intel_crtc_state *pipe_config)
11329 struct drm_i915_private *dev_priv = to_i915(dev);
11330 u32 dpll = pipe_config->dpll_hw_state.dpll;
11332 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
11333 return dev_priv->vbt.lvds_ssc_freq;
11334 else if (HAS_PCH_SPLIT(dev))
11336 else if (!IS_GEN2(dev))
11342 /* Returns the clock of the currently programmed mode of the given pipe. */
11343 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
11344 struct intel_crtc_state *pipe_config)
11346 struct drm_device *dev = crtc->base.dev;
11347 struct drm_i915_private *dev_priv = to_i915(dev);
11348 int pipe = pipe_config->cpu_transcoder;
11349 u32 dpll = pipe_config->dpll_hw_state.dpll;
11353 int refclk = i9xx_pll_refclk(dev, pipe_config);
11355 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
11356 fp = pipe_config->dpll_hw_state.fp0;
11358 fp = pipe_config->dpll_hw_state.fp1;
11360 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
11361 if (IS_PINEVIEW(dev)) {
11362 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
11363 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
11365 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
11366 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
11369 if (!IS_GEN2(dev)) {
11370 if (IS_PINEVIEW(dev))
11371 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
11372 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
11374 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
11375 DPLL_FPA01_P1_POST_DIV_SHIFT);
11377 switch (dpll & DPLL_MODE_MASK) {
11378 case DPLLB_MODE_DAC_SERIAL:
11379 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
11382 case DPLLB_MODE_LVDS:
11383 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
11387 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
11388 "mode\n", (int)(dpll & DPLL_MODE_MASK));
11392 if (IS_PINEVIEW(dev))
11393 port_clock = pnv_calc_dpll_params(refclk, &clock);
11395 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11397 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
11398 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
11401 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
11402 DPLL_FPA01_P1_POST_DIV_SHIFT);
11404 if (lvds & LVDS_CLKB_POWER_UP)
11409 if (dpll & PLL_P1_DIVIDE_BY_TWO)
11412 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
11413 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
11415 if (dpll & PLL_P2_DIVIDE_BY_4)
11421 port_clock = i9xx_calc_dpll_params(refclk, &clock);
11425 * This value includes pixel_multiplier. We will use
11426 * port_clock to compute adjusted_mode.crtc_clock in the
11427 * encoder's get_config() function.
11429 pipe_config->port_clock = port_clock;
11432 int intel_dotclock_calculate(int link_freq,
11433 const struct intel_link_m_n *m_n)
11436 * The calculation for the data clock is:
11437 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
11438 * But we want to avoid losing precison if possible, so:
11439 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
11441 * and the link clock is simpler:
11442 * link_clock = (m * link_clock) / n
11448 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
11451 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
11452 struct intel_crtc_state *pipe_config)
11454 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
11456 /* read out port_clock from the DPLL */
11457 i9xx_crtc_clock_get(crtc, pipe_config);
11460 * In case there is an active pipe without active ports,
11461 * we may need some idea for the dotclock anyway.
11462 * Calculate one based on the FDI configuration.
11464 pipe_config->base.adjusted_mode.crtc_clock =
11465 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
11466 &pipe_config->fdi_m_n);
11469 /** Returns the currently programmed mode of the given pipe. */
11470 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
11471 struct drm_crtc *crtc)
11473 struct drm_i915_private *dev_priv = to_i915(dev);
11474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11475 enum transcoder cpu_transcoder;
11476 struct drm_display_mode *mode;
11477 struct intel_crtc_state *pipe_config;
11478 u32 htot, hsync, vtot, vsync;
11479 enum pipe pipe = intel_crtc->pipe;
11481 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
11485 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
11486 if (!pipe_config) {
11492 * Construct a pipe_config sufficient for getting the clock info
11493 * back out of crtc_clock_get.
11495 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
11496 * to use a real value here instead.
11498 pipe_config->cpu_transcoder = (enum transcoder) pipe;
11499 pipe_config->pixel_multiplier = 1;
11500 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
11501 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
11502 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
11503 i9xx_crtc_clock_get(intel_crtc, pipe_config);
11505 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
11507 cpu_transcoder = pipe_config->cpu_transcoder;
11508 htot = I915_READ(HTOTAL(cpu_transcoder));
11509 hsync = I915_READ(HSYNC(cpu_transcoder));
11510 vtot = I915_READ(VTOTAL(cpu_transcoder));
11511 vsync = I915_READ(VSYNC(cpu_transcoder));
11513 mode->hdisplay = (htot & 0xffff) + 1;
11514 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
11515 mode->hsync_start = (hsync & 0xffff) + 1;
11516 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
11517 mode->vdisplay = (vtot & 0xffff) + 1;
11518 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
11519 mode->vsync_start = (vsync & 0xffff) + 1;
11520 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
11522 drm_mode_set_name(mode);
11524 kfree(pipe_config);
11529 static void intel_crtc_destroy(struct drm_crtc *crtc)
11531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11532 struct drm_device *dev = crtc->dev;
11533 struct intel_flip_work *work;
11535 spin_lock_irq(&dev->event_lock);
11536 work = intel_crtc->flip_work;
11537 intel_crtc->flip_work = NULL;
11538 spin_unlock_irq(&dev->event_lock);
11541 cancel_work_sync(&work->mmio_work);
11542 cancel_work_sync(&work->unpin_work);
11546 drm_crtc_cleanup(crtc);
11551 static void intel_unpin_work_fn(struct work_struct *__work)
11553 struct intel_flip_work *work =
11554 container_of(__work, struct intel_flip_work, unpin_work);
11555 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
11556 struct drm_device *dev = crtc->base.dev;
11557 struct drm_plane *primary = crtc->base.primary;
11559 if (is_mmio_work(work))
11560 flush_work(&work->mmio_work);
11562 mutex_lock(&dev->struct_mutex);
11563 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
11564 i915_gem_object_put(work->pending_flip_obj);
11565 mutex_unlock(&dev->struct_mutex);
11567 i915_gem_request_put(work->flip_queued_req);
11569 intel_frontbuffer_flip_complete(to_i915(dev),
11570 to_intel_plane(primary)->frontbuffer_bit);
11571 intel_fbc_post_update(crtc);
11572 drm_framebuffer_unreference(work->old_fb);
11574 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
11575 atomic_dec(&crtc->unpin_work_count);
11580 /* Is 'a' after or equal to 'b'? */
11581 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11583 return !((a - b) & 0x80000000);
11586 static bool __pageflip_finished_cs(struct intel_crtc *crtc,
11587 struct intel_flip_work *work)
11589 struct drm_device *dev = crtc->base.dev;
11590 struct drm_i915_private *dev_priv = to_i915(dev);
11592 if (abort_flip_on_reset(crtc))
11596 * The relevant registers doen't exist on pre-ctg.
11597 * As the flip done interrupt doesn't trigger for mmio
11598 * flips on gmch platforms, a flip count check isn't
11599 * really needed there. But since ctg has the registers,
11600 * include it in the check anyway.
11602 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11606 * BDW signals flip done immediately if the plane
11607 * is disabled, even if the plane enable is already
11608 * armed to occur at the next vblank :(
11612 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11613 * used the same base address. In that case the mmio flip might
11614 * have completed, but the CS hasn't even executed the flip yet.
11616 * A flip count check isn't enough as the CS might have updated
11617 * the base address just after start of vblank, but before we
11618 * managed to process the interrupt. This means we'd complete the
11619 * CS flip too soon.
11621 * Combining both checks should get us a good enough result. It may
11622 * still happen that the CS flip has been executed, but has not
11623 * yet actually completed. But in case the base address is the same
11624 * anyway, we don't really care.
11626 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11627 crtc->flip_work->gtt_offset &&
11628 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11629 crtc->flip_work->flip_count);
11633 __pageflip_finished_mmio(struct intel_crtc *crtc,
11634 struct intel_flip_work *work)
11637 * MMIO work completes when vblank is different from
11638 * flip_queued_vblank.
11640 * Reset counter value doesn't matter, this is handled by
11641 * i915_wait_request finishing early, so no need to handle
11644 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
11648 static bool pageflip_finished(struct intel_crtc *crtc,
11649 struct intel_flip_work *work)
11651 if (!atomic_read(&work->pending))
11656 if (is_mmio_work(work))
11657 return __pageflip_finished_mmio(crtc, work);
11659 return __pageflip_finished_cs(crtc, work);
11662 void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
11664 struct drm_device *dev = &dev_priv->drm;
11665 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11667 struct intel_flip_work *work;
11668 unsigned long flags;
11670 /* Ignore early vblank irqs */
11675 * This is called both by irq handlers and the reset code (to complete
11676 * lost pageflips) so needs the full irqsave spinlocks.
11678 spin_lock_irqsave(&dev->event_lock, flags);
11679 work = intel_crtc->flip_work;
11681 if (work != NULL &&
11682 !is_mmio_work(work) &&
11683 pageflip_finished(intel_crtc, work))
11684 page_flip_completed(intel_crtc);
11686 spin_unlock_irqrestore(&dev->event_lock, flags);
11689 void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
11691 struct drm_device *dev = &dev_priv->drm;
11692 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11694 struct intel_flip_work *work;
11695 unsigned long flags;
11697 /* Ignore early vblank irqs */
11702 * This is called both by irq handlers and the reset code (to complete
11703 * lost pageflips) so needs the full irqsave spinlocks.
11705 spin_lock_irqsave(&dev->event_lock, flags);
11706 work = intel_crtc->flip_work;
11708 if (work != NULL &&
11709 is_mmio_work(work) &&
11710 pageflip_finished(intel_crtc, work))
11711 page_flip_completed(intel_crtc);
11713 spin_unlock_irqrestore(&dev->event_lock, flags);
11716 static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
11717 struct intel_flip_work *work)
11719 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
11721 /* Ensure that the work item is consistent when activating it ... */
11722 smp_mb__before_atomic();
11723 atomic_set(&work->pending, 1);
11726 static int intel_gen2_queue_flip(struct drm_device *dev,
11727 struct drm_crtc *crtc,
11728 struct drm_framebuffer *fb,
11729 struct drm_i915_gem_object *obj,
11730 struct drm_i915_gem_request *req,
11733 struct intel_ring *ring = req->ring;
11734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11738 ret = intel_ring_begin(req, 6);
11742 /* Can't queue multiple flips, so wait for the previous
11743 * one to finish before executing the next.
11745 if (intel_crtc->plane)
11746 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11748 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11749 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11750 intel_ring_emit(ring, MI_NOOP);
11751 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11752 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11753 intel_ring_emit(ring, fb->pitches[0]);
11754 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11755 intel_ring_emit(ring, 0); /* aux display base address, unused */
11760 static int intel_gen3_queue_flip(struct drm_device *dev,
11761 struct drm_crtc *crtc,
11762 struct drm_framebuffer *fb,
11763 struct drm_i915_gem_object *obj,
11764 struct drm_i915_gem_request *req,
11767 struct intel_ring *ring = req->ring;
11768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11772 ret = intel_ring_begin(req, 6);
11776 if (intel_crtc->plane)
11777 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11779 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11780 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11781 intel_ring_emit(ring, MI_NOOP);
11782 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11783 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11784 intel_ring_emit(ring, fb->pitches[0]);
11785 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11786 intel_ring_emit(ring, MI_NOOP);
11791 static int intel_gen4_queue_flip(struct drm_device *dev,
11792 struct drm_crtc *crtc,
11793 struct drm_framebuffer *fb,
11794 struct drm_i915_gem_object *obj,
11795 struct drm_i915_gem_request *req,
11798 struct intel_ring *ring = req->ring;
11799 struct drm_i915_private *dev_priv = to_i915(dev);
11800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11801 uint32_t pf, pipesrc;
11804 ret = intel_ring_begin(req, 4);
11808 /* i965+ uses the linear or tiled offsets from the
11809 * Display Registers (which do not change across a page-flip)
11810 * so we need only reprogram the base address.
11812 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11813 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11814 intel_ring_emit(ring, fb->pitches[0]);
11815 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset |
11816 intel_fb_modifier_to_tiling(fb->modifier[0]));
11818 /* XXX Enabling the panel-fitter across page-flip is so far
11819 * untested on non-native modes, so ignore it for now.
11820 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11823 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11824 intel_ring_emit(ring, pf | pipesrc);
11829 static int intel_gen6_queue_flip(struct drm_device *dev,
11830 struct drm_crtc *crtc,
11831 struct drm_framebuffer *fb,
11832 struct drm_i915_gem_object *obj,
11833 struct drm_i915_gem_request *req,
11836 struct intel_ring *ring = req->ring;
11837 struct drm_i915_private *dev_priv = to_i915(dev);
11838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11839 uint32_t pf, pipesrc;
11842 ret = intel_ring_begin(req, 4);
11846 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11847 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11848 intel_ring_emit(ring, fb->pitches[0] |
11849 intel_fb_modifier_to_tiling(fb->modifier[0]));
11850 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11852 /* Contrary to the suggestions in the documentation,
11853 * "Enable Panel Fitter" does not seem to be required when page
11854 * flipping with a non-native mode, and worse causes a normal
11856 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11859 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11860 intel_ring_emit(ring, pf | pipesrc);
11865 static int intel_gen7_queue_flip(struct drm_device *dev,
11866 struct drm_crtc *crtc,
11867 struct drm_framebuffer *fb,
11868 struct drm_i915_gem_object *obj,
11869 struct drm_i915_gem_request *req,
11872 struct intel_ring *ring = req->ring;
11873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11874 uint32_t plane_bit = 0;
11877 switch (intel_crtc->plane) {
11879 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11882 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11885 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11888 WARN_ONCE(1, "unknown plane in flip command\n");
11893 if (req->engine->id == RCS) {
11896 * On Gen 8, SRM is now taking an extra dword to accommodate
11897 * 48bits addresses, and we need a NOOP for the batch size to
11905 * BSpec MI_DISPLAY_FLIP for IVB:
11906 * "The full packet must be contained within the same cache line."
11908 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11909 * cacheline, if we ever start emitting more commands before
11910 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11911 * then do the cacheline alignment, and finally emit the
11914 ret = intel_ring_cacheline_align(req);
11918 ret = intel_ring_begin(req, len);
11922 /* Unmask the flip-done completion message. Note that the bspec says that
11923 * we should do this for both the BCS and RCS, and that we must not unmask
11924 * more than one flip event at any time (or ensure that one flip message
11925 * can be sent by waiting for flip-done prior to queueing new flips).
11926 * Experimentation says that BCS works despite DERRMR masking all
11927 * flip-done completion events and that unmasking all planes at once
11928 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11929 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11931 if (req->engine->id == RCS) {
11932 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11933 intel_ring_emit_reg(ring, DERRMR);
11934 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11935 DERRMR_PIPEB_PRI_FLIP_DONE |
11936 DERRMR_PIPEC_PRI_FLIP_DONE));
11938 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11939 MI_SRM_LRM_GLOBAL_GTT);
11941 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11942 MI_SRM_LRM_GLOBAL_GTT);
11943 intel_ring_emit_reg(ring, DERRMR);
11944 intel_ring_emit(ring,
11945 i915_ggtt_offset(req->engine->scratch) + 256);
11946 if (IS_GEN8(dev)) {
11947 intel_ring_emit(ring, 0);
11948 intel_ring_emit(ring, MI_NOOP);
11952 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11953 intel_ring_emit(ring, fb->pitches[0] |
11954 intel_fb_modifier_to_tiling(fb->modifier[0]));
11955 intel_ring_emit(ring, intel_crtc->flip_work->gtt_offset);
11956 intel_ring_emit(ring, (MI_NOOP));
11961 static bool use_mmio_flip(struct intel_engine_cs *engine,
11962 struct drm_i915_gem_object *obj)
11964 struct reservation_object *resv;
11967 * This is not being used for older platforms, because
11968 * non-availability of flip done interrupt forces us to use
11969 * CS flips. Older platforms derive flip done using some clever
11970 * tricks involving the flip_pending status bits and vblank irqs.
11971 * So using MMIO flips there would disrupt this mechanism.
11974 if (engine == NULL)
11977 if (INTEL_GEN(engine->i915) < 5)
11980 if (i915.use_mmio_flip < 0)
11982 else if (i915.use_mmio_flip > 0)
11984 else if (i915.enable_execlists)
11987 resv = i915_gem_object_get_dmabuf_resv(obj);
11988 if (resv && !reservation_object_test_signaled_rcu(resv, false))
11991 return engine != i915_gem_active_get_engine(&obj->last_write,
11992 &obj->base.dev->struct_mutex);
11995 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11996 unsigned int rotation,
11997 struct intel_flip_work *work)
11999 struct drm_device *dev = intel_crtc->base.dev;
12000 struct drm_i915_private *dev_priv = to_i915(dev);
12001 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12002 const enum pipe pipe = intel_crtc->pipe;
12003 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
12005 ctl = I915_READ(PLANE_CTL(pipe, 0));
12006 ctl &= ~PLANE_CTL_TILED_MASK;
12007 switch (fb->modifier[0]) {
12008 case DRM_FORMAT_MOD_NONE:
12010 case I915_FORMAT_MOD_X_TILED:
12011 ctl |= PLANE_CTL_TILED_X;
12013 case I915_FORMAT_MOD_Y_TILED:
12014 ctl |= PLANE_CTL_TILED_Y;
12016 case I915_FORMAT_MOD_Yf_TILED:
12017 ctl |= PLANE_CTL_TILED_YF;
12020 MISSING_CASE(fb->modifier[0]);
12024 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
12025 * PLANE_SURF updates, the update is then guaranteed to be atomic.
12027 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
12028 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
12030 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
12031 POSTING_READ(PLANE_SURF(pipe, 0));
12034 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
12035 struct intel_flip_work *work)
12037 struct drm_device *dev = intel_crtc->base.dev;
12038 struct drm_i915_private *dev_priv = to_i915(dev);
12039 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
12040 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
12043 dspcntr = I915_READ(reg);
12045 if (fb->modifier[0] == I915_FORMAT_MOD_X_TILED)
12046 dspcntr |= DISPPLANE_TILED;
12048 dspcntr &= ~DISPPLANE_TILED;
12050 I915_WRITE(reg, dspcntr);
12052 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
12053 POSTING_READ(DSPSURF(intel_crtc->plane));
12056 static void intel_mmio_flip_work_func(struct work_struct *w)
12058 struct intel_flip_work *work =
12059 container_of(w, struct intel_flip_work, mmio_work);
12060 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
12061 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
12062 struct intel_framebuffer *intel_fb =
12063 to_intel_framebuffer(crtc->base.primary->fb);
12064 struct drm_i915_gem_object *obj = intel_fb->obj;
12065 struct reservation_object *resv;
12067 if (work->flip_queued_req)
12068 WARN_ON(i915_wait_request(work->flip_queued_req,
12069 0, NULL, NO_WAITBOOST));
12071 /* For framebuffer backed by dmabuf, wait for fence */
12072 resv = i915_gem_object_get_dmabuf_resv(obj);
12074 WARN_ON(reservation_object_wait_timeout_rcu(resv, false, false,
12075 MAX_SCHEDULE_TIMEOUT) < 0);
12077 intel_pipe_update_start(crtc);
12079 if (INTEL_GEN(dev_priv) >= 9)
12080 skl_do_mmio_flip(crtc, work->rotation, work);
12082 /* use_mmio_flip() retricts MMIO flips to ilk+ */
12083 ilk_do_mmio_flip(crtc, work);
12085 intel_pipe_update_end(crtc, work);
12088 static int intel_default_queue_flip(struct drm_device *dev,
12089 struct drm_crtc *crtc,
12090 struct drm_framebuffer *fb,
12091 struct drm_i915_gem_object *obj,
12092 struct drm_i915_gem_request *req,
12098 static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
12099 struct intel_crtc *intel_crtc,
12100 struct intel_flip_work *work)
12104 if (!atomic_read(&work->pending))
12109 vblank = intel_crtc_get_vblank_counter(intel_crtc);
12110 if (work->flip_ready_vblank == 0) {
12111 if (work->flip_queued_req &&
12112 !i915_gem_request_completed(work->flip_queued_req))
12115 work->flip_ready_vblank = vblank;
12118 if (vblank - work->flip_ready_vblank < 3)
12121 /* Potential stall - if we see that the flip has happened,
12122 * assume a missed interrupt. */
12123 if (INTEL_GEN(dev_priv) >= 4)
12124 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
12126 addr = I915_READ(DSPADDR(intel_crtc->plane));
12128 /* There is a potential issue here with a false positive after a flip
12129 * to the same address. We could address this by checking for a
12130 * non-incrementing frame counter.
12132 return addr == work->gtt_offset;
12135 void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
12137 struct drm_device *dev = &dev_priv->drm;
12138 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
12139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12140 struct intel_flip_work *work;
12142 WARN_ON(!in_interrupt());
12147 spin_lock(&dev->event_lock);
12148 work = intel_crtc->flip_work;
12150 if (work != NULL && !is_mmio_work(work) &&
12151 __pageflip_stall_check_cs(dev_priv, intel_crtc, work)) {
12153 "Kicking stuck page flip: queued at %d, now %d\n",
12154 work->flip_queued_vblank, intel_crtc_get_vblank_counter(intel_crtc));
12155 page_flip_completed(intel_crtc);
12159 if (work != NULL && !is_mmio_work(work) &&
12160 intel_crtc_get_vblank_counter(intel_crtc) - work->flip_queued_vblank > 1)
12161 intel_queue_rps_boost_for_request(work->flip_queued_req);
12162 spin_unlock(&dev->event_lock);
12165 static int intel_crtc_page_flip(struct drm_crtc *crtc,
12166 struct drm_framebuffer *fb,
12167 struct drm_pending_vblank_event *event,
12168 uint32_t page_flip_flags)
12170 struct drm_device *dev = crtc->dev;
12171 struct drm_i915_private *dev_priv = to_i915(dev);
12172 struct drm_framebuffer *old_fb = crtc->primary->fb;
12173 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12175 struct drm_plane *primary = crtc->primary;
12176 enum pipe pipe = intel_crtc->pipe;
12177 struct intel_flip_work *work;
12178 struct intel_engine_cs *engine;
12180 struct drm_i915_gem_request *request;
12181 struct i915_vma *vma;
12185 * drm_mode_page_flip_ioctl() should already catch this, but double
12186 * check to be safe. In the future we may enable pageflipping from
12187 * a disabled primary plane.
12189 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
12192 /* Can't change pixel format via MI display flips. */
12193 if (fb->pixel_format != crtc->primary->fb->pixel_format)
12197 * TILEOFF/LINOFF registers can't be changed via MI display flips.
12198 * Note that pitch changes could also affect these register.
12200 if (INTEL_INFO(dev)->gen > 3 &&
12201 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
12202 fb->pitches[0] != crtc->primary->fb->pitches[0]))
12205 if (i915_terminally_wedged(&dev_priv->gpu_error))
12208 work = kzalloc(sizeof(*work), GFP_KERNEL);
12212 work->event = event;
12214 work->old_fb = old_fb;
12215 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
12217 ret = drm_crtc_vblank_get(crtc);
12221 /* We borrow the event spin lock for protecting flip_work */
12222 spin_lock_irq(&dev->event_lock);
12223 if (intel_crtc->flip_work) {
12224 /* Before declaring the flip queue wedged, check if
12225 * the hardware completed the operation behind our backs.
12227 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
12228 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
12229 page_flip_completed(intel_crtc);
12231 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
12232 spin_unlock_irq(&dev->event_lock);
12234 drm_crtc_vblank_put(crtc);
12239 intel_crtc->flip_work = work;
12240 spin_unlock_irq(&dev->event_lock);
12242 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
12243 flush_workqueue(dev_priv->wq);
12245 /* Reference the objects for the scheduled work. */
12246 drm_framebuffer_reference(work->old_fb);
12248 crtc->primary->fb = fb;
12249 update_state_fb(crtc->primary);
12251 work->pending_flip_obj = i915_gem_object_get(obj);
12253 ret = i915_mutex_lock_interruptible(dev);
12257 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
12258 if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) {
12263 atomic_inc(&intel_crtc->unpin_work_count);
12265 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
12266 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
12268 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
12269 engine = &dev_priv->engine[BCS];
12270 if (fb->modifier[0] != old_fb->modifier[0])
12271 /* vlv: DISPLAY_FLIP fails to change tiling */
12273 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
12274 engine = &dev_priv->engine[BCS];
12275 } else if (INTEL_INFO(dev)->gen >= 7) {
12276 engine = i915_gem_active_get_engine(&obj->last_write,
12277 &obj->base.dev->struct_mutex);
12278 if (engine == NULL || engine->id != RCS)
12279 engine = &dev_priv->engine[BCS];
12281 engine = &dev_priv->engine[RCS];
12284 mmio_flip = use_mmio_flip(engine, obj);
12286 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
12288 ret = PTR_ERR(vma);
12289 goto cleanup_pending;
12292 work->gtt_offset = intel_fb_gtt_offset(fb, primary->state->rotation);
12293 work->gtt_offset += intel_crtc->dspaddr_offset;
12294 work->rotation = crtc->primary->state->rotation;
12297 * There's the potential that the next frame will not be compatible with
12298 * FBC, so we want to call pre_update() before the actual page flip.
12299 * The problem is that pre_update() caches some information about the fb
12300 * object, so we want to do this only after the object is pinned. Let's
12301 * be on the safe side and do this immediately before scheduling the
12304 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
12305 to_intel_plane_state(primary->state));
12308 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
12310 work->flip_queued_req = i915_gem_active_get(&obj->last_write,
12311 &obj->base.dev->struct_mutex);
12312 schedule_work(&work->mmio_work);
12314 request = i915_gem_request_alloc(engine, engine->last_context);
12315 if (IS_ERR(request)) {
12316 ret = PTR_ERR(request);
12317 goto cleanup_unpin;
12320 ret = i915_gem_request_await_object(request, obj, false);
12322 goto cleanup_request;
12324 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
12327 goto cleanup_request;
12329 intel_mark_page_flip_active(intel_crtc, work);
12331 work->flip_queued_req = i915_gem_request_get(request);
12332 i915_add_request_no_flush(request);
12335 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
12336 to_intel_plane(primary)->frontbuffer_bit);
12337 mutex_unlock(&dev->struct_mutex);
12339 intel_frontbuffer_flip_prepare(to_i915(dev),
12340 to_intel_plane(primary)->frontbuffer_bit);
12342 trace_i915_flip_request(intel_crtc->plane, obj);
12347 i915_add_request_no_flush(request);
12349 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
12351 atomic_dec(&intel_crtc->unpin_work_count);
12353 mutex_unlock(&dev->struct_mutex);
12355 crtc->primary->fb = old_fb;
12356 update_state_fb(crtc->primary);
12358 i915_gem_object_put_unlocked(obj);
12359 drm_framebuffer_unreference(work->old_fb);
12361 spin_lock_irq(&dev->event_lock);
12362 intel_crtc->flip_work = NULL;
12363 spin_unlock_irq(&dev->event_lock);
12365 drm_crtc_vblank_put(crtc);
12370 struct drm_atomic_state *state;
12371 struct drm_plane_state *plane_state;
12374 state = drm_atomic_state_alloc(dev);
12377 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
12380 plane_state = drm_atomic_get_plane_state(state, primary);
12381 ret = PTR_ERR_OR_ZERO(plane_state);
12383 drm_atomic_set_fb_for_plane(plane_state, fb);
12385 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
12387 ret = drm_atomic_commit(state);
12390 if (ret == -EDEADLK) {
12391 drm_modeset_backoff(state->acquire_ctx);
12392 drm_atomic_state_clear(state);
12397 drm_atomic_state_free(state);
12399 if (ret == 0 && event) {
12400 spin_lock_irq(&dev->event_lock);
12401 drm_crtc_send_vblank_event(crtc, event);
12402 spin_unlock_irq(&dev->event_lock);
12410 * intel_wm_need_update - Check whether watermarks need updating
12411 * @plane: drm plane
12412 * @state: new plane state
12414 * Check current plane state versus the new one to determine whether
12415 * watermarks need to be recalculated.
12417 * Returns true or false.
12419 static bool intel_wm_need_update(struct drm_plane *plane,
12420 struct drm_plane_state *state)
12422 struct intel_plane_state *new = to_intel_plane_state(state);
12423 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
12425 /* Update watermarks on tiling or size changes. */
12426 if (new->base.visible != cur->base.visible)
12429 if (!cur->base.fb || !new->base.fb)
12432 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
12433 cur->base.rotation != new->base.rotation ||
12434 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
12435 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
12436 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
12437 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
12443 static bool needs_scaling(struct intel_plane_state *state)
12445 int src_w = drm_rect_width(&state->base.src) >> 16;
12446 int src_h = drm_rect_height(&state->base.src) >> 16;
12447 int dst_w = drm_rect_width(&state->base.dst);
12448 int dst_h = drm_rect_height(&state->base.dst);
12450 return (src_w != dst_w || src_h != dst_h);
12453 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
12454 struct drm_plane_state *plane_state)
12456 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
12457 struct drm_crtc *crtc = crtc_state->crtc;
12458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12459 struct drm_plane *plane = plane_state->plane;
12460 struct drm_device *dev = crtc->dev;
12461 struct drm_i915_private *dev_priv = to_i915(dev);
12462 struct intel_plane_state *old_plane_state =
12463 to_intel_plane_state(plane->state);
12464 bool mode_changed = needs_modeset(crtc_state);
12465 bool was_crtc_enabled = crtc->state->active;
12466 bool is_crtc_enabled = crtc_state->active;
12467 bool turn_off, turn_on, visible, was_visible;
12468 struct drm_framebuffer *fb = plane_state->fb;
12471 if (INTEL_GEN(dev) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) {
12472 ret = skl_update_scaler_plane(
12473 to_intel_crtc_state(crtc_state),
12474 to_intel_plane_state(plane_state));
12479 was_visible = old_plane_state->base.visible;
12480 visible = to_intel_plane_state(plane_state)->base.visible;
12482 if (!was_crtc_enabled && WARN_ON(was_visible))
12483 was_visible = false;
12486 * Visibility is calculated as if the crtc was on, but
12487 * after scaler setup everything depends on it being off
12488 * when the crtc isn't active.
12490 * FIXME this is wrong for watermarks. Watermarks should also
12491 * be computed as if the pipe would be active. Perhaps move
12492 * per-plane wm computation to the .check_plane() hook, and
12493 * only combine the results from all planes in the current place?
12495 if (!is_crtc_enabled)
12496 to_intel_plane_state(plane_state)->base.visible = visible = false;
12498 if (!was_visible && !visible)
12501 if (fb != old_plane_state->base.fb)
12502 pipe_config->fb_changed = true;
12504 turn_off = was_visible && (!visible || mode_changed);
12505 turn_on = visible && (!was_visible || mode_changed);
12507 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
12508 intel_crtc->base.base.id,
12509 intel_crtc->base.name,
12510 plane->base.id, plane->name,
12511 fb ? fb->base.id : -1);
12513 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
12514 plane->base.id, plane->name,
12515 was_visible, visible,
12516 turn_off, turn_on, mode_changed);
12519 pipe_config->update_wm_pre = true;
12521 /* must disable cxsr around plane enable/disable */
12522 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12523 pipe_config->disable_cxsr = true;
12524 } else if (turn_off) {
12525 pipe_config->update_wm_post = true;
12527 /* must disable cxsr around plane enable/disable */
12528 if (plane->type != DRM_PLANE_TYPE_CURSOR)
12529 pipe_config->disable_cxsr = true;
12530 } else if (intel_wm_need_update(plane, plane_state)) {
12531 /* FIXME bollocks */
12532 pipe_config->update_wm_pre = true;
12533 pipe_config->update_wm_post = true;
12536 /* Pre-gen9 platforms need two-step watermark updates */
12537 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
12538 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
12539 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
12541 if (visible || was_visible)
12542 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
12545 * WaCxSRDisabledForSpriteScaling:ivb
12547 * cstate->update_wm was already set above, so this flag will
12548 * take effect when we commit and program watermarks.
12550 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
12551 needs_scaling(to_intel_plane_state(plane_state)) &&
12552 !needs_scaling(old_plane_state))
12553 pipe_config->disable_lp_wm = true;
12558 static bool encoders_cloneable(const struct intel_encoder *a,
12559 const struct intel_encoder *b)
12561 /* masks could be asymmetric, so check both ways */
12562 return a == b || (a->cloneable & (1 << b->type) &&
12563 b->cloneable & (1 << a->type));
12566 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12567 struct intel_crtc *crtc,
12568 struct intel_encoder *encoder)
12570 struct intel_encoder *source_encoder;
12571 struct drm_connector *connector;
12572 struct drm_connector_state *connector_state;
12575 for_each_connector_in_state(state, connector, connector_state, i) {
12576 if (connector_state->crtc != &crtc->base)
12580 to_intel_encoder(connector_state->best_encoder);
12581 if (!encoders_cloneable(encoder, source_encoder))
12588 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12589 struct drm_crtc_state *crtc_state)
12591 struct drm_device *dev = crtc->dev;
12592 struct drm_i915_private *dev_priv = to_i915(dev);
12593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12594 struct intel_crtc_state *pipe_config =
12595 to_intel_crtc_state(crtc_state);
12596 struct drm_atomic_state *state = crtc_state->state;
12598 bool mode_changed = needs_modeset(crtc_state);
12600 if (mode_changed && !crtc_state->active)
12601 pipe_config->update_wm_post = true;
12603 if (mode_changed && crtc_state->enable &&
12604 dev_priv->display.crtc_compute_clock &&
12605 !WARN_ON(pipe_config->shared_dpll)) {
12606 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12612 if (crtc_state->color_mgmt_changed) {
12613 ret = intel_color_check(crtc, crtc_state);
12618 * Changing color management on Intel hardware is
12619 * handled as part of planes update.
12621 crtc_state->planes_changed = true;
12625 if (dev_priv->display.compute_pipe_wm) {
12626 ret = dev_priv->display.compute_pipe_wm(pipe_config);
12628 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12633 if (dev_priv->display.compute_intermediate_wm &&
12634 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12635 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12639 * Calculate 'intermediate' watermarks that satisfy both the
12640 * old state and the new state. We can program these
12643 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12647 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12650 } else if (dev_priv->display.compute_intermediate_wm) {
12651 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
12652 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
12655 if (INTEL_INFO(dev)->gen >= 9) {
12657 ret = skl_update_scaler_crtc(pipe_config);
12660 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12667 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12668 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12669 .atomic_begin = intel_begin_crtc_commit,
12670 .atomic_flush = intel_finish_crtc_commit,
12671 .atomic_check = intel_crtc_atomic_check,
12674 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12676 struct intel_connector *connector;
12678 for_each_intel_connector(dev, connector) {
12679 if (connector->base.state->crtc)
12680 drm_connector_unreference(&connector->base);
12682 if (connector->base.encoder) {
12683 connector->base.state->best_encoder =
12684 connector->base.encoder;
12685 connector->base.state->crtc =
12686 connector->base.encoder->crtc;
12688 drm_connector_reference(&connector->base);
12690 connector->base.state->best_encoder = NULL;
12691 connector->base.state->crtc = NULL;
12697 connected_sink_compute_bpp(struct intel_connector *connector,
12698 struct intel_crtc_state *pipe_config)
12700 const struct drm_display_info *info = &connector->base.display_info;
12701 int bpp = pipe_config->pipe_bpp;
12703 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12704 connector->base.base.id,
12705 connector->base.name);
12707 /* Don't use an invalid EDID bpc value */
12708 if (info->bpc != 0 && info->bpc * 3 < bpp) {
12709 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12710 bpp, info->bpc * 3);
12711 pipe_config->pipe_bpp = info->bpc * 3;
12714 /* Clamp bpp to 8 on screens without EDID 1.4 */
12715 if (info->bpc == 0 && bpp > 24) {
12716 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12718 pipe_config->pipe_bpp = 24;
12723 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12724 struct intel_crtc_state *pipe_config)
12726 struct drm_device *dev = crtc->base.dev;
12727 struct drm_atomic_state *state;
12728 struct drm_connector *connector;
12729 struct drm_connector_state *connector_state;
12732 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12734 else if (INTEL_INFO(dev)->gen >= 5)
12740 pipe_config->pipe_bpp = bpp;
12742 state = pipe_config->base.state;
12744 /* Clamp display bpp to EDID value */
12745 for_each_connector_in_state(state, connector, connector_state, i) {
12746 if (connector_state->crtc != &crtc->base)
12749 connected_sink_compute_bpp(to_intel_connector(connector),
12756 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12758 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12759 "type: 0x%x flags: 0x%x\n",
12761 mode->crtc_hdisplay, mode->crtc_hsync_start,
12762 mode->crtc_hsync_end, mode->crtc_htotal,
12763 mode->crtc_vdisplay, mode->crtc_vsync_start,
12764 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12767 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12768 struct intel_crtc_state *pipe_config,
12769 const char *context)
12771 struct drm_device *dev = crtc->base.dev;
12772 struct drm_plane *plane;
12773 struct intel_plane *intel_plane;
12774 struct intel_plane_state *state;
12775 struct drm_framebuffer *fb;
12777 DRM_DEBUG_KMS("[CRTC:%d:%s]%s config %p for pipe %c\n",
12778 crtc->base.base.id, crtc->base.name,
12779 context, pipe_config, pipe_name(crtc->pipe));
12781 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12782 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12783 pipe_config->pipe_bpp, pipe_config->dither);
12784 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12785 pipe_config->has_pch_encoder,
12786 pipe_config->fdi_lanes,
12787 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12788 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12789 pipe_config->fdi_m_n.tu);
12790 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12791 intel_crtc_has_dp_encoder(pipe_config),
12792 pipe_config->lane_count,
12793 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12794 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12795 pipe_config->dp_m_n.tu);
12797 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12798 intel_crtc_has_dp_encoder(pipe_config),
12799 pipe_config->lane_count,
12800 pipe_config->dp_m2_n2.gmch_m,
12801 pipe_config->dp_m2_n2.gmch_n,
12802 pipe_config->dp_m2_n2.link_m,
12803 pipe_config->dp_m2_n2.link_n,
12804 pipe_config->dp_m2_n2.tu);
12806 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12807 pipe_config->has_audio,
12808 pipe_config->has_infoframe);
12810 DRM_DEBUG_KMS("requested mode:\n");
12811 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12812 DRM_DEBUG_KMS("adjusted mode:\n");
12813 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12814 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12815 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12816 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12817 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12818 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12820 pipe_config->scaler_state.scaler_users,
12821 pipe_config->scaler_state.scaler_id);
12822 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12823 pipe_config->gmch_pfit.control,
12824 pipe_config->gmch_pfit.pgm_ratios,
12825 pipe_config->gmch_pfit.lvds_border_bits);
12826 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12827 pipe_config->pch_pfit.pos,
12828 pipe_config->pch_pfit.size,
12829 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12830 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12831 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12833 if (IS_BROXTON(dev)) {
12834 DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12835 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12836 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12837 pipe_config->dpll_hw_state.ebb0,
12838 pipe_config->dpll_hw_state.ebb4,
12839 pipe_config->dpll_hw_state.pll0,
12840 pipe_config->dpll_hw_state.pll1,
12841 pipe_config->dpll_hw_state.pll2,
12842 pipe_config->dpll_hw_state.pll3,
12843 pipe_config->dpll_hw_state.pll6,
12844 pipe_config->dpll_hw_state.pll8,
12845 pipe_config->dpll_hw_state.pll9,
12846 pipe_config->dpll_hw_state.pll10,
12847 pipe_config->dpll_hw_state.pcsdw12);
12848 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12849 DRM_DEBUG_KMS("dpll_hw_state: "
12850 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12851 pipe_config->dpll_hw_state.ctrl1,
12852 pipe_config->dpll_hw_state.cfgcr1,
12853 pipe_config->dpll_hw_state.cfgcr2);
12854 } else if (HAS_DDI(dev)) {
12855 DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12856 pipe_config->dpll_hw_state.wrpll,
12857 pipe_config->dpll_hw_state.spll);
12859 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12860 "fp0: 0x%x, fp1: 0x%x\n",
12861 pipe_config->dpll_hw_state.dpll,
12862 pipe_config->dpll_hw_state.dpll_md,
12863 pipe_config->dpll_hw_state.fp0,
12864 pipe_config->dpll_hw_state.fp1);
12867 DRM_DEBUG_KMS("planes on this crtc\n");
12868 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12870 intel_plane = to_intel_plane(plane);
12871 if (intel_plane->pipe != crtc->pipe)
12874 state = to_intel_plane_state(plane->state);
12875 fb = state->base.fb;
12877 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
12878 plane->base.id, plane->name, state->scaler_id);
12882 format_name = drm_get_format_name(fb->pixel_format);
12884 DRM_DEBUG_KMS("[PLANE:%d:%s] enabled",
12885 plane->base.id, plane->name);
12886 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = %s",
12887 fb->base.id, fb->width, fb->height, format_name);
12888 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
12890 state->base.src.x1 >> 16,
12891 state->base.src.y1 >> 16,
12892 drm_rect_width(&state->base.src) >> 16,
12893 drm_rect_height(&state->base.src) >> 16,
12894 state->base.dst.x1, state->base.dst.y1,
12895 drm_rect_width(&state->base.dst),
12896 drm_rect_height(&state->base.dst));
12898 kfree(format_name);
12902 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12904 struct drm_device *dev = state->dev;
12905 struct drm_connector *connector;
12906 unsigned int used_ports = 0;
12907 unsigned int used_mst_ports = 0;
12910 * Walk the connector list instead of the encoder
12911 * list to detect the problem on ddi platforms
12912 * where there's just one encoder per digital port.
12914 drm_for_each_connector(connector, dev) {
12915 struct drm_connector_state *connector_state;
12916 struct intel_encoder *encoder;
12918 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12919 if (!connector_state)
12920 connector_state = connector->state;
12922 if (!connector_state->best_encoder)
12925 encoder = to_intel_encoder(connector_state->best_encoder);
12927 WARN_ON(!connector_state->crtc);
12929 switch (encoder->type) {
12930 unsigned int port_mask;
12931 case INTEL_OUTPUT_UNKNOWN:
12932 if (WARN_ON(!HAS_DDI(dev)))
12934 case INTEL_OUTPUT_DP:
12935 case INTEL_OUTPUT_HDMI:
12936 case INTEL_OUTPUT_EDP:
12937 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12939 /* the same port mustn't appear more than once */
12940 if (used_ports & port_mask)
12943 used_ports |= port_mask;
12945 case INTEL_OUTPUT_DP_MST:
12947 1 << enc_to_mst(&encoder->base)->primary->port;
12954 /* can't mix MST and SST/HDMI on the same port */
12955 if (used_ports & used_mst_ports)
12962 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12964 struct drm_crtc_state tmp_state;
12965 struct intel_crtc_scaler_state scaler_state;
12966 struct intel_dpll_hw_state dpll_hw_state;
12967 struct intel_shared_dpll *shared_dpll;
12970 /* FIXME: before the switch to atomic started, a new pipe_config was
12971 * kzalloc'd. Code that depends on any field being zero should be
12972 * fixed, so that the crtc_state can be safely duplicated. For now,
12973 * only fields that are know to not cause problems are preserved. */
12975 tmp_state = crtc_state->base;
12976 scaler_state = crtc_state->scaler_state;
12977 shared_dpll = crtc_state->shared_dpll;
12978 dpll_hw_state = crtc_state->dpll_hw_state;
12979 force_thru = crtc_state->pch_pfit.force_thru;
12981 memset(crtc_state, 0, sizeof *crtc_state);
12983 crtc_state->base = tmp_state;
12984 crtc_state->scaler_state = scaler_state;
12985 crtc_state->shared_dpll = shared_dpll;
12986 crtc_state->dpll_hw_state = dpll_hw_state;
12987 crtc_state->pch_pfit.force_thru = force_thru;
12991 intel_modeset_pipe_config(struct drm_crtc *crtc,
12992 struct intel_crtc_state *pipe_config)
12994 struct drm_atomic_state *state = pipe_config->base.state;
12995 struct intel_encoder *encoder;
12996 struct drm_connector *connector;
12997 struct drm_connector_state *connector_state;
12998 int base_bpp, ret = -EINVAL;
13002 clear_intel_crtc_state(pipe_config);
13004 pipe_config->cpu_transcoder =
13005 (enum transcoder) to_intel_crtc(crtc)->pipe;
13008 * Sanitize sync polarity flags based on requested ones. If neither
13009 * positive or negative polarity is requested, treat this as meaning
13010 * negative polarity.
13012 if (!(pipe_config->base.adjusted_mode.flags &
13013 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
13014 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
13016 if (!(pipe_config->base.adjusted_mode.flags &
13017 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
13018 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
13020 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
13026 * Determine the real pipe dimensions. Note that stereo modes can
13027 * increase the actual pipe size due to the frame doubling and
13028 * insertion of additional space for blanks between the frame. This
13029 * is stored in the crtc timings. We use the requested mode to do this
13030 * computation to clearly distinguish it from the adjusted mode, which
13031 * can be changed by the connectors in the below retry loop.
13033 drm_crtc_get_hv_timing(&pipe_config->base.mode,
13034 &pipe_config->pipe_src_w,
13035 &pipe_config->pipe_src_h);
13037 for_each_connector_in_state(state, connector, connector_state, i) {
13038 if (connector_state->crtc != crtc)
13041 encoder = to_intel_encoder(connector_state->best_encoder);
13043 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
13044 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
13049 * Determine output_types before calling the .compute_config()
13050 * hooks so that the hooks can use this information safely.
13052 pipe_config->output_types |= 1 << encoder->type;
13056 /* Ensure the port clock defaults are reset when retrying. */
13057 pipe_config->port_clock = 0;
13058 pipe_config->pixel_multiplier = 1;
13060 /* Fill in default crtc timings, allow encoders to overwrite them. */
13061 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
13062 CRTC_STEREO_DOUBLE);
13064 /* Pass our mode to the connectors and the CRTC to give them a chance to
13065 * adjust it according to limitations or connector properties, and also
13066 * a chance to reject the mode entirely.
13068 for_each_connector_in_state(state, connector, connector_state, i) {
13069 if (connector_state->crtc != crtc)
13072 encoder = to_intel_encoder(connector_state->best_encoder);
13074 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
13075 DRM_DEBUG_KMS("Encoder config failure\n");
13080 /* Set default port clock if not overwritten by the encoder. Needs to be
13081 * done afterwards in case the encoder adjusts the mode. */
13082 if (!pipe_config->port_clock)
13083 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
13084 * pipe_config->pixel_multiplier;
13086 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
13088 DRM_DEBUG_KMS("CRTC fixup failed\n");
13092 if (ret == RETRY) {
13093 if (WARN(!retry, "loop in pipe configuration computation\n")) {
13098 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
13100 goto encoder_retry;
13103 /* Dithering seems to not pass-through bits correctly when it should, so
13104 * only enable it on 6bpc panels. */
13105 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
13106 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
13107 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
13114 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
13116 struct drm_crtc *crtc;
13117 struct drm_crtc_state *crtc_state;
13120 /* Double check state. */
13121 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13122 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
13124 /* Update hwmode for vblank functions */
13125 if (crtc->state->active)
13126 crtc->hwmode = crtc->state->adjusted_mode;
13128 crtc->hwmode.crtc_clock = 0;
13131 * Update legacy state to satisfy fbc code. This can
13132 * be removed when fbc uses the atomic state.
13134 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
13135 struct drm_plane_state *plane_state = crtc->primary->state;
13137 crtc->primary->fb = plane_state->fb;
13138 crtc->x = plane_state->src_x >> 16;
13139 crtc->y = plane_state->src_y >> 16;
13144 static bool intel_fuzzy_clock_check(int clock1, int clock2)
13148 if (clock1 == clock2)
13151 if (!clock1 || !clock2)
13154 diff = abs(clock1 - clock2);
13156 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
13163 intel_compare_m_n(unsigned int m, unsigned int n,
13164 unsigned int m2, unsigned int n2,
13167 if (m == m2 && n == n2)
13170 if (exact || !m || !n || !m2 || !n2)
13173 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
13180 } else if (n < n2) {
13190 return intel_fuzzy_clock_check(m, m2);
13194 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
13195 struct intel_link_m_n *m2_n2,
13198 if (m_n->tu == m2_n2->tu &&
13199 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
13200 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
13201 intel_compare_m_n(m_n->link_m, m_n->link_n,
13202 m2_n2->link_m, m2_n2->link_n, !adjust)) {
13213 intel_pipe_config_compare(struct drm_device *dev,
13214 struct intel_crtc_state *current_config,
13215 struct intel_crtc_state *pipe_config,
13220 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
13223 DRM_ERROR(fmt, ##__VA_ARGS__); \
13225 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
13228 #define PIPE_CONF_CHECK_X(name) \
13229 if (current_config->name != pipe_config->name) { \
13230 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13231 "(expected 0x%08x, found 0x%08x)\n", \
13232 current_config->name, \
13233 pipe_config->name); \
13237 #define PIPE_CONF_CHECK_I(name) \
13238 if (current_config->name != pipe_config->name) { \
13239 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13240 "(expected %i, found %i)\n", \
13241 current_config->name, \
13242 pipe_config->name); \
13246 #define PIPE_CONF_CHECK_P(name) \
13247 if (current_config->name != pipe_config->name) { \
13248 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13249 "(expected %p, found %p)\n", \
13250 current_config->name, \
13251 pipe_config->name); \
13255 #define PIPE_CONF_CHECK_M_N(name) \
13256 if (!intel_compare_link_m_n(¤t_config->name, \
13257 &pipe_config->name,\
13259 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13260 "(expected tu %i gmch %i/%i link %i/%i, " \
13261 "found tu %i, gmch %i/%i link %i/%i)\n", \
13262 current_config->name.tu, \
13263 current_config->name.gmch_m, \
13264 current_config->name.gmch_n, \
13265 current_config->name.link_m, \
13266 current_config->name.link_n, \
13267 pipe_config->name.tu, \
13268 pipe_config->name.gmch_m, \
13269 pipe_config->name.gmch_n, \
13270 pipe_config->name.link_m, \
13271 pipe_config->name.link_n); \
13275 /* This is required for BDW+ where there is only one set of registers for
13276 * switching between high and low RR.
13277 * This macro can be used whenever a comparison has to be made between one
13278 * hw state and multiple sw state variables.
13280 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
13281 if (!intel_compare_link_m_n(¤t_config->name, \
13282 &pipe_config->name, adjust) && \
13283 !intel_compare_link_m_n(¤t_config->alt_name, \
13284 &pipe_config->name, adjust)) { \
13285 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13286 "(expected tu %i gmch %i/%i link %i/%i, " \
13287 "or tu %i gmch %i/%i link %i/%i, " \
13288 "found tu %i, gmch %i/%i link %i/%i)\n", \
13289 current_config->name.tu, \
13290 current_config->name.gmch_m, \
13291 current_config->name.gmch_n, \
13292 current_config->name.link_m, \
13293 current_config->name.link_n, \
13294 current_config->alt_name.tu, \
13295 current_config->alt_name.gmch_m, \
13296 current_config->alt_name.gmch_n, \
13297 current_config->alt_name.link_m, \
13298 current_config->alt_name.link_n, \
13299 pipe_config->name.tu, \
13300 pipe_config->name.gmch_m, \
13301 pipe_config->name.gmch_n, \
13302 pipe_config->name.link_m, \
13303 pipe_config->name.link_n); \
13307 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
13308 if ((current_config->name ^ pipe_config->name) & (mask)) { \
13309 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
13310 "(expected %i, found %i)\n", \
13311 current_config->name & (mask), \
13312 pipe_config->name & (mask)); \
13316 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
13317 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
13318 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
13319 "(expected %i, found %i)\n", \
13320 current_config->name, \
13321 pipe_config->name); \
13325 #define PIPE_CONF_QUIRK(quirk) \
13326 ((current_config->quirks | pipe_config->quirks) & (quirk))
13328 PIPE_CONF_CHECK_I(cpu_transcoder);
13330 PIPE_CONF_CHECK_I(has_pch_encoder);
13331 PIPE_CONF_CHECK_I(fdi_lanes);
13332 PIPE_CONF_CHECK_M_N(fdi_m_n);
13334 PIPE_CONF_CHECK_I(lane_count);
13335 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
13337 if (INTEL_INFO(dev)->gen < 8) {
13338 PIPE_CONF_CHECK_M_N(dp_m_n);
13340 if (current_config->has_drrs)
13341 PIPE_CONF_CHECK_M_N(dp_m2_n2);
13343 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
13345 PIPE_CONF_CHECK_X(output_types);
13347 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
13348 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
13349 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
13350 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
13351 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
13352 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
13354 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
13355 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
13356 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
13357 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
13358 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
13359 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
13361 PIPE_CONF_CHECK_I(pixel_multiplier);
13362 PIPE_CONF_CHECK_I(has_hdmi_sink);
13363 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
13364 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
13365 PIPE_CONF_CHECK_I(limited_color_range);
13366 PIPE_CONF_CHECK_I(has_infoframe);
13368 PIPE_CONF_CHECK_I(has_audio);
13370 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13371 DRM_MODE_FLAG_INTERLACE);
13373 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
13374 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13375 DRM_MODE_FLAG_PHSYNC);
13376 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13377 DRM_MODE_FLAG_NHSYNC);
13378 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13379 DRM_MODE_FLAG_PVSYNC);
13380 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
13381 DRM_MODE_FLAG_NVSYNC);
13384 PIPE_CONF_CHECK_X(gmch_pfit.control);
13385 /* pfit ratios are autocomputed by the hw on gen4+ */
13386 if (INTEL_INFO(dev)->gen < 4)
13387 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
13388 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
13391 PIPE_CONF_CHECK_I(pipe_src_w);
13392 PIPE_CONF_CHECK_I(pipe_src_h);
13394 PIPE_CONF_CHECK_I(pch_pfit.enabled);
13395 if (current_config->pch_pfit.enabled) {
13396 PIPE_CONF_CHECK_X(pch_pfit.pos);
13397 PIPE_CONF_CHECK_X(pch_pfit.size);
13400 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
13403 /* BDW+ don't expose a synchronous way to read the state */
13404 if (IS_HASWELL(dev))
13405 PIPE_CONF_CHECK_I(ips_enabled);
13407 PIPE_CONF_CHECK_I(double_wide);
13409 PIPE_CONF_CHECK_P(shared_dpll);
13410 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
13411 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
13412 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
13413 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
13414 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
13415 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
13416 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
13417 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
13418 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
13420 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
13421 PIPE_CONF_CHECK_X(dsi_pll.div);
13423 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
13424 PIPE_CONF_CHECK_I(pipe_bpp);
13426 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
13427 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
13429 #undef PIPE_CONF_CHECK_X
13430 #undef PIPE_CONF_CHECK_I
13431 #undef PIPE_CONF_CHECK_P
13432 #undef PIPE_CONF_CHECK_FLAGS
13433 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
13434 #undef PIPE_CONF_QUIRK
13435 #undef INTEL_ERR_OR_DBG_KMS
13440 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
13441 const struct intel_crtc_state *pipe_config)
13443 if (pipe_config->has_pch_encoder) {
13444 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
13445 &pipe_config->fdi_m_n);
13446 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
13449 * FDI already provided one idea for the dotclock.
13450 * Yell if the encoder disagrees.
13452 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
13453 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13454 fdi_dotclock, dotclock);
13458 static void verify_wm_state(struct drm_crtc *crtc,
13459 struct drm_crtc_state *new_state)
13461 struct drm_device *dev = crtc->dev;
13462 struct drm_i915_private *dev_priv = to_i915(dev);
13463 struct skl_ddb_allocation hw_ddb, *sw_ddb;
13464 struct skl_ddb_entry *hw_entry, *sw_entry;
13465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13466 const enum pipe pipe = intel_crtc->pipe;
13469 if (INTEL_INFO(dev)->gen < 9 || !new_state->active)
13472 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
13473 sw_ddb = &dev_priv->wm.skl_hw.ddb;
13476 for_each_plane(dev_priv, pipe, plane) {
13477 hw_entry = &hw_ddb.plane[pipe][plane];
13478 sw_entry = &sw_ddb->plane[pipe][plane];
13480 if (skl_ddb_entry_equal(hw_entry, sw_entry))
13483 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
13484 "(expected (%u,%u), found (%u,%u))\n",
13485 pipe_name(pipe), plane + 1,
13486 sw_entry->start, sw_entry->end,
13487 hw_entry->start, hw_entry->end);
13492 * If the cursor plane isn't active, we may not have updated it's ddb
13493 * allocation. In that case since the ddb allocation will be updated
13494 * once the plane becomes visible, we can skip this check
13496 if (intel_crtc->cursor_addr) {
13497 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
13498 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
13500 if (!skl_ddb_entry_equal(hw_entry, sw_entry)) {
13501 DRM_ERROR("mismatch in DDB state pipe %c cursor "
13502 "(expected (%u,%u), found (%u,%u))\n",
13504 sw_entry->start, sw_entry->end,
13505 hw_entry->start, hw_entry->end);
13511 verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc)
13513 struct drm_connector *connector;
13515 drm_for_each_connector(connector, dev) {
13516 struct drm_encoder *encoder = connector->encoder;
13517 struct drm_connector_state *state = connector->state;
13519 if (state->crtc != crtc)
13522 intel_connector_verify_state(to_intel_connector(connector));
13524 I915_STATE_WARN(state->best_encoder != encoder,
13525 "connector's atomic encoder doesn't match legacy encoder\n");
13530 verify_encoder_state(struct drm_device *dev)
13532 struct intel_encoder *encoder;
13533 struct intel_connector *connector;
13535 for_each_intel_encoder(dev, encoder) {
13536 bool enabled = false;
13539 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
13540 encoder->base.base.id,
13541 encoder->base.name);
13543 for_each_intel_connector(dev, connector) {
13544 if (connector->base.state->best_encoder != &encoder->base)
13548 I915_STATE_WARN(connector->base.state->crtc !=
13549 encoder->base.crtc,
13550 "connector's crtc doesn't match encoder crtc\n");
13553 I915_STATE_WARN(!!encoder->base.crtc != enabled,
13554 "encoder's enabled state mismatch "
13555 "(expected %i, found %i)\n",
13556 !!encoder->base.crtc, enabled);
13558 if (!encoder->base.crtc) {
13561 active = encoder->get_hw_state(encoder, &pipe);
13562 I915_STATE_WARN(active,
13563 "encoder detached but still enabled on pipe %c.\n",
13570 verify_crtc_state(struct drm_crtc *crtc,
13571 struct drm_crtc_state *old_crtc_state,
13572 struct drm_crtc_state *new_crtc_state)
13574 struct drm_device *dev = crtc->dev;
13575 struct drm_i915_private *dev_priv = to_i915(dev);
13576 struct intel_encoder *encoder;
13577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13578 struct intel_crtc_state *pipe_config, *sw_config;
13579 struct drm_atomic_state *old_state;
13582 old_state = old_crtc_state->state;
13583 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
13584 pipe_config = to_intel_crtc_state(old_crtc_state);
13585 memset(pipe_config, 0, sizeof(*pipe_config));
13586 pipe_config->base.crtc = crtc;
13587 pipe_config->base.state = old_state;
13589 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
13591 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
13593 /* hw state is inconsistent with the pipe quirk */
13594 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13595 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13596 active = new_crtc_state->active;
13598 I915_STATE_WARN(new_crtc_state->active != active,
13599 "crtc active state doesn't match with hw state "
13600 "(expected %i, found %i)\n", new_crtc_state->active, active);
13602 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
13603 "transitional active state does not match atomic hw state "
13604 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
13606 for_each_encoder_on_crtc(dev, crtc, encoder) {
13609 active = encoder->get_hw_state(encoder, &pipe);
13610 I915_STATE_WARN(active != new_crtc_state->active,
13611 "[ENCODER:%i] active %i with crtc active %i\n",
13612 encoder->base.base.id, active, new_crtc_state->active);
13614 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13615 "Encoder connected to wrong pipe %c\n",
13619 pipe_config->output_types |= 1 << encoder->type;
13620 encoder->get_config(encoder, pipe_config);
13624 if (!new_crtc_state->active)
13627 intel_pipe_config_sanity_check(dev_priv, pipe_config);
13629 sw_config = to_intel_crtc_state(crtc->state);
13630 if (!intel_pipe_config_compare(dev, sw_config,
13631 pipe_config, false)) {
13632 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13633 intel_dump_pipe_config(intel_crtc, pipe_config,
13635 intel_dump_pipe_config(intel_crtc, sw_config,
13641 verify_single_dpll_state(struct drm_i915_private *dev_priv,
13642 struct intel_shared_dpll *pll,
13643 struct drm_crtc *crtc,
13644 struct drm_crtc_state *new_state)
13646 struct intel_dpll_hw_state dpll_hw_state;
13647 unsigned crtc_mask;
13650 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13652 DRM_DEBUG_KMS("%s\n", pll->name);
13654 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
13656 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
13657 I915_STATE_WARN(!pll->on && pll->active_mask,
13658 "pll in active use but not on in sw tracking\n");
13659 I915_STATE_WARN(pll->on && !pll->active_mask,
13660 "pll is on but not used by any active crtc\n");
13661 I915_STATE_WARN(pll->on != active,
13662 "pll on state mismatch (expected %i, found %i)\n",
13667 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
13668 "more active pll users than references: %x vs %x\n",
13669 pll->active_mask, pll->config.crtc_mask);
13674 crtc_mask = 1 << drm_crtc_index(crtc);
13676 if (new_state->active)
13677 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
13678 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
13679 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13681 I915_STATE_WARN(pll->active_mask & crtc_mask,
13682 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
13683 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
13685 I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask),
13686 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
13687 crtc_mask, pll->config.crtc_mask);
13689 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state,
13691 sizeof(dpll_hw_state)),
13692 "pll hw state mismatch\n");
13696 verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
13697 struct drm_crtc_state *old_crtc_state,
13698 struct drm_crtc_state *new_crtc_state)
13700 struct drm_i915_private *dev_priv = to_i915(dev);
13701 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
13702 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
13704 if (new_state->shared_dpll)
13705 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
13707 if (old_state->shared_dpll &&
13708 old_state->shared_dpll != new_state->shared_dpll) {
13709 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
13710 struct intel_shared_dpll *pll = old_state->shared_dpll;
13712 I915_STATE_WARN(pll->active_mask & crtc_mask,
13713 "pll active mismatch (didn't expect pipe %c in active mask)\n",
13714 pipe_name(drm_crtc_index(crtc)));
13715 I915_STATE_WARN(pll->config.crtc_mask & crtc_mask,
13716 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
13717 pipe_name(drm_crtc_index(crtc)));
13722 intel_modeset_verify_crtc(struct drm_crtc *crtc,
13723 struct drm_crtc_state *old_state,
13724 struct drm_crtc_state *new_state)
13726 if (!needs_modeset(new_state) &&
13727 !to_intel_crtc_state(new_state)->update_pipe)
13730 verify_wm_state(crtc, new_state);
13731 verify_connector_state(crtc->dev, crtc);
13732 verify_crtc_state(crtc, old_state, new_state);
13733 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
13737 verify_disabled_dpll_state(struct drm_device *dev)
13739 struct drm_i915_private *dev_priv = to_i915(dev);
13742 for (i = 0; i < dev_priv->num_shared_dpll; i++)
13743 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
13747 intel_modeset_verify_disabled(struct drm_device *dev)
13749 verify_encoder_state(dev);
13750 verify_connector_state(dev, NULL);
13751 verify_disabled_dpll_state(dev);
13754 static void update_scanline_offset(struct intel_crtc *crtc)
13756 struct drm_device *dev = crtc->base.dev;
13759 * The scanline counter increments at the leading edge of hsync.
13761 * On most platforms it starts counting from vtotal-1 on the
13762 * first active line. That means the scanline counter value is
13763 * always one less than what we would expect. Ie. just after
13764 * start of vblank, which also occurs at start of hsync (on the
13765 * last active line), the scanline counter will read vblank_start-1.
13767 * On gen2 the scanline counter starts counting from 1 instead
13768 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13769 * to keep the value positive), instead of adding one.
13771 * On HSW+ the behaviour of the scanline counter depends on the output
13772 * type. For DP ports it behaves like most other platforms, but on HDMI
13773 * there's an extra 1 line difference. So we need to add two instead of
13774 * one to the value.
13776 * On VLV/CHV DSI the scanline counter would appear to increment
13777 * approx. 1/3 of a scanline before start of vblank. Unfortunately
13778 * that means we can't tell whether we're in vblank or not while
13779 * we're on that particular line. We must still set scanline_offset
13780 * to 1 so that the vblank timestamps come out correct when we query
13781 * the scanline counter from within the vblank interrupt handler.
13782 * However if queried just before the start of vblank we'll get an
13783 * answer that's slightly in the future.
13785 if (IS_GEN2(dev)) {
13786 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13789 vtotal = adjusted_mode->crtc_vtotal;
13790 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13793 crtc->scanline_offset = vtotal - 1;
13794 } else if (HAS_DDI(dev) &&
13795 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
13796 crtc->scanline_offset = 2;
13798 crtc->scanline_offset = 1;
13801 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13803 struct drm_device *dev = state->dev;
13804 struct drm_i915_private *dev_priv = to_i915(dev);
13805 struct intel_shared_dpll_config *shared_dpll = NULL;
13806 struct drm_crtc *crtc;
13807 struct drm_crtc_state *crtc_state;
13810 if (!dev_priv->display.crtc_compute_clock)
13813 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13815 struct intel_shared_dpll *old_dpll =
13816 to_intel_crtc_state(crtc->state)->shared_dpll;
13818 if (!needs_modeset(crtc_state))
13821 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13827 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13829 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13834 * This implements the workaround described in the "notes" section of the mode
13835 * set sequence documentation. When going from no pipes or single pipe to
13836 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13837 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13839 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13841 struct drm_crtc_state *crtc_state;
13842 struct intel_crtc *intel_crtc;
13843 struct drm_crtc *crtc;
13844 struct intel_crtc_state *first_crtc_state = NULL;
13845 struct intel_crtc_state *other_crtc_state = NULL;
13846 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13849 /* look at all crtc's that are going to be enabled in during modeset */
13850 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13851 intel_crtc = to_intel_crtc(crtc);
13853 if (!crtc_state->active || !needs_modeset(crtc_state))
13856 if (first_crtc_state) {
13857 other_crtc_state = to_intel_crtc_state(crtc_state);
13860 first_crtc_state = to_intel_crtc_state(crtc_state);
13861 first_pipe = intel_crtc->pipe;
13865 /* No workaround needed? */
13866 if (!first_crtc_state)
13869 /* w/a possibly needed, check how many crtc's are already enabled. */
13870 for_each_intel_crtc(state->dev, intel_crtc) {
13871 struct intel_crtc_state *pipe_config;
13873 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13874 if (IS_ERR(pipe_config))
13875 return PTR_ERR(pipe_config);
13877 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13879 if (!pipe_config->base.active ||
13880 needs_modeset(&pipe_config->base))
13883 /* 2 or more enabled crtcs means no need for w/a */
13884 if (enabled_pipe != INVALID_PIPE)
13887 enabled_pipe = intel_crtc->pipe;
13890 if (enabled_pipe != INVALID_PIPE)
13891 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13892 else if (other_crtc_state)
13893 other_crtc_state->hsw_workaround_pipe = first_pipe;
13898 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13900 struct drm_crtc *crtc;
13901 struct drm_crtc_state *crtc_state;
13904 /* add all active pipes to the state */
13905 for_each_crtc(state->dev, crtc) {
13906 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13907 if (IS_ERR(crtc_state))
13908 return PTR_ERR(crtc_state);
13910 if (!crtc_state->active || needs_modeset(crtc_state))
13913 crtc_state->mode_changed = true;
13915 ret = drm_atomic_add_affected_connectors(state, crtc);
13919 ret = drm_atomic_add_affected_planes(state, crtc);
13927 static int intel_modeset_checks(struct drm_atomic_state *state)
13929 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13930 struct drm_i915_private *dev_priv = to_i915(state->dev);
13931 struct drm_crtc *crtc;
13932 struct drm_crtc_state *crtc_state;
13935 if (!check_digital_port_conflicts(state)) {
13936 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13940 intel_state->modeset = true;
13941 intel_state->active_crtcs = dev_priv->active_crtcs;
13943 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13944 if (crtc_state->active)
13945 intel_state->active_crtcs |= 1 << i;
13947 intel_state->active_crtcs &= ~(1 << i);
13949 if (crtc_state->active != crtc->state->active)
13950 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
13954 * See if the config requires any additional preparation, e.g.
13955 * to adjust global state with pipes off. We need to do this
13956 * here so we can get the modeset_pipe updated config for the new
13957 * mode set on this crtc. For other crtcs we need to use the
13958 * adjusted_mode bits in the crtc directly.
13960 if (dev_priv->display.modeset_calc_cdclk) {
13961 if (!intel_state->cdclk_pll_vco)
13962 intel_state->cdclk_pll_vco = dev_priv->cdclk_pll.vco;
13963 if (!intel_state->cdclk_pll_vco)
13964 intel_state->cdclk_pll_vco = dev_priv->skl_preferred_vco_freq;
13966 ret = dev_priv->display.modeset_calc_cdclk(state);
13970 if (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
13971 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco)
13972 ret = intel_modeset_all_pipes(state);
13977 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13978 intel_state->cdclk, intel_state->dev_cdclk);
13980 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13983 intel_modeset_clear_plls(state);
13985 if (IS_HASWELL(dev_priv))
13986 return haswell_mode_set_planes_workaround(state);
13992 * Handle calculation of various watermark data at the end of the atomic check
13993 * phase. The code here should be run after the per-crtc and per-plane 'check'
13994 * handlers to ensure that all derived state has been updated.
13996 static int calc_watermark_data(struct drm_atomic_state *state)
13998 struct drm_device *dev = state->dev;
13999 struct drm_i915_private *dev_priv = to_i915(dev);
14001 /* Is there platform-specific watermark information to calculate? */
14002 if (dev_priv->display.compute_global_watermarks)
14003 return dev_priv->display.compute_global_watermarks(state);
14009 * intel_atomic_check - validate state object
14011 * @state: state to validate
14013 static int intel_atomic_check(struct drm_device *dev,
14014 struct drm_atomic_state *state)
14016 struct drm_i915_private *dev_priv = to_i915(dev);
14017 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14018 struct drm_crtc *crtc;
14019 struct drm_crtc_state *crtc_state;
14021 bool any_ms = false;
14023 ret = drm_atomic_helper_check_modeset(dev, state);
14027 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14028 struct intel_crtc_state *pipe_config =
14029 to_intel_crtc_state(crtc_state);
14031 /* Catch I915_MODE_FLAG_INHERITED */
14032 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
14033 crtc_state->mode_changed = true;
14035 if (!needs_modeset(crtc_state))
14038 if (!crtc_state->enable) {
14043 /* FIXME: For only active_changed we shouldn't need to do any
14044 * state recomputation at all. */
14046 ret = drm_atomic_add_affected_connectors(state, crtc);
14050 ret = intel_modeset_pipe_config(crtc, pipe_config);
14052 intel_dump_pipe_config(to_intel_crtc(crtc),
14053 pipe_config, "[failed]");
14057 if (i915.fastboot &&
14058 intel_pipe_config_compare(dev,
14059 to_intel_crtc_state(crtc->state),
14060 pipe_config, true)) {
14061 crtc_state->mode_changed = false;
14062 to_intel_crtc_state(crtc_state)->update_pipe = true;
14065 if (needs_modeset(crtc_state))
14068 ret = drm_atomic_add_affected_planes(state, crtc);
14072 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
14073 needs_modeset(crtc_state) ?
14074 "[modeset]" : "[fastset]");
14078 ret = intel_modeset_checks(state);
14083 intel_state->cdclk = dev_priv->atomic_cdclk_freq;
14086 ret = drm_atomic_helper_check_planes(dev, state);
14090 intel_fbc_choose_crtc(dev_priv, state);
14091 return calc_watermark_data(state);
14094 static int intel_atomic_prepare_commit(struct drm_device *dev,
14095 struct drm_atomic_state *state,
14098 struct drm_i915_private *dev_priv = to_i915(dev);
14099 struct drm_plane_state *plane_state;
14100 struct drm_crtc_state *crtc_state;
14101 struct drm_plane *plane;
14102 struct drm_crtc *crtc;
14105 for_each_crtc_in_state(state, crtc, crtc_state, i) {
14106 if (state->legacy_cursor_update)
14109 ret = intel_crtc_wait_for_pending_flips(crtc);
14113 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
14114 flush_workqueue(dev_priv->wq);
14117 ret = mutex_lock_interruptible(&dev->struct_mutex);
14121 ret = drm_atomic_helper_prepare_planes(dev, state);
14122 mutex_unlock(&dev->struct_mutex);
14124 if (!ret && !nonblock) {
14125 for_each_plane_in_state(state, plane, plane_state, i) {
14126 struct intel_plane_state *intel_plane_state =
14127 to_intel_plane_state(plane_state);
14129 if (!intel_plane_state->wait_req)
14132 ret = i915_wait_request(intel_plane_state->wait_req,
14133 I915_WAIT_INTERRUPTIBLE,
14136 /* Any hang should be swallowed by the wait */
14137 WARN_ON(ret == -EIO);
14138 mutex_lock(&dev->struct_mutex);
14139 drm_atomic_helper_cleanup_planes(dev, state);
14140 mutex_unlock(&dev->struct_mutex);
14149 u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
14151 struct drm_device *dev = crtc->base.dev;
14153 if (!dev->max_vblank_count)
14154 return drm_accurate_vblank_count(&crtc->base);
14156 return dev->driver->get_vblank_counter(dev, crtc->pipe);
14159 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
14160 struct drm_i915_private *dev_priv,
14161 unsigned crtc_mask)
14163 unsigned last_vblank_count[I915_MAX_PIPES];
14170 for_each_pipe(dev_priv, pipe) {
14171 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14173 if (!((1 << pipe) & crtc_mask))
14176 ret = drm_crtc_vblank_get(crtc);
14177 if (WARN_ON(ret != 0)) {
14178 crtc_mask &= ~(1 << pipe);
14182 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
14185 for_each_pipe(dev_priv, pipe) {
14186 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
14189 if (!((1 << pipe) & crtc_mask))
14192 lret = wait_event_timeout(dev->vblank[pipe].queue,
14193 last_vblank_count[pipe] !=
14194 drm_crtc_vblank_count(crtc),
14195 msecs_to_jiffies(50));
14197 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
14199 drm_crtc_vblank_put(crtc);
14203 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
14205 /* fb updated, need to unpin old fb */
14206 if (crtc_state->fb_changed)
14209 /* wm changes, need vblank before final wm's */
14210 if (crtc_state->update_wm_post)
14214 * cxsr is re-enabled after vblank.
14215 * This is already handled by crtc_state->update_wm_post,
14216 * but added for clarity.
14218 if (crtc_state->disable_cxsr)
14224 static void intel_update_crtc(struct drm_crtc *crtc,
14225 struct drm_atomic_state *state,
14226 struct drm_crtc_state *old_crtc_state,
14227 unsigned int *crtc_vblank_mask)
14229 struct drm_device *dev = crtc->dev;
14230 struct drm_i915_private *dev_priv = to_i915(dev);
14231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14232 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state);
14233 bool modeset = needs_modeset(crtc->state);
14236 update_scanline_offset(intel_crtc);
14237 dev_priv->display.crtc_enable(pipe_config, state);
14239 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14242 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
14244 intel_crtc, pipe_config,
14245 to_intel_plane_state(crtc->primary->state));
14248 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
14250 if (needs_vblank_wait(pipe_config))
14251 *crtc_vblank_mask |= drm_crtc_mask(crtc);
14254 static void intel_update_crtcs(struct drm_atomic_state *state,
14255 unsigned int *crtc_vblank_mask)
14257 struct drm_crtc *crtc;
14258 struct drm_crtc_state *old_crtc_state;
14261 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14262 if (!crtc->state->active)
14265 intel_update_crtc(crtc, state, old_crtc_state,
14270 static void skl_update_crtcs(struct drm_atomic_state *state,
14271 unsigned int *crtc_vblank_mask)
14273 struct drm_device *dev = state->dev;
14274 struct drm_i915_private *dev_priv = to_i915(dev);
14275 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14276 struct drm_crtc *crtc;
14277 struct drm_crtc_state *old_crtc_state;
14278 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
14279 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
14280 unsigned int updated = 0;
14285 * Whenever the number of active pipes changes, we need to make sure we
14286 * update the pipes in the right order so that their ddb allocations
14287 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
14288 * cause pipe underruns and other bad stuff.
14294 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14295 bool vbl_wait = false;
14296 unsigned int cmask = drm_crtc_mask(crtc);
14297 pipe = to_intel_crtc(crtc)->pipe;
14299 if (updated & cmask || !crtc->state->active)
14301 if (skl_ddb_allocation_overlaps(state, cur_ddb, new_ddb,
14308 * If this is an already active pipe, it's DDB changed,
14309 * and this isn't the last pipe that needs updating
14310 * then we need to wait for a vblank to pass for the
14311 * new ddb allocation to take effect.
14313 if (!skl_ddb_allocation_equals(cur_ddb, new_ddb, pipe) &&
14314 !crtc->state->active_changed &&
14315 intel_state->wm_results.dirty_pipes != updated)
14318 intel_update_crtc(crtc, state, old_crtc_state,
14322 intel_wait_for_vblank(dev, pipe);
14326 } while (progress);
14329 static void intel_atomic_commit_tail(struct drm_atomic_state *state)
14331 struct drm_device *dev = state->dev;
14332 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14333 struct drm_i915_private *dev_priv = to_i915(dev);
14334 struct drm_crtc_state *old_crtc_state;
14335 struct drm_crtc *crtc;
14336 struct intel_crtc_state *intel_cstate;
14337 struct drm_plane *plane;
14338 struct drm_plane_state *plane_state;
14339 bool hw_check = intel_state->modeset;
14340 unsigned long put_domains[I915_MAX_PIPES] = {};
14341 unsigned crtc_vblank_mask = 0;
14344 for_each_plane_in_state(state, plane, plane_state, i) {
14345 struct intel_plane_state *intel_plane_state =
14346 to_intel_plane_state(plane->state);
14348 if (!intel_plane_state->wait_req)
14351 ret = i915_wait_request(intel_plane_state->wait_req,
14353 /* EIO should be eaten, and we can't get interrupted in the
14354 * worker, and blocking commits have waited already. */
14358 drm_atomic_helper_wait_for_dependencies(state);
14360 if (intel_state->modeset) {
14361 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
14362 sizeof(intel_state->min_pixclk));
14363 dev_priv->active_crtcs = intel_state->active_crtcs;
14364 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
14366 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
14369 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14372 if (needs_modeset(crtc->state) ||
14373 to_intel_crtc_state(crtc->state)->update_pipe) {
14376 put_domains[to_intel_crtc(crtc)->pipe] =
14377 modeset_get_crtc_power_domains(crtc,
14378 to_intel_crtc_state(crtc->state));
14381 if (!needs_modeset(crtc->state))
14384 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
14386 if (old_crtc_state->active) {
14387 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
14388 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
14389 intel_crtc->active = false;
14390 intel_fbc_disable(intel_crtc);
14391 intel_disable_shared_dpll(intel_crtc);
14394 * Underruns don't always raise
14395 * interrupts, so check manually.
14397 intel_check_cpu_fifo_underruns(dev_priv);
14398 intel_check_pch_fifo_underruns(dev_priv);
14400 if (!crtc->state->active)
14401 intel_update_watermarks(crtc);
14405 /* Only after disabling all output pipelines that will be changed can we
14406 * update the the output configuration. */
14407 intel_modeset_update_crtc_state(state);
14409 if (intel_state->modeset) {
14410 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
14412 if (dev_priv->display.modeset_commit_cdclk &&
14413 (intel_state->dev_cdclk != dev_priv->cdclk_freq ||
14414 intel_state->cdclk_pll_vco != dev_priv->cdclk_pll.vco))
14415 dev_priv->display.modeset_commit_cdclk(state);
14418 * SKL workaround: bspec recommends we disable the SAGV when we
14419 * have more then one pipe enabled
14421 if (!intel_can_enable_sagv(state))
14422 intel_disable_sagv(dev_priv);
14424 intel_modeset_verify_disabled(dev);
14427 /* Complete the events for pipes that have now been disabled */
14428 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14429 bool modeset = needs_modeset(crtc->state);
14431 /* Complete events for now disable pipes here. */
14432 if (modeset && !crtc->state->active && crtc->state->event) {
14433 spin_lock_irq(&dev->event_lock);
14434 drm_crtc_send_vblank_event(crtc, crtc->state->event);
14435 spin_unlock_irq(&dev->event_lock);
14437 crtc->state->event = NULL;
14441 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
14442 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
14444 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
14445 * already, but still need the state for the delayed optimization. To
14447 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
14448 * - schedule that vblank worker _before_ calling hw_done
14449 * - at the start of commit_tail, cancel it _synchrously
14450 * - switch over to the vblank wait helper in the core after that since
14451 * we don't need out special handling any more.
14453 if (!state->legacy_cursor_update)
14454 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
14457 * Now that the vblank has passed, we can go ahead and program the
14458 * optimal watermarks on platforms that need two-step watermark
14461 * TODO: Move this (and other cleanup) to an async worker eventually.
14463 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14464 intel_cstate = to_intel_crtc_state(crtc->state);
14466 if (dev_priv->display.optimize_watermarks)
14467 dev_priv->display.optimize_watermarks(intel_cstate);
14470 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
14471 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
14473 if (put_domains[i])
14474 modeset_put_power_domains(dev_priv, put_domains[i]);
14476 intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
14479 if (intel_state->modeset && intel_can_enable_sagv(state))
14480 intel_enable_sagv(dev_priv);
14482 drm_atomic_helper_commit_hw_done(state);
14484 if (intel_state->modeset)
14485 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
14487 mutex_lock(&dev->struct_mutex);
14488 drm_atomic_helper_cleanup_planes(dev, state);
14489 mutex_unlock(&dev->struct_mutex);
14491 drm_atomic_helper_commit_cleanup_done(state);
14493 drm_atomic_state_free(state);
14495 /* As one of the primary mmio accessors, KMS has a high likelihood
14496 * of triggering bugs in unclaimed access. After we finish
14497 * modesetting, see if an error has been flagged, and if so
14498 * enable debugging for the next modeset - and hope we catch
14501 * XXX note that we assume display power is on at this point.
14502 * This might hold true now but we need to add pm helper to check
14503 * unclaimed only when the hardware is on, as atomic commits
14504 * can happen also when the device is completely off.
14506 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
14509 static void intel_atomic_commit_work(struct work_struct *work)
14511 struct drm_atomic_state *state = container_of(work,
14512 struct drm_atomic_state,
14514 intel_atomic_commit_tail(state);
14517 static void intel_atomic_track_fbs(struct drm_atomic_state *state)
14519 struct drm_plane_state *old_plane_state;
14520 struct drm_plane *plane;
14523 for_each_plane_in_state(state, plane, old_plane_state, i)
14524 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
14525 intel_fb_obj(plane->state->fb),
14526 to_intel_plane(plane)->frontbuffer_bit);
14530 * intel_atomic_commit - commit validated state object
14532 * @state: the top-level driver state object
14533 * @nonblock: nonblocking commit
14535 * This function commits a top-level state object that has been validated
14536 * with drm_atomic_helper_check().
14538 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
14539 * nonblocking commits are only safe for pure plane updates. Everything else
14540 * should work though.
14543 * Zero for success or -errno.
14545 static int intel_atomic_commit(struct drm_device *dev,
14546 struct drm_atomic_state *state,
14549 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14550 struct drm_i915_private *dev_priv = to_i915(dev);
14553 if (intel_state->modeset && nonblock) {
14554 DRM_DEBUG_KMS("nonblocking commit for modeset not yet implemented.\n");
14558 ret = drm_atomic_helper_setup_commit(state, nonblock);
14562 INIT_WORK(&state->commit_work, intel_atomic_commit_work);
14564 ret = intel_atomic_prepare_commit(dev, state, nonblock);
14566 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
14570 drm_atomic_helper_swap_state(state, true);
14571 dev_priv->wm.distrust_bios_wm = false;
14572 dev_priv->wm.skl_results = intel_state->wm_results;
14573 intel_shared_dpll_commit(state);
14574 intel_atomic_track_fbs(state);
14577 queue_work(system_unbound_wq, &state->commit_work);
14579 intel_atomic_commit_tail(state);
14584 void intel_crtc_restore_mode(struct drm_crtc *crtc)
14586 struct drm_device *dev = crtc->dev;
14587 struct drm_atomic_state *state;
14588 struct drm_crtc_state *crtc_state;
14591 state = drm_atomic_state_alloc(dev);
14593 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
14594 crtc->base.id, crtc->name);
14598 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
14601 crtc_state = drm_atomic_get_crtc_state(state, crtc);
14602 ret = PTR_ERR_OR_ZERO(crtc_state);
14604 if (!crtc_state->active)
14607 crtc_state->mode_changed = true;
14608 ret = drm_atomic_commit(state);
14611 if (ret == -EDEADLK) {
14612 drm_atomic_state_clear(state);
14613 drm_modeset_backoff(state->acquire_ctx);
14619 drm_atomic_state_free(state);
14623 * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling
14624 * drm_atomic_helper_legacy_gamma_set() directly.
14626 static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc,
14627 u16 *red, u16 *green, u16 *blue,
14630 struct drm_device *dev = crtc->dev;
14631 struct drm_mode_config *config = &dev->mode_config;
14632 struct drm_crtc_state *state;
14635 ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size);
14640 * Make sure we update the legacy properties so this works when
14641 * atomic is not enabled.
14644 state = crtc->state;
14646 drm_object_property_set_value(&crtc->base,
14647 config->degamma_lut_property,
14648 (state->degamma_lut) ?
14649 state->degamma_lut->base.id : 0);
14651 drm_object_property_set_value(&crtc->base,
14652 config->ctm_property,
14654 state->ctm->base.id : 0);
14656 drm_object_property_set_value(&crtc->base,
14657 config->gamma_lut_property,
14658 (state->gamma_lut) ?
14659 state->gamma_lut->base.id : 0);
14664 static const struct drm_crtc_funcs intel_crtc_funcs = {
14665 .gamma_set = intel_atomic_legacy_gamma_set,
14666 .set_config = drm_atomic_helper_set_config,
14667 .set_property = drm_atomic_helper_crtc_set_property,
14668 .destroy = intel_crtc_destroy,
14669 .page_flip = intel_crtc_page_flip,
14670 .atomic_duplicate_state = intel_crtc_duplicate_state,
14671 .atomic_destroy_state = intel_crtc_destroy_state,
14675 * intel_prepare_plane_fb - Prepare fb for usage on plane
14676 * @plane: drm plane to prepare for
14677 * @fb: framebuffer to prepare for presentation
14679 * Prepares a framebuffer for usage on a display plane. Generally this
14680 * involves pinning the underlying object and updating the frontbuffer tracking
14681 * bits. Some older platforms need special physical address handling for
14684 * Must be called with struct_mutex held.
14686 * Returns 0 on success, negative error code on failure.
14689 intel_prepare_plane_fb(struct drm_plane *plane,
14690 struct drm_plane_state *new_state)
14692 struct drm_device *dev = plane->dev;
14693 struct drm_framebuffer *fb = new_state->fb;
14694 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14695 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
14696 struct reservation_object *resv;
14699 if (!obj && !old_obj)
14703 struct drm_crtc_state *crtc_state =
14704 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
14706 /* Big Hammer, we also need to ensure that any pending
14707 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
14708 * current scanout is retired before unpinning the old
14709 * framebuffer. Note that we rely on userspace rendering
14710 * into the buffer attached to the pipe they are waiting
14711 * on. If not, userspace generates a GPU hang with IPEHR
14712 * point to the MI_WAIT_FOR_EVENT.
14714 * This should only fail upon a hung GPU, in which case we
14715 * can safely continue.
14717 if (needs_modeset(crtc_state))
14718 ret = i915_gem_object_wait_rendering(old_obj, true);
14720 /* GPU hangs should have been swallowed by the wait */
14721 WARN_ON(ret == -EIO);
14729 /* For framebuffer backed by dmabuf, wait for fence */
14730 resv = i915_gem_object_get_dmabuf_resv(obj);
14734 lret = reservation_object_wait_timeout_rcu(resv, false, true,
14735 MAX_SCHEDULE_TIMEOUT);
14736 if (lret == -ERESTARTSYS)
14739 WARN(lret < 0, "waiting returns %li\n", lret);
14742 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
14743 INTEL_INFO(dev)->cursor_needs_physical) {
14744 int align = IS_I830(dev) ? 16 * 1024 : 256;
14745 ret = i915_gem_object_attach_phys(obj, align);
14747 DRM_DEBUG_KMS("failed to attach phys object\n");
14749 struct i915_vma *vma;
14751 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
14753 ret = PTR_ERR(vma);
14757 to_intel_plane_state(new_state)->wait_req =
14758 i915_gem_active_get(&obj->last_write,
14759 &obj->base.dev->struct_mutex);
14766 * intel_cleanup_plane_fb - Cleans up an fb after plane use
14767 * @plane: drm plane to clean up for
14768 * @fb: old framebuffer that was on plane
14770 * Cleans up a framebuffer that has just been removed from a plane.
14772 * Must be called with struct_mutex held.
14775 intel_cleanup_plane_fb(struct drm_plane *plane,
14776 struct drm_plane_state *old_state)
14778 struct drm_device *dev = plane->dev;
14779 struct intel_plane_state *old_intel_state;
14780 struct intel_plane_state *intel_state = to_intel_plane_state(plane->state);
14781 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
14782 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
14784 old_intel_state = to_intel_plane_state(old_state);
14786 if (!obj && !old_obj)
14789 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
14790 !INTEL_INFO(dev)->cursor_needs_physical))
14791 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
14793 i915_gem_request_assign(&intel_state->wait_req, NULL);
14794 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14798 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14801 int crtc_clock, cdclk;
14803 if (!intel_crtc || !crtc_state->base.enable)
14804 return DRM_PLANE_HELPER_NO_SCALING;
14806 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14807 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14809 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14810 return DRM_PLANE_HELPER_NO_SCALING;
14813 * skl max scale is lower of:
14814 * close to 3 but not 3, -1 is for that purpose
14818 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14824 intel_check_primary_plane(struct drm_plane *plane,
14825 struct intel_crtc_state *crtc_state,
14826 struct intel_plane_state *state)
14828 struct drm_i915_private *dev_priv = to_i915(plane->dev);
14829 struct drm_crtc *crtc = state->base.crtc;
14830 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14831 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14832 bool can_position = false;
14835 if (INTEL_GEN(dev_priv) >= 9) {
14836 /* use scaler when colorkey is not required */
14837 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
14839 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14841 can_position = true;
14844 ret = drm_plane_helper_check_state(&state->base,
14846 min_scale, max_scale,
14847 can_position, true);
14851 if (!state->base.fb)
14854 if (INTEL_GEN(dev_priv) >= 9) {
14855 ret = skl_check_plane_surface(state);
14863 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14864 struct drm_crtc_state *old_crtc_state)
14866 struct drm_device *dev = crtc->dev;
14867 struct drm_i915_private *dev_priv = to_i915(dev);
14868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14869 struct intel_crtc_state *old_intel_state =
14870 to_intel_crtc_state(old_crtc_state);
14871 bool modeset = needs_modeset(crtc->state);
14872 enum pipe pipe = intel_crtc->pipe;
14874 /* Perform vblank evasion around commit operation */
14875 intel_pipe_update_start(intel_crtc);
14880 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
14881 intel_color_set_csc(crtc->state);
14882 intel_color_load_luts(crtc->state);
14885 if (to_intel_crtc_state(crtc->state)->update_pipe)
14886 intel_update_pipe_config(intel_crtc, old_intel_state);
14887 else if (INTEL_GEN(dev_priv) >= 9) {
14888 skl_detach_scalers(intel_crtc);
14890 I915_WRITE(PIPE_WM_LINETIME(pipe),
14891 dev_priv->wm.skl_hw.wm_linetime[pipe]);
14895 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14896 struct drm_crtc_state *old_crtc_state)
14898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14900 intel_pipe_update_end(intel_crtc, NULL);
14904 * intel_plane_destroy - destroy a plane
14905 * @plane: plane to destroy
14907 * Common destruction function for all types of planes (primary, cursor,
14910 void intel_plane_destroy(struct drm_plane *plane)
14915 drm_plane_cleanup(plane);
14916 kfree(to_intel_plane(plane));
14919 const struct drm_plane_funcs intel_plane_funcs = {
14920 .update_plane = drm_atomic_helper_update_plane,
14921 .disable_plane = drm_atomic_helper_disable_plane,
14922 .destroy = intel_plane_destroy,
14923 .set_property = drm_atomic_helper_plane_set_property,
14924 .atomic_get_property = intel_plane_atomic_get_property,
14925 .atomic_set_property = intel_plane_atomic_set_property,
14926 .atomic_duplicate_state = intel_plane_duplicate_state,
14927 .atomic_destroy_state = intel_plane_destroy_state,
14931 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14934 struct intel_plane *primary = NULL;
14935 struct intel_plane_state *state = NULL;
14936 const uint32_t *intel_primary_formats;
14937 unsigned int num_formats;
14940 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14944 state = intel_create_plane_state(&primary->base);
14947 primary->base.state = &state->base;
14949 primary->can_scale = false;
14950 primary->max_downscale = 1;
14951 if (INTEL_INFO(dev)->gen >= 9) {
14952 primary->can_scale = true;
14953 state->scaler_id = -1;
14955 primary->pipe = pipe;
14956 primary->plane = pipe;
14957 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14958 primary->check_plane = intel_check_primary_plane;
14959 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14960 primary->plane = !pipe;
14962 if (INTEL_INFO(dev)->gen >= 9) {
14963 intel_primary_formats = skl_primary_formats;
14964 num_formats = ARRAY_SIZE(skl_primary_formats);
14966 primary->update_plane = skylake_update_primary_plane;
14967 primary->disable_plane = skylake_disable_primary_plane;
14968 } else if (HAS_PCH_SPLIT(dev)) {
14969 intel_primary_formats = i965_primary_formats;
14970 num_formats = ARRAY_SIZE(i965_primary_formats);
14972 primary->update_plane = ironlake_update_primary_plane;
14973 primary->disable_plane = i9xx_disable_primary_plane;
14974 } else if (INTEL_INFO(dev)->gen >= 4) {
14975 intel_primary_formats = i965_primary_formats;
14976 num_formats = ARRAY_SIZE(i965_primary_formats);
14978 primary->update_plane = i9xx_update_primary_plane;
14979 primary->disable_plane = i9xx_disable_primary_plane;
14981 intel_primary_formats = i8xx_primary_formats;
14982 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14984 primary->update_plane = i9xx_update_primary_plane;
14985 primary->disable_plane = i9xx_disable_primary_plane;
14988 if (INTEL_INFO(dev)->gen >= 9)
14989 ret = drm_universal_plane_init(dev, &primary->base, 0,
14990 &intel_plane_funcs,
14991 intel_primary_formats, num_formats,
14992 DRM_PLANE_TYPE_PRIMARY,
14993 "plane 1%c", pipe_name(pipe));
14994 else if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
14995 ret = drm_universal_plane_init(dev, &primary->base, 0,
14996 &intel_plane_funcs,
14997 intel_primary_formats, num_formats,
14998 DRM_PLANE_TYPE_PRIMARY,
14999 "primary %c", pipe_name(pipe));
15001 ret = drm_universal_plane_init(dev, &primary->base, 0,
15002 &intel_plane_funcs,
15003 intel_primary_formats, num_formats,
15004 DRM_PLANE_TYPE_PRIMARY,
15005 "plane %c", plane_name(primary->plane));
15009 if (INTEL_INFO(dev)->gen >= 4)
15010 intel_create_rotation_property(dev, primary);
15012 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
15014 return &primary->base;
15023 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
15025 if (!dev->mode_config.rotation_property) {
15026 unsigned long flags = DRM_ROTATE_0 |
15029 if (INTEL_INFO(dev)->gen >= 9)
15030 flags |= DRM_ROTATE_90 | DRM_ROTATE_270;
15032 dev->mode_config.rotation_property =
15033 drm_mode_create_rotation_property(dev, flags);
15035 if (dev->mode_config.rotation_property)
15036 drm_object_attach_property(&plane->base.base,
15037 dev->mode_config.rotation_property,
15038 plane->base.state->rotation);
15042 intel_check_cursor_plane(struct drm_plane *plane,
15043 struct intel_crtc_state *crtc_state,
15044 struct intel_plane_state *state)
15046 struct drm_framebuffer *fb = state->base.fb;
15047 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
15048 enum pipe pipe = to_intel_plane(plane)->pipe;
15052 ret = drm_plane_helper_check_state(&state->base,
15054 DRM_PLANE_HELPER_NO_SCALING,
15055 DRM_PLANE_HELPER_NO_SCALING,
15060 /* if we want to turn off the cursor ignore width and height */
15064 /* Check for which cursor types we support */
15065 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
15066 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
15067 state->base.crtc_w, state->base.crtc_h);
15071 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
15072 if (obj->base.size < stride * state->base.crtc_h) {
15073 DRM_DEBUG_KMS("buffer is too small\n");
15077 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
15078 DRM_DEBUG_KMS("cursor cannot be tiled\n");
15083 * There's something wrong with the cursor on CHV pipe C.
15084 * If it straddles the left edge of the screen then
15085 * moving it away from the edge or disabling it often
15086 * results in a pipe underrun, and often that can lead to
15087 * dead pipe (constant underrun reported, and it scans
15088 * out just a solid color). To recover from that, the
15089 * display power well must be turned off and on again.
15090 * Refuse the put the cursor into that compromised position.
15092 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
15093 state->base.visible && state->base.crtc_x < 0) {
15094 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
15102 intel_disable_cursor_plane(struct drm_plane *plane,
15103 struct drm_crtc *crtc)
15105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15107 intel_crtc->cursor_addr = 0;
15108 intel_crtc_update_cursor(crtc, NULL);
15112 intel_update_cursor_plane(struct drm_plane *plane,
15113 const struct intel_crtc_state *crtc_state,
15114 const struct intel_plane_state *state)
15116 struct drm_crtc *crtc = crtc_state->base.crtc;
15117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
15118 struct drm_device *dev = plane->dev;
15119 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
15124 else if (!INTEL_INFO(dev)->cursor_needs_physical)
15125 addr = i915_gem_object_ggtt_offset(obj, NULL);
15127 addr = obj->phys_handle->busaddr;
15129 intel_crtc->cursor_addr = addr;
15130 intel_crtc_update_cursor(crtc, state);
15133 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
15136 struct intel_plane *cursor = NULL;
15137 struct intel_plane_state *state = NULL;
15140 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
15144 state = intel_create_plane_state(&cursor->base);
15147 cursor->base.state = &state->base;
15149 cursor->can_scale = false;
15150 cursor->max_downscale = 1;
15151 cursor->pipe = pipe;
15152 cursor->plane = pipe;
15153 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
15154 cursor->check_plane = intel_check_cursor_plane;
15155 cursor->update_plane = intel_update_cursor_plane;
15156 cursor->disable_plane = intel_disable_cursor_plane;
15158 ret = drm_universal_plane_init(dev, &cursor->base, 0,
15159 &intel_plane_funcs,
15160 intel_cursor_formats,
15161 ARRAY_SIZE(intel_cursor_formats),
15162 DRM_PLANE_TYPE_CURSOR,
15163 "cursor %c", pipe_name(pipe));
15167 if (INTEL_INFO(dev)->gen >= 4) {
15168 if (!dev->mode_config.rotation_property)
15169 dev->mode_config.rotation_property =
15170 drm_mode_create_rotation_property(dev,
15173 if (dev->mode_config.rotation_property)
15174 drm_object_attach_property(&cursor->base.base,
15175 dev->mode_config.rotation_property,
15176 state->base.rotation);
15179 if (INTEL_INFO(dev)->gen >=9)
15180 state->scaler_id = -1;
15182 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
15184 return &cursor->base;
15193 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
15194 struct intel_crtc_state *crtc_state)
15197 struct intel_scaler *intel_scaler;
15198 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
15200 for (i = 0; i < intel_crtc->num_scalers; i++) {
15201 intel_scaler = &scaler_state->scalers[i];
15202 intel_scaler->in_use = 0;
15203 intel_scaler->mode = PS_SCALER_MODE_DYN;
15206 scaler_state->scaler_id = -1;
15209 static void intel_crtc_init(struct drm_device *dev, int pipe)
15211 struct drm_i915_private *dev_priv = to_i915(dev);
15212 struct intel_crtc *intel_crtc;
15213 struct intel_crtc_state *crtc_state = NULL;
15214 struct drm_plane *primary = NULL;
15215 struct drm_plane *cursor = NULL;
15218 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
15219 if (intel_crtc == NULL)
15222 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
15225 intel_crtc->config = crtc_state;
15226 intel_crtc->base.state = &crtc_state->base;
15227 crtc_state->base.crtc = &intel_crtc->base;
15229 /* initialize shared scalers */
15230 if (INTEL_INFO(dev)->gen >= 9) {
15231 if (pipe == PIPE_C)
15232 intel_crtc->num_scalers = 1;
15234 intel_crtc->num_scalers = SKL_NUM_SCALERS;
15236 skl_init_scalers(dev, intel_crtc, crtc_state);
15239 primary = intel_primary_plane_create(dev, pipe);
15243 cursor = intel_cursor_plane_create(dev, pipe);
15247 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
15248 cursor, &intel_crtc_funcs,
15249 "pipe %c", pipe_name(pipe));
15254 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
15255 * is hooked to pipe B. Hence we want plane A feeding pipe B.
15257 intel_crtc->pipe = pipe;
15258 intel_crtc->plane = pipe;
15259 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
15260 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
15261 intel_crtc->plane = !pipe;
15264 intel_crtc->cursor_base = ~0;
15265 intel_crtc->cursor_cntl = ~0;
15266 intel_crtc->cursor_size = ~0;
15268 intel_crtc->wm.cxsr_allowed = true;
15270 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
15271 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
15272 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
15273 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
15275 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
15277 intel_color_init(&intel_crtc->base);
15279 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
15283 intel_plane_destroy(primary);
15284 intel_plane_destroy(cursor);
15289 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
15291 struct drm_encoder *encoder = connector->base.encoder;
15292 struct drm_device *dev = connector->base.dev;
15294 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
15296 if (!encoder || WARN_ON(!encoder->crtc))
15297 return INVALID_PIPE;
15299 return to_intel_crtc(encoder->crtc)->pipe;
15302 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
15303 struct drm_file *file)
15305 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
15306 struct drm_crtc *drmmode_crtc;
15307 struct intel_crtc *crtc;
15309 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
15313 crtc = to_intel_crtc(drmmode_crtc);
15314 pipe_from_crtc_id->pipe = crtc->pipe;
15319 static int intel_encoder_clones(struct intel_encoder *encoder)
15321 struct drm_device *dev = encoder->base.dev;
15322 struct intel_encoder *source_encoder;
15323 int index_mask = 0;
15326 for_each_intel_encoder(dev, source_encoder) {
15327 if (encoders_cloneable(encoder, source_encoder))
15328 index_mask |= (1 << entry);
15336 static bool has_edp_a(struct drm_device *dev)
15338 struct drm_i915_private *dev_priv = to_i915(dev);
15340 if (!IS_MOBILE(dev))
15343 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
15346 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
15352 static bool intel_crt_present(struct drm_device *dev)
15354 struct drm_i915_private *dev_priv = to_i915(dev);
15356 if (INTEL_INFO(dev)->gen >= 9)
15359 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
15362 if (IS_CHERRYVIEW(dev))
15365 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
15368 /* DDI E can't be used if DDI A requires 4 lanes */
15369 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
15372 if (!dev_priv->vbt.int_crt_support)
15378 void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
15383 if (HAS_DDI(dev_priv))
15386 * This w/a is needed at least on CPT/PPT, but to be sure apply it
15387 * everywhere where registers can be write protected.
15389 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15394 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
15395 u32 val = I915_READ(PP_CONTROL(pps_idx));
15397 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
15398 I915_WRITE(PP_CONTROL(pps_idx), val);
15402 static void intel_pps_init(struct drm_i915_private *dev_priv)
15404 if (HAS_PCH_SPLIT(dev_priv) || IS_BROXTON(dev_priv))
15405 dev_priv->pps_mmio_base = PCH_PPS_BASE;
15406 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15407 dev_priv->pps_mmio_base = VLV_PPS_BASE;
15409 dev_priv->pps_mmio_base = PPS_BASE;
15411 intel_pps_unlock_regs_wa(dev_priv);
15414 static void intel_setup_outputs(struct drm_device *dev)
15416 struct drm_i915_private *dev_priv = to_i915(dev);
15417 struct intel_encoder *encoder;
15418 bool dpd_is_edp = false;
15420 intel_pps_init(dev_priv);
15423 * intel_edp_init_connector() depends on this completing first, to
15424 * prevent the registeration of both eDP and LVDS and the incorrect
15425 * sharing of the PPS.
15427 intel_lvds_init(dev);
15429 if (intel_crt_present(dev))
15430 intel_crt_init(dev);
15432 if (IS_BROXTON(dev)) {
15434 * FIXME: Broxton doesn't support port detection via the
15435 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
15436 * detect the ports.
15438 intel_ddi_init(dev, PORT_A);
15439 intel_ddi_init(dev, PORT_B);
15440 intel_ddi_init(dev, PORT_C);
15442 intel_dsi_init(dev);
15443 } else if (HAS_DDI(dev)) {
15447 * Haswell uses DDI functions to detect digital outputs.
15448 * On SKL pre-D0 the strap isn't connected, so we assume
15451 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
15452 /* WaIgnoreDDIAStrap: skl */
15453 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15454 intel_ddi_init(dev, PORT_A);
15456 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
15458 found = I915_READ(SFUSE_STRAP);
15460 if (found & SFUSE_STRAP_DDIB_DETECTED)
15461 intel_ddi_init(dev, PORT_B);
15462 if (found & SFUSE_STRAP_DDIC_DETECTED)
15463 intel_ddi_init(dev, PORT_C);
15464 if (found & SFUSE_STRAP_DDID_DETECTED)
15465 intel_ddi_init(dev, PORT_D);
15467 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
15469 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
15470 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
15471 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
15472 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
15473 intel_ddi_init(dev, PORT_E);
15475 } else if (HAS_PCH_SPLIT(dev)) {
15477 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
15479 if (has_edp_a(dev))
15480 intel_dp_init(dev, DP_A, PORT_A);
15482 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
15483 /* PCH SDVOB multiplex with HDMIB */
15484 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
15486 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
15487 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
15488 intel_dp_init(dev, PCH_DP_B, PORT_B);
15491 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
15492 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
15494 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
15495 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
15497 if (I915_READ(PCH_DP_C) & DP_DETECTED)
15498 intel_dp_init(dev, PCH_DP_C, PORT_C);
15500 if (I915_READ(PCH_DP_D) & DP_DETECTED)
15501 intel_dp_init(dev, PCH_DP_D, PORT_D);
15502 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15503 bool has_edp, has_port;
15506 * The DP_DETECTED bit is the latched state of the DDC
15507 * SDA pin at boot. However since eDP doesn't require DDC
15508 * (no way to plug in a DP->HDMI dongle) the DDC pins for
15509 * eDP ports may have been muxed to an alternate function.
15510 * Thus we can't rely on the DP_DETECTED bit alone to detect
15511 * eDP ports. Consult the VBT as well as DP_DETECTED to
15512 * detect eDP ports.
15514 * Sadly the straps seem to be missing sometimes even for HDMI
15515 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
15516 * and VBT for the presence of the port. Additionally we can't
15517 * trust the port type the VBT declares as we've seen at least
15518 * HDMI ports that the VBT claim are DP or eDP.
15520 has_edp = intel_dp_is_edp(dev, PORT_B);
15521 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
15522 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
15523 has_edp &= intel_dp_init(dev, VLV_DP_B, PORT_B);
15524 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
15525 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
15527 has_edp = intel_dp_is_edp(dev, PORT_C);
15528 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
15529 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
15530 has_edp &= intel_dp_init(dev, VLV_DP_C, PORT_C);
15531 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
15532 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
15534 if (IS_CHERRYVIEW(dev)) {
15536 * eDP not supported on port D,
15537 * so no need to worry about it
15539 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
15540 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
15541 intel_dp_init(dev, CHV_DP_D, PORT_D);
15542 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
15543 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
15546 intel_dsi_init(dev);
15547 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
15548 bool found = false;
15550 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15551 DRM_DEBUG_KMS("probing SDVOB\n");
15552 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
15553 if (!found && IS_G4X(dev)) {
15554 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
15555 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
15558 if (!found && IS_G4X(dev))
15559 intel_dp_init(dev, DP_B, PORT_B);
15562 /* Before G4X SDVOC doesn't have its own detect register */
15564 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
15565 DRM_DEBUG_KMS("probing SDVOC\n");
15566 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
15569 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
15572 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
15573 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
15576 intel_dp_init(dev, DP_C, PORT_C);
15580 (I915_READ(DP_D) & DP_DETECTED))
15581 intel_dp_init(dev, DP_D, PORT_D);
15582 } else if (IS_GEN2(dev))
15583 intel_dvo_init(dev);
15585 if (SUPPORTS_TV(dev))
15586 intel_tv_init(dev);
15588 intel_psr_init(dev);
15590 for_each_intel_encoder(dev, encoder) {
15591 encoder->base.possible_crtcs = encoder->crtc_mask;
15592 encoder->base.possible_clones =
15593 intel_encoder_clones(encoder);
15596 intel_init_pch_refclk(dev);
15598 drm_helper_move_panel_connectors_to_head(dev);
15601 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
15603 struct drm_device *dev = fb->dev;
15604 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15606 drm_framebuffer_cleanup(fb);
15607 mutex_lock(&dev->struct_mutex);
15608 WARN_ON(!intel_fb->obj->framebuffer_references--);
15609 i915_gem_object_put(intel_fb->obj);
15610 mutex_unlock(&dev->struct_mutex);
15614 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
15615 struct drm_file *file,
15616 unsigned int *handle)
15618 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15619 struct drm_i915_gem_object *obj = intel_fb->obj;
15621 if (obj->userptr.mm) {
15622 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
15626 return drm_gem_handle_create(file, &obj->base, handle);
15629 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
15630 struct drm_file *file,
15631 unsigned flags, unsigned color,
15632 struct drm_clip_rect *clips,
15633 unsigned num_clips)
15635 struct drm_device *dev = fb->dev;
15636 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
15637 struct drm_i915_gem_object *obj = intel_fb->obj;
15639 mutex_lock(&dev->struct_mutex);
15640 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
15641 mutex_unlock(&dev->struct_mutex);
15646 static const struct drm_framebuffer_funcs intel_fb_funcs = {
15647 .destroy = intel_user_framebuffer_destroy,
15648 .create_handle = intel_user_framebuffer_create_handle,
15649 .dirty = intel_user_framebuffer_dirty,
15653 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
15654 uint32_t pixel_format)
15656 u32 gen = INTEL_INFO(dev)->gen;
15659 int cpp = drm_format_plane_cpp(pixel_format, 0);
15661 /* "The stride in bytes must not exceed the of the size of 8K
15662 * pixels and 32K bytes."
15664 return min(8192 * cpp, 32768);
15665 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15667 } else if (gen >= 4) {
15668 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15672 } else if (gen >= 3) {
15673 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
15678 /* XXX DSPC is limited to 4k tiled */
15683 static int intel_framebuffer_init(struct drm_device *dev,
15684 struct intel_framebuffer *intel_fb,
15685 struct drm_mode_fb_cmd2 *mode_cmd,
15686 struct drm_i915_gem_object *obj)
15688 struct drm_i915_private *dev_priv = to_i915(dev);
15689 unsigned int tiling = i915_gem_object_get_tiling(obj);
15691 u32 pitch_limit, stride_alignment;
15694 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
15696 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
15698 * If there's a fence, enforce that
15699 * the fb modifier and tiling mode match.
15701 if (tiling != I915_TILING_NONE &&
15702 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15703 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
15707 if (tiling == I915_TILING_X) {
15708 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
15709 } else if (tiling == I915_TILING_Y) {
15710 DRM_DEBUG("No Y tiling for legacy addfb\n");
15715 /* Passed in modifier sanity checking. */
15716 switch (mode_cmd->modifier[0]) {
15717 case I915_FORMAT_MOD_Y_TILED:
15718 case I915_FORMAT_MOD_Yf_TILED:
15719 if (INTEL_INFO(dev)->gen < 9) {
15720 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
15721 mode_cmd->modifier[0]);
15724 case DRM_FORMAT_MOD_NONE:
15725 case I915_FORMAT_MOD_X_TILED:
15728 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
15729 mode_cmd->modifier[0]);
15734 * gen2/3 display engine uses the fence if present,
15735 * so the tiling mode must match the fb modifier exactly.
15737 if (INTEL_INFO(dev_priv)->gen < 4 &&
15738 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
15739 DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n");
15743 stride_alignment = intel_fb_stride_alignment(dev_priv,
15744 mode_cmd->modifier[0],
15745 mode_cmd->pixel_format);
15746 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
15747 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
15748 mode_cmd->pitches[0], stride_alignment);
15752 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
15753 mode_cmd->pixel_format);
15754 if (mode_cmd->pitches[0] > pitch_limit) {
15755 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
15756 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
15757 "tiled" : "linear",
15758 mode_cmd->pitches[0], pitch_limit);
15763 * If there's a fence, enforce that
15764 * the fb pitch and fence stride match.
15766 if (tiling != I915_TILING_NONE &&
15767 mode_cmd->pitches[0] != i915_gem_object_get_stride(obj)) {
15768 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
15769 mode_cmd->pitches[0],
15770 i915_gem_object_get_stride(obj));
15774 /* Reject formats not supported by any plane early. */
15775 switch (mode_cmd->pixel_format) {
15776 case DRM_FORMAT_C8:
15777 case DRM_FORMAT_RGB565:
15778 case DRM_FORMAT_XRGB8888:
15779 case DRM_FORMAT_ARGB8888:
15781 case DRM_FORMAT_XRGB1555:
15782 if (INTEL_INFO(dev)->gen > 3) {
15783 format_name = drm_get_format_name(mode_cmd->pixel_format);
15784 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15785 kfree(format_name);
15789 case DRM_FORMAT_ABGR8888:
15790 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
15791 INTEL_INFO(dev)->gen < 9) {
15792 format_name = drm_get_format_name(mode_cmd->pixel_format);
15793 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15794 kfree(format_name);
15798 case DRM_FORMAT_XBGR8888:
15799 case DRM_FORMAT_XRGB2101010:
15800 case DRM_FORMAT_XBGR2101010:
15801 if (INTEL_INFO(dev)->gen < 4) {
15802 format_name = drm_get_format_name(mode_cmd->pixel_format);
15803 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15804 kfree(format_name);
15808 case DRM_FORMAT_ABGR2101010:
15809 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
15810 format_name = drm_get_format_name(mode_cmd->pixel_format);
15811 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15812 kfree(format_name);
15816 case DRM_FORMAT_YUYV:
15817 case DRM_FORMAT_UYVY:
15818 case DRM_FORMAT_YVYU:
15819 case DRM_FORMAT_VYUY:
15820 if (INTEL_INFO(dev)->gen < 5) {
15821 format_name = drm_get_format_name(mode_cmd->pixel_format);
15822 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15823 kfree(format_name);
15828 format_name = drm_get_format_name(mode_cmd->pixel_format);
15829 DRM_DEBUG("unsupported pixel format: %s\n", format_name);
15830 kfree(format_name);
15834 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
15835 if (mode_cmd->offsets[0] != 0)
15838 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
15839 intel_fb->obj = obj;
15841 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
15845 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
15847 DRM_ERROR("framebuffer init failed %d\n", ret);
15851 intel_fb->obj->framebuffer_references++;
15856 static struct drm_framebuffer *
15857 intel_user_framebuffer_create(struct drm_device *dev,
15858 struct drm_file *filp,
15859 const struct drm_mode_fb_cmd2 *user_mode_cmd)
15861 struct drm_framebuffer *fb;
15862 struct drm_i915_gem_object *obj;
15863 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
15865 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
15867 return ERR_PTR(-ENOENT);
15869 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
15871 i915_gem_object_put_unlocked(obj);
15876 #ifndef CONFIG_DRM_FBDEV_EMULATION
15877 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
15882 static const struct drm_mode_config_funcs intel_mode_funcs = {
15883 .fb_create = intel_user_framebuffer_create,
15884 .output_poll_changed = intel_fbdev_output_poll_changed,
15885 .atomic_check = intel_atomic_check,
15886 .atomic_commit = intel_atomic_commit,
15887 .atomic_state_alloc = intel_atomic_state_alloc,
15888 .atomic_state_clear = intel_atomic_state_clear,
15892 * intel_init_display_hooks - initialize the display modesetting hooks
15893 * @dev_priv: device private
15895 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
15897 if (INTEL_INFO(dev_priv)->gen >= 9) {
15898 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15899 dev_priv->display.get_initial_plane_config =
15900 skylake_get_initial_plane_config;
15901 dev_priv->display.crtc_compute_clock =
15902 haswell_crtc_compute_clock;
15903 dev_priv->display.crtc_enable = haswell_crtc_enable;
15904 dev_priv->display.crtc_disable = haswell_crtc_disable;
15905 } else if (HAS_DDI(dev_priv)) {
15906 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15907 dev_priv->display.get_initial_plane_config =
15908 ironlake_get_initial_plane_config;
15909 dev_priv->display.crtc_compute_clock =
15910 haswell_crtc_compute_clock;
15911 dev_priv->display.crtc_enable = haswell_crtc_enable;
15912 dev_priv->display.crtc_disable = haswell_crtc_disable;
15913 } else if (HAS_PCH_SPLIT(dev_priv)) {
15914 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15915 dev_priv->display.get_initial_plane_config =
15916 ironlake_get_initial_plane_config;
15917 dev_priv->display.crtc_compute_clock =
15918 ironlake_crtc_compute_clock;
15919 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15920 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15921 } else if (IS_CHERRYVIEW(dev_priv)) {
15922 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15923 dev_priv->display.get_initial_plane_config =
15924 i9xx_get_initial_plane_config;
15925 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
15926 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15927 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15928 } else if (IS_VALLEYVIEW(dev_priv)) {
15929 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15930 dev_priv->display.get_initial_plane_config =
15931 i9xx_get_initial_plane_config;
15932 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
15933 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15934 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15935 } else if (IS_G4X(dev_priv)) {
15936 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15937 dev_priv->display.get_initial_plane_config =
15938 i9xx_get_initial_plane_config;
15939 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
15940 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15941 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15942 } else if (IS_PINEVIEW(dev_priv)) {
15943 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15944 dev_priv->display.get_initial_plane_config =
15945 i9xx_get_initial_plane_config;
15946 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
15947 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15948 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15949 } else if (!IS_GEN2(dev_priv)) {
15950 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15951 dev_priv->display.get_initial_plane_config =
15952 i9xx_get_initial_plane_config;
15953 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15954 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15955 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15957 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15958 dev_priv->display.get_initial_plane_config =
15959 i9xx_get_initial_plane_config;
15960 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
15961 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15962 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15965 /* Returns the core display clock speed */
15966 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
15967 dev_priv->display.get_display_clock_speed =
15968 skylake_get_display_clock_speed;
15969 else if (IS_BROXTON(dev_priv))
15970 dev_priv->display.get_display_clock_speed =
15971 broxton_get_display_clock_speed;
15972 else if (IS_BROADWELL(dev_priv))
15973 dev_priv->display.get_display_clock_speed =
15974 broadwell_get_display_clock_speed;
15975 else if (IS_HASWELL(dev_priv))
15976 dev_priv->display.get_display_clock_speed =
15977 haswell_get_display_clock_speed;
15978 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15979 dev_priv->display.get_display_clock_speed =
15980 valleyview_get_display_clock_speed;
15981 else if (IS_GEN5(dev_priv))
15982 dev_priv->display.get_display_clock_speed =
15983 ilk_get_display_clock_speed;
15984 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
15985 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
15986 dev_priv->display.get_display_clock_speed =
15987 i945_get_display_clock_speed;
15988 else if (IS_GM45(dev_priv))
15989 dev_priv->display.get_display_clock_speed =
15990 gm45_get_display_clock_speed;
15991 else if (IS_CRESTLINE(dev_priv))
15992 dev_priv->display.get_display_clock_speed =
15993 i965gm_get_display_clock_speed;
15994 else if (IS_PINEVIEW(dev_priv))
15995 dev_priv->display.get_display_clock_speed =
15996 pnv_get_display_clock_speed;
15997 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
15998 dev_priv->display.get_display_clock_speed =
15999 g33_get_display_clock_speed;
16000 else if (IS_I915G(dev_priv))
16001 dev_priv->display.get_display_clock_speed =
16002 i915_get_display_clock_speed;
16003 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
16004 dev_priv->display.get_display_clock_speed =
16005 i9xx_misc_get_display_clock_speed;
16006 else if (IS_I915GM(dev_priv))
16007 dev_priv->display.get_display_clock_speed =
16008 i915gm_get_display_clock_speed;
16009 else if (IS_I865G(dev_priv))
16010 dev_priv->display.get_display_clock_speed =
16011 i865_get_display_clock_speed;
16012 else if (IS_I85X(dev_priv))
16013 dev_priv->display.get_display_clock_speed =
16014 i85x_get_display_clock_speed;
16016 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16017 dev_priv->display.get_display_clock_speed =
16018 i830_get_display_clock_speed;
16021 if (IS_GEN5(dev_priv)) {
16022 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
16023 } else if (IS_GEN6(dev_priv)) {
16024 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
16025 } else if (IS_IVYBRIDGE(dev_priv)) {
16026 /* FIXME: detect B0+ stepping and use auto training */
16027 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
16028 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
16029 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
16032 if (IS_BROADWELL(dev_priv)) {
16033 dev_priv->display.modeset_commit_cdclk =
16034 broadwell_modeset_commit_cdclk;
16035 dev_priv->display.modeset_calc_cdclk =
16036 broadwell_modeset_calc_cdclk;
16037 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
16038 dev_priv->display.modeset_commit_cdclk =
16039 valleyview_modeset_commit_cdclk;
16040 dev_priv->display.modeset_calc_cdclk =
16041 valleyview_modeset_calc_cdclk;
16042 } else if (IS_BROXTON(dev_priv)) {
16043 dev_priv->display.modeset_commit_cdclk =
16044 bxt_modeset_commit_cdclk;
16045 dev_priv->display.modeset_calc_cdclk =
16046 bxt_modeset_calc_cdclk;
16047 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
16048 dev_priv->display.modeset_commit_cdclk =
16049 skl_modeset_commit_cdclk;
16050 dev_priv->display.modeset_calc_cdclk =
16051 skl_modeset_calc_cdclk;
16054 if (dev_priv->info.gen >= 9)
16055 dev_priv->display.update_crtcs = skl_update_crtcs;
16057 dev_priv->display.update_crtcs = intel_update_crtcs;
16059 switch (INTEL_INFO(dev_priv)->gen) {
16061 dev_priv->display.queue_flip = intel_gen2_queue_flip;
16065 dev_priv->display.queue_flip = intel_gen3_queue_flip;
16070 dev_priv->display.queue_flip = intel_gen4_queue_flip;
16074 dev_priv->display.queue_flip = intel_gen6_queue_flip;
16077 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
16078 dev_priv->display.queue_flip = intel_gen7_queue_flip;
16081 /* Drop through - unsupported since execlist only. */
16083 /* Default just returns -ENODEV to indicate unsupported */
16084 dev_priv->display.queue_flip = intel_default_queue_flip;
16089 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
16090 * resume, or other times. This quirk makes sure that's the case for
16091 * affected systems.
16093 static void quirk_pipea_force(struct drm_device *dev)
16095 struct drm_i915_private *dev_priv = to_i915(dev);
16097 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
16098 DRM_INFO("applying pipe a force quirk\n");
16101 static void quirk_pipeb_force(struct drm_device *dev)
16103 struct drm_i915_private *dev_priv = to_i915(dev);
16105 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
16106 DRM_INFO("applying pipe b force quirk\n");
16110 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
16112 static void quirk_ssc_force_disable(struct drm_device *dev)
16114 struct drm_i915_private *dev_priv = to_i915(dev);
16115 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
16116 DRM_INFO("applying lvds SSC disable quirk\n");
16120 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
16123 static void quirk_invert_brightness(struct drm_device *dev)
16125 struct drm_i915_private *dev_priv = to_i915(dev);
16126 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
16127 DRM_INFO("applying inverted panel brightness quirk\n");
16130 /* Some VBT's incorrectly indicate no backlight is present */
16131 static void quirk_backlight_present(struct drm_device *dev)
16133 struct drm_i915_private *dev_priv = to_i915(dev);
16134 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
16135 DRM_INFO("applying backlight present quirk\n");
16138 struct intel_quirk {
16140 int subsystem_vendor;
16141 int subsystem_device;
16142 void (*hook)(struct drm_device *dev);
16145 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
16146 struct intel_dmi_quirk {
16147 void (*hook)(struct drm_device *dev);
16148 const struct dmi_system_id (*dmi_id_list)[];
16151 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
16153 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
16157 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
16159 .dmi_id_list = &(const struct dmi_system_id[]) {
16161 .callback = intel_dmi_reverse_brightness,
16162 .ident = "NCR Corporation",
16163 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
16164 DMI_MATCH(DMI_PRODUCT_NAME, ""),
16167 { } /* terminating entry */
16169 .hook = quirk_invert_brightness,
16173 static struct intel_quirk intel_quirks[] = {
16174 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
16175 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
16177 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
16178 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
16180 /* 830 needs to leave pipe A & dpll A up */
16181 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
16183 /* 830 needs to leave pipe B & dpll B up */
16184 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
16186 /* Lenovo U160 cannot use SSC on LVDS */
16187 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
16189 /* Sony Vaio Y cannot use SSC on LVDS */
16190 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
16192 /* Acer Aspire 5734Z must invert backlight brightness */
16193 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
16195 /* Acer/eMachines G725 */
16196 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
16198 /* Acer/eMachines e725 */
16199 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
16201 /* Acer/Packard Bell NCL20 */
16202 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
16204 /* Acer Aspire 4736Z */
16205 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
16207 /* Acer Aspire 5336 */
16208 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
16210 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
16211 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
16213 /* Acer C720 Chromebook (Core i3 4005U) */
16214 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
16216 /* Apple Macbook 2,1 (Core 2 T7400) */
16217 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
16219 /* Apple Macbook 4,1 */
16220 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
16222 /* Toshiba CB35 Chromebook (Celeron 2955U) */
16223 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
16225 /* HP Chromebook 14 (Celeron 2955U) */
16226 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
16228 /* Dell Chromebook 11 */
16229 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
16231 /* Dell Chromebook 11 (2015 version) */
16232 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
16235 static void intel_init_quirks(struct drm_device *dev)
16237 struct pci_dev *d = dev->pdev;
16240 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
16241 struct intel_quirk *q = &intel_quirks[i];
16243 if (d->device == q->device &&
16244 (d->subsystem_vendor == q->subsystem_vendor ||
16245 q->subsystem_vendor == PCI_ANY_ID) &&
16246 (d->subsystem_device == q->subsystem_device ||
16247 q->subsystem_device == PCI_ANY_ID))
16250 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
16251 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
16252 intel_dmi_quirks[i].hook(dev);
16256 /* Disable the VGA plane that we never use */
16257 static void i915_disable_vga(struct drm_device *dev)
16259 struct drm_i915_private *dev_priv = to_i915(dev);
16260 struct pci_dev *pdev = dev_priv->drm.pdev;
16262 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16264 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
16265 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
16266 outb(SR01, VGA_SR_INDEX);
16267 sr1 = inb(VGA_SR_DATA);
16268 outb(sr1 | 1<<5, VGA_SR_DATA);
16269 vga_put(pdev, VGA_RSRC_LEGACY_IO);
16272 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
16273 POSTING_READ(vga_reg);
16276 void intel_modeset_init_hw(struct drm_device *dev)
16278 struct drm_i915_private *dev_priv = to_i915(dev);
16280 intel_update_cdclk(dev);
16282 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16284 intel_init_clock_gating(dev);
16288 * Calculate what we think the watermarks should be for the state we've read
16289 * out of the hardware and then immediately program those watermarks so that
16290 * we ensure the hardware settings match our internal state.
16292 * We can calculate what we think WM's should be by creating a duplicate of the
16293 * current state (which was constructed during hardware readout) and running it
16294 * through the atomic check code to calculate new watermark values in the
16297 static void sanitize_watermarks(struct drm_device *dev)
16299 struct drm_i915_private *dev_priv = to_i915(dev);
16300 struct drm_atomic_state *state;
16301 struct drm_crtc *crtc;
16302 struct drm_crtc_state *cstate;
16303 struct drm_modeset_acquire_ctx ctx;
16307 /* Only supported on platforms that use atomic watermark design */
16308 if (!dev_priv->display.optimize_watermarks)
16312 * We need to hold connection_mutex before calling duplicate_state so
16313 * that the connector loop is protected.
16315 drm_modeset_acquire_init(&ctx, 0);
16317 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16318 if (ret == -EDEADLK) {
16319 drm_modeset_backoff(&ctx);
16321 } else if (WARN_ON(ret)) {
16325 state = drm_atomic_helper_duplicate_state(dev, &ctx);
16326 if (WARN_ON(IS_ERR(state)))
16330 * Hardware readout is the only time we don't want to calculate
16331 * intermediate watermarks (since we don't trust the current
16334 to_intel_atomic_state(state)->skip_intermediate_wm = true;
16336 ret = intel_atomic_check(dev, state);
16339 * If we fail here, it means that the hardware appears to be
16340 * programmed in a way that shouldn't be possible, given our
16341 * understanding of watermark requirements. This might mean a
16342 * mistake in the hardware readout code or a mistake in the
16343 * watermark calculations for a given platform. Raise a WARN
16344 * so that this is noticeable.
16346 * If this actually happens, we'll have to just leave the
16347 * BIOS-programmed watermarks untouched and hope for the best.
16349 WARN(true, "Could not determine valid watermarks for inherited state\n");
16353 /* Write calculated watermark values back */
16354 for_each_crtc_in_state(state, crtc, cstate, i) {
16355 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
16357 cs->wm.need_postvbl_update = true;
16358 dev_priv->display.optimize_watermarks(cs);
16361 drm_atomic_state_free(state);
16363 drm_modeset_drop_locks(&ctx);
16364 drm_modeset_acquire_fini(&ctx);
16367 void intel_modeset_init(struct drm_device *dev)
16369 struct drm_i915_private *dev_priv = to_i915(dev);
16370 struct i915_ggtt *ggtt = &dev_priv->ggtt;
16373 struct intel_crtc *crtc;
16375 drm_mode_config_init(dev);
16377 dev->mode_config.min_width = 0;
16378 dev->mode_config.min_height = 0;
16380 dev->mode_config.preferred_depth = 24;
16381 dev->mode_config.prefer_shadow = 1;
16383 dev->mode_config.allow_fb_modifiers = true;
16385 dev->mode_config.funcs = &intel_mode_funcs;
16387 intel_init_quirks(dev);
16389 intel_init_pm(dev);
16391 if (INTEL_INFO(dev)->num_pipes == 0)
16395 * There may be no VBT; and if the BIOS enabled SSC we can
16396 * just keep using it to avoid unnecessary flicker. Whereas if the
16397 * BIOS isn't using it, don't assume it will work even if the VBT
16398 * indicates as much.
16400 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
16401 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
16404 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
16405 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
16406 bios_lvds_use_ssc ? "en" : "dis",
16407 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
16408 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
16412 if (IS_GEN2(dev)) {
16413 dev->mode_config.max_width = 2048;
16414 dev->mode_config.max_height = 2048;
16415 } else if (IS_GEN3(dev)) {
16416 dev->mode_config.max_width = 4096;
16417 dev->mode_config.max_height = 4096;
16419 dev->mode_config.max_width = 8192;
16420 dev->mode_config.max_height = 8192;
16423 if (IS_845G(dev) || IS_I865G(dev)) {
16424 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
16425 dev->mode_config.cursor_height = 1023;
16426 } else if (IS_GEN2(dev)) {
16427 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
16428 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
16430 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
16431 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
16434 dev->mode_config.fb_base = ggtt->mappable_base;
16436 DRM_DEBUG_KMS("%d display pipe%s available.\n",
16437 INTEL_INFO(dev)->num_pipes,
16438 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
16440 for_each_pipe(dev_priv, pipe) {
16441 intel_crtc_init(dev, pipe);
16442 for_each_sprite(dev_priv, pipe, sprite) {
16443 ret = intel_plane_init(dev, pipe, sprite);
16445 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
16446 pipe_name(pipe), sprite_name(pipe, sprite), ret);
16450 intel_update_czclk(dev_priv);
16451 intel_update_cdclk(dev);
16452 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
16454 intel_shared_dpll_init(dev);
16456 if (dev_priv->max_cdclk_freq == 0)
16457 intel_update_max_cdclk(dev);
16459 /* Just disable it once at startup */
16460 i915_disable_vga(dev);
16461 intel_setup_outputs(dev);
16463 drm_modeset_lock_all(dev);
16464 intel_modeset_setup_hw_state(dev);
16465 drm_modeset_unlock_all(dev);
16467 for_each_intel_crtc(dev, crtc) {
16468 struct intel_initial_plane_config plane_config = {};
16474 * Note that reserving the BIOS fb up front prevents us
16475 * from stuffing other stolen allocations like the ring
16476 * on top. This prevents some ugliness at boot time, and
16477 * can even allow for smooth boot transitions if the BIOS
16478 * fb is large enough for the active pipe configuration.
16480 dev_priv->display.get_initial_plane_config(crtc,
16484 * If the fb is shared between multiple heads, we'll
16485 * just get the first one.
16487 intel_find_initial_plane_obj(crtc, &plane_config);
16491 * Make sure hardware watermarks really match the state we read out.
16492 * Note that we need to do this after reconstructing the BIOS fb's
16493 * since the watermark calculation done here will use pstate->fb.
16495 sanitize_watermarks(dev);
16498 static void intel_enable_pipe_a(struct drm_device *dev)
16500 struct intel_connector *connector;
16501 struct drm_connector *crt = NULL;
16502 struct intel_load_detect_pipe load_detect_temp;
16503 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
16505 /* We can't just switch on the pipe A, we need to set things up with a
16506 * proper mode and output configuration. As a gross hack, enable pipe A
16507 * by enabling the load detect pipe once. */
16508 for_each_intel_connector(dev, connector) {
16509 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
16510 crt = &connector->base;
16518 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
16519 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
16523 intel_check_plane_mapping(struct intel_crtc *crtc)
16525 struct drm_device *dev = crtc->base.dev;
16526 struct drm_i915_private *dev_priv = to_i915(dev);
16529 if (INTEL_INFO(dev)->num_pipes == 1)
16532 val = I915_READ(DSPCNTR(!crtc->plane));
16534 if ((val & DISPLAY_PLANE_ENABLE) &&
16535 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
16541 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
16543 struct drm_device *dev = crtc->base.dev;
16544 struct intel_encoder *encoder;
16546 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
16552 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
16554 struct drm_device *dev = encoder->base.dev;
16555 struct intel_connector *connector;
16557 for_each_connector_on_encoder(dev, &encoder->base, connector)
16563 static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
16564 enum transcoder pch_transcoder)
16566 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
16567 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
16570 static void intel_sanitize_crtc(struct intel_crtc *crtc)
16572 struct drm_device *dev = crtc->base.dev;
16573 struct drm_i915_private *dev_priv = to_i915(dev);
16574 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
16576 /* Clear any frame start delays used for debugging left by the BIOS */
16577 if (!transcoder_is_dsi(cpu_transcoder)) {
16578 i915_reg_t reg = PIPECONF(cpu_transcoder);
16581 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
16584 /* restore vblank interrupts to correct state */
16585 drm_crtc_vblank_reset(&crtc->base);
16586 if (crtc->active) {
16587 struct intel_plane *plane;
16589 drm_crtc_vblank_on(&crtc->base);
16591 /* Disable everything but the primary plane */
16592 for_each_intel_plane_on_crtc(dev, crtc, plane) {
16593 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
16596 plane->disable_plane(&plane->base, &crtc->base);
16600 /* We need to sanitize the plane -> pipe mapping first because this will
16601 * disable the crtc (and hence change the state) if it is wrong. Note
16602 * that gen4+ has a fixed plane -> pipe mapping. */
16603 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
16606 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
16607 crtc->base.base.id, crtc->base.name);
16609 /* Pipe has the wrong plane attached and the plane is active.
16610 * Temporarily change the plane mapping and disable everything
16612 plane = crtc->plane;
16613 to_intel_plane_state(crtc->base.primary->state)->base.visible = true;
16614 crtc->plane = !plane;
16615 intel_crtc_disable_noatomic(&crtc->base);
16616 crtc->plane = plane;
16619 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
16620 crtc->pipe == PIPE_A && !crtc->active) {
16621 /* BIOS forgot to enable pipe A, this mostly happens after
16622 * resume. Force-enable the pipe to fix this, the update_dpms
16623 * call below we restore the pipe to the right state, but leave
16624 * the required bits on. */
16625 intel_enable_pipe_a(dev);
16628 /* Adjust the state of the output pipe according to whether we
16629 * have active connectors/encoders. */
16630 if (crtc->active && !intel_crtc_has_encoders(crtc))
16631 intel_crtc_disable_noatomic(&crtc->base);
16633 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
16635 * We start out with underrun reporting disabled to avoid races.
16636 * For correct bookkeeping mark this on active crtcs.
16638 * Also on gmch platforms we dont have any hardware bits to
16639 * disable the underrun reporting. Which means we need to start
16640 * out with underrun reporting disabled also on inactive pipes,
16641 * since otherwise we'll complain about the garbage we read when
16642 * e.g. coming up after runtime pm.
16644 * No protection against concurrent access is required - at
16645 * worst a fifo underrun happens which also sets this to false.
16647 crtc->cpu_fifo_underrun_disabled = true;
16649 * We track the PCH trancoder underrun reporting state
16650 * within the crtc. With crtc for pipe A housing the underrun
16651 * reporting state for PCH transcoder A, crtc for pipe B housing
16652 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
16653 * and marking underrun reporting as disabled for the non-existing
16654 * PCH transcoders B and C would prevent enabling the south
16655 * error interrupt (see cpt_can_enable_serr_int()).
16657 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
16658 crtc->pch_fifo_underrun_disabled = true;
16662 static void intel_sanitize_encoder(struct intel_encoder *encoder)
16664 struct intel_connector *connector;
16666 /* We need to check both for a crtc link (meaning that the
16667 * encoder is active and trying to read from a pipe) and the
16668 * pipe itself being active. */
16669 bool has_active_crtc = encoder->base.crtc &&
16670 to_intel_crtc(encoder->base.crtc)->active;
16672 connector = intel_encoder_find_connector(encoder);
16673 if (connector && !has_active_crtc) {
16674 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
16675 encoder->base.base.id,
16676 encoder->base.name);
16678 /* Connector is active, but has no active pipe. This is
16679 * fallout from our resume register restoring. Disable
16680 * the encoder manually again. */
16681 if (encoder->base.crtc) {
16682 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
16684 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
16685 encoder->base.base.id,
16686 encoder->base.name);
16687 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16688 if (encoder->post_disable)
16689 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
16691 encoder->base.crtc = NULL;
16693 /* Inconsistent output/port/pipe state happens presumably due to
16694 * a bug in one of the get_hw_state functions. Or someplace else
16695 * in our code, like the register restore mess on resume. Clamp
16696 * things to off as a safer default. */
16698 connector->base.dpms = DRM_MODE_DPMS_OFF;
16699 connector->base.encoder = NULL;
16701 /* Enabled encoders without active connectors will be fixed in
16702 * the crtc fixup. */
16705 void i915_redisable_vga_power_on(struct drm_device *dev)
16707 struct drm_i915_private *dev_priv = to_i915(dev);
16708 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
16710 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
16711 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
16712 i915_disable_vga(dev);
16716 void i915_redisable_vga(struct drm_device *dev)
16718 struct drm_i915_private *dev_priv = to_i915(dev);
16720 /* This function can be called both from intel_modeset_setup_hw_state or
16721 * at a very early point in our resume sequence, where the power well
16722 * structures are not yet restored. Since this function is at a very
16723 * paranoid "someone might have enabled VGA while we were not looking"
16724 * level, just check if the power well is enabled instead of trying to
16725 * follow the "don't touch the power well if we don't need it" policy
16726 * the rest of the driver uses. */
16727 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
16730 i915_redisable_vga_power_on(dev);
16732 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
16735 static bool primary_get_hw_state(struct intel_plane *plane)
16737 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
16739 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
16742 /* FIXME read out full plane state for all planes */
16743 static void readout_plane_state(struct intel_crtc *crtc)
16745 struct drm_plane *primary = crtc->base.primary;
16746 struct intel_plane_state *plane_state =
16747 to_intel_plane_state(primary->state);
16749 plane_state->base.visible = crtc->active &&
16750 primary_get_hw_state(to_intel_plane(primary));
16752 if (plane_state->base.visible)
16753 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
16756 static void intel_modeset_readout_hw_state(struct drm_device *dev)
16758 struct drm_i915_private *dev_priv = to_i915(dev);
16760 struct intel_crtc *crtc;
16761 struct intel_encoder *encoder;
16762 struct intel_connector *connector;
16765 dev_priv->active_crtcs = 0;
16767 for_each_intel_crtc(dev, crtc) {
16768 struct intel_crtc_state *crtc_state = crtc->config;
16770 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
16771 memset(crtc_state, 0, sizeof(*crtc_state));
16772 crtc_state->base.crtc = &crtc->base;
16774 crtc_state->base.active = crtc_state->base.enable =
16775 dev_priv->display.get_pipe_config(crtc, crtc_state);
16777 crtc->base.enabled = crtc_state->base.enable;
16778 crtc->active = crtc_state->base.active;
16780 if (crtc_state->base.active)
16781 dev_priv->active_crtcs |= 1 << crtc->pipe;
16783 readout_plane_state(crtc);
16785 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
16786 crtc->base.base.id, crtc->base.name,
16787 crtc->active ? "enabled" : "disabled");
16790 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16791 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16793 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
16794 &pll->config.hw_state);
16795 pll->config.crtc_mask = 0;
16796 for_each_intel_crtc(dev, crtc) {
16797 if (crtc->active && crtc->config->shared_dpll == pll)
16798 pll->config.crtc_mask |= 1 << crtc->pipe;
16800 pll->active_mask = pll->config.crtc_mask;
16802 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
16803 pll->name, pll->config.crtc_mask, pll->on);
16806 for_each_intel_encoder(dev, encoder) {
16809 if (encoder->get_hw_state(encoder, &pipe)) {
16810 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16811 encoder->base.crtc = &crtc->base;
16812 crtc->config->output_types |= 1 << encoder->type;
16813 encoder->get_config(encoder, crtc->config);
16815 encoder->base.crtc = NULL;
16818 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
16819 encoder->base.base.id,
16820 encoder->base.name,
16821 encoder->base.crtc ? "enabled" : "disabled",
16825 for_each_intel_connector(dev, connector) {
16826 if (connector->get_hw_state(connector)) {
16827 connector->base.dpms = DRM_MODE_DPMS_ON;
16829 encoder = connector->encoder;
16830 connector->base.encoder = &encoder->base;
16832 if (encoder->base.crtc &&
16833 encoder->base.crtc->state->active) {
16835 * This has to be done during hardware readout
16836 * because anything calling .crtc_disable may
16837 * rely on the connector_mask being accurate.
16839 encoder->base.crtc->state->connector_mask |=
16840 1 << drm_connector_index(&connector->base);
16841 encoder->base.crtc->state->encoder_mask |=
16842 1 << drm_encoder_index(&encoder->base);
16846 connector->base.dpms = DRM_MODE_DPMS_OFF;
16847 connector->base.encoder = NULL;
16849 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
16850 connector->base.base.id,
16851 connector->base.name,
16852 connector->base.encoder ? "enabled" : "disabled");
16855 for_each_intel_crtc(dev, crtc) {
16858 crtc->base.hwmode = crtc->config->base.adjusted_mode;
16860 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
16861 if (crtc->base.state->active) {
16862 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
16863 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
16864 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
16867 * The initial mode needs to be set in order to keep
16868 * the atomic core happy. It wants a valid mode if the
16869 * crtc's enabled, so we do the above call.
16871 * At this point some state updated by the connectors
16872 * in their ->detect() callback has not run yet, so
16873 * no recalculation can be done yet.
16875 * Even if we could do a recalculation and modeset
16876 * right now it would cause a double modeset if
16877 * fbdev or userspace chooses a different initial mode.
16879 * If that happens, someone indicated they wanted a
16880 * mode change, which means it's safe to do a full
16883 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
16885 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
16886 pixclk = ilk_pipe_pixel_rate(crtc->config);
16887 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16888 pixclk = crtc->config->base.adjusted_mode.crtc_clock;
16890 WARN_ON(dev_priv->display.modeset_calc_cdclk);
16892 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
16893 if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled)
16894 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
16896 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
16897 update_scanline_offset(crtc);
16900 dev_priv->min_pixclk[crtc->pipe] = pixclk;
16902 intel_pipe_config_sanity_check(dev_priv, crtc->config);
16906 /* Scan out the current hw modeset state,
16907 * and sanitizes it to the current state
16910 intel_modeset_setup_hw_state(struct drm_device *dev)
16912 struct drm_i915_private *dev_priv = to_i915(dev);
16914 struct intel_crtc *crtc;
16915 struct intel_encoder *encoder;
16918 intel_modeset_readout_hw_state(dev);
16920 /* HW state is read out, now we need to sanitize this mess. */
16921 for_each_intel_encoder(dev, encoder) {
16922 intel_sanitize_encoder(encoder);
16925 for_each_pipe(dev_priv, pipe) {
16926 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
16927 intel_sanitize_crtc(crtc);
16928 intel_dump_pipe_config(crtc, crtc->config,
16929 "[setup_hw_state]");
16932 intel_modeset_update_connector_atomic_state(dev);
16934 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
16935 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
16937 if (!pll->on || pll->active_mask)
16940 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
16942 pll->funcs.disable(dev_priv, pll);
16946 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
16947 vlv_wm_get_hw_state(dev);
16948 else if (IS_GEN9(dev))
16949 skl_wm_get_hw_state(dev);
16950 else if (HAS_PCH_SPLIT(dev))
16951 ilk_wm_get_hw_state(dev);
16953 for_each_intel_crtc(dev, crtc) {
16954 unsigned long put_domains;
16956 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
16957 if (WARN_ON(put_domains))
16958 modeset_put_power_domains(dev_priv, put_domains);
16960 intel_display_set_init_power(dev_priv, false);
16962 intel_fbc_init_pipe_state(dev_priv);
16965 void intel_display_resume(struct drm_device *dev)
16967 struct drm_i915_private *dev_priv = to_i915(dev);
16968 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
16969 struct drm_modeset_acquire_ctx ctx;
16972 dev_priv->modeset_restore_state = NULL;
16974 state->acquire_ctx = &ctx;
16977 * This is a cludge because with real atomic modeset mode_config.mutex
16978 * won't be taken. Unfortunately some probed state like
16979 * audio_codec_enable is still protected by mode_config.mutex, so lock
16982 mutex_lock(&dev->mode_config.mutex);
16983 drm_modeset_acquire_init(&ctx, 0);
16986 ret = drm_modeset_lock_all_ctx(dev, &ctx);
16987 if (ret != -EDEADLK)
16990 drm_modeset_backoff(&ctx);
16994 ret = __intel_display_resume(dev, state);
16996 drm_modeset_drop_locks(&ctx);
16997 drm_modeset_acquire_fini(&ctx);
16998 mutex_unlock(&dev->mode_config.mutex);
17001 DRM_ERROR("Restoring old state failed with %i\n", ret);
17002 drm_atomic_state_free(state);
17006 void intel_modeset_gem_init(struct drm_device *dev)
17008 struct drm_i915_private *dev_priv = to_i915(dev);
17009 struct drm_crtc *c;
17010 struct drm_i915_gem_object *obj;
17012 intel_init_gt_powersave(dev_priv);
17014 intel_modeset_init_hw(dev);
17016 intel_setup_overlay(dev_priv);
17019 * Make sure any fbs we allocated at startup are properly
17020 * pinned & fenced. When we do the allocation it's too early
17023 for_each_crtc(dev, c) {
17024 struct i915_vma *vma;
17026 obj = intel_fb_obj(c->primary->fb);
17030 mutex_lock(&dev->struct_mutex);
17031 vma = intel_pin_and_fence_fb_obj(c->primary->fb,
17032 c->primary->state->rotation);
17033 mutex_unlock(&dev->struct_mutex);
17035 DRM_ERROR("failed to pin boot fb on pipe %d\n",
17036 to_intel_crtc(c)->pipe);
17037 drm_framebuffer_unreference(c->primary->fb);
17038 c->primary->fb = NULL;
17039 c->primary->crtc = c->primary->state->crtc = NULL;
17040 update_state_fb(c->primary);
17041 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
17046 int intel_connector_register(struct drm_connector *connector)
17048 struct intel_connector *intel_connector = to_intel_connector(connector);
17051 ret = intel_backlight_device_register(intel_connector);
17061 void intel_connector_unregister(struct drm_connector *connector)
17063 struct intel_connector *intel_connector = to_intel_connector(connector);
17065 intel_backlight_device_unregister(intel_connector);
17066 intel_panel_destroy_backlight(connector);
17069 void intel_modeset_cleanup(struct drm_device *dev)
17071 struct drm_i915_private *dev_priv = to_i915(dev);
17073 intel_disable_gt_powersave(dev_priv);
17076 * Interrupts and polling as the first thing to avoid creating havoc.
17077 * Too much stuff here (turning of connectors, ...) would
17078 * experience fancy races otherwise.
17080 intel_irq_uninstall(dev_priv);
17083 * Due to the hpd irq storm handling the hotplug work can re-arm the
17084 * poll handlers. Hence disable polling after hpd handling is shut down.
17086 drm_kms_helper_poll_fini(dev);
17088 intel_unregister_dsm_handler();
17090 intel_fbc_global_disable(dev_priv);
17092 /* flush any delayed tasks or pending work */
17093 flush_scheduled_work();
17095 drm_mode_config_cleanup(dev);
17097 intel_cleanup_overlay(dev_priv);
17099 intel_cleanup_gt_powersave(dev_priv);
17101 intel_teardown_gmbus(dev);
17104 void intel_connector_attach_encoder(struct intel_connector *connector,
17105 struct intel_encoder *encoder)
17107 connector->encoder = encoder;
17108 drm_mode_connector_attach_encoder(&connector->base,
17113 * set vga decode state - true == enable VGA decode
17115 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
17117 struct drm_i915_private *dev_priv = to_i915(dev);
17118 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
17121 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
17122 DRM_ERROR("failed to read control word\n");
17126 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
17130 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
17132 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
17134 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
17135 DRM_ERROR("failed to write control word\n");
17142 struct intel_display_error_state {
17144 u32 power_well_driver;
17146 int num_transcoders;
17148 struct intel_cursor_error_state {
17153 } cursor[I915_MAX_PIPES];
17155 struct intel_pipe_error_state {
17156 bool power_domain_on;
17159 } pipe[I915_MAX_PIPES];
17161 struct intel_plane_error_state {
17169 } plane[I915_MAX_PIPES];
17171 struct intel_transcoder_error_state {
17172 bool power_domain_on;
17173 enum transcoder cpu_transcoder;
17186 struct intel_display_error_state *
17187 intel_display_capture_error_state(struct drm_i915_private *dev_priv)
17189 struct intel_display_error_state *error;
17190 int transcoders[] = {
17198 if (INTEL_INFO(dev_priv)->num_pipes == 0)
17201 error = kzalloc(sizeof(*error), GFP_ATOMIC);
17205 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
17206 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
17208 for_each_pipe(dev_priv, i) {
17209 error->pipe[i].power_domain_on =
17210 __intel_display_power_is_enabled(dev_priv,
17211 POWER_DOMAIN_PIPE(i));
17212 if (!error->pipe[i].power_domain_on)
17215 error->cursor[i].control = I915_READ(CURCNTR(i));
17216 error->cursor[i].position = I915_READ(CURPOS(i));
17217 error->cursor[i].base = I915_READ(CURBASE(i));
17219 error->plane[i].control = I915_READ(DSPCNTR(i));
17220 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
17221 if (INTEL_GEN(dev_priv) <= 3) {
17222 error->plane[i].size = I915_READ(DSPSIZE(i));
17223 error->plane[i].pos = I915_READ(DSPPOS(i));
17225 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
17226 error->plane[i].addr = I915_READ(DSPADDR(i));
17227 if (INTEL_GEN(dev_priv) >= 4) {
17228 error->plane[i].surface = I915_READ(DSPSURF(i));
17229 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
17232 error->pipe[i].source = I915_READ(PIPESRC(i));
17234 if (HAS_GMCH_DISPLAY(dev_priv))
17235 error->pipe[i].stat = I915_READ(PIPESTAT(i));
17238 /* Note: this does not include DSI transcoders. */
17239 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
17240 if (HAS_DDI(dev_priv))
17241 error->num_transcoders++; /* Account for eDP. */
17243 for (i = 0; i < error->num_transcoders; i++) {
17244 enum transcoder cpu_transcoder = transcoders[i];
17246 error->transcoder[i].power_domain_on =
17247 __intel_display_power_is_enabled(dev_priv,
17248 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
17249 if (!error->transcoder[i].power_domain_on)
17252 error->transcoder[i].cpu_transcoder = cpu_transcoder;
17254 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
17255 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
17256 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
17257 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
17258 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
17259 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
17260 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
17266 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
17269 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
17270 struct drm_device *dev,
17271 struct intel_display_error_state *error)
17273 struct drm_i915_private *dev_priv = to_i915(dev);
17279 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
17280 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
17281 err_printf(m, "PWR_WELL_CTL2: %08x\n",
17282 error->power_well_driver);
17283 for_each_pipe(dev_priv, i) {
17284 err_printf(m, "Pipe [%d]:\n", i);
17285 err_printf(m, " Power: %s\n",
17286 onoff(error->pipe[i].power_domain_on));
17287 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
17288 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
17290 err_printf(m, "Plane [%d]:\n", i);
17291 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
17292 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
17293 if (INTEL_INFO(dev)->gen <= 3) {
17294 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
17295 err_printf(m, " POS: %08x\n", error->plane[i].pos);
17297 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
17298 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
17299 if (INTEL_INFO(dev)->gen >= 4) {
17300 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
17301 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
17304 err_printf(m, "Cursor [%d]:\n", i);
17305 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
17306 err_printf(m, " POS: %08x\n", error->cursor[i].position);
17307 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
17310 for (i = 0; i < error->num_transcoders; i++) {
17311 err_printf(m, "CPU transcoder: %s\n",
17312 transcoder_name(error->transcoder[i].cpu_transcoder));
17313 err_printf(m, " Power: %s\n",
17314 onoff(error->transcoder[i].power_domain_on));
17315 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
17316 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
17317 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
17318 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
17319 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
17320 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
17321 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);