2 * Copyright © 2014-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #ifndef _INTEL_DEVICE_INFO_H_
26 #define _INTEL_DEVICE_INFO_H_
28 #include <uapi/drm/i915_drm.h>
30 #include "display/intel_display.h"
32 #include "gt/intel_engine_types.h"
33 #include "gt/intel_context_types.h"
34 #include "gt/intel_sseu.h"
37 struct drm_i915_private;
39 /* Keep in gen based order, and chronological order within a gen */
41 INTEL_PLATFORM_UNINITIALIZED = 0,
90 * Subplatform bits share the same namespace per parent platform. In other words
91 * it is fine for the same bit to be used on multiple parent platforms.
94 #define INTEL_SUBPLATFORM_BITS (3)
96 /* HSW/BDW/SKL/KBL/CFL */
97 #define INTEL_SUBPLATFORM_ULT (0)
98 #define INTEL_SUBPLATFORM_ULX (1)
101 #define INTEL_SUBPLATFORM_PORTF (0)
103 enum intel_ppgtt_type {
104 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
105 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
106 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
109 #define DEV_INFO_FOR_EACH_FLAG(func) \
112 func(require_force_probe); \
114 /* Keep has_* in alphabetical order */ \
115 func(has_64bit_reloc); \
116 func(gpu_reset_clobbers_display); \
117 func(has_reset_engine); \
118 func(has_fpga_dbg); \
119 func(has_global_mocs); \
123 func(has_logical_ring_contexts); \
124 func(has_logical_ring_elsq); \
125 func(has_logical_ring_preemption); \
126 func(has_master_unit_irq); \
127 func(has_pooled_eu); \
131 func(has_runtime_pm); \
133 func(has_coherent_ggtt); \
134 func(unfenced_needs_alignment); \
135 func(hws_needs_physical);
137 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
138 /* Keep in alphabetical order */ \
139 func(cursor_needs_physical); \
151 func(has_modular_fia); \
154 func(has_psr_hw_tracking); \
155 func(overlay_needs_physical); \
158 struct intel_device_info {
162 u8 gt; /* GT number, 0 if undefined */
163 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
165 enum intel_platform platform;
167 unsigned int dma_mask_size; /* available DMA address bits */
169 enum intel_ppgtt_type ppgtt_type;
170 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
172 unsigned int page_sizes; /* page sizes supported by the HW */
174 u32 memory_regions; /* regions supported by the HW */
176 u32 display_mmio_offset;
179 u8 cpu_transcoder_mask;
183 #define DEFINE_FLAG(name) u8 name:1
184 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
188 #define DEFINE_FLAG(name) u8 name:1
189 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
193 u16 ddb_size; /* in blocks */
194 u8 num_supported_dbuf_slices; /* number of DBuf slices */
196 /* Register offsets for the various display pipes and transcoders */
197 int pipe_offsets[I915_MAX_TRANSCODERS];
198 int trans_offsets[I915_MAX_TRANSCODERS];
199 int cursor_offsets[I915_MAX_PIPES];
202 u32 degamma_lut_size;
204 u32 degamma_lut_tests;
209 struct intel_runtime_info {
211 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
212 * into single runtime conditionals, and also to provide groundwork
213 * for future per platform, or per SKU build optimizations.
215 * Array can be extended when necessary if the corresponding
216 * BUILD_BUG_ON is hit.
218 u32 platform_mask[2];
222 u8 num_sprites[I915_MAX_PIPES];
223 u8 num_scalers[I915_MAX_PIPES];
227 u32 cs_timestamp_frequency_hz;
228 u32 cs_timestamp_period_ns;
231 struct intel_driver_caps {
232 unsigned int scheduler;
233 bool has_logical_contexts:1;
236 const char *intel_platform_name(enum intel_platform platform);
238 void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
239 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
241 void intel_device_info_print_static(const struct intel_device_info *info,
242 struct drm_printer *p);
243 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
244 struct drm_printer *p);
246 void intel_driver_caps_print(const struct intel_driver_caps *caps,
247 struct drm_printer *p);