drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  */
  36
  37 #define I915_CSR_KBL "/*(DEBLOBBED)*/"
  38 /*(DEBLOBBED)*/
  39 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 1)
  40
  41 #define I915_CSR_SKL "/*(DEBLOBBED)*/"
  42 /*(DEBLOBBED)*/
  43 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 26)
  44
  45 #define I915_CSR_BXT "/*(DEBLOBBED)*/"
  46 /*(DEBLOBBED)*/
  47 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  48
  49 #define FIRMWARE_URL  "/*(DEBLOBBED)*/"
  50
  51
  52
  53
  54 #define CSR_MAX_FW_SIZE                 0x2FFF
  55 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  56
  57 struct intel_css_header {
  58         /* 0x09 for DMC */
  59         uint32_t module_type;
  60
  61         /* Includes the DMC specific header in dwords */
  62         uint32_t header_len;
  63
  64         /* always value would be 0x10000 */
  65         uint32_t header_ver;
  66
  67         /* Not used */
  68         uint32_t module_id;
  69
  70         /* Not used */
  71         uint32_t module_vendor;
  72
  73         /* in YYYYMMDD format */
  74         uint32_t date;
  75
  76         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  77         uint32_t size;
  78
  79         /* Not used */
  80         uint32_t key_size;
  81
  82         /* Not used */
  83         uint32_t modulus_size;
  84
  85         /* Not used */
  86         uint32_t exponent_size;
  87
  88         /* Not used */
  89         uint32_t reserved1[12];
  90
  91         /* Major Minor */
  92         uint32_t version;
  93
  94         /* Not used */
  95         uint32_t reserved2[8];
  96
  97         /* Not used */
  98         uint32_t kernel_header_info;
  99 } __packed;
 100
 101 struct intel_fw_info {
 102         uint16_t reserved1;
 103
 104         /* Stepping (A, B, C, ..., *). * is a wildcard */
 105         char stepping;
 106
 107         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 108         char substepping;
 109
 110         uint32_t offset;
 111         uint32_t reserved2;
 112 } __packed;
 113
 114 struct intel_package_header {
 115         /* DMC container header length in dwords */
 116         unsigned char header_len;
 117
 118         /* always value would be 0x01 */
 119         unsigned char header_ver;
 120
 121         unsigned char reserved[10];
 122
 123         /* Number of valid entries in the FWInfo array below */
 124         uint32_t num_entries;
 125
 126         struct intel_fw_info fw_info[20];
 127 } __packed;
 128
 129 struct intel_dmc_header {
 130         /* always value would be 0x40403E3E */
 131         uint32_t signature;
 132
 133         /* DMC binary header length */
 134         unsigned char header_len;
 135
 136         /* 0x01 */
 137         unsigned char header_ver;
 138
 139         /* Reserved */
 140         uint16_t dmcc_ver;
 141
 142         /* Major, Minor */
 143         uint32_t        project;
 144
 145         /* Firmware program size (excluding header) in dwords */
 146         uint32_t        fw_size;
 147
 148         /* Major Minor version */
 149         uint32_t fw_version;
 150
 151         /* Number of valid MMIO cycles present. */
 152         uint32_t mmio_count;
 153
 154         /* MMIO address */
 155         uint32_t mmioaddr[8];
 156
 157         /* MMIO data */
 158         uint32_t mmiodata[8];
 159
 160         /* FW filename  */
 161         unsigned char dfile[32];
 162
 163         uint32_t reserved1[2];
 164 } __packed;
 165
 166 struct stepping_info {
 167         char stepping;
 168         char substepping;
 169 };
 170
 171 static const struct stepping_info kbl_stepping_info[] = {
 172         {'A', '0'}, {'B', '0'}, {'C', '0'},
 173         {'D', '0'}, {'E', '0'}, {'F', '0'},
 174         {'G', '0'}, {'H', '0'}, {'I', '0'},
 175 };
 176
 177 static const struct stepping_info skl_stepping_info[] = {
 178         {'A', '0'}, {'B', '0'}, {'C', '0'},
 179         {'D', '0'}, {'E', '0'}, {'F', '0'},
 180         {'G', '0'}, {'H', '0'}, {'I', '0'},
 181         {'J', '0'}, {'K', '0'}
 182 };
 183
 184 static const struct stepping_info bxt_stepping_info[] = {
 185         {'A', '0'}, {'A', '1'}, {'A', '2'},
 186         {'B', '0'}, {'B', '1'}, {'B', '2'}
 187 };
 188
 189 static const struct stepping_info no_stepping_info = { '*', '*' };
 190
 191 static const struct stepping_info *
 192 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 193 {
 194         const struct stepping_info *si;
 195         unsigned int size;
 196
 197         if (IS_KABYLAKE(dev_priv)) {
 198                 size = ARRAY_SIZE(kbl_stepping_info);
 199                 si = kbl_stepping_info;
 200         } else if (IS_SKYLAKE(dev_priv)) {
 201                 size = ARRAY_SIZE(skl_stepping_info);
 202                 si = skl_stepping_info;
 203         } else if (IS_BROXTON(dev_priv)) {
 204                 size = ARRAY_SIZE(bxt_stepping_info);
 205                 si = bxt_stepping_info;
 206         } else {
 207                 size = 0;
 208         }
 209
 210         if (INTEL_REVID(dev_priv) < size)
 211                 return si + INTEL_REVID(dev_priv);
 212
 213         return &no_stepping_info;
 214 }
 215
 216 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 217 {
 218         uint32_t val, mask;
 219
 220         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 221
 222         if (IS_BROXTON(dev_priv))
 223                 mask |= DC_STATE_DEBUG_MASK_CORES;
 224
 225         /* The below bit doesn't need to be cleared ever afterwards */
 226         val = I915_READ(DC_STATE_DEBUG);
 227         if ((val & mask) != mask) {
 228                 val |= mask;
 229                 I915_WRITE(DC_STATE_DEBUG, val);
 230                 POSTING_READ(DC_STATE_DEBUG);
 231         }
 232 }
 233
 234 /**
 235  * intel_csr_load_program() - write the firmware from memory to register.
 236  * @dev_priv: i915 drm device.
 237  *
 238  * CSR firmware is read from a .bin file and kept in internal memory one time.
 239  * Everytime display comes back from low power state this function is called to
 240  * copy the firmware from internal memory to registers.
 241  */
 242 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 243 {
 244         u32 *payload = dev_priv->csr.dmc_payload;
 245         uint32_t i, fw_size;
 246
 247         if (!IS_GEN9(dev_priv)) {
 248                 DRM_ERROR("No CSR support available for this platform\n");
 249                 return;
 250         }
 251
 252         if (!dev_priv->csr.dmc_payload) {
 253                 DRM_ERROR("Tried to program CSR with empty payload\n");
 254                 return;
 255         }
 256
 257         fw_size = dev_priv->csr.dmc_fw_size;
 258         for (i = 0; i < fw_size; i++)
 259                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
 260
 261         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 262                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 263                            dev_priv->csr.mmiodata[i]);
 264         }
 265
 266         dev_priv->csr.dc_state = 0;
 267
 268         gen9_set_dc_state_debugmask(dev_priv);
 269 }
 270
 271 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 272                               const struct firmware *fw)
 273 {
 274         struct intel_css_header *css_header;
 275         struct intel_package_header *package_header;
 276         struct intel_dmc_header *dmc_header;
 277         struct intel_csr *csr = &dev_priv->csr;
 278         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 279         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 280         uint32_t i;
 281         uint32_t *dmc_payload;
 282         uint32_t required_version;
 283         size_t fsize;
 284
 285         if (!fw)
 286                 return NULL;
 287
 288         fsize = sizeof(struct intel_css_header) +
 289                 sizeof(struct intel_package_header) +
 290                 sizeof(struct intel_dmc_header);
 291         if (fsize > fw->size)
 292                 goto error_truncated;
 293
 294         /* Extract CSS Header information*/
 295         css_header = (struct intel_css_header *)fw->data;
 296         if (sizeof(struct intel_css_header) !=
 297             (css_header->header_len * 4)) {
 298                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 299                           (css_header->header_len * 4));
 300                 return NULL;
 301         }
 302
 303         csr->version = css_header->version;
 304
 305         if (IS_KABYLAKE(dev_priv)) {
 306                 required_version = KBL_CSR_VERSION_REQUIRED;
 307         } else if (IS_SKYLAKE(dev_priv)) {
 308                 required_version = SKL_CSR_VERSION_REQUIRED;
 309         } else if (IS_BROXTON(dev_priv)) {
 310                 required_version = BXT_CSR_VERSION_REQUIRED;
 311         } else {
 312                 MISSING_CASE(INTEL_REVID(dev_priv));
 313                 required_version = 0;
 314         }
 315
 316         if (csr->version != required_version) {
 317                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 318                          " please use v%u.%u [" FIRMWARE_URL "].\n",
 319                          CSR_VERSION_MAJOR(csr->version),
 320                          CSR_VERSION_MINOR(csr->version),
 321                          CSR_VERSION_MAJOR(required_version),
 322                          CSR_VERSION_MINOR(required_version));
 323                 return NULL;
 324         }
 325
 326         readcount += sizeof(struct intel_css_header);
 327
 328         /* Extract Package Header information*/
 329         package_header = (struct intel_package_header *)
 330                 &fw->data[readcount];
 331         if (sizeof(struct intel_package_header) !=
 332             (package_header->header_len * 4)) {
 333                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 334                           (package_header->header_len * 4));
 335                 return NULL;
 336         }
 337         readcount += sizeof(struct intel_package_header);
 338
 339         /* Search for dmc_offset to find firware binary. */
 340         for (i = 0; i < package_header->num_entries; i++) {
 341                 if (package_header->fw_info[i].substepping == '*' &&
 342                     si->stepping == package_header->fw_info[i].stepping) {
 343                         dmc_offset = package_header->fw_info[i].offset;
 344                         break;
 345                 } else if (si->stepping == package_header->fw_info[i].stepping &&
 346                            si->substepping == package_header->fw_info[i].substepping) {
 347                         dmc_offset = package_header->fw_info[i].offset;
 348                         break;
 349                 } else if (package_header->fw_info[i].stepping == '*' &&
 350                            package_header->fw_info[i].substepping == '*')
 351                         dmc_offset = package_header->fw_info[i].offset;
 352         }
 353         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 354                 DRM_ERROR("Firmware not supported for %c stepping\n",
 355                           si->stepping);
 356                 return NULL;
 357         }
 358         readcount += dmc_offset;
 359         fsize += dmc_offset;
 360         if (fsize > fw->size)
 361                 goto error_truncated;
 362
 363         /* Extract dmc_header information. */
 364         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 365         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 366                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 367                           (dmc_header->header_len));
 368                 return NULL;
 369         }
 370         readcount += sizeof(struct intel_dmc_header);
 371
 372         /* Cache the dmc header info. */
 373         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 374                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 375                           dmc_header->mmio_count);
 376                 return NULL;
 377         }
 378         csr->mmio_count = dmc_header->mmio_count;
 379         for (i = 0; i < dmc_header->mmio_count; i++) {
 380                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 381                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 382                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 383                                   dmc_header->mmioaddr[i]);
 384                         return NULL;
 385                 }
 386                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 387                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 388         }
 389
 390         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 391         nbytes = dmc_header->fw_size * 4;
 392         fsize += nbytes;
 393         if (fsize > fw->size)
 394                 goto error_truncated;
 395
 396         if (nbytes > CSR_MAX_FW_SIZE) {
 397                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 398                 return NULL;
 399         }
 400         csr->dmc_fw_size = dmc_header->fw_size;
 401
 402         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 403         if (!dmc_payload) {
 404                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 405                 return NULL;
 406         }
 407
 408         return memcpy(dmc_payload, &fw->data[readcount], nbytes);
 409
 410 error_truncated:
 411         DRM_ERROR("Truncated DMC firmware, rejecting.\n");
 412         return NULL;
 413 }
 414
 415 static void csr_load_work_fn(struct work_struct *work)
 416 {
 417         struct drm_i915_private *dev_priv;
 418         struct intel_csr *csr;
 419         const struct firmware *fw;
 420         int ret;
 421
 422         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 423         csr = &dev_priv->csr;
 424
 425         ret = reject_firmware(&fw, dev_priv->csr.fw_path,
 426                                &dev_priv->drm.pdev->dev);
 427         if (fw)
 428                 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 429
 430         if (dev_priv->csr.dmc_payload) {
 431                 intel_csr_load_program(dev_priv);
 432
 433                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 434
 435                 DRM_INFO("Finished loading %s (v%u.%u)\n",
 436                          dev_priv->csr.fw_path,
 437                          CSR_VERSION_MAJOR(csr->version),
 438                          CSR_VERSION_MINOR(csr->version));
 439         } else {
 440                 dev_notice(dev_priv->drm.dev,
 441                            "Failed to load DMC firmware"
 442                            " [" FIRMWARE_URL "],"
 443                            " disabling runtime power management.\n");
 444         }
 445
 446         release_firmware(fw);
 447 }
 448
 449 /**
 450  * intel_csr_ucode_init() - initialize the firmware loading.
 451  * @dev_priv: i915 drm device.
 452  *
 453  * This function is called at the time of loading the display driver to read
 454  * firmware from a .bin file and copied into a internal memory.
 455  */
 456 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 457 {
 458         struct intel_csr *csr = &dev_priv->csr;
 459
 460         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 461
 462         if (!HAS_CSR(dev_priv))
 463                 return;
 464
 465         if (IS_KABYLAKE(dev_priv))
 466                 csr->fw_path = I915_CSR_KBL;
 467         else if (IS_SKYLAKE(dev_priv))
 468                 csr->fw_path = I915_CSR_SKL;
 469         else if (IS_BROXTON(dev_priv))
 470                 csr->fw_path = I915_CSR_BXT;
 471         else {
 472                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 473                 return;
 474         }
 475
 476         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 477
 478         /*
 479          * Obtain a runtime pm reference, until CSR is loaded,
 480          * to avoid entering runtime-suspend.
 481          */
 482         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 483
 484         schedule_work(&dev_priv->csr.work);
 485 }
 486
 487 /**
 488  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 489  * @dev_priv: i915 drm device
 490  *
 491  * Prepare the DMC firmware before entering system suspend. This includes
 492  * flushing pending work items and releasing any resources acquired during
 493  * init.
 494  */
 495 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 496 {
 497         if (!HAS_CSR(dev_priv))
 498                 return;
 499
 500         flush_work(&dev_priv->csr.work);
 501
 502         /* Drop the reference held in case DMC isn't loaded. */
 503         if (!dev_priv->csr.dmc_payload)
 504                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 505 }
 506
 507 /**
 508  * intel_csr_ucode_resume() - init CSR firmware during system resume
 509  * @dev_priv: i915 drm device
 510  *
 511  * Reinitialize the DMC firmware during system resume, reacquiring any
 512  * resources released in intel_csr_ucode_suspend().
 513  */
 514 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 515 {
 516         if (!HAS_CSR(dev_priv))
 517                 return;
 518
 519         /*
 520          * Reacquire the reference to keep RPM disabled in case DMC isn't
 521          * loaded.
 522          */
 523         if (!dev_priv->csr.dmc_payload)
 524                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 525 }
 526
 527 /**
 528  * intel_csr_ucode_fini() - unload the CSR firmware.
 529  * @dev_priv: i915 drm device.
 530  *
 531  * Firmmware unloading includes freeing the internal memory and reset the
 532  * firmware loading status.
 533  */
 534 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 535 {
 536         if (!HAS_CSR(dev_priv))
 537                 return;
 538
 539         intel_csr_ucode_suspend(dev_priv);
 540
 541         kfree(dev_priv->csr.dmc_payload);
 542 }