drivers/gpu/drm/i915/intel_csr.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24 #include <linux/firmware.h>
  25 #include "i915_drv.h"
  26 #include "i915_reg.h"
  27
  28 /**
  29  * DOC: csr support for dmc
  30  *
  31  * Display Context Save and Restore (CSR) firmware support added from gen9
  32  * onwards to drive newly added DMC (Display microcontroller) in display
  33  * engine to save and restore the state of display engine when it enter into
  34  * low-power state and comes back to normal.
  35  */
  36
  37 #define I915_CSR_GLK "/*(DEBLOBBED)*/"
  38 #define GLK_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  39
  40 #define I915_CSR_CNL "/*(DEBLOBBED)*/"
  41 #define CNL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 4)
  42
  43 #define I915_CSR_KBL "/*(DEBLOBBED)*/"
  44 /*(DEBLOBBED)*/
  45 #define KBL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 1)
  46
  47 #define I915_CSR_SKL "/*(DEBLOBBED)*/"
  48 /*(DEBLOBBED)*/
  49 #define SKL_CSR_VERSION_REQUIRED        CSR_VERSION(1, 26)
  50
  51 #define I915_CSR_BXT "/*(DEBLOBBED)*/"
  52 /*(DEBLOBBED)*/
  53 #define BXT_CSR_VERSION_REQUIRED        CSR_VERSION(1, 7)
  54
  55 #define FIRMWARE_URL  "/*(DEBLOBBED)*/"
  56
  57
  58
  59
  60 #define CSR_MAX_FW_SIZE                 0x2FFF
  61 #define CSR_DEFAULT_FW_OFFSET           0xFFFFFFFF
  62
  63 struct intel_css_header {
  64         /* 0x09 for DMC */
  65         uint32_t module_type;
  66
  67         /* Includes the DMC specific header in dwords */
  68         uint32_t header_len;
  69
  70         /* always value would be 0x10000 */
  71         uint32_t header_ver;
  72
  73         /* Not used */
  74         uint32_t module_id;
  75
  76         /* Not used */
  77         uint32_t module_vendor;
  78
  79         /* in YYYYMMDD format */
  80         uint32_t date;
  81
  82         /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
  83         uint32_t size;
  84
  85         /* Not used */
  86         uint32_t key_size;
  87
  88         /* Not used */
  89         uint32_t modulus_size;
  90
  91         /* Not used */
  92         uint32_t exponent_size;
  93
  94         /* Not used */
  95         uint32_t reserved1[12];
  96
  97         /* Major Minor */
  98         uint32_t version;
  99
 100         /* Not used */
 101         uint32_t reserved2[8];
 102
 103         /* Not used */
 104         uint32_t kernel_header_info;
 105 } __packed;
 106
 107 struct intel_fw_info {
 108         uint16_t reserved1;
 109
 110         /* Stepping (A, B, C, ..., *). * is a wildcard */
 111         char stepping;
 112
 113         /* Sub-stepping (0, 1, ..., *). * is a wildcard */
 114         char substepping;
 115
 116         uint32_t offset;
 117         uint32_t reserved2;
 118 } __packed;
 119
 120 struct intel_package_header {
 121         /* DMC container header length in dwords */
 122         unsigned char header_len;
 123
 124         /* always value would be 0x01 */
 125         unsigned char header_ver;
 126
 127         unsigned char reserved[10];
 128
 129         /* Number of valid entries in the FWInfo array below */
 130         uint32_t num_entries;
 131
 132         struct intel_fw_info fw_info[20];
 133 } __packed;
 134
 135 struct intel_dmc_header {
 136         /* always value would be 0x40403E3E */
 137         uint32_t signature;
 138
 139         /* DMC binary header length */
 140         unsigned char header_len;
 141
 142         /* 0x01 */
 143         unsigned char header_ver;
 144
 145         /* Reserved */
 146         uint16_t dmcc_ver;
 147
 148         /* Major, Minor */
 149         uint32_t        project;
 150
 151         /* Firmware program size (excluding header) in dwords */
 152         uint32_t        fw_size;
 153
 154         /* Major Minor version */
 155         uint32_t fw_version;
 156
 157         /* Number of valid MMIO cycles present. */
 158         uint32_t mmio_count;
 159
 160         /* MMIO address */
 161         uint32_t mmioaddr[8];
 162
 163         /* MMIO data */
 164         uint32_t mmiodata[8];
 165
 166         /* FW filename  */
 167         unsigned char dfile[32];
 168
 169         uint32_t reserved1[2];
 170 } __packed;
 171
 172 struct stepping_info {
 173         char stepping;
 174         char substepping;
 175 };
 176
 177 static const struct stepping_info skl_stepping_info[] = {
 178         {'A', '0'}, {'B', '0'}, {'C', '0'},
 179         {'D', '0'}, {'E', '0'}, {'F', '0'},
 180         {'G', '0'}, {'H', '0'}, {'I', '0'},
 181         {'J', '0'}, {'K', '0'}
 182 };
 183
 184 static const struct stepping_info bxt_stepping_info[] = {
 185         {'A', '0'}, {'A', '1'}, {'A', '2'},
 186         {'B', '0'}, {'B', '1'}, {'B', '2'}
 187 };
 188
 189 static const struct stepping_info no_stepping_info = { '*', '*' };
 190
 191 static const struct stepping_info *
 192 intel_get_stepping_info(struct drm_i915_private *dev_priv)
 193 {
 194         const struct stepping_info *si;
 195         unsigned int size;
 196
 197         if (IS_SKYLAKE(dev_priv)) {
 198                 size = ARRAY_SIZE(skl_stepping_info);
 199                 si = skl_stepping_info;
 200         } else if (IS_BROXTON(dev_priv)) {
 201                 size = ARRAY_SIZE(bxt_stepping_info);
 202                 si = bxt_stepping_info;
 203         } else {
 204                 size = 0;
 205         }
 206
 207         if (INTEL_REVID(dev_priv) < size)
 208                 return si + INTEL_REVID(dev_priv);
 209
 210         return &no_stepping_info;
 211 }
 212
 213 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
 214 {
 215         uint32_t val, mask;
 216
 217         mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
 218
 219         if (IS_GEN9_LP(dev_priv))
 220                 mask |= DC_STATE_DEBUG_MASK_CORES;
 221
 222         /* The below bit doesn't need to be cleared ever afterwards */
 223         val = I915_READ(DC_STATE_DEBUG);
 224         if ((val & mask) != mask) {
 225                 val |= mask;
 226                 I915_WRITE(DC_STATE_DEBUG, val);
 227                 POSTING_READ(DC_STATE_DEBUG);
 228         }
 229 }
 230
 231 /**
 232  * intel_csr_load_program() - write the firmware from memory to register.
 233  * @dev_priv: i915 drm device.
 234  *
 235  * CSR firmware is read from a .bin file and kept in internal memory one time.
 236  * Everytime display comes back from low power state this function is called to
 237  * copy the firmware from internal memory to registers.
 238  */
 239 void intel_csr_load_program(struct drm_i915_private *dev_priv)
 240 {
 241         u32 *payload = dev_priv->csr.dmc_payload;
 242         uint32_t i, fw_size;
 243
 244         if (!HAS_CSR(dev_priv)) {
 245                 DRM_ERROR("No CSR support available for this platform\n");
 246                 return;
 247         }
 248
 249         if (!dev_priv->csr.dmc_payload) {
 250                 DRM_ERROR("Tried to program CSR with empty payload\n");
 251                 return;
 252         }
 253
 254         fw_size = dev_priv->csr.dmc_fw_size;
 255         for (i = 0; i < fw_size; i++)
 256                 I915_WRITE(CSR_PROGRAM(i), payload[i]);
 257
 258         for (i = 0; i < dev_priv->csr.mmio_count; i++) {
 259                 I915_WRITE(dev_priv->csr.mmioaddr[i],
 260                            dev_priv->csr.mmiodata[i]);
 261         }
 262
 263         dev_priv->csr.dc_state = 0;
 264
 265         gen9_set_dc_state_debugmask(dev_priv);
 266 }
 267
 268 static uint32_t *parse_csr_fw(struct drm_i915_private *dev_priv,
 269                               const struct firmware *fw)
 270 {
 271         struct intel_css_header *css_header;
 272         struct intel_package_header *package_header;
 273         struct intel_dmc_header *dmc_header;
 274         struct intel_csr *csr = &dev_priv->csr;
 275         const struct stepping_info *si = intel_get_stepping_info(dev_priv);
 276         uint32_t dmc_offset = CSR_DEFAULT_FW_OFFSET, readcount = 0, nbytes;
 277         uint32_t i;
 278         uint32_t *dmc_payload;
 279         uint32_t required_version;
 280         size_t fsize;
 281
 282         if (!fw)
 283                 return NULL;
 284
 285         fsize = sizeof(struct intel_css_header) +
 286                 sizeof(struct intel_package_header) +
 287                 sizeof(struct intel_dmc_header);
 288         if (fsize > fw->size)
 289                 goto error_truncated;
 290
 291         /* Extract CSS Header information*/
 292         css_header = (struct intel_css_header *)fw->data;
 293         if (sizeof(struct intel_css_header) !=
 294             (css_header->header_len * 4)) {
 295                 DRM_ERROR("Firmware has wrong CSS header length %u bytes\n",
 296                           (css_header->header_len * 4));
 297                 return NULL;
 298         }
 299
 300         csr->version = css_header->version;
 301
 302         if (IS_CANNONLAKE(dev_priv)) {
 303                 required_version = CNL_CSR_VERSION_REQUIRED;
 304         } else if (IS_GEMINILAKE(dev_priv)) {
 305                 required_version = GLK_CSR_VERSION_REQUIRED;
 306         } else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) {
 307                 required_version = KBL_CSR_VERSION_REQUIRED;
 308         } else if (IS_SKYLAKE(dev_priv)) {
 309                 required_version = SKL_CSR_VERSION_REQUIRED;
 310         } else if (IS_BROXTON(dev_priv)) {
 311                 required_version = BXT_CSR_VERSION_REQUIRED;
 312         } else {
 313                 MISSING_CASE(INTEL_REVID(dev_priv));
 314                 required_version = 0;
 315         }
 316
 317         if (csr->version != required_version) {
 318                 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
 319                          " please use v%u.%u [" FIRMWARE_URL "].\n",
 320                          CSR_VERSION_MAJOR(csr->version),
 321                          CSR_VERSION_MINOR(csr->version),
 322                          CSR_VERSION_MAJOR(required_version),
 323                          CSR_VERSION_MINOR(required_version));
 324                 return NULL;
 325         }
 326
 327         readcount += sizeof(struct intel_css_header);
 328
 329         /* Extract Package Header information*/
 330         package_header = (struct intel_package_header *)
 331                 &fw->data[readcount];
 332         if (sizeof(struct intel_package_header) !=
 333             (package_header->header_len * 4)) {
 334                 DRM_ERROR("Firmware has wrong package header length %u bytes\n",
 335                           (package_header->header_len * 4));
 336                 return NULL;
 337         }
 338         readcount += sizeof(struct intel_package_header);
 339
 340         /* Search for dmc_offset to find firware binary. */
 341         for (i = 0; i < package_header->num_entries; i++) {
 342                 if (package_header->fw_info[i].substepping == '*' &&
 343                     si->stepping == package_header->fw_info[i].stepping) {
 344                         dmc_offset = package_header->fw_info[i].offset;
 345                         break;
 346                 } else if (si->stepping == package_header->fw_info[i].stepping &&
 347                            si->substepping == package_header->fw_info[i].substepping) {
 348                         dmc_offset = package_header->fw_info[i].offset;
 349                         break;
 350                 } else if (package_header->fw_info[i].stepping == '*' &&
 351                            package_header->fw_info[i].substepping == '*')
 352                         dmc_offset = package_header->fw_info[i].offset;
 353         }
 354         if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
 355                 DRM_ERROR("Firmware not supported for %c stepping\n",
 356                           si->stepping);
 357                 return NULL;
 358         }
 359         readcount += dmc_offset;
 360         fsize += dmc_offset;
 361         if (fsize > fw->size)
 362                 goto error_truncated;
 363
 364         /* Extract dmc_header information. */
 365         dmc_header = (struct intel_dmc_header *)&fw->data[readcount];
 366         if (sizeof(struct intel_dmc_header) != (dmc_header->header_len)) {
 367                 DRM_ERROR("Firmware has wrong dmc header length %u bytes\n",
 368                           (dmc_header->header_len));
 369                 return NULL;
 370         }
 371         readcount += sizeof(struct intel_dmc_header);
 372
 373         /* Cache the dmc header info. */
 374         if (dmc_header->mmio_count > ARRAY_SIZE(csr->mmioaddr)) {
 375                 DRM_ERROR("Firmware has wrong mmio count %u\n",
 376                           dmc_header->mmio_count);
 377                 return NULL;
 378         }
 379         csr->mmio_count = dmc_header->mmio_count;
 380         for (i = 0; i < dmc_header->mmio_count; i++) {
 381                 if (dmc_header->mmioaddr[i] < CSR_MMIO_START_RANGE ||
 382                     dmc_header->mmioaddr[i] > CSR_MMIO_END_RANGE) {
 383                         DRM_ERROR(" Firmware has wrong mmio address 0x%x\n",
 384                                   dmc_header->mmioaddr[i]);
 385                         return NULL;
 386                 }
 387                 csr->mmioaddr[i] = _MMIO(dmc_header->mmioaddr[i]);
 388                 csr->mmiodata[i] = dmc_header->mmiodata[i];
 389         }
 390
 391         /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
 392         nbytes = dmc_header->fw_size * 4;
 393         fsize += nbytes;
 394         if (fsize > fw->size)
 395                 goto error_truncated;
 396
 397         if (nbytes > CSR_MAX_FW_SIZE) {
 398                 DRM_ERROR("CSR firmware too big (%u) bytes\n", nbytes);
 399                 return NULL;
 400         }
 401         csr->dmc_fw_size = dmc_header->fw_size;
 402
 403         dmc_payload = kmalloc(nbytes, GFP_KERNEL);
 404         if (!dmc_payload) {
 405                 DRM_ERROR("Memory allocation failed for dmc payload\n");
 406                 return NULL;
 407         }
 408
 409         return memcpy(dmc_payload, &fw->data[readcount], nbytes);
 410
 411 error_truncated:
 412         DRM_ERROR("Truncated DMC firmware, rejecting.\n");
 413         return NULL;
 414 }
 415
 416 static void csr_load_work_fn(struct work_struct *work)
 417 {
 418         struct drm_i915_private *dev_priv;
 419         struct intel_csr *csr;
 420         const struct firmware *fw = NULL;
 421
 422         dev_priv = container_of(work, typeof(*dev_priv), csr.work);
 423         csr = &dev_priv->csr;
 424
 425         reject_firmware(&fw, dev_priv->csr.fw_path, &dev_priv->drm.pdev->dev);
 426         if (fw)
 427                 dev_priv->csr.dmc_payload = parse_csr_fw(dev_priv, fw);
 428
 429         if (dev_priv->csr.dmc_payload) {
 430                 intel_csr_load_program(dev_priv);
 431
 432                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 433
 434                 DRM_INFO("Finished loading DMC firmware %s (v%u.%u)\n",
 435                          dev_priv->csr.fw_path,
 436                          CSR_VERSION_MAJOR(csr->version),
 437                          CSR_VERSION_MINOR(csr->version));
 438         } else {
 439                 dev_notice(dev_priv->drm.dev,
 440                            "Failed to load DMC firmware"
 441                            " [" FIRMWARE_URL "],"
 442                            " disabling runtime power management.\n");
 443         }
 444
 445         release_firmware(fw);
 446 }
 447
 448 /**
 449  * intel_csr_ucode_init() - initialize the firmware loading.
 450  * @dev_priv: i915 drm device.
 451  *
 452  * This function is called at the time of loading the display driver to read
 453  * firmware from a .bin file and copied into a internal memory.
 454  */
 455 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 456 {
 457         struct intel_csr *csr = &dev_priv->csr;
 458
 459         INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
 460
 461         if (!HAS_CSR(dev_priv))
 462                 return;
 463
 464         if (IS_CANNONLAKE(dev_priv))
 465                 csr->fw_path = I915_CSR_CNL;
 466         else if (IS_GEMINILAKE(dev_priv))
 467                 csr->fw_path = I915_CSR_GLK;
 468         else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
 469                 csr->fw_path = I915_CSR_KBL;
 470         else if (IS_SKYLAKE(dev_priv))
 471                 csr->fw_path = I915_CSR_SKL;
 472         else if (IS_BROXTON(dev_priv))
 473                 csr->fw_path = I915_CSR_BXT;
 474         else {
 475                 DRM_ERROR("Unexpected: no known CSR firmware for platform\n");
 476                 return;
 477         }
 478
 479         DRM_DEBUG_KMS("Loading %s\n", csr->fw_path);
 480
 481         /*
 482          * Obtain a runtime pm reference, until CSR is loaded,
 483          * to avoid entering runtime-suspend.
 484          */
 485         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 486
 487         schedule_work(&dev_priv->csr.work);
 488 }
 489
 490 /**
 491  * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
 492  * @dev_priv: i915 drm device
 493  *
 494  * Prepare the DMC firmware before entering system suspend. This includes
 495  * flushing pending work items and releasing any resources acquired during
 496  * init.
 497  */
 498 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
 499 {
 500         if (!HAS_CSR(dev_priv))
 501                 return;
 502
 503         flush_work(&dev_priv->csr.work);
 504
 505         /* Drop the reference held in case DMC isn't loaded. */
 506         if (!dev_priv->csr.dmc_payload)
 507                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 508 }
 509
 510 /**
 511  * intel_csr_ucode_resume() - init CSR firmware during system resume
 512  * @dev_priv: i915 drm device
 513  *
 514  * Reinitialize the DMC firmware during system resume, reacquiring any
 515  * resources released in intel_csr_ucode_suspend().
 516  */
 517 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
 518 {
 519         if (!HAS_CSR(dev_priv))
 520                 return;
 521
 522         /*
 523          * Reacquire the reference to keep RPM disabled in case DMC isn't
 524          * loaded.
 525          */
 526         if (!dev_priv->csr.dmc_payload)
 527                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 528 }
 529
 530 /**
 531  * intel_csr_ucode_fini() - unload the CSR firmware.
 532  * @dev_priv: i915 drm device.
 533  *
 534  * Firmmware unloading includes freeing the internal memory and reset the
 535  * firmware loading status.
 536  */
 537 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
 538 {
 539         if (!HAS_CSR(dev_priv))
 540                 return;
 541
 542         intel_csr_ucode_suspend(dev_priv);
 543
 544         kfree(dev_priv->csr.dmc_payload);
 545 }