drivers/gpu/drm/i915/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "intel_drv.h"
  25
  26 /**
  27  * DOC: CDCLK / RAWCLK
  28  *
  29  * The display engine uses several different clocks to do its work. There
  30  * are two main clocks involved that aren't directly related to the actual
  31  * pixel clock or any symbol/bit clock of the actual output port. These
  32  * are the core display clock (CDCLK) and RAWCLK.
  33  *
  34  * CDCLK clocks most of the display pipe logic, and thus its frequency
  35  * must be high enough to support the rate at which pixels are flowing
  36  * through the pipes. Downscaling must also be accounted as that increases
  37  * the effective pixel rate.
  38  *
  39  * On several platforms the CDCLK frequency can be changed dynamically
  40  * to minimize power consumption for a given display configuration.
  41  * Typically changes to the CDCLK frequency require all the display pipes
  42  * to be shut down while the frequency is being changed.
  43  *
  44  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  45  * DMC will not change the active CDCLK frequency however, so that part
  46  * will still be performed by the driver directly.
  47  *
  48  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  49  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  50  * really need to know about RAWCLK is its frequency so that various
  51  * dividers can be programmed correctly.
  52  */
  53
  54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
  55                                    struct intel_cdclk_state *cdclk_state)
  56 {
  57         cdclk_state->cdclk = 133333;
  58 }
  59
  60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
  61                                    struct intel_cdclk_state *cdclk_state)
  62 {
  63         cdclk_state->cdclk = 200000;
  64 }
  65
  66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
  67                                    struct intel_cdclk_state *cdclk_state)
  68 {
  69         cdclk_state->cdclk = 266667;
  70 }
  71
  72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
  73                                    struct intel_cdclk_state *cdclk_state)
  74 {
  75         cdclk_state->cdclk = 333333;
  76 }
  77
  78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
  79                                    struct intel_cdclk_state *cdclk_state)
  80 {
  81         cdclk_state->cdclk = 400000;
  82 }
  83
  84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
  85                                    struct intel_cdclk_state *cdclk_state)
  86 {
  87         cdclk_state->cdclk = 450000;
  88 }
  89
  90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
  91                            struct intel_cdclk_state *cdclk_state)
  92 {
  93         struct pci_dev *pdev = dev_priv->drm.pdev;
  94         u16 hpllcc = 0;
  95
  96         /*
  97          * 852GM/852GMV only supports 133 MHz and the HPLLCC
  98          * encoding is different :(
  99          * FIXME is this the right way to detect 852GM/852GMV?
 100          */
 101         if (pdev->revision == 0x1) {
 102                 cdclk_state->cdclk = 133333;
 103                 return;
 104         }
 105
 106         pci_bus_read_config_word(pdev->bus,
 107                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 108
 109         /* Assume that the hardware is in the high speed state.  This
 110          * should be the default.
 111          */
 112         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 113         case GC_CLOCK_133_200:
 114         case GC_CLOCK_133_200_2:
 115         case GC_CLOCK_100_200:
 116                 cdclk_state->cdclk = 200000;
 117                 break;
 118         case GC_CLOCK_166_250:
 119                 cdclk_state->cdclk = 250000;
 120                 break;
 121         case GC_CLOCK_100_133:
 122                 cdclk_state->cdclk = 133333;
 123                 break;
 124         case GC_CLOCK_133_266:
 125         case GC_CLOCK_133_266_2:
 126         case GC_CLOCK_166_266:
 127                 cdclk_state->cdclk = 266667;
 128                 break;
 129         }
 130 }
 131
 132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 133                              struct intel_cdclk_state *cdclk_state)
 134 {
 135         struct pci_dev *pdev = dev_priv->drm.pdev;
 136         u16 gcfgc = 0;
 137
 138         pci_read_config_word(pdev, GCFGC, &gcfgc);
 139
 140         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 141                 cdclk_state->cdclk = 133333;
 142                 return;
 143         }
 144
 145         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 146         case GC_DISPLAY_CLOCK_333_320_MHZ:
 147                 cdclk_state->cdclk = 333333;
 148                 break;
 149         default:
 150         case GC_DISPLAY_CLOCK_190_200_MHZ:
 151                 cdclk_state->cdclk = 190000;
 152                 break;
 153         }
 154 }
 155
 156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 157                              struct intel_cdclk_state *cdclk_state)
 158 {
 159         struct pci_dev *pdev = dev_priv->drm.pdev;
 160         u16 gcfgc = 0;
 161
 162         pci_read_config_word(pdev, GCFGC, &gcfgc);
 163
 164         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 165                 cdclk_state->cdclk = 133333;
 166                 return;
 167         }
 168
 169         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 170         case GC_DISPLAY_CLOCK_333_320_MHZ:
 171                 cdclk_state->cdclk = 320000;
 172                 break;
 173         default:
 174         case GC_DISPLAY_CLOCK_190_200_MHZ:
 175                 cdclk_state->cdclk = 200000;
 176                 break;
 177         }
 178 }
 179
 180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 181 {
 182         static const unsigned int blb_vco[8] = {
 183                 [0] = 3200000,
 184                 [1] = 4000000,
 185                 [2] = 5333333,
 186                 [3] = 4800000,
 187                 [4] = 6400000,
 188         };
 189         static const unsigned int pnv_vco[8] = {
 190                 [0] = 3200000,
 191                 [1] = 4000000,
 192                 [2] = 5333333,
 193                 [3] = 4800000,
 194                 [4] = 2666667,
 195         };
 196         static const unsigned int cl_vco[8] = {
 197                 [0] = 3200000,
 198                 [1] = 4000000,
 199                 [2] = 5333333,
 200                 [3] = 6400000,
 201                 [4] = 3333333,
 202                 [5] = 3566667,
 203                 [6] = 4266667,
 204         };
 205         static const unsigned int elk_vco[8] = {
 206                 [0] = 3200000,
 207                 [1] = 4000000,
 208                 [2] = 5333333,
 209                 [3] = 4800000,
 210         };
 211         static const unsigned int ctg_vco[8] = {
 212                 [0] = 3200000,
 213                 [1] = 4000000,
 214                 [2] = 5333333,
 215                 [3] = 6400000,
 216                 [4] = 2666667,
 217                 [5] = 4266667,
 218         };
 219         const unsigned int *vco_table;
 220         unsigned int vco;
 221         uint8_t tmp = 0;
 222
 223         /* FIXME other chipsets? */
 224         if (IS_GM45(dev_priv))
 225                 vco_table = ctg_vco;
 226         else if (IS_G45(dev_priv))
 227                 vco_table = elk_vco;
 228         else if (IS_I965GM(dev_priv))
 229                 vco_table = cl_vco;
 230         else if (IS_PINEVIEW(dev_priv))
 231                 vco_table = pnv_vco;
 232         else if (IS_G33(dev_priv))
 233                 vco_table = blb_vco;
 234         else
 235                 return 0;
 236
 237         tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 238
 239         vco = vco_table[tmp & 0x7];
 240         if (vco == 0)
 241                 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
 242         else
 243                 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
 244
 245         return vco;
 246 }
 247
 248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 249                           struct intel_cdclk_state *cdclk_state)
 250 {
 251         struct pci_dev *pdev = dev_priv->drm.pdev;
 252         static const uint8_t div_3200[] = { 12, 10,  8,  7, 5, 16 };
 253         static const uint8_t div_4000[] = { 14, 12, 10,  8, 6, 20 };
 254         static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
 255         static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
 256         const uint8_t *div_table;
 257         unsigned int cdclk_sel;
 258         uint16_t tmp = 0;
 259
 260         cdclk_state->vco = intel_hpll_vco(dev_priv);
 261
 262         pci_read_config_word(pdev, GCFGC, &tmp);
 263
 264         cdclk_sel = (tmp >> 4) & 0x7;
 265
 266         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 267                 goto fail;
 268
 269         switch (cdclk_state->vco) {
 270         case 3200000:
 271                 div_table = div_3200;
 272                 break;
 273         case 4000000:
 274                 div_table = div_4000;
 275                 break;
 276         case 4800000:
 277                 div_table = div_4800;
 278                 break;
 279         case 5333333:
 280                 div_table = div_5333;
 281                 break;
 282         default:
 283                 goto fail;
 284         }
 285
 286         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 287                                                div_table[cdclk_sel]);
 288         return;
 289
 290 fail:
 291         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 292                   cdclk_state->vco, tmp);
 293         cdclk_state->cdclk = 190476;
 294 }
 295
 296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 297                           struct intel_cdclk_state *cdclk_state)
 298 {
 299         struct pci_dev *pdev = dev_priv->drm.pdev;
 300         u16 gcfgc = 0;
 301
 302         pci_read_config_word(pdev, GCFGC, &gcfgc);
 303
 304         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 305         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 306                 cdclk_state->cdclk = 266667;
 307                 break;
 308         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 309                 cdclk_state->cdclk = 333333;
 310                 break;
 311         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 312                 cdclk_state->cdclk = 444444;
 313                 break;
 314         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 315                 cdclk_state->cdclk = 200000;
 316                 break;
 317         default:
 318                 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
 319         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 320                 cdclk_state->cdclk = 133333;
 321                 break;
 322         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 323                 cdclk_state->cdclk = 166667;
 324                 break;
 325         }
 326 }
 327
 328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 329                              struct intel_cdclk_state *cdclk_state)
 330 {
 331         struct pci_dev *pdev = dev_priv->drm.pdev;
 332         static const uint8_t div_3200[] = { 16, 10,  8 };
 333         static const uint8_t div_4000[] = { 20, 12, 10 };
 334         static const uint8_t div_5333[] = { 24, 16, 14 };
 335         const uint8_t *div_table;
 336         unsigned int cdclk_sel;
 337         uint16_t tmp = 0;
 338
 339         cdclk_state->vco = intel_hpll_vco(dev_priv);
 340
 341         pci_read_config_word(pdev, GCFGC, &tmp);
 342
 343         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 344
 345         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 346                 goto fail;
 347
 348         switch (cdclk_state->vco) {
 349         case 3200000:
 350                 div_table = div_3200;
 351                 break;
 352         case 4000000:
 353                 div_table = div_4000;
 354                 break;
 355         case 5333333:
 356                 div_table = div_5333;
 357                 break;
 358         default:
 359                 goto fail;
 360         }
 361
 362         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
 363                                                div_table[cdclk_sel]);
 364         return;
 365
 366 fail:
 367         DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 368                   cdclk_state->vco, tmp);
 369         cdclk_state->cdclk = 200000;
 370 }
 371
 372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 373                            struct intel_cdclk_state *cdclk_state)
 374 {
 375         struct pci_dev *pdev = dev_priv->drm.pdev;
 376         unsigned int cdclk_sel;
 377         uint16_t tmp = 0;
 378
 379         cdclk_state->vco = intel_hpll_vco(dev_priv);
 380
 381         pci_read_config_word(pdev, GCFGC, &tmp);
 382
 383         cdclk_sel = (tmp >> 12) & 0x1;
 384
 385         switch (cdclk_state->vco) {
 386         case 2666667:
 387         case 4000000:
 388         case 5333333:
 389                 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
 390                 break;
 391         case 3200000:
 392                 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
 393                 break;
 394         default:
 395                 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 396                           cdclk_state->vco, tmp);
 397                 cdclk_state->cdclk = 222222;
 398                 break;
 399         }
 400 }
 401
 402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 403                           struct intel_cdclk_state *cdclk_state)
 404 {
 405         uint32_t lcpll = I915_READ(LCPLL_CTL);
 406         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 407
 408         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 409                 cdclk_state->cdclk = 800000;
 410         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 411                 cdclk_state->cdclk = 450000;
 412         else if (freq == LCPLL_CLK_FREQ_450)
 413                 cdclk_state->cdclk = 450000;
 414         else if (IS_HSW_ULT(dev_priv))
 415                 cdclk_state->cdclk = 337500;
 416         else
 417                 cdclk_state->cdclk = 540000;
 418 }
 419
 420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv,
 421                           int max_pixclk)
 422 {
 423         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 424                 333333 : 320000;
 425         int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
 426
 427         /*
 428          * We seem to get an unstable or solid color picture at 200MHz.
 429          * Not sure what's wrong. For now use 200MHz only when all pipes
 430          * are off.
 431          */
 432         if (!IS_CHERRYVIEW(dev_priv) &&
 433             max_pixclk > freq_320*limit/100)
 434                 return 400000;
 435         else if (max_pixclk > 266667*limit/100)
 436                 return freq_320;
 437         else if (max_pixclk > 0)
 438                 return 266667;
 439         else
 440                 return 200000;
 441 }
 442
 443 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 444                           struct intel_cdclk_state *cdclk_state)
 445 {
 446         cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
 447         cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 448                                                CCK_DISPLAY_CLOCK_CONTROL,
 449                                                cdclk_state->vco);
 450 }
 451
 452 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 453 {
 454         unsigned int credits, default_credits;
 455
 456         if (IS_CHERRYVIEW(dev_priv))
 457                 default_credits = PFI_CREDIT(12);
 458         else
 459                 default_credits = PFI_CREDIT(8);
 460
 461         if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 462                 /* CHV suggested value is 31 or 63 */
 463                 if (IS_CHERRYVIEW(dev_priv))
 464                         credits = PFI_CREDIT_63;
 465                 else
 466                         credits = PFI_CREDIT(15);
 467         } else {
 468                 credits = default_credits;
 469         }
 470
 471         /*
 472          * WA - write default credits before re-programming
 473          * FIXME: should we also set the resend bit here?
 474          */
 475         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 476                    default_credits);
 477
 478         I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
 479                    credits | PFI_CREDIT_RESEND);
 480
 481         /*
 482          * FIXME is this guaranteed to clear
 483          * immediately or should we poll for it?
 484          */
 485         WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
 486 }
 487
 488 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 489                           const struct intel_cdclk_state *cdclk_state)
 490 {
 491         int cdclk = cdclk_state->cdclk;
 492         u32 val, cmd;
 493
 494         /* There are cases where we can end up here with power domains
 495          * off and a CDCLK frequency other than the minimum, like when
 496          * issuing a modeset without actually changing any display after
 497          * a system suspend.  So grab the PIPE-A domain, which covers
 498          * the HW blocks needed for the following programming.
 499          */
 500         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 501
 502         if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 503                 cmd = 2;
 504         else if (cdclk == 266667)
 505                 cmd = 1;
 506         else
 507                 cmd = 0;
 508
 509         mutex_lock(&dev_priv->rps.hw_lock);
 510         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 511         val &= ~DSPFREQGUAR_MASK;
 512         val |= (cmd << DSPFREQGUAR_SHIFT);
 513         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 514         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 515                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 516                      50)) {
 517                 DRM_ERROR("timed out waiting for CDclk change\n");
 518         }
 519         mutex_unlock(&dev_priv->rps.hw_lock);
 520
 521         mutex_lock(&dev_priv->sb_lock);
 522
 523         if (cdclk == 400000) {
 524                 u32 divider;
 525
 526                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 527                                             cdclk) - 1;
 528
 529                 /* adjust cdclk divider */
 530                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 531                 val &= ~CCK_FREQUENCY_VALUES;
 532                 val |= divider;
 533                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 534
 535                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 536                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 537                              50))
 538                         DRM_ERROR("timed out waiting for CDclk change\n");
 539         }
 540
 541         /* adjust self-refresh exit latency value */
 542         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 543         val &= ~0x7f;
 544
 545         /*
 546          * For high bandwidth configs, we set a higher latency in the bunit
 547          * so that the core display fetch happens in time to avoid underruns.
 548          */
 549         if (cdclk == 400000)
 550                 val |= 4500 / 250; /* 4.5 usec */
 551         else
 552                 val |= 3000 / 250; /* 3.0 usec */
 553         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 554
 555         mutex_unlock(&dev_priv->sb_lock);
 556
 557         intel_update_cdclk(dev_priv);
 558
 559         vlv_program_pfi_credits(dev_priv);
 560
 561         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 562 }
 563
 564 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 565                           const struct intel_cdclk_state *cdclk_state)
 566 {
 567         int cdclk = cdclk_state->cdclk;
 568         u32 val, cmd;
 569
 570         switch (cdclk) {
 571         case 333333:
 572         case 320000:
 573         case 266667:
 574         case 200000:
 575                 break;
 576         default:
 577                 MISSING_CASE(cdclk);
 578                 return;
 579         }
 580
 581         /* There are cases where we can end up here with power domains
 582          * off and a CDCLK frequency other than the minimum, like when
 583          * issuing a modeset without actually changing any display after
 584          * a system suspend.  So grab the PIPE-A domain, which covers
 585          * the HW blocks needed for the following programming.
 586          */
 587         intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
 588
 589         /*
 590          * Specs are full of misinformation, but testing on actual
 591          * hardware has shown that we just need to write the desired
 592          * CCK divider into the Punit register.
 593          */
 594         cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 595
 596         mutex_lock(&dev_priv->rps.hw_lock);
 597         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 598         val &= ~DSPFREQGUAR_MASK_CHV;
 599         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 600         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 601         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
 602                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 603                      50)) {
 604                 DRM_ERROR("timed out waiting for CDclk change\n");
 605         }
 606         mutex_unlock(&dev_priv->rps.hw_lock);
 607
 608         intel_update_cdclk(dev_priv);
 609
 610         vlv_program_pfi_credits(dev_priv);
 611
 612         intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 613 }
 614
 615 static int bdw_calc_cdclk(int max_pixclk)
 616 {
 617         if (max_pixclk > 540000)
 618                 return 675000;
 619         else if (max_pixclk > 450000)
 620                 return 540000;
 621         else if (max_pixclk > 337500)
 622                 return 450000;
 623         else
 624                 return 337500;
 625 }
 626
 627 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 628                           struct intel_cdclk_state *cdclk_state)
 629 {
 630         uint32_t lcpll = I915_READ(LCPLL_CTL);
 631         uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
 632
 633         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 634                 cdclk_state->cdclk = 800000;
 635         else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
 636                 cdclk_state->cdclk = 450000;
 637         else if (freq == LCPLL_CLK_FREQ_450)
 638                 cdclk_state->cdclk = 450000;
 639         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 640                 cdclk_state->cdclk = 540000;
 641         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 642                 cdclk_state->cdclk = 337500;
 643         else
 644                 cdclk_state->cdclk = 675000;
 645 }
 646
 647 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 648                           const struct intel_cdclk_state *cdclk_state)
 649 {
 650         int cdclk = cdclk_state->cdclk;
 651         uint32_t val, data;
 652         int ret;
 653
 654         if (WARN((I915_READ(LCPLL_CTL) &
 655                   (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 656                    LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 657                    LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 658                    LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 659                  "trying to change cdclk frequency with cdclk not enabled\n"))
 660                 return;
 661
 662         mutex_lock(&dev_priv->rps.hw_lock);
 663         ret = sandybridge_pcode_write(dev_priv,
 664                                       BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 665         mutex_unlock(&dev_priv->rps.hw_lock);
 666         if (ret) {
 667                 DRM_ERROR("failed to inform pcode about cdclk change\n");
 668                 return;
 669         }
 670
 671         val = I915_READ(LCPLL_CTL);
 672         val |= LCPLL_CD_SOURCE_FCLK;
 673         I915_WRITE(LCPLL_CTL, val);
 674
 675         if (wait_for_us(I915_READ(LCPLL_CTL) &
 676                         LCPLL_CD_SOURCE_FCLK_DONE, 1))
 677                 DRM_ERROR("Switching to FCLK failed\n");
 678
 679         val = I915_READ(LCPLL_CTL);
 680         val &= ~LCPLL_CLK_FREQ_MASK;
 681
 682         switch (cdclk) {
 683         case 450000:
 684                 val |= LCPLL_CLK_FREQ_450;
 685                 data = 0;
 686                 break;
 687         case 540000:
 688                 val |= LCPLL_CLK_FREQ_54O_BDW;
 689                 data = 1;
 690                 break;
 691         case 337500:
 692                 val |= LCPLL_CLK_FREQ_337_5_BDW;
 693                 data = 2;
 694                 break;
 695         case 675000:
 696                 val |= LCPLL_CLK_FREQ_675_BDW;
 697                 data = 3;
 698                 break;
 699         default:
 700                 WARN(1, "invalid cdclk frequency\n");
 701                 return;
 702         }
 703
 704         I915_WRITE(LCPLL_CTL, val);
 705
 706         val = I915_READ(LCPLL_CTL);
 707         val &= ~LCPLL_CD_SOURCE_FCLK;
 708         I915_WRITE(LCPLL_CTL, val);
 709
 710         if (wait_for_us((I915_READ(LCPLL_CTL) &
 711                         LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 712                 DRM_ERROR("Switching back to LCPLL failed\n");
 713
 714         mutex_lock(&dev_priv->rps.hw_lock);
 715         sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
 716         mutex_unlock(&dev_priv->rps.hw_lock);
 717
 718         I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 719
 720         intel_update_cdclk(dev_priv);
 721
 722         WARN(cdclk != dev_priv->cdclk.hw.cdclk,
 723              "cdclk requested %d kHz but got %d kHz\n",
 724              cdclk, dev_priv->cdclk.hw.cdclk);
 725 }
 726
 727 static int skl_calc_cdclk(int max_pixclk, int vco)
 728 {
 729         if (vco == 8640000) {
 730                 if (max_pixclk > 540000)
 731                         return 617143;
 732                 else if (max_pixclk > 432000)
 733                         return 540000;
 734                 else if (max_pixclk > 308571)
 735                         return 432000;
 736                 else
 737                         return 308571;
 738         } else {
 739                 if (max_pixclk > 540000)
 740                         return 675000;
 741                 else if (max_pixclk > 450000)
 742                         return 540000;
 743                 else if (max_pixclk > 337500)
 744                         return 450000;
 745                 else
 746                         return 337500;
 747         }
 748 }
 749
 750 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 751                              struct intel_cdclk_state *cdclk_state)
 752 {
 753         u32 val;
 754
 755         cdclk_state->ref = 24000;
 756         cdclk_state->vco = 0;
 757
 758         val = I915_READ(LCPLL1_CTL);
 759         if ((val & LCPLL_PLL_ENABLE) == 0)
 760                 return;
 761
 762         if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
 763                 return;
 764
 765         val = I915_READ(DPLL_CTRL1);
 766
 767         if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 768                             DPLL_CTRL1_SSC(SKL_DPLL0) |
 769                             DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 770                     DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 771                 return;
 772
 773         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 774         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 775         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 776         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 777         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 778                 cdclk_state->vco = 8100000;
 779                 break;
 780         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 781         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 782                 cdclk_state->vco = 8640000;
 783                 break;
 784         default:
 785                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 786                 break;
 787         }
 788 }
 789
 790 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 791                           struct intel_cdclk_state *cdclk_state)
 792 {
 793         u32 cdctl;
 794
 795         skl_dpll0_update(dev_priv, cdclk_state);
 796
 797         cdclk_state->cdclk = cdclk_state->ref;
 798
 799         if (cdclk_state->vco == 0)
 800                 return;
 801
 802         cdctl = I915_READ(CDCLK_CTL);
 803
 804         if (cdclk_state->vco == 8640000) {
 805                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 806                 case CDCLK_FREQ_450_432:
 807                         cdclk_state->cdclk = 432000;
 808                         break;
 809                 case CDCLK_FREQ_337_308:
 810                         cdclk_state->cdclk = 308571;
 811                         break;
 812                 case CDCLK_FREQ_540:
 813                         cdclk_state->cdclk = 540000;
 814                         break;
 815                 case CDCLK_FREQ_675_617:
 816                         cdclk_state->cdclk = 617143;
 817                         break;
 818                 default:
 819                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 820                         break;
 821                 }
 822         } else {
 823                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 824                 case CDCLK_FREQ_450_432:
 825                         cdclk_state->cdclk = 450000;
 826                         break;
 827                 case CDCLK_FREQ_337_308:
 828                         cdclk_state->cdclk = 337500;
 829                         break;
 830                 case CDCLK_FREQ_540:
 831                         cdclk_state->cdclk = 540000;
 832                         break;
 833                 case CDCLK_FREQ_675_617:
 834                         cdclk_state->cdclk = 675000;
 835                         break;
 836                 default:
 837                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 838                         break;
 839                 }
 840         }
 841 }
 842
 843 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 844 static int skl_cdclk_decimal(int cdclk)
 845 {
 846         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 847 }
 848
 849 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 850                                         int vco)
 851 {
 852         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 853
 854         dev_priv->skl_preferred_vco_freq = vco;
 855
 856         if (changed)
 857                 intel_update_max_cdclk(dev_priv);
 858 }
 859
 860 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
 861 {
 862         u32 val;
 863
 864         WARN_ON(vco != 8100000 && vco != 8640000);
 865
 866         /*
 867          * We always enable DPLL0 with the lowest link rate possible, but still
 868          * taking into account the VCO required to operate the eDP panel at the
 869          * desired frequency. The usual DP link rates operate with a VCO of
 870          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
 871          * The modeset code is responsible for the selection of the exact link
 872          * rate later on, with the constraint of choosing a frequency that
 873          * works with vco.
 874          */
 875         val = I915_READ(DPLL_CTRL1);
 876
 877         val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
 878                  DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 879         val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
 880         if (vco == 8640000)
 881                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
 882                                             SKL_DPLL0);
 883         else
 884                 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
 885                                             SKL_DPLL0);
 886
 887         I915_WRITE(DPLL_CTRL1, val);
 888         POSTING_READ(DPLL_CTRL1);
 889
 890         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
 891
 892         if (intel_wait_for_register(dev_priv,
 893                                     LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
 894                                     5))
 895                 DRM_ERROR("DPLL0 not locked\n");
 896
 897         dev_priv->cdclk.hw.vco = vco;
 898
 899         /* We'll want to keep using the current vco from now on. */
 900         skl_set_preferred_cdclk_vco(dev_priv, vco);
 901 }
 902
 903 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
 904 {
 905         I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
 906         if (intel_wait_for_register(dev_priv,
 907                                    LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
 908                                    1))
 909                 DRM_ERROR("Couldn't disable DPLL0\n");
 910
 911         dev_priv->cdclk.hw.vco = 0;
 912 }
 913
 914 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
 915                           const struct intel_cdclk_state *cdclk_state)
 916 {
 917         int cdclk = cdclk_state->cdclk;
 918         int vco = cdclk_state->vco;
 919         u32 freq_select, pcu_ack, cdclk_ctl;
 920         int ret;
 921
 922         WARN_ON((cdclk == 24000) != (vco == 0));
 923
 924         mutex_lock(&dev_priv->rps.hw_lock);
 925         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
 926                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
 927                                 SKL_CDCLK_READY_FOR_CHANGE,
 928                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
 929         mutex_unlock(&dev_priv->rps.hw_lock);
 930         if (ret) {
 931                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
 932                           ret);
 933                 return;
 934         }
 935
 936         /* Choose frequency for this cdclk */
 937         switch (cdclk) {
 938         case 450000:
 939         case 432000:
 940                 freq_select = CDCLK_FREQ_450_432;
 941                 pcu_ack = 1;
 942                 break;
 943         case 540000:
 944                 freq_select = CDCLK_FREQ_540;
 945                 pcu_ack = 2;
 946                 break;
 947         case 308571:
 948         case 337500:
 949         default:
 950                 freq_select = CDCLK_FREQ_337_308;
 951                 pcu_ack = 0;
 952                 break;
 953         case 617143:
 954         case 675000:
 955                 freq_select = CDCLK_FREQ_675_617;
 956                 pcu_ack = 3;
 957                 break;
 958         }
 959
 960         if (dev_priv->cdclk.hw.vco != 0 &&
 961             dev_priv->cdclk.hw.vco != vco)
 962                 skl_dpll0_disable(dev_priv);
 963
 964         cdclk_ctl = I915_READ(CDCLK_CTL);
 965
 966         if (dev_priv->cdclk.hw.vco != vco) {
 967                 /* Wa Display #1183: skl,kbl,cfl */
 968                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
 969                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
 970                 I915_WRITE(CDCLK_CTL, cdclk_ctl);
 971         }
 972
 973         /* Wa Display #1183: skl,kbl,cfl */
 974         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
 975         I915_WRITE(CDCLK_CTL, cdclk_ctl);
 976         POSTING_READ(CDCLK_CTL);
 977
 978         if (dev_priv->cdclk.hw.vco != vco)
 979                 skl_dpll0_enable(dev_priv, vco);
 980
 981         /* Wa Display #1183: skl,kbl,cfl */
 982         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
 983         I915_WRITE(CDCLK_CTL, cdclk_ctl);
 984
 985         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
 986         I915_WRITE(CDCLK_CTL, cdclk_ctl);
 987
 988         /* Wa Display #1183: skl,kbl,cfl */
 989         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
 990         I915_WRITE(CDCLK_CTL, cdclk_ctl);
 991         POSTING_READ(CDCLK_CTL);
 992
 993         /* inform PCU of the change */
 994         mutex_lock(&dev_priv->rps.hw_lock);
 995         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
 996         mutex_unlock(&dev_priv->rps.hw_lock);
 997
 998         intel_update_cdclk(dev_priv);
 999 }
1000
1001 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1002 {
1003         uint32_t cdctl, expected;
1004
1005         /*
1006          * check if the pre-os initialized the display
1007          * There is SWF18 scratchpad register defined which is set by the
1008          * pre-os which can be used by the OS drivers to check the status
1009          */
1010         if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1011                 goto sanitize;
1012
1013         intel_update_cdclk(dev_priv);
1014         /* Is PLL enabled and locked ? */
1015         if (dev_priv->cdclk.hw.vco == 0 ||
1016             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1017                 goto sanitize;
1018
1019         /* DPLL okay; verify the cdclock
1020          *
1021          * Noticed in some instances that the freq selection is correct but
1022          * decimal part is programmed wrong from BIOS where pre-os does not
1023          * enable display. Verify the same as well.
1024          */
1025         cdctl = I915_READ(CDCLK_CTL);
1026         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1027                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1028         if (cdctl == expected)
1029                 /* All well; nothing to sanitize */
1030                 return;
1031
1032 sanitize:
1033         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1034
1035         /* force cdclk programming */
1036         dev_priv->cdclk.hw.cdclk = 0;
1037         /* force full PLL disable + enable */
1038         dev_priv->cdclk.hw.vco = -1;
1039 }
1040
1041 /**
1042  * skl_init_cdclk - Initialize CDCLK on SKL
1043  * @dev_priv: i915 device
1044  *
1045  * Initialize CDCLK for SKL and derivatives. This is generally
1046  * done only during the display core initialization sequence,
1047  * after which the DMC will take care of turning CDCLK off/on
1048  * as needed.
1049  */
1050 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1051 {
1052         struct intel_cdclk_state cdclk_state;
1053
1054         skl_sanitize_cdclk(dev_priv);
1055
1056         if (dev_priv->cdclk.hw.cdclk != 0 &&
1057             dev_priv->cdclk.hw.vco != 0) {
1058                 /*
1059                  * Use the current vco as our initial
1060                  * guess as to what the preferred vco is.
1061                  */
1062                 if (dev_priv->skl_preferred_vco_freq == 0)
1063                         skl_set_preferred_cdclk_vco(dev_priv,
1064                                                     dev_priv->cdclk.hw.vco);
1065                 return;
1066         }
1067
1068         cdclk_state = dev_priv->cdclk.hw;
1069
1070         cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1071         if (cdclk_state.vco == 0)
1072                 cdclk_state.vco = 8100000;
1073         cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1074
1075         skl_set_cdclk(dev_priv, &cdclk_state);
1076 }
1077
1078 /**
1079  * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1080  * @dev_priv: i915 device
1081  *
1082  * Uninitialize CDCLK for SKL and derivatives. This is done only
1083  * during the display core uninitialization sequence.
1084  */
1085 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1086 {
1087         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1088
1089         cdclk_state.cdclk = cdclk_state.ref;
1090         cdclk_state.vco = 0;
1091
1092         skl_set_cdclk(dev_priv, &cdclk_state);
1093 }
1094
1095 static int bxt_calc_cdclk(int max_pixclk)
1096 {
1097         if (max_pixclk > 576000)
1098                 return 624000;
1099         else if (max_pixclk > 384000)
1100                 return 576000;
1101         else if (max_pixclk > 288000)
1102                 return 384000;
1103         else if (max_pixclk > 144000)
1104                 return 288000;
1105         else
1106                 return 144000;
1107 }
1108
1109 static int glk_calc_cdclk(int max_pixclk)
1110 {
1111         /*
1112          * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1113          * as a temporary workaround. Use a higher cdclk instead. (Note that
1114          * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1115          * cdclk.)
1116          */
1117         if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
1118                 return 316800;
1119         else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
1120                 return 158400;
1121         else
1122                 return 79200;
1123 }
1124
1125 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1126 {
1127         int ratio;
1128
1129         if (cdclk == dev_priv->cdclk.hw.ref)
1130                 return 0;
1131
1132         switch (cdclk) {
1133         default:
1134                 MISSING_CASE(cdclk);
1135         case 144000:
1136         case 288000:
1137         case 384000:
1138         case 576000:
1139                 ratio = 60;
1140                 break;
1141         case 624000:
1142                 ratio = 65;
1143                 break;
1144         }
1145
1146         return dev_priv->cdclk.hw.ref * ratio;
1147 }
1148
1149 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1150 {
1151         int ratio;
1152
1153         if (cdclk == dev_priv->cdclk.hw.ref)
1154                 return 0;
1155
1156         switch (cdclk) {
1157         default:
1158                 MISSING_CASE(cdclk);
1159         case  79200:
1160         case 158400:
1161         case 316800:
1162                 ratio = 33;
1163                 break;
1164         }
1165
1166         return dev_priv->cdclk.hw.ref * ratio;
1167 }
1168
1169 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1170                               struct intel_cdclk_state *cdclk_state)
1171 {
1172         u32 val;
1173
1174         cdclk_state->ref = 19200;
1175         cdclk_state->vco = 0;
1176
1177         val = I915_READ(BXT_DE_PLL_ENABLE);
1178         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1179                 return;
1180
1181         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1182                 return;
1183
1184         val = I915_READ(BXT_DE_PLL_CTL);
1185         cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1186 }
1187
1188 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1189                           struct intel_cdclk_state *cdclk_state)
1190 {
1191         u32 divider;
1192         int div;
1193
1194         bxt_de_pll_update(dev_priv, cdclk_state);
1195
1196         cdclk_state->cdclk = cdclk_state->ref;
1197
1198         if (cdclk_state->vco == 0)
1199                 return;
1200
1201         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1202
1203         switch (divider) {
1204         case BXT_CDCLK_CD2X_DIV_SEL_1:
1205                 div = 2;
1206                 break;
1207         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1208                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1209                 div = 3;
1210                 break;
1211         case BXT_CDCLK_CD2X_DIV_SEL_2:
1212                 div = 4;
1213                 break;
1214         case BXT_CDCLK_CD2X_DIV_SEL_4:
1215                 div = 8;
1216                 break;
1217         default:
1218                 MISSING_CASE(divider);
1219                 return;
1220         }
1221
1222         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1223 }
1224
1225 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1226 {
1227         I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1228
1229         /* Timeout 200us */
1230         if (intel_wait_for_register(dev_priv,
1231                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1232                                     1))
1233                 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1234
1235         dev_priv->cdclk.hw.vco = 0;
1236 }
1237
1238 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1239 {
1240         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1241         u32 val;
1242
1243         val = I915_READ(BXT_DE_PLL_CTL);
1244         val &= ~BXT_DE_PLL_RATIO_MASK;
1245         val |= BXT_DE_PLL_RATIO(ratio);
1246         I915_WRITE(BXT_DE_PLL_CTL, val);
1247
1248         I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1249
1250         /* Timeout 200us */
1251         if (intel_wait_for_register(dev_priv,
1252                                     BXT_DE_PLL_ENABLE,
1253                                     BXT_DE_PLL_LOCK,
1254                                     BXT_DE_PLL_LOCK,
1255                                     1))
1256                 DRM_ERROR("timeout waiting for DE PLL lock\n");
1257
1258         dev_priv->cdclk.hw.vco = vco;
1259 }
1260
1261 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1262                           const struct intel_cdclk_state *cdclk_state)
1263 {
1264         int cdclk = cdclk_state->cdclk;
1265         int vco = cdclk_state->vco;
1266         u32 val, divider;
1267         int ret;
1268
1269         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1270         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1271         case 8:
1272                 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1273                 break;
1274         case 4:
1275                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1276                 break;
1277         case 3:
1278                 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1279                 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1280                 break;
1281         case 2:
1282                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1283                 break;
1284         default:
1285                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1286                 WARN_ON(vco != 0);
1287
1288                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1289                 break;
1290         }
1291
1292         mutex_lock(&dev_priv->rps.hw_lock);
1293         /*
1294          * Inform power controller of upcoming frequency change. BSpec
1295          * requires us to wait up to 150usec, but that leads to timeouts;
1296          * the 2ms used here is based on experiment.
1297          */
1298         ret = sandybridge_pcode_write_timeout(dev_priv,
1299                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1300                                               0x80000000, 2000);
1301         mutex_unlock(&dev_priv->rps.hw_lock);
1302
1303         if (ret) {
1304                 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1305                           ret, cdclk);
1306                 return;
1307         }
1308
1309         if (dev_priv->cdclk.hw.vco != 0 &&
1310             dev_priv->cdclk.hw.vco != vco)
1311                 bxt_de_pll_disable(dev_priv);
1312
1313         if (dev_priv->cdclk.hw.vco != vco)
1314                 bxt_de_pll_enable(dev_priv, vco);
1315
1316         val = divider | skl_cdclk_decimal(cdclk);
1317         /*
1318          * FIXME if only the cd2x divider needs changing, it could be done
1319          * without shutting off the pipe (if only one pipe is active).
1320          */
1321         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1322         /*
1323          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1324          * enable otherwise.
1325          */
1326         if (cdclk >= 500000)
1327                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1328         I915_WRITE(CDCLK_CTL, val);
1329
1330         mutex_lock(&dev_priv->rps.hw_lock);
1331         /*
1332          * The timeout isn't specified, the 2ms used here is based on
1333          * experiment.
1334          * FIXME: Waiting for the request completion could be delayed until
1335          * the next PCODE request based on BSpec.
1336          */
1337         ret = sandybridge_pcode_write_timeout(dev_priv,
1338                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1339                                               DIV_ROUND_UP(cdclk, 25000), 2000);
1340         mutex_unlock(&dev_priv->rps.hw_lock);
1341
1342         if (ret) {
1343                 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1344                           ret, cdclk);
1345                 return;
1346         }
1347
1348         intel_update_cdclk(dev_priv);
1349 }
1350
1351 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1352 {
1353         u32 cdctl, expected;
1354
1355         intel_update_cdclk(dev_priv);
1356
1357         if (dev_priv->cdclk.hw.vco == 0 ||
1358             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1359                 goto sanitize;
1360
1361         /* DPLL okay; verify the cdclock
1362          *
1363          * Some BIOS versions leave an incorrect decimal frequency value and
1364          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1365          * so sanitize this register.
1366          */
1367         cdctl = I915_READ(CDCLK_CTL);
1368         /*
1369          * Let's ignore the pipe field, since BIOS could have configured the
1370          * dividers both synching to an active pipe, or asynchronously
1371          * (PIPE_NONE).
1372          */
1373         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1374
1375         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1376                 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1377         /*
1378          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1379          * enable otherwise.
1380          */
1381         if (dev_priv->cdclk.hw.cdclk >= 500000)
1382                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1383
1384         if (cdctl == expected)
1385                 /* All well; nothing to sanitize */
1386                 return;
1387
1388 sanitize:
1389         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1390
1391         /* force cdclk programming */
1392         dev_priv->cdclk.hw.cdclk = 0;
1393
1394         /* force full PLL disable + enable */
1395         dev_priv->cdclk.hw.vco = -1;
1396 }
1397
1398 /**
1399  * bxt_init_cdclk - Initialize CDCLK on BXT
1400  * @dev_priv: i915 device
1401  *
1402  * Initialize CDCLK for BXT and derivatives. This is generally
1403  * done only during the display core initialization sequence,
1404  * after which the DMC will take care of turning CDCLK off/on
1405  * as needed.
1406  */
1407 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1408 {
1409         struct intel_cdclk_state cdclk_state;
1410
1411         bxt_sanitize_cdclk(dev_priv);
1412
1413         if (dev_priv->cdclk.hw.cdclk != 0 &&
1414             dev_priv->cdclk.hw.vco != 0)
1415                 return;
1416
1417         cdclk_state = dev_priv->cdclk.hw;
1418
1419         /*
1420          * FIXME:
1421          * - The initial CDCLK needs to be read from VBT.
1422          *   Need to make this change after VBT has changes for BXT.
1423          */
1424         if (IS_GEMINILAKE(dev_priv)) {
1425                 cdclk_state.cdclk = glk_calc_cdclk(0);
1426                 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1427         } else {
1428                 cdclk_state.cdclk = bxt_calc_cdclk(0);
1429                 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1430         }
1431
1432         bxt_set_cdclk(dev_priv, &cdclk_state);
1433 }
1434
1435 /**
1436  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1437  * @dev_priv: i915 device
1438  *
1439  * Uninitialize CDCLK for BXT and derivatives. This is done only
1440  * during the display core uninitialization sequence.
1441  */
1442 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1443 {
1444         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1445
1446         cdclk_state.cdclk = cdclk_state.ref;
1447         cdclk_state.vco = 0;
1448
1449         bxt_set_cdclk(dev_priv, &cdclk_state);
1450 }
1451
1452 static int cnl_calc_cdclk(int max_pixclk)
1453 {
1454         if (max_pixclk > 336000)
1455                 return 528000;
1456         else if (max_pixclk > 168000)
1457                 return 336000;
1458         else
1459                 return 168000;
1460 }
1461
1462 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1463                                  struct intel_cdclk_state *cdclk_state)
1464 {
1465         u32 val;
1466
1467         if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1468                 cdclk_state->ref = 24000;
1469         else
1470                 cdclk_state->ref = 19200;
1471
1472         cdclk_state->vco = 0;
1473
1474         val = I915_READ(BXT_DE_PLL_ENABLE);
1475         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1476                 return;
1477
1478         if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1479                 return;
1480
1481         cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1482 }
1483
1484 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1485                          struct intel_cdclk_state *cdclk_state)
1486 {
1487         u32 divider;
1488         int div;
1489
1490         cnl_cdclk_pll_update(dev_priv, cdclk_state);
1491
1492         cdclk_state->cdclk = cdclk_state->ref;
1493
1494         if (cdclk_state->vco == 0)
1495                 return;
1496
1497         divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1498
1499         switch (divider) {
1500         case BXT_CDCLK_CD2X_DIV_SEL_1:
1501                 div = 2;
1502                 break;
1503         case BXT_CDCLK_CD2X_DIV_SEL_2:
1504                 div = 4;
1505                 break;
1506         default:
1507                 MISSING_CASE(divider);
1508                 return;
1509         }
1510
1511         cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1512 }
1513
1514 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1515 {
1516         u32 val;
1517
1518         val = I915_READ(BXT_DE_PLL_ENABLE);
1519         val &= ~BXT_DE_PLL_PLL_ENABLE;
1520         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1521
1522         /* Timeout 200us */
1523         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1524                 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1525
1526         dev_priv->cdclk.hw.vco = 0;
1527 }
1528
1529 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1530 {
1531         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1532         u32 val;
1533
1534         val = CNL_CDCLK_PLL_RATIO(ratio);
1535         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1536
1537         val |= BXT_DE_PLL_PLL_ENABLE;
1538         I915_WRITE(BXT_DE_PLL_ENABLE, val);
1539
1540         /* Timeout 200us */
1541         if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1542                 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1543
1544         dev_priv->cdclk.hw.vco = vco;
1545 }
1546
1547 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1548                           const struct intel_cdclk_state *cdclk_state)
1549 {
1550         int cdclk = cdclk_state->cdclk;
1551         int vco = cdclk_state->vco;
1552         u32 val, divider, pcu_ack;
1553         int ret;
1554
1555         mutex_lock(&dev_priv->rps.hw_lock);
1556         ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1557                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1558                                 SKL_CDCLK_READY_FOR_CHANGE,
1559                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1560         mutex_unlock(&dev_priv->rps.hw_lock);
1561         if (ret) {
1562                 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1563                           ret);
1564                 return;
1565         }
1566
1567         /* cdclk = vco / 2 / div{1,2} */
1568         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1569         case 4:
1570                 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1571                 break;
1572         case 2:
1573                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1574                 break;
1575         default:
1576                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1577                 WARN_ON(vco != 0);
1578
1579                 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1580                 break;
1581         }
1582
1583         switch (cdclk) {
1584         case 528000:
1585                 pcu_ack = 2;
1586                 break;
1587         case 336000:
1588                 pcu_ack = 1;
1589                 break;
1590         case 168000:
1591         default:
1592                 pcu_ack = 0;
1593                 break;
1594         }
1595
1596         if (dev_priv->cdclk.hw.vco != 0 &&
1597             dev_priv->cdclk.hw.vco != vco)
1598                 cnl_cdclk_pll_disable(dev_priv);
1599
1600         if (dev_priv->cdclk.hw.vco != vco)
1601                 cnl_cdclk_pll_enable(dev_priv, vco);
1602
1603         val = divider | skl_cdclk_decimal(cdclk);
1604         /*
1605          * FIXME if only the cd2x divider needs changing, it could be done
1606          * without shutting off the pipe (if only one pipe is active).
1607          */
1608         val |= BXT_CDCLK_CD2X_PIPE_NONE;
1609         I915_WRITE(CDCLK_CTL, val);
1610
1611         /* inform PCU of the change */
1612         mutex_lock(&dev_priv->rps.hw_lock);
1613         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1614         mutex_unlock(&dev_priv->rps.hw_lock);
1615
1616         intel_update_cdclk(dev_priv);
1617 }
1618
1619 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1620 {
1621         int ratio;
1622
1623         if (cdclk == dev_priv->cdclk.hw.ref)
1624                 return 0;
1625
1626         switch (cdclk) {
1627         default:
1628                 MISSING_CASE(cdclk);
1629         case 168000:
1630         case 336000:
1631                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1632                 break;
1633         case 528000:
1634                 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1635                 break;
1636         }
1637
1638         return dev_priv->cdclk.hw.ref * ratio;
1639 }
1640
1641 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1642 {
1643         u32 cdctl, expected;
1644
1645         intel_update_cdclk(dev_priv);
1646
1647         if (dev_priv->cdclk.hw.vco == 0 ||
1648             dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1649                 goto sanitize;
1650
1651         /* DPLL okay; verify the cdclock
1652          *
1653          * Some BIOS versions leave an incorrect decimal frequency value and
1654          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1655          * so sanitize this register.
1656          */
1657         cdctl = I915_READ(CDCLK_CTL);
1658         /*
1659          * Let's ignore the pipe field, since BIOS could have configured the
1660          * dividers both synching to an active pipe, or asynchronously
1661          * (PIPE_NONE).
1662          */
1663         cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1664
1665         expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1666                    skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1667
1668         if (cdctl == expected)
1669                 /* All well; nothing to sanitize */
1670                 return;
1671
1672 sanitize:
1673         DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1674
1675         /* force cdclk programming */
1676         dev_priv->cdclk.hw.cdclk = 0;
1677
1678         /* force full PLL disable + enable */
1679         dev_priv->cdclk.hw.vco = -1;
1680 }
1681
1682 /**
1683  * cnl_init_cdclk - Initialize CDCLK on CNL
1684  * @dev_priv: i915 device
1685  *
1686  * Initialize CDCLK for CNL. This is generally
1687  * done only during the display core initialization sequence,
1688  * after which the DMC will take care of turning CDCLK off/on
1689  * as needed.
1690  */
1691 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1692 {
1693         struct intel_cdclk_state cdclk_state;
1694
1695         cnl_sanitize_cdclk(dev_priv);
1696
1697         if (dev_priv->cdclk.hw.cdclk != 0 &&
1698             dev_priv->cdclk.hw.vco != 0)
1699                 return;
1700
1701         cdclk_state = dev_priv->cdclk.hw;
1702
1703         cdclk_state.cdclk = cnl_calc_cdclk(0);
1704         cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1705
1706         cnl_set_cdclk(dev_priv, &cdclk_state);
1707 }
1708
1709 /**
1710  * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1711  * @dev_priv: i915 device
1712  *
1713  * Uninitialize CDCLK for CNL. This is done only
1714  * during the display core uninitialization sequence.
1715  */
1716 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1717 {
1718         struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1719
1720         cdclk_state.cdclk = cdclk_state.ref;
1721         cdclk_state.vco = 0;
1722
1723         cnl_set_cdclk(dev_priv, &cdclk_state);
1724 }
1725
1726 /**
1727  * intel_cdclk_state_compare - Determine if two CDCLK states differ
1728  * @a: first CDCLK state
1729  * @b: second CDCLK state
1730  *
1731  * Returns:
1732  * True if the CDCLK states are identical, false if they differ.
1733  */
1734 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1735                                const struct intel_cdclk_state *b)
1736 {
1737         return memcmp(a, b, sizeof(*a)) == 0;
1738 }
1739
1740 /**
1741  * intel_set_cdclk - Push the CDCLK state to the hardware
1742  * @dev_priv: i915 device
1743  * @cdclk_state: new CDCLK state
1744  *
1745  * Program the hardware based on the passed in CDCLK state,
1746  * if necessary.
1747  */
1748 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1749                      const struct intel_cdclk_state *cdclk_state)
1750 {
1751         if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
1752                 return;
1753
1754         if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1755                 return;
1756
1757         DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1758                          cdclk_state->cdclk, cdclk_state->vco,
1759                          cdclk_state->ref);
1760
1761         dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1762 }
1763
1764 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
1765                                           int pixel_rate)
1766 {
1767         struct drm_i915_private *dev_priv =
1768                 to_i915(crtc_state->base.crtc->dev);
1769
1770         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1771         if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1772                 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
1773
1774         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1775          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1776          * there may be audio corruption or screen corruption." This cdclk
1777          * restriction for GLK is 316.8 MHz and since GLK can output two
1778          * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.
1779          */
1780         if (intel_crtc_has_dp_encoder(crtc_state) &&
1781             crtc_state->has_audio &&
1782             crtc_state->port_clock >= 540000 &&
1783             crtc_state->lane_count == 4) {
1784                 if (IS_CANNONLAKE(dev_priv))
1785                         pixel_rate = max(316800, pixel_rate);
1786                 else if (IS_GEMINILAKE(dev_priv))
1787                         pixel_rate = max(2 * 316800, pixel_rate);
1788                 else
1789                         pixel_rate = max(432000, pixel_rate);
1790         }
1791
1792         /* According to BSpec, "The CD clock frequency must be at least twice
1793          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1794          * The check for GLK has to be adjusted as the platform can output
1795          * two pixels per clock.
1796          */
1797         if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
1798                 if (IS_GEMINILAKE(dev_priv))
1799                         pixel_rate = max(2 * 2 * 96000, pixel_rate);
1800                 else
1801                         pixel_rate = max(2 * 96000, pixel_rate);
1802         }
1803
1804         return pixel_rate;
1805 }
1806
1807 /* compute the max rate for new configuration */
1808 static int intel_max_pixel_rate(struct drm_atomic_state *state)
1809 {
1810         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1811         struct drm_i915_private *dev_priv = to_i915(state->dev);
1812         struct drm_crtc *crtc;
1813         struct drm_crtc_state *cstate;
1814         struct intel_crtc_state *crtc_state;
1815         unsigned int max_pixel_rate = 0, i;
1816         enum pipe pipe;
1817
1818         memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
1819                sizeof(intel_state->min_pixclk));
1820
1821         for_each_new_crtc_in_state(state, crtc, cstate, i) {
1822                 int pixel_rate;
1823
1824                 crtc_state = to_intel_crtc_state(cstate);
1825                 if (!crtc_state->base.enable) {
1826                         intel_state->min_pixclk[i] = 0;
1827                         continue;
1828                 }
1829
1830                 pixel_rate = crtc_state->pixel_rate;
1831
1832                 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1833                         pixel_rate =
1834                                 bdw_adjust_min_pipe_pixel_rate(crtc_state,
1835                                                                pixel_rate);
1836
1837                 intel_state->min_pixclk[i] = pixel_rate;
1838         }
1839
1840         for_each_pipe(dev_priv, pipe)
1841                 max_pixel_rate = max(intel_state->min_pixclk[pipe],
1842                                      max_pixel_rate);
1843
1844         return max_pixel_rate;
1845 }
1846
1847 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1848 {
1849         struct drm_i915_private *dev_priv = to_i915(state->dev);
1850         int max_pixclk = intel_max_pixel_rate(state);
1851         struct intel_atomic_state *intel_state =
1852                 to_intel_atomic_state(state);
1853         int cdclk;
1854
1855         cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
1856
1857         if (cdclk > dev_priv->max_cdclk_freq) {
1858                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1859                               cdclk, dev_priv->max_cdclk_freq);
1860                 return -EINVAL;
1861         }
1862
1863         intel_state->cdclk.logical.cdclk = cdclk;
1864
1865         if (!intel_state->active_crtcs) {
1866                 cdclk = vlv_calc_cdclk(dev_priv, 0);
1867
1868                 intel_state->cdclk.actual.cdclk = cdclk;
1869         } else {
1870                 intel_state->cdclk.actual =
1871                         intel_state->cdclk.logical;
1872         }
1873
1874         return 0;
1875 }
1876
1877 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1878 {
1879         struct drm_i915_private *dev_priv = to_i915(state->dev);
1880         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1881         int max_pixclk = intel_max_pixel_rate(state);
1882         int cdclk;
1883
1884         /*
1885          * FIXME should also account for plane ratio
1886          * once 64bpp pixel formats are supported.
1887          */
1888         cdclk = bdw_calc_cdclk(max_pixclk);
1889
1890         if (cdclk > dev_priv->max_cdclk_freq) {
1891                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1892                               cdclk, dev_priv->max_cdclk_freq);
1893                 return -EINVAL;
1894         }
1895
1896         intel_state->cdclk.logical.cdclk = cdclk;
1897
1898         if (!intel_state->active_crtcs) {
1899                 cdclk = bdw_calc_cdclk(0);
1900
1901                 intel_state->cdclk.actual.cdclk = cdclk;
1902         } else {
1903                 intel_state->cdclk.actual =
1904                         intel_state->cdclk.logical;
1905         }
1906
1907         return 0;
1908 }
1909
1910 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1911 {
1912         struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1913         struct drm_i915_private *dev_priv = to_i915(state->dev);
1914         const int max_pixclk = intel_max_pixel_rate(state);
1915         int cdclk, vco;
1916
1917         vco = intel_state->cdclk.logical.vco;
1918         if (!vco)
1919                 vco = dev_priv->skl_preferred_vco_freq;
1920
1921         /*
1922          * FIXME should also account for plane ratio
1923          * once 64bpp pixel formats are supported.
1924          */
1925         cdclk = skl_calc_cdclk(max_pixclk, vco);
1926
1927         if (cdclk > dev_priv->max_cdclk_freq) {
1928                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1929                               cdclk, dev_priv->max_cdclk_freq);
1930                 return -EINVAL;
1931         }
1932
1933         intel_state->cdclk.logical.vco = vco;
1934         intel_state->cdclk.logical.cdclk = cdclk;
1935
1936         if (!intel_state->active_crtcs) {
1937                 cdclk = skl_calc_cdclk(0, vco);
1938
1939                 intel_state->cdclk.actual.vco = vco;
1940                 intel_state->cdclk.actual.cdclk = cdclk;
1941         } else {
1942                 intel_state->cdclk.actual =
1943                         intel_state->cdclk.logical;
1944         }
1945
1946         return 0;
1947 }
1948
1949 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1950 {
1951         struct drm_i915_private *dev_priv = to_i915(state->dev);
1952         int max_pixclk = intel_max_pixel_rate(state);
1953         struct intel_atomic_state *intel_state =
1954                 to_intel_atomic_state(state);
1955         int cdclk, vco;
1956
1957         if (IS_GEMINILAKE(dev_priv)) {
1958                 cdclk = glk_calc_cdclk(max_pixclk);
1959                 vco = glk_de_pll_vco(dev_priv, cdclk);
1960         } else {
1961                 cdclk = bxt_calc_cdclk(max_pixclk);
1962                 vco = bxt_de_pll_vco(dev_priv, cdclk);
1963         }
1964
1965         if (cdclk > dev_priv->max_cdclk_freq) {
1966                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1967                               cdclk, dev_priv->max_cdclk_freq);
1968                 return -EINVAL;
1969         }
1970
1971         intel_state->cdclk.logical.vco = vco;
1972         intel_state->cdclk.logical.cdclk = cdclk;
1973
1974         if (!intel_state->active_crtcs) {
1975                 if (IS_GEMINILAKE(dev_priv)) {
1976                         cdclk = glk_calc_cdclk(0);
1977                         vco = glk_de_pll_vco(dev_priv, cdclk);
1978                 } else {
1979                         cdclk = bxt_calc_cdclk(0);
1980                         vco = bxt_de_pll_vco(dev_priv, cdclk);
1981                 }
1982
1983                 intel_state->cdclk.actual.vco = vco;
1984                 intel_state->cdclk.actual.cdclk = cdclk;
1985         } else {
1986                 intel_state->cdclk.actual =
1987                         intel_state->cdclk.logical;
1988         }
1989
1990         return 0;
1991 }
1992
1993 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
1994 {
1995         struct drm_i915_private *dev_priv = to_i915(state->dev);
1996         struct intel_atomic_state *intel_state =
1997                 to_intel_atomic_state(state);
1998         int max_pixclk = intel_max_pixel_rate(state);
1999         int cdclk, vco;
2000
2001         cdclk = cnl_calc_cdclk(max_pixclk);
2002         vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2003
2004         if (cdclk > dev_priv->max_cdclk_freq) {
2005                 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
2006                               cdclk, dev_priv->max_cdclk_freq);
2007                 return -EINVAL;
2008         }
2009
2010         intel_state->cdclk.logical.vco = vco;
2011         intel_state->cdclk.logical.cdclk = cdclk;
2012
2013         if (!intel_state->active_crtcs) {
2014                 cdclk = cnl_calc_cdclk(0);
2015                 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2016
2017                 intel_state->cdclk.actual.vco = vco;
2018                 intel_state->cdclk.actual.cdclk = cdclk;
2019         } else {
2020                 intel_state->cdclk.actual =
2021                         intel_state->cdclk.logical;
2022         }
2023
2024         return 0;
2025 }
2026
2027 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2028 {
2029         int max_cdclk_freq = dev_priv->max_cdclk_freq;
2030
2031         if (IS_GEMINILAKE(dev_priv))
2032                 /*
2033                  * FIXME: Limiting to 99% as a temporary workaround. See
2034                  * glk_calc_cdclk() for details.
2035                  */
2036                 return 2 * max_cdclk_freq * 99 / 100;
2037         else if (INTEL_INFO(dev_priv)->gen >= 9 ||
2038                  IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2039                 return max_cdclk_freq;
2040         else if (IS_CHERRYVIEW(dev_priv))
2041                 return max_cdclk_freq*95/100;
2042         else if (INTEL_INFO(dev_priv)->gen < 4)
2043                 return 2*max_cdclk_freq*90/100;
2044         else
2045                 return max_cdclk_freq*90/100;
2046 }
2047
2048 /**
2049  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2050  * @dev_priv: i915 device
2051  *
2052  * Determine the maximum CDCLK frequency the platform supports, and also
2053  * derive the maximum dot clock frequency the maximum CDCLK frequency
2054  * allows.
2055  */
2056 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2057 {
2058         if (IS_CANNONLAKE(dev_priv)) {
2059                 dev_priv->max_cdclk_freq = 528000;
2060         } else if (IS_GEN9_BC(dev_priv)) {
2061                 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2062                 int max_cdclk, vco;
2063
2064                 vco = dev_priv->skl_preferred_vco_freq;
2065                 WARN_ON(vco != 8100000 && vco != 8640000);
2066
2067                 /*
2068                  * Use the lower (vco 8640) cdclk values as a
2069                  * first guess. skl_calc_cdclk() will correct it
2070                  * if the preferred vco is 8100 instead.
2071                  */
2072                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2073                         max_cdclk = 617143;
2074                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2075                         max_cdclk = 540000;
2076                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2077                         max_cdclk = 432000;
2078                 else
2079                         max_cdclk = 308571;
2080
2081                 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2082         } else if (IS_GEMINILAKE(dev_priv)) {
2083                 dev_priv->max_cdclk_freq = 316800;
2084         } else if (IS_BROXTON(dev_priv)) {
2085                 dev_priv->max_cdclk_freq = 624000;
2086         } else if (IS_BROADWELL(dev_priv))  {
2087                 /*
2088                  * FIXME with extra cooling we can allow
2089                  * 540 MHz for ULX and 675 Mhz for ULT.
2090                  * How can we know if extra cooling is
2091                  * available? PCI ID, VTB, something else?
2092                  */
2093                 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2094                         dev_priv->max_cdclk_freq = 450000;
2095                 else if (IS_BDW_ULX(dev_priv))
2096                         dev_priv->max_cdclk_freq = 450000;
2097                 else if (IS_BDW_ULT(dev_priv))
2098                         dev_priv->max_cdclk_freq = 540000;
2099                 else
2100                         dev_priv->max_cdclk_freq = 675000;
2101         } else if (IS_CHERRYVIEW(dev_priv)) {
2102                 dev_priv->max_cdclk_freq = 320000;
2103         } else if (IS_VALLEYVIEW(dev_priv)) {
2104                 dev_priv->max_cdclk_freq = 400000;
2105         } else {
2106                 /* otherwise assume cdclk is fixed */
2107                 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2108         }
2109
2110         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2111
2112         DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2113                          dev_priv->max_cdclk_freq);
2114
2115         DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2116                          dev_priv->max_dotclk_freq);
2117 }
2118
2119 /**
2120  * intel_update_cdclk - Determine the current CDCLK frequency
2121  * @dev_priv: i915 device
2122  *
2123  * Determine the current CDCLK frequency.
2124  */
2125 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2126 {
2127         dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2128
2129         DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2130                          dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
2131                          dev_priv->cdclk.hw.ref);
2132
2133         /*
2134          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2135          * Programmng [sic] note: bit[9:2] should be programmed to the number
2136          * of cdclk that generates 4MHz reference clock freq which is used to
2137          * generate GMBus clock. This will vary with the cdclk freq.
2138          */
2139         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2140                 I915_WRITE(GMBUSFREQ_VLV,
2141                            DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2142 }
2143
2144 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2145 {
2146         u32 rawclk;
2147         int divider, fraction;
2148
2149         if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2150                 /* 24 MHz */
2151                 divider = 24000;
2152                 fraction = 0;
2153         } else {
2154                 /* 19.2 MHz */
2155                 divider = 19000;
2156                 fraction = 200;
2157         }
2158
2159         rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2160         if (fraction)
2161                 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2162                                                             fraction) - 1);
2163
2164         I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2165         return divider + fraction;
2166 }
2167
2168 static int pch_rawclk(struct drm_i915_private *dev_priv)
2169 {
2170         return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2171 }
2172
2173 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2174 {
2175         /* RAWCLK_FREQ_VLV register updated from power well code */
2176         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2177                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
2178 }
2179
2180 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2181 {
2182         uint32_t clkcfg;
2183
2184         /* hrawclock is 1/4 the FSB frequency */
2185         clkcfg = I915_READ(CLKCFG);
2186         switch (clkcfg & CLKCFG_FSB_MASK) {
2187         case CLKCFG_FSB_400:
2188                 return 100000;
2189         case CLKCFG_FSB_533:
2190                 return 133333;
2191         case CLKCFG_FSB_667:
2192                 return 166667;
2193         case CLKCFG_FSB_800:
2194                 return 200000;
2195         case CLKCFG_FSB_1067:
2196         case CLKCFG_FSB_1067_ALT:
2197                 return 266667;
2198         case CLKCFG_FSB_1333:
2199         case CLKCFG_FSB_1333_ALT:
2200                 return 333333;
2201         default:
2202                 return 133333;
2203         }
2204 }
2205
2206 /**
2207  * intel_update_rawclk - Determine the current RAWCLK frequency
2208  * @dev_priv: i915 device
2209  *
2210  * Determine the current RAWCLK frequency. RAWCLK is a fixed
2211  * frequency clock so this needs to done only once.
2212  */
2213 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2214 {
2215
2216         if (HAS_PCH_CNP(dev_priv))
2217                 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2218         else if (HAS_PCH_SPLIT(dev_priv))
2219                 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2220         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2221                 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2222         else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2223                 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2224         else
2225                 /* no rawclk on other platforms, or no need to know it */
2226                 return;
2227
2228         DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2229 }
2230
2231 /**
2232  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2233  * @dev_priv: i915 device
2234  */
2235 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2236 {
2237         if (IS_CHERRYVIEW(dev_priv)) {
2238                 dev_priv->display.set_cdclk = chv_set_cdclk;
2239                 dev_priv->display.modeset_calc_cdclk =
2240                         vlv_modeset_calc_cdclk;
2241         } else if (IS_VALLEYVIEW(dev_priv)) {
2242                 dev_priv->display.set_cdclk = vlv_set_cdclk;
2243                 dev_priv->display.modeset_calc_cdclk =
2244                         vlv_modeset_calc_cdclk;
2245         } else if (IS_BROADWELL(dev_priv)) {
2246                 dev_priv->display.set_cdclk = bdw_set_cdclk;
2247                 dev_priv->display.modeset_calc_cdclk =
2248                         bdw_modeset_calc_cdclk;
2249         } else if (IS_GEN9_LP(dev_priv)) {
2250                 dev_priv->display.set_cdclk = bxt_set_cdclk;
2251                 dev_priv->display.modeset_calc_cdclk =
2252                         bxt_modeset_calc_cdclk;
2253         } else if (IS_GEN9_BC(dev_priv)) {
2254                 dev_priv->display.set_cdclk = skl_set_cdclk;
2255                 dev_priv->display.modeset_calc_cdclk =
2256                         skl_modeset_calc_cdclk;
2257         } else if (IS_CANNONLAKE(dev_priv)) {
2258                 dev_priv->display.set_cdclk = cnl_set_cdclk;
2259                 dev_priv->display.modeset_calc_cdclk =
2260                         cnl_modeset_calc_cdclk;
2261         }
2262
2263         if (IS_CANNONLAKE(dev_priv))
2264                 dev_priv->display.get_cdclk = cnl_get_cdclk;
2265         else if (IS_GEN9_BC(dev_priv))
2266                 dev_priv->display.get_cdclk = skl_get_cdclk;
2267         else if (IS_GEN9_LP(dev_priv))
2268                 dev_priv->display.get_cdclk = bxt_get_cdclk;
2269         else if (IS_BROADWELL(dev_priv))
2270                 dev_priv->display.get_cdclk = bdw_get_cdclk;
2271         else if (IS_HASWELL(dev_priv))
2272                 dev_priv->display.get_cdclk = hsw_get_cdclk;
2273         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2274                 dev_priv->display.get_cdclk = vlv_get_cdclk;
2275         else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2276                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2277         else if (IS_GEN5(dev_priv))
2278                 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2279         else if (IS_GM45(dev_priv))
2280                 dev_priv->display.get_cdclk = gm45_get_cdclk;
2281         else if (IS_G45(dev_priv))
2282                 dev_priv->display.get_cdclk = g33_get_cdclk;
2283         else if (IS_I965GM(dev_priv))
2284                 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2285         else if (IS_I965G(dev_priv))
2286                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2287         else if (IS_PINEVIEW(dev_priv))
2288                 dev_priv->display.get_cdclk = pnv_get_cdclk;
2289         else if (IS_G33(dev_priv))
2290                 dev_priv->display.get_cdclk = g33_get_cdclk;
2291         else if (IS_I945GM(dev_priv))
2292                 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2293         else if (IS_I945G(dev_priv))
2294                 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2295         else if (IS_I915GM(dev_priv))
2296                 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2297         else if (IS_I915G(dev_priv))
2298                 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2299         else if (IS_I865G(dev_priv))
2300                 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2301         else if (IS_I85X(dev_priv))
2302                 dev_priv->display.get_cdclk = i85x_get_cdclk;
2303         else if (IS_I845G(dev_priv))
2304                 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2305         else { /* 830 */
2306                 WARN(!IS_I830(dev_priv),
2307                      "Unknown platform. Assuming 133 MHz CDCLK\n");
2308                 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;
2309         }
2310 }