2 * Copyright © 2006-2017 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include "intel_drv.h"
29 * The display engine uses several different clocks to do its work. There
30 * are two main clocks involved that aren't directly related to the actual
31 * pixel clock or any symbol/bit clock of the actual output port. These
32 * are the core display clock (CDCLK) and RAWCLK.
34 * CDCLK clocks most of the display pipe logic, and thus its frequency
35 * must be high enough to support the rate at which pixels are flowing
36 * through the pipes. Downscaling must also be accounted as that increases
37 * the effective pixel rate.
39 * On several platforms the CDCLK frequency can be changed dynamically
40 * to minimize power consumption for a given display configuration.
41 * Typically changes to the CDCLK frequency require all the display pipes
42 * to be shut down while the frequency is being changed.
44 * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
45 * DMC will not change the active CDCLK frequency however, so that part
46 * will still be performed by the driver directly.
48 * RAWCLK is a fixed frequency clock, often used by various auxiliary
49 * blocks such as AUX CH or backlight PWM. Hence the only thing we
50 * really need to know about RAWCLK is its frequency so that various
51 * dividers can be programmed correctly.
54 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
55 struct intel_cdclk_state *cdclk_state)
57 cdclk_state->cdclk = 133333;
60 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
61 struct intel_cdclk_state *cdclk_state)
63 cdclk_state->cdclk = 200000;
66 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
67 struct intel_cdclk_state *cdclk_state)
69 cdclk_state->cdclk = 266667;
72 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
73 struct intel_cdclk_state *cdclk_state)
75 cdclk_state->cdclk = 333333;
78 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
79 struct intel_cdclk_state *cdclk_state)
81 cdclk_state->cdclk = 400000;
84 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
85 struct intel_cdclk_state *cdclk_state)
87 cdclk_state->cdclk = 450000;
90 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
91 struct intel_cdclk_state *cdclk_state)
93 struct pci_dev *pdev = dev_priv->drm.pdev;
97 * 852GM/852GMV only supports 133 MHz and the HPLLCC
98 * encoding is different :(
99 * FIXME is this the right way to detect 852GM/852GMV?
101 if (pdev->revision == 0x1) {
102 cdclk_state->cdclk = 133333;
106 pci_bus_read_config_word(pdev->bus,
107 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
109 /* Assume that the hardware is in the high speed state. This
110 * should be the default.
112 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
113 case GC_CLOCK_133_200:
114 case GC_CLOCK_133_200_2:
115 case GC_CLOCK_100_200:
116 cdclk_state->cdclk = 200000;
118 case GC_CLOCK_166_250:
119 cdclk_state->cdclk = 250000;
121 case GC_CLOCK_100_133:
122 cdclk_state->cdclk = 133333;
124 case GC_CLOCK_133_266:
125 case GC_CLOCK_133_266_2:
126 case GC_CLOCK_166_266:
127 cdclk_state->cdclk = 266667;
132 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
133 struct intel_cdclk_state *cdclk_state)
135 struct pci_dev *pdev = dev_priv->drm.pdev;
138 pci_read_config_word(pdev, GCFGC, &gcfgc);
140 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
141 cdclk_state->cdclk = 133333;
145 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
146 case GC_DISPLAY_CLOCK_333_320_MHZ:
147 cdclk_state->cdclk = 333333;
150 case GC_DISPLAY_CLOCK_190_200_MHZ:
151 cdclk_state->cdclk = 190000;
156 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
157 struct intel_cdclk_state *cdclk_state)
159 struct pci_dev *pdev = dev_priv->drm.pdev;
162 pci_read_config_word(pdev, GCFGC, &gcfgc);
164 if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
165 cdclk_state->cdclk = 133333;
169 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
170 case GC_DISPLAY_CLOCK_333_320_MHZ:
171 cdclk_state->cdclk = 320000;
174 case GC_DISPLAY_CLOCK_190_200_MHZ:
175 cdclk_state->cdclk = 200000;
180 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
182 static const unsigned int blb_vco[8] = {
189 static const unsigned int pnv_vco[8] = {
196 static const unsigned int cl_vco[8] = {
205 static const unsigned int elk_vco[8] = {
211 static const unsigned int ctg_vco[8] = {
219 const unsigned int *vco_table;
223 /* FIXME other chipsets? */
224 if (IS_GM45(dev_priv))
226 else if (IS_G45(dev_priv))
228 else if (IS_I965GM(dev_priv))
230 else if (IS_PINEVIEW(dev_priv))
232 else if (IS_G33(dev_priv))
237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
239 vco = vco_table[tmp & 0x7];
241 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
243 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
248 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
249 struct intel_cdclk_state *cdclk_state)
251 struct pci_dev *pdev = dev_priv->drm.pdev;
252 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
253 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
254 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
255 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
256 const uint8_t *div_table;
257 unsigned int cdclk_sel;
260 cdclk_state->vco = intel_hpll_vco(dev_priv);
262 pci_read_config_word(pdev, GCFGC, &tmp);
264 cdclk_sel = (tmp >> 4) & 0x7;
266 if (cdclk_sel >= ARRAY_SIZE(div_3200))
269 switch (cdclk_state->vco) {
271 div_table = div_3200;
274 div_table = div_4000;
277 div_table = div_4800;
280 div_table = div_5333;
286 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
287 div_table[cdclk_sel]);
291 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
292 cdclk_state->vco, tmp);
293 cdclk_state->cdclk = 190476;
296 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
297 struct intel_cdclk_state *cdclk_state)
299 struct pci_dev *pdev = dev_priv->drm.pdev;
302 pci_read_config_word(pdev, GCFGC, &gcfgc);
304 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
305 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
306 cdclk_state->cdclk = 266667;
308 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
309 cdclk_state->cdclk = 333333;
311 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
312 cdclk_state->cdclk = 444444;
314 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
315 cdclk_state->cdclk = 200000;
318 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
319 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
320 cdclk_state->cdclk = 133333;
322 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
323 cdclk_state->cdclk = 166667;
328 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
329 struct intel_cdclk_state *cdclk_state)
331 struct pci_dev *pdev = dev_priv->drm.pdev;
332 static const uint8_t div_3200[] = { 16, 10, 8 };
333 static const uint8_t div_4000[] = { 20, 12, 10 };
334 static const uint8_t div_5333[] = { 24, 16, 14 };
335 const uint8_t *div_table;
336 unsigned int cdclk_sel;
339 cdclk_state->vco = intel_hpll_vco(dev_priv);
341 pci_read_config_word(pdev, GCFGC, &tmp);
343 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
345 if (cdclk_sel >= ARRAY_SIZE(div_3200))
348 switch (cdclk_state->vco) {
350 div_table = div_3200;
353 div_table = div_4000;
356 div_table = div_5333;
362 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco,
363 div_table[cdclk_sel]);
367 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
368 cdclk_state->vco, tmp);
369 cdclk_state->cdclk = 200000;
372 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
373 struct intel_cdclk_state *cdclk_state)
375 struct pci_dev *pdev = dev_priv->drm.pdev;
376 unsigned int cdclk_sel;
379 cdclk_state->vco = intel_hpll_vco(dev_priv);
381 pci_read_config_word(pdev, GCFGC, &tmp);
383 cdclk_sel = (tmp >> 12) & 0x1;
385 switch (cdclk_state->vco) {
389 cdclk_state->cdclk = cdclk_sel ? 333333 : 222222;
392 cdclk_state->cdclk = cdclk_sel ? 320000 : 228571;
395 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
396 cdclk_state->vco, tmp);
397 cdclk_state->cdclk = 222222;
402 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
403 struct intel_cdclk_state *cdclk_state)
405 uint32_t lcpll = I915_READ(LCPLL_CTL);
406 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
408 if (lcpll & LCPLL_CD_SOURCE_FCLK)
409 cdclk_state->cdclk = 800000;
410 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
411 cdclk_state->cdclk = 450000;
412 else if (freq == LCPLL_CLK_FREQ_450)
413 cdclk_state->cdclk = 450000;
414 else if (IS_HSW_ULT(dev_priv))
415 cdclk_state->cdclk = 337500;
417 cdclk_state->cdclk = 540000;
420 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv,
423 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ?
425 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
428 * We seem to get an unstable or solid color picture at 200MHz.
429 * Not sure what's wrong. For now use 200MHz only when all pipes
432 if (!IS_CHERRYVIEW(dev_priv) &&
433 max_pixclk > freq_320*limit/100)
435 else if (max_pixclk > 266667*limit/100)
437 else if (max_pixclk > 0)
443 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
444 struct intel_cdclk_state *cdclk_state)
446 cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
447 cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
448 CCK_DISPLAY_CLOCK_CONTROL,
452 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
454 unsigned int credits, default_credits;
456 if (IS_CHERRYVIEW(dev_priv))
457 default_credits = PFI_CREDIT(12);
459 default_credits = PFI_CREDIT(8);
461 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) {
462 /* CHV suggested value is 31 or 63 */
463 if (IS_CHERRYVIEW(dev_priv))
464 credits = PFI_CREDIT_63;
466 credits = PFI_CREDIT(15);
468 credits = default_credits;
472 * WA - write default credits before re-programming
473 * FIXME: should we also set the resend bit here?
475 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
478 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
479 credits | PFI_CREDIT_RESEND);
482 * FIXME is this guaranteed to clear
483 * immediately or should we poll for it?
485 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
488 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
489 const struct intel_cdclk_state *cdclk_state)
491 int cdclk = cdclk_state->cdclk;
494 /* There are cases where we can end up here with power domains
495 * off and a CDCLK frequency other than the minimum, like when
496 * issuing a modeset without actually changing any display after
497 * a system suspend. So grab the PIPE-A domain, which covers
498 * the HW blocks needed for the following programming.
500 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
502 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
504 else if (cdclk == 266667)
509 mutex_lock(&dev_priv->rps.hw_lock);
510 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
511 val &= ~DSPFREQGUAR_MASK;
512 val |= (cmd << DSPFREQGUAR_SHIFT);
513 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
514 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
515 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
517 DRM_ERROR("timed out waiting for CDclk change\n");
519 mutex_unlock(&dev_priv->rps.hw_lock);
521 mutex_lock(&dev_priv->sb_lock);
523 if (cdclk == 400000) {
526 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
529 /* adjust cdclk divider */
530 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
531 val &= ~CCK_FREQUENCY_VALUES;
533 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
535 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
536 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
538 DRM_ERROR("timed out waiting for CDclk change\n");
541 /* adjust self-refresh exit latency value */
542 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
546 * For high bandwidth configs, we set a higher latency in the bunit
547 * so that the core display fetch happens in time to avoid underruns.
550 val |= 4500 / 250; /* 4.5 usec */
552 val |= 3000 / 250; /* 3.0 usec */
553 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
555 mutex_unlock(&dev_priv->sb_lock);
557 intel_update_cdclk(dev_priv);
559 vlv_program_pfi_credits(dev_priv);
561 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
564 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
565 const struct intel_cdclk_state *cdclk_state)
567 int cdclk = cdclk_state->cdclk;
581 /* There are cases where we can end up here with power domains
582 * off and a CDCLK frequency other than the minimum, like when
583 * issuing a modeset without actually changing any display after
584 * a system suspend. So grab the PIPE-A domain, which covers
585 * the HW blocks needed for the following programming.
587 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
590 * Specs are full of misinformation, but testing on actual
591 * hardware has shown that we just need to write the desired
592 * CCK divider into the Punit register.
594 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
596 mutex_lock(&dev_priv->rps.hw_lock);
597 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
598 val &= ~DSPFREQGUAR_MASK_CHV;
599 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
600 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
601 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
602 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
604 DRM_ERROR("timed out waiting for CDclk change\n");
606 mutex_unlock(&dev_priv->rps.hw_lock);
608 intel_update_cdclk(dev_priv);
610 vlv_program_pfi_credits(dev_priv);
612 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
615 static int bdw_calc_cdclk(int max_pixclk)
617 if (max_pixclk > 540000)
619 else if (max_pixclk > 450000)
621 else if (max_pixclk > 337500)
627 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
628 struct intel_cdclk_state *cdclk_state)
630 uint32_t lcpll = I915_READ(LCPLL_CTL);
631 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
633 if (lcpll & LCPLL_CD_SOURCE_FCLK)
634 cdclk_state->cdclk = 800000;
635 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
636 cdclk_state->cdclk = 450000;
637 else if (freq == LCPLL_CLK_FREQ_450)
638 cdclk_state->cdclk = 450000;
639 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
640 cdclk_state->cdclk = 540000;
641 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
642 cdclk_state->cdclk = 337500;
644 cdclk_state->cdclk = 675000;
647 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
648 const struct intel_cdclk_state *cdclk_state)
650 int cdclk = cdclk_state->cdclk;
654 if (WARN((I915_READ(LCPLL_CTL) &
655 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
656 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
657 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
658 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
659 "trying to change cdclk frequency with cdclk not enabled\n"))
662 mutex_lock(&dev_priv->rps.hw_lock);
663 ret = sandybridge_pcode_write(dev_priv,
664 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
665 mutex_unlock(&dev_priv->rps.hw_lock);
667 DRM_ERROR("failed to inform pcode about cdclk change\n");
671 val = I915_READ(LCPLL_CTL);
672 val |= LCPLL_CD_SOURCE_FCLK;
673 I915_WRITE(LCPLL_CTL, val);
675 if (wait_for_us(I915_READ(LCPLL_CTL) &
676 LCPLL_CD_SOURCE_FCLK_DONE, 1))
677 DRM_ERROR("Switching to FCLK failed\n");
679 val = I915_READ(LCPLL_CTL);
680 val &= ~LCPLL_CLK_FREQ_MASK;
684 val |= LCPLL_CLK_FREQ_450;
688 val |= LCPLL_CLK_FREQ_54O_BDW;
692 val |= LCPLL_CLK_FREQ_337_5_BDW;
696 val |= LCPLL_CLK_FREQ_675_BDW;
700 WARN(1, "invalid cdclk frequency\n");
704 I915_WRITE(LCPLL_CTL, val);
706 val = I915_READ(LCPLL_CTL);
707 val &= ~LCPLL_CD_SOURCE_FCLK;
708 I915_WRITE(LCPLL_CTL, val);
710 if (wait_for_us((I915_READ(LCPLL_CTL) &
711 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
712 DRM_ERROR("Switching back to LCPLL failed\n");
714 mutex_lock(&dev_priv->rps.hw_lock);
715 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
716 mutex_unlock(&dev_priv->rps.hw_lock);
718 I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
720 intel_update_cdclk(dev_priv);
722 WARN(cdclk != dev_priv->cdclk.hw.cdclk,
723 "cdclk requested %d kHz but got %d kHz\n",
724 cdclk, dev_priv->cdclk.hw.cdclk);
727 static int skl_calc_cdclk(int max_pixclk, int vco)
729 if (vco == 8640000) {
730 if (max_pixclk > 540000)
732 else if (max_pixclk > 432000)
734 else if (max_pixclk > 308571)
739 if (max_pixclk > 540000)
741 else if (max_pixclk > 450000)
743 else if (max_pixclk > 337500)
750 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
751 struct intel_cdclk_state *cdclk_state)
755 cdclk_state->ref = 24000;
756 cdclk_state->vco = 0;
758 val = I915_READ(LCPLL1_CTL);
759 if ((val & LCPLL_PLL_ENABLE) == 0)
762 if (WARN_ON((val & LCPLL_PLL_LOCK) == 0))
765 val = I915_READ(DPLL_CTRL1);
767 if (WARN_ON((val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
768 DPLL_CTRL1_SSC(SKL_DPLL0) |
769 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
770 DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
773 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
774 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
775 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
776 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
777 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
778 cdclk_state->vco = 8100000;
780 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
781 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
782 cdclk_state->vco = 8640000;
785 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
790 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
791 struct intel_cdclk_state *cdclk_state)
795 skl_dpll0_update(dev_priv, cdclk_state);
797 cdclk_state->cdclk = cdclk_state->ref;
799 if (cdclk_state->vco == 0)
802 cdctl = I915_READ(CDCLK_CTL);
804 if (cdclk_state->vco == 8640000) {
805 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
806 case CDCLK_FREQ_450_432:
807 cdclk_state->cdclk = 432000;
809 case CDCLK_FREQ_337_308:
810 cdclk_state->cdclk = 308571;
813 cdclk_state->cdclk = 540000;
815 case CDCLK_FREQ_675_617:
816 cdclk_state->cdclk = 617143;
819 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
823 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
824 case CDCLK_FREQ_450_432:
825 cdclk_state->cdclk = 450000;
827 case CDCLK_FREQ_337_308:
828 cdclk_state->cdclk = 337500;
831 cdclk_state->cdclk = 540000;
833 case CDCLK_FREQ_675_617:
834 cdclk_state->cdclk = 675000;
837 MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
843 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
844 static int skl_cdclk_decimal(int cdclk)
846 return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
849 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
852 bool changed = dev_priv->skl_preferred_vco_freq != vco;
854 dev_priv->skl_preferred_vco_freq = vco;
857 intel_update_max_cdclk(dev_priv);
860 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
864 WARN_ON(vco != 8100000 && vco != 8640000);
867 * We always enable DPLL0 with the lowest link rate possible, but still
868 * taking into account the VCO required to operate the eDP panel at the
869 * desired frequency. The usual DP link rates operate with a VCO of
870 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
871 * The modeset code is responsible for the selection of the exact link
872 * rate later on, with the constraint of choosing a frequency that
875 val = I915_READ(DPLL_CTRL1);
877 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
878 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
879 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
881 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
884 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
887 I915_WRITE(DPLL_CTRL1, val);
888 POSTING_READ(DPLL_CTRL1);
890 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
892 if (intel_wait_for_register(dev_priv,
893 LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
895 DRM_ERROR("DPLL0 not locked\n");
897 dev_priv->cdclk.hw.vco = vco;
899 /* We'll want to keep using the current vco from now on. */
900 skl_set_preferred_cdclk_vco(dev_priv, vco);
903 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
905 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
906 if (intel_wait_for_register(dev_priv,
907 LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
909 DRM_ERROR("Couldn't disable DPLL0\n");
911 dev_priv->cdclk.hw.vco = 0;
914 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
915 const struct intel_cdclk_state *cdclk_state)
917 int cdclk = cdclk_state->cdclk;
918 int vco = cdclk_state->vco;
919 u32 freq_select, pcu_ack, cdclk_ctl;
922 WARN_ON((cdclk == 24000) != (vco == 0));
924 mutex_lock(&dev_priv->rps.hw_lock);
925 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
926 SKL_CDCLK_PREPARE_FOR_CHANGE,
927 SKL_CDCLK_READY_FOR_CHANGE,
928 SKL_CDCLK_READY_FOR_CHANGE, 3);
929 mutex_unlock(&dev_priv->rps.hw_lock);
931 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
936 /* Choose frequency for this cdclk */
940 freq_select = CDCLK_FREQ_450_432;
944 freq_select = CDCLK_FREQ_540;
950 freq_select = CDCLK_FREQ_337_308;
955 freq_select = CDCLK_FREQ_675_617;
960 if (dev_priv->cdclk.hw.vco != 0 &&
961 dev_priv->cdclk.hw.vco != vco)
962 skl_dpll0_disable(dev_priv);
964 cdclk_ctl = I915_READ(CDCLK_CTL);
966 if (dev_priv->cdclk.hw.vco != vco) {
967 /* Wa Display #1183: skl,kbl,cfl */
968 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
969 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
970 I915_WRITE(CDCLK_CTL, cdclk_ctl);
973 /* Wa Display #1183: skl,kbl,cfl */
974 cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
975 I915_WRITE(CDCLK_CTL, cdclk_ctl);
976 POSTING_READ(CDCLK_CTL);
978 if (dev_priv->cdclk.hw.vco != vco)
979 skl_dpll0_enable(dev_priv, vco);
981 /* Wa Display #1183: skl,kbl,cfl */
982 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
983 I915_WRITE(CDCLK_CTL, cdclk_ctl);
985 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
986 I915_WRITE(CDCLK_CTL, cdclk_ctl);
988 /* Wa Display #1183: skl,kbl,cfl */
989 cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
990 I915_WRITE(CDCLK_CTL, cdclk_ctl);
991 POSTING_READ(CDCLK_CTL);
993 /* inform PCU of the change */
994 mutex_lock(&dev_priv->rps.hw_lock);
995 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
996 mutex_unlock(&dev_priv->rps.hw_lock);
998 intel_update_cdclk(dev_priv);
1001 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1003 uint32_t cdctl, expected;
1006 * check if the pre-os initialized the display
1007 * There is SWF18 scratchpad register defined which is set by the
1008 * pre-os which can be used by the OS drivers to check the status
1010 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1013 intel_update_cdclk(dev_priv);
1014 /* Is PLL enabled and locked ? */
1015 if (dev_priv->cdclk.hw.vco == 0 ||
1016 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1019 /* DPLL okay; verify the cdclock
1021 * Noticed in some instances that the freq selection is correct but
1022 * decimal part is programmed wrong from BIOS where pre-os does not
1023 * enable display. Verify the same as well.
1025 cdctl = I915_READ(CDCLK_CTL);
1026 expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1027 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1028 if (cdctl == expected)
1029 /* All well; nothing to sanitize */
1033 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1035 /* force cdclk programming */
1036 dev_priv->cdclk.hw.cdclk = 0;
1037 /* force full PLL disable + enable */
1038 dev_priv->cdclk.hw.vco = -1;
1042 * skl_init_cdclk - Initialize CDCLK on SKL
1043 * @dev_priv: i915 device
1045 * Initialize CDCLK for SKL and derivatives. This is generally
1046 * done only during the display core initialization sequence,
1047 * after which the DMC will take care of turning CDCLK off/on
1050 void skl_init_cdclk(struct drm_i915_private *dev_priv)
1052 struct intel_cdclk_state cdclk_state;
1054 skl_sanitize_cdclk(dev_priv);
1056 if (dev_priv->cdclk.hw.cdclk != 0 &&
1057 dev_priv->cdclk.hw.vco != 0) {
1059 * Use the current vco as our initial
1060 * guess as to what the preferred vco is.
1062 if (dev_priv->skl_preferred_vco_freq == 0)
1063 skl_set_preferred_cdclk_vco(dev_priv,
1064 dev_priv->cdclk.hw.vco);
1068 cdclk_state = dev_priv->cdclk.hw;
1070 cdclk_state.vco = dev_priv->skl_preferred_vco_freq;
1071 if (cdclk_state.vco == 0)
1072 cdclk_state.vco = 8100000;
1073 cdclk_state.cdclk = skl_calc_cdclk(0, cdclk_state.vco);
1075 skl_set_cdclk(dev_priv, &cdclk_state);
1079 * skl_uninit_cdclk - Uninitialize CDCLK on SKL
1080 * @dev_priv: i915 device
1082 * Uninitialize CDCLK for SKL and derivatives. This is done only
1083 * during the display core uninitialization sequence.
1085 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
1087 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1089 cdclk_state.cdclk = cdclk_state.ref;
1090 cdclk_state.vco = 0;
1092 skl_set_cdclk(dev_priv, &cdclk_state);
1095 static int bxt_calc_cdclk(int max_pixclk)
1097 if (max_pixclk > 576000)
1099 else if (max_pixclk > 384000)
1101 else if (max_pixclk > 288000)
1103 else if (max_pixclk > 144000)
1109 static int glk_calc_cdclk(int max_pixclk)
1112 * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk
1113 * as a temporary workaround. Use a higher cdclk instead. (Note that
1114 * intel_compute_max_dotclk() limits the max pixel clock to 99% of max
1117 if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
1119 else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
1125 static int bxt_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1129 if (cdclk == dev_priv->cdclk.hw.ref)
1134 MISSING_CASE(cdclk);
1146 return dev_priv->cdclk.hw.ref * ratio;
1149 static int glk_de_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1153 if (cdclk == dev_priv->cdclk.hw.ref)
1158 MISSING_CASE(cdclk);
1166 return dev_priv->cdclk.hw.ref * ratio;
1169 static void bxt_de_pll_update(struct drm_i915_private *dev_priv,
1170 struct intel_cdclk_state *cdclk_state)
1174 cdclk_state->ref = 19200;
1175 cdclk_state->vco = 0;
1177 val = I915_READ(BXT_DE_PLL_ENABLE);
1178 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1181 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1184 val = I915_READ(BXT_DE_PLL_CTL);
1185 cdclk_state->vco = (val & BXT_DE_PLL_RATIO_MASK) * cdclk_state->ref;
1188 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1189 struct intel_cdclk_state *cdclk_state)
1194 bxt_de_pll_update(dev_priv, cdclk_state);
1196 cdclk_state->cdclk = cdclk_state->ref;
1198 if (cdclk_state->vco == 0)
1201 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1204 case BXT_CDCLK_CD2X_DIV_SEL_1:
1207 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1208 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1211 case BXT_CDCLK_CD2X_DIV_SEL_2:
1214 case BXT_CDCLK_CD2X_DIV_SEL_4:
1218 MISSING_CASE(divider);
1222 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1225 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1227 I915_WRITE(BXT_DE_PLL_ENABLE, 0);
1230 if (intel_wait_for_register(dev_priv,
1231 BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
1233 DRM_ERROR("timeout waiting for DE PLL unlock\n");
1235 dev_priv->cdclk.hw.vco = 0;
1238 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1240 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1243 val = I915_READ(BXT_DE_PLL_CTL);
1244 val &= ~BXT_DE_PLL_RATIO_MASK;
1245 val |= BXT_DE_PLL_RATIO(ratio);
1246 I915_WRITE(BXT_DE_PLL_CTL, val);
1248 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1251 if (intel_wait_for_register(dev_priv,
1256 DRM_ERROR("timeout waiting for DE PLL lock\n");
1258 dev_priv->cdclk.hw.vco = vco;
1261 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1262 const struct intel_cdclk_state *cdclk_state)
1264 int cdclk = cdclk_state->cdclk;
1265 int vco = cdclk_state->vco;
1269 /* cdclk = vco / 2 / div{1,1.5,2,4} */
1270 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1272 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
1275 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1278 WARN(IS_GEMINILAKE(dev_priv), "Unsupported divider\n");
1279 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
1282 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1285 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1288 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1292 mutex_lock(&dev_priv->rps.hw_lock);
1294 * Inform power controller of upcoming frequency change. BSpec
1295 * requires us to wait up to 150usec, but that leads to timeouts;
1296 * the 2ms used here is based on experiment.
1298 ret = sandybridge_pcode_write_timeout(dev_priv,
1299 HSW_PCODE_DE_WRITE_FREQ_REQ,
1301 mutex_unlock(&dev_priv->rps.hw_lock);
1304 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
1309 if (dev_priv->cdclk.hw.vco != 0 &&
1310 dev_priv->cdclk.hw.vco != vco)
1311 bxt_de_pll_disable(dev_priv);
1313 if (dev_priv->cdclk.hw.vco != vco)
1314 bxt_de_pll_enable(dev_priv, vco);
1316 val = divider | skl_cdclk_decimal(cdclk);
1318 * FIXME if only the cd2x divider needs changing, it could be done
1319 * without shutting off the pipe (if only one pipe is active).
1321 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1323 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1326 if (cdclk >= 500000)
1327 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1328 I915_WRITE(CDCLK_CTL, val);
1330 mutex_lock(&dev_priv->rps.hw_lock);
1332 * The timeout isn't specified, the 2ms used here is based on
1334 * FIXME: Waiting for the request completion could be delayed until
1335 * the next PCODE request based on BSpec.
1337 ret = sandybridge_pcode_write_timeout(dev_priv,
1338 HSW_PCODE_DE_WRITE_FREQ_REQ,
1339 DIV_ROUND_UP(cdclk, 25000), 2000);
1340 mutex_unlock(&dev_priv->rps.hw_lock);
1343 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
1348 intel_update_cdclk(dev_priv);
1351 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1353 u32 cdctl, expected;
1355 intel_update_cdclk(dev_priv);
1357 if (dev_priv->cdclk.hw.vco == 0 ||
1358 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1361 /* DPLL okay; verify the cdclock
1363 * Some BIOS versions leave an incorrect decimal frequency value and
1364 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1365 * so sanitize this register.
1367 cdctl = I915_READ(CDCLK_CTL);
1369 * Let's ignore the pipe field, since BIOS could have configured the
1370 * dividers both synching to an active pipe, or asynchronously
1373 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1375 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1376 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1378 * Disable SSA Precharge when CD clock frequency < 500 MHz,
1381 if (dev_priv->cdclk.hw.cdclk >= 500000)
1382 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1384 if (cdctl == expected)
1385 /* All well; nothing to sanitize */
1389 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1391 /* force cdclk programming */
1392 dev_priv->cdclk.hw.cdclk = 0;
1394 /* force full PLL disable + enable */
1395 dev_priv->cdclk.hw.vco = -1;
1399 * bxt_init_cdclk - Initialize CDCLK on BXT
1400 * @dev_priv: i915 device
1402 * Initialize CDCLK for BXT and derivatives. This is generally
1403 * done only during the display core initialization sequence,
1404 * after which the DMC will take care of turning CDCLK off/on
1407 void bxt_init_cdclk(struct drm_i915_private *dev_priv)
1409 struct intel_cdclk_state cdclk_state;
1411 bxt_sanitize_cdclk(dev_priv);
1413 if (dev_priv->cdclk.hw.cdclk != 0 &&
1414 dev_priv->cdclk.hw.vco != 0)
1417 cdclk_state = dev_priv->cdclk.hw;
1421 * - The initial CDCLK needs to be read from VBT.
1422 * Need to make this change after VBT has changes for BXT.
1424 if (IS_GEMINILAKE(dev_priv)) {
1425 cdclk_state.cdclk = glk_calc_cdclk(0);
1426 cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
1428 cdclk_state.cdclk = bxt_calc_cdclk(0);
1429 cdclk_state.vco = bxt_de_pll_vco(dev_priv, cdclk_state.cdclk);
1432 bxt_set_cdclk(dev_priv, &cdclk_state);
1436 * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
1437 * @dev_priv: i915 device
1439 * Uninitialize CDCLK for BXT and derivatives. This is done only
1440 * during the display core uninitialization sequence.
1442 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv)
1444 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1446 cdclk_state.cdclk = cdclk_state.ref;
1447 cdclk_state.vco = 0;
1449 bxt_set_cdclk(dev_priv, &cdclk_state);
1452 static int cnl_calc_cdclk(int max_pixclk)
1454 if (max_pixclk > 336000)
1456 else if (max_pixclk > 168000)
1462 static void cnl_cdclk_pll_update(struct drm_i915_private *dev_priv,
1463 struct intel_cdclk_state *cdclk_state)
1467 if (I915_READ(SKL_DSSM) & CNL_DSSM_CDCLK_PLL_REFCLK_24MHz)
1468 cdclk_state->ref = 24000;
1470 cdclk_state->ref = 19200;
1472 cdclk_state->vco = 0;
1474 val = I915_READ(BXT_DE_PLL_ENABLE);
1475 if ((val & BXT_DE_PLL_PLL_ENABLE) == 0)
1478 if (WARN_ON((val & BXT_DE_PLL_LOCK) == 0))
1481 cdclk_state->vco = (val & CNL_CDCLK_PLL_RATIO_MASK) * cdclk_state->ref;
1484 static void cnl_get_cdclk(struct drm_i915_private *dev_priv,
1485 struct intel_cdclk_state *cdclk_state)
1490 cnl_cdclk_pll_update(dev_priv, cdclk_state);
1492 cdclk_state->cdclk = cdclk_state->ref;
1494 if (cdclk_state->vco == 0)
1497 divider = I915_READ(CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1500 case BXT_CDCLK_CD2X_DIV_SEL_1:
1503 case BXT_CDCLK_CD2X_DIV_SEL_2:
1507 MISSING_CASE(divider);
1511 cdclk_state->cdclk = DIV_ROUND_CLOSEST(cdclk_state->vco, div);
1514 static void cnl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1518 val = I915_READ(BXT_DE_PLL_ENABLE);
1519 val &= ~BXT_DE_PLL_PLL_ENABLE;
1520 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1523 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
1524 DRM_ERROR("timout waiting for CDCLK PLL unlock\n");
1526 dev_priv->cdclk.hw.vco = 0;
1529 static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1531 int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
1534 val = CNL_CDCLK_PLL_RATIO(ratio);
1535 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1537 val |= BXT_DE_PLL_PLL_ENABLE;
1538 I915_WRITE(BXT_DE_PLL_ENABLE, val);
1541 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
1542 DRM_ERROR("timout waiting for CDCLK PLL lock\n");
1544 dev_priv->cdclk.hw.vco = vco;
1547 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
1548 const struct intel_cdclk_state *cdclk_state)
1550 int cdclk = cdclk_state->cdclk;
1551 int vco = cdclk_state->vco;
1552 u32 val, divider, pcu_ack;
1555 mutex_lock(&dev_priv->rps.hw_lock);
1556 ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
1557 SKL_CDCLK_PREPARE_FOR_CHANGE,
1558 SKL_CDCLK_READY_FOR_CHANGE,
1559 SKL_CDCLK_READY_FOR_CHANGE, 3);
1560 mutex_unlock(&dev_priv->rps.hw_lock);
1562 DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
1567 /* cdclk = vco / 2 / div{1,2} */
1568 switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1570 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
1573 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1576 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
1579 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
1596 if (dev_priv->cdclk.hw.vco != 0 &&
1597 dev_priv->cdclk.hw.vco != vco)
1598 cnl_cdclk_pll_disable(dev_priv);
1600 if (dev_priv->cdclk.hw.vco != vco)
1601 cnl_cdclk_pll_enable(dev_priv, vco);
1603 val = divider | skl_cdclk_decimal(cdclk);
1605 * FIXME if only the cd2x divider needs changing, it could be done
1606 * without shutting off the pipe (if only one pipe is active).
1608 val |= BXT_CDCLK_CD2X_PIPE_NONE;
1609 I915_WRITE(CDCLK_CTL, val);
1611 /* inform PCU of the change */
1612 mutex_lock(&dev_priv->rps.hw_lock);
1613 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
1614 mutex_unlock(&dev_priv->rps.hw_lock);
1616 intel_update_cdclk(dev_priv);
1619 static int cnl_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1623 if (cdclk == dev_priv->cdclk.hw.ref)
1628 MISSING_CASE(cdclk);
1631 ratio = dev_priv->cdclk.hw.ref == 19200 ? 35 : 28;
1634 ratio = dev_priv->cdclk.hw.ref == 19200 ? 55 : 44;
1638 return dev_priv->cdclk.hw.ref * ratio;
1641 static void cnl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1643 u32 cdctl, expected;
1645 intel_update_cdclk(dev_priv);
1647 if (dev_priv->cdclk.hw.vco == 0 ||
1648 dev_priv->cdclk.hw.cdclk == dev_priv->cdclk.hw.ref)
1651 /* DPLL okay; verify the cdclock
1653 * Some BIOS versions leave an incorrect decimal frequency value and
1654 * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1655 * so sanitize this register.
1657 cdctl = I915_READ(CDCLK_CTL);
1659 * Let's ignore the pipe field, since BIOS could have configured the
1660 * dividers both synching to an active pipe, or asynchronously
1663 cdctl &= ~BXT_CDCLK_CD2X_PIPE_NONE;
1665 expected = (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) |
1666 skl_cdclk_decimal(dev_priv->cdclk.hw.cdclk);
1668 if (cdctl == expected)
1669 /* All well; nothing to sanitize */
1673 DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
1675 /* force cdclk programming */
1676 dev_priv->cdclk.hw.cdclk = 0;
1678 /* force full PLL disable + enable */
1679 dev_priv->cdclk.hw.vco = -1;
1683 * cnl_init_cdclk - Initialize CDCLK on CNL
1684 * @dev_priv: i915 device
1686 * Initialize CDCLK for CNL. This is generally
1687 * done only during the display core initialization sequence,
1688 * after which the DMC will take care of turning CDCLK off/on
1691 void cnl_init_cdclk(struct drm_i915_private *dev_priv)
1693 struct intel_cdclk_state cdclk_state;
1695 cnl_sanitize_cdclk(dev_priv);
1697 if (dev_priv->cdclk.hw.cdclk != 0 &&
1698 dev_priv->cdclk.hw.vco != 0)
1701 cdclk_state = dev_priv->cdclk.hw;
1703 cdclk_state.cdclk = cnl_calc_cdclk(0);
1704 cdclk_state.vco = cnl_cdclk_pll_vco(dev_priv, cdclk_state.cdclk);
1706 cnl_set_cdclk(dev_priv, &cdclk_state);
1710 * cnl_uninit_cdclk - Uninitialize CDCLK on CNL
1711 * @dev_priv: i915 device
1713 * Uninitialize CDCLK for CNL. This is done only
1714 * during the display core uninitialization sequence.
1716 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv)
1718 struct intel_cdclk_state cdclk_state = dev_priv->cdclk.hw;
1720 cdclk_state.cdclk = cdclk_state.ref;
1721 cdclk_state.vco = 0;
1723 cnl_set_cdclk(dev_priv, &cdclk_state);
1727 * intel_cdclk_state_compare - Determine if two CDCLK states differ
1728 * @a: first CDCLK state
1729 * @b: second CDCLK state
1732 * True if the CDCLK states are identical, false if they differ.
1734 bool intel_cdclk_state_compare(const struct intel_cdclk_state *a,
1735 const struct intel_cdclk_state *b)
1737 return memcmp(a, b, sizeof(*a)) == 0;
1741 * intel_set_cdclk - Push the CDCLK state to the hardware
1742 * @dev_priv: i915 device
1743 * @cdclk_state: new CDCLK state
1745 * Program the hardware based on the passed in CDCLK state,
1748 void intel_set_cdclk(struct drm_i915_private *dev_priv,
1749 const struct intel_cdclk_state *cdclk_state)
1751 if (intel_cdclk_state_compare(&dev_priv->cdclk.hw, cdclk_state))
1754 if (WARN_ON_ONCE(!dev_priv->display.set_cdclk))
1757 DRM_DEBUG_DRIVER("Changing CDCLK to %d kHz, VCO %d kHz, ref %d kHz\n",
1758 cdclk_state->cdclk, cdclk_state->vco,
1761 dev_priv->display.set_cdclk(dev_priv, cdclk_state);
1764 static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
1767 struct drm_i915_private *dev_priv =
1768 to_i915(crtc_state->base.crtc->dev);
1770 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
1771 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
1772 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
1774 /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
1775 * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
1776 * there may be audio corruption or screen corruption." This cdclk
1777 * restriction for GLK is 316.8 MHz and since GLK can output two
1778 * pixels per clock, the pixel rate becomes 2 * 316.8 MHz.
1780 if (intel_crtc_has_dp_encoder(crtc_state) &&
1781 crtc_state->has_audio &&
1782 crtc_state->port_clock >= 540000 &&
1783 crtc_state->lane_count == 4) {
1784 if (IS_CANNONLAKE(dev_priv))
1785 pixel_rate = max(316800, pixel_rate);
1786 else if (IS_GEMINILAKE(dev_priv))
1787 pixel_rate = max(2 * 316800, pixel_rate);
1789 pixel_rate = max(432000, pixel_rate);
1792 /* According to BSpec, "The CD clock frequency must be at least twice
1793 * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
1794 * The check for GLK has to be adjusted as the platform can output
1795 * two pixels per clock.
1797 if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
1798 if (IS_GEMINILAKE(dev_priv))
1799 pixel_rate = max(2 * 2 * 96000, pixel_rate);
1801 pixel_rate = max(2 * 96000, pixel_rate);
1807 /* compute the max rate for new configuration */
1808 static int intel_max_pixel_rate(struct drm_atomic_state *state)
1810 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1811 struct drm_i915_private *dev_priv = to_i915(state->dev);
1812 struct drm_crtc *crtc;
1813 struct drm_crtc_state *cstate;
1814 struct intel_crtc_state *crtc_state;
1815 unsigned int max_pixel_rate = 0, i;
1818 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
1819 sizeof(intel_state->min_pixclk));
1821 for_each_new_crtc_in_state(state, crtc, cstate, i) {
1824 crtc_state = to_intel_crtc_state(cstate);
1825 if (!crtc_state->base.enable) {
1826 intel_state->min_pixclk[i] = 0;
1830 pixel_rate = crtc_state->pixel_rate;
1832 if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
1834 bdw_adjust_min_pipe_pixel_rate(crtc_state,
1837 intel_state->min_pixclk[i] = pixel_rate;
1840 for_each_pipe(dev_priv, pipe)
1841 max_pixel_rate = max(intel_state->min_pixclk[pipe],
1844 return max_pixel_rate;
1847 static int vlv_modeset_calc_cdclk(struct drm_atomic_state *state)
1849 struct drm_i915_private *dev_priv = to_i915(state->dev);
1850 int max_pixclk = intel_max_pixel_rate(state);
1851 struct intel_atomic_state *intel_state =
1852 to_intel_atomic_state(state);
1855 cdclk = vlv_calc_cdclk(dev_priv, max_pixclk);
1857 if (cdclk > dev_priv->max_cdclk_freq) {
1858 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1859 cdclk, dev_priv->max_cdclk_freq);
1863 intel_state->cdclk.logical.cdclk = cdclk;
1865 if (!intel_state->active_crtcs) {
1866 cdclk = vlv_calc_cdclk(dev_priv, 0);
1868 intel_state->cdclk.actual.cdclk = cdclk;
1870 intel_state->cdclk.actual =
1871 intel_state->cdclk.logical;
1877 static int bdw_modeset_calc_cdclk(struct drm_atomic_state *state)
1879 struct drm_i915_private *dev_priv = to_i915(state->dev);
1880 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1881 int max_pixclk = intel_max_pixel_rate(state);
1885 * FIXME should also account for plane ratio
1886 * once 64bpp pixel formats are supported.
1888 cdclk = bdw_calc_cdclk(max_pixclk);
1890 if (cdclk > dev_priv->max_cdclk_freq) {
1891 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1892 cdclk, dev_priv->max_cdclk_freq);
1896 intel_state->cdclk.logical.cdclk = cdclk;
1898 if (!intel_state->active_crtcs) {
1899 cdclk = bdw_calc_cdclk(0);
1901 intel_state->cdclk.actual.cdclk = cdclk;
1903 intel_state->cdclk.actual =
1904 intel_state->cdclk.logical;
1910 static int skl_modeset_calc_cdclk(struct drm_atomic_state *state)
1912 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
1913 struct drm_i915_private *dev_priv = to_i915(state->dev);
1914 const int max_pixclk = intel_max_pixel_rate(state);
1917 vco = intel_state->cdclk.logical.vco;
1919 vco = dev_priv->skl_preferred_vco_freq;
1922 * FIXME should also account for plane ratio
1923 * once 64bpp pixel formats are supported.
1925 cdclk = skl_calc_cdclk(max_pixclk, vco);
1927 if (cdclk > dev_priv->max_cdclk_freq) {
1928 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1929 cdclk, dev_priv->max_cdclk_freq);
1933 intel_state->cdclk.logical.vco = vco;
1934 intel_state->cdclk.logical.cdclk = cdclk;
1936 if (!intel_state->active_crtcs) {
1937 cdclk = skl_calc_cdclk(0, vco);
1939 intel_state->cdclk.actual.vco = vco;
1940 intel_state->cdclk.actual.cdclk = cdclk;
1942 intel_state->cdclk.actual =
1943 intel_state->cdclk.logical;
1949 static int bxt_modeset_calc_cdclk(struct drm_atomic_state *state)
1951 struct drm_i915_private *dev_priv = to_i915(state->dev);
1952 int max_pixclk = intel_max_pixel_rate(state);
1953 struct intel_atomic_state *intel_state =
1954 to_intel_atomic_state(state);
1957 if (IS_GEMINILAKE(dev_priv)) {
1958 cdclk = glk_calc_cdclk(max_pixclk);
1959 vco = glk_de_pll_vco(dev_priv, cdclk);
1961 cdclk = bxt_calc_cdclk(max_pixclk);
1962 vco = bxt_de_pll_vco(dev_priv, cdclk);
1965 if (cdclk > dev_priv->max_cdclk_freq) {
1966 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
1967 cdclk, dev_priv->max_cdclk_freq);
1971 intel_state->cdclk.logical.vco = vco;
1972 intel_state->cdclk.logical.cdclk = cdclk;
1974 if (!intel_state->active_crtcs) {
1975 if (IS_GEMINILAKE(dev_priv)) {
1976 cdclk = glk_calc_cdclk(0);
1977 vco = glk_de_pll_vco(dev_priv, cdclk);
1979 cdclk = bxt_calc_cdclk(0);
1980 vco = bxt_de_pll_vco(dev_priv, cdclk);
1983 intel_state->cdclk.actual.vco = vco;
1984 intel_state->cdclk.actual.cdclk = cdclk;
1986 intel_state->cdclk.actual =
1987 intel_state->cdclk.logical;
1993 static int cnl_modeset_calc_cdclk(struct drm_atomic_state *state)
1995 struct drm_i915_private *dev_priv = to_i915(state->dev);
1996 struct intel_atomic_state *intel_state =
1997 to_intel_atomic_state(state);
1998 int max_pixclk = intel_max_pixel_rate(state);
2001 cdclk = cnl_calc_cdclk(max_pixclk);
2002 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2004 if (cdclk > dev_priv->max_cdclk_freq) {
2005 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
2006 cdclk, dev_priv->max_cdclk_freq);
2010 intel_state->cdclk.logical.vco = vco;
2011 intel_state->cdclk.logical.cdclk = cdclk;
2013 if (!intel_state->active_crtcs) {
2014 cdclk = cnl_calc_cdclk(0);
2015 vco = cnl_cdclk_pll_vco(dev_priv, cdclk);
2017 intel_state->cdclk.actual.vco = vco;
2018 intel_state->cdclk.actual.cdclk = cdclk;
2020 intel_state->cdclk.actual =
2021 intel_state->cdclk.logical;
2027 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
2029 int max_cdclk_freq = dev_priv->max_cdclk_freq;
2031 if (IS_GEMINILAKE(dev_priv))
2033 * FIXME: Limiting to 99% as a temporary workaround. See
2034 * glk_calc_cdclk() for details.
2036 return 2 * max_cdclk_freq * 99 / 100;
2037 else if (INTEL_INFO(dev_priv)->gen >= 9 ||
2038 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2039 return max_cdclk_freq;
2040 else if (IS_CHERRYVIEW(dev_priv))
2041 return max_cdclk_freq*95/100;
2042 else if (INTEL_INFO(dev_priv)->gen < 4)
2043 return 2*max_cdclk_freq*90/100;
2045 return max_cdclk_freq*90/100;
2049 * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
2050 * @dev_priv: i915 device
2052 * Determine the maximum CDCLK frequency the platform supports, and also
2053 * derive the maximum dot clock frequency the maximum CDCLK frequency
2056 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
2058 if (IS_CANNONLAKE(dev_priv)) {
2059 dev_priv->max_cdclk_freq = 528000;
2060 } else if (IS_GEN9_BC(dev_priv)) {
2061 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
2064 vco = dev_priv->skl_preferred_vco_freq;
2065 WARN_ON(vco != 8100000 && vco != 8640000);
2068 * Use the lower (vco 8640) cdclk values as a
2069 * first guess. skl_calc_cdclk() will correct it
2070 * if the preferred vco is 8100 instead.
2072 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
2074 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
2076 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
2081 dev_priv->max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
2082 } else if (IS_GEMINILAKE(dev_priv)) {
2083 dev_priv->max_cdclk_freq = 316800;
2084 } else if (IS_BROXTON(dev_priv)) {
2085 dev_priv->max_cdclk_freq = 624000;
2086 } else if (IS_BROADWELL(dev_priv)) {
2088 * FIXME with extra cooling we can allow
2089 * 540 MHz for ULX and 675 Mhz for ULT.
2090 * How can we know if extra cooling is
2091 * available? PCI ID, VTB, something else?
2093 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
2094 dev_priv->max_cdclk_freq = 450000;
2095 else if (IS_BDW_ULX(dev_priv))
2096 dev_priv->max_cdclk_freq = 450000;
2097 else if (IS_BDW_ULT(dev_priv))
2098 dev_priv->max_cdclk_freq = 540000;
2100 dev_priv->max_cdclk_freq = 675000;
2101 } else if (IS_CHERRYVIEW(dev_priv)) {
2102 dev_priv->max_cdclk_freq = 320000;
2103 } else if (IS_VALLEYVIEW(dev_priv)) {
2104 dev_priv->max_cdclk_freq = 400000;
2106 /* otherwise assume cdclk is fixed */
2107 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk;
2110 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
2112 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
2113 dev_priv->max_cdclk_freq);
2115 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
2116 dev_priv->max_dotclk_freq);
2120 * intel_update_cdclk - Determine the current CDCLK frequency
2121 * @dev_priv: i915 device
2123 * Determine the current CDCLK frequency.
2125 void intel_update_cdclk(struct drm_i915_private *dev_priv)
2127 dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);
2129 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
2130 dev_priv->cdclk.hw.cdclk, dev_priv->cdclk.hw.vco,
2131 dev_priv->cdclk.hw.ref);
2134 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
2135 * Programmng [sic] note: bit[9:2] should be programmed to the number
2136 * of cdclk that generates 4MHz reference clock freq which is used to
2137 * generate GMBus clock. This will vary with the cdclk freq.
2139 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2140 I915_WRITE(GMBUSFREQ_VLV,
2141 DIV_ROUND_UP(dev_priv->cdclk.hw.cdclk, 1000));
2144 static int cnp_rawclk(struct drm_i915_private *dev_priv)
2147 int divider, fraction;
2149 if (I915_READ(SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
2159 rawclk = CNP_RAWCLK_DIV((divider / 1000) - 1);
2161 rawclk |= CNP_RAWCLK_FRAC(DIV_ROUND_CLOSEST(1000,
2164 I915_WRITE(PCH_RAWCLK_FREQ, rawclk);
2165 return divider + fraction;
2168 static int pch_rawclk(struct drm_i915_private *dev_priv)
2170 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
2173 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
2175 /* RAWCLK_FREQ_VLV register updated from power well code */
2176 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
2177 CCK_DISPLAY_REF_CLOCK_CONTROL);
2180 static int g4x_hrawclk(struct drm_i915_private *dev_priv)
2184 /* hrawclock is 1/4 the FSB frequency */
2185 clkcfg = I915_READ(CLKCFG);
2186 switch (clkcfg & CLKCFG_FSB_MASK) {
2187 case CLKCFG_FSB_400:
2189 case CLKCFG_FSB_533:
2191 case CLKCFG_FSB_667:
2193 case CLKCFG_FSB_800:
2195 case CLKCFG_FSB_1067:
2196 case CLKCFG_FSB_1067_ALT:
2198 case CLKCFG_FSB_1333:
2199 case CLKCFG_FSB_1333_ALT:
2207 * intel_update_rawclk - Determine the current RAWCLK frequency
2208 * @dev_priv: i915 device
2210 * Determine the current RAWCLK frequency. RAWCLK is a fixed
2211 * frequency clock so this needs to done only once.
2213 void intel_update_rawclk(struct drm_i915_private *dev_priv)
2216 if (HAS_PCH_CNP(dev_priv))
2217 dev_priv->rawclk_freq = cnp_rawclk(dev_priv);
2218 else if (HAS_PCH_SPLIT(dev_priv))
2219 dev_priv->rawclk_freq = pch_rawclk(dev_priv);
2220 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2221 dev_priv->rawclk_freq = vlv_hrawclk(dev_priv);
2222 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
2223 dev_priv->rawclk_freq = g4x_hrawclk(dev_priv);
2225 /* no rawclk on other platforms, or no need to know it */
2228 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
2232 * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
2233 * @dev_priv: i915 device
2235 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
2237 if (IS_CHERRYVIEW(dev_priv)) {
2238 dev_priv->display.set_cdclk = chv_set_cdclk;
2239 dev_priv->display.modeset_calc_cdclk =
2240 vlv_modeset_calc_cdclk;
2241 } else if (IS_VALLEYVIEW(dev_priv)) {
2242 dev_priv->display.set_cdclk = vlv_set_cdclk;
2243 dev_priv->display.modeset_calc_cdclk =
2244 vlv_modeset_calc_cdclk;
2245 } else if (IS_BROADWELL(dev_priv)) {
2246 dev_priv->display.set_cdclk = bdw_set_cdclk;
2247 dev_priv->display.modeset_calc_cdclk =
2248 bdw_modeset_calc_cdclk;
2249 } else if (IS_GEN9_LP(dev_priv)) {
2250 dev_priv->display.set_cdclk = bxt_set_cdclk;
2251 dev_priv->display.modeset_calc_cdclk =
2252 bxt_modeset_calc_cdclk;
2253 } else if (IS_GEN9_BC(dev_priv)) {
2254 dev_priv->display.set_cdclk = skl_set_cdclk;
2255 dev_priv->display.modeset_calc_cdclk =
2256 skl_modeset_calc_cdclk;
2257 } else if (IS_CANNONLAKE(dev_priv)) {
2258 dev_priv->display.set_cdclk = cnl_set_cdclk;
2259 dev_priv->display.modeset_calc_cdclk =
2260 cnl_modeset_calc_cdclk;
2263 if (IS_CANNONLAKE(dev_priv))
2264 dev_priv->display.get_cdclk = cnl_get_cdclk;
2265 else if (IS_GEN9_BC(dev_priv))
2266 dev_priv->display.get_cdclk = skl_get_cdclk;
2267 else if (IS_GEN9_LP(dev_priv))
2268 dev_priv->display.get_cdclk = bxt_get_cdclk;
2269 else if (IS_BROADWELL(dev_priv))
2270 dev_priv->display.get_cdclk = bdw_get_cdclk;
2271 else if (IS_HASWELL(dev_priv))
2272 dev_priv->display.get_cdclk = hsw_get_cdclk;
2273 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2274 dev_priv->display.get_cdclk = vlv_get_cdclk;
2275 else if (IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
2276 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2277 else if (IS_GEN5(dev_priv))
2278 dev_priv->display.get_cdclk = fixed_450mhz_get_cdclk;
2279 else if (IS_GM45(dev_priv))
2280 dev_priv->display.get_cdclk = gm45_get_cdclk;
2281 else if (IS_G45(dev_priv))
2282 dev_priv->display.get_cdclk = g33_get_cdclk;
2283 else if (IS_I965GM(dev_priv))
2284 dev_priv->display.get_cdclk = i965gm_get_cdclk;
2285 else if (IS_I965G(dev_priv))
2286 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2287 else if (IS_PINEVIEW(dev_priv))
2288 dev_priv->display.get_cdclk = pnv_get_cdclk;
2289 else if (IS_G33(dev_priv))
2290 dev_priv->display.get_cdclk = g33_get_cdclk;
2291 else if (IS_I945GM(dev_priv))
2292 dev_priv->display.get_cdclk = i945gm_get_cdclk;
2293 else if (IS_I945G(dev_priv))
2294 dev_priv->display.get_cdclk = fixed_400mhz_get_cdclk;
2295 else if (IS_I915GM(dev_priv))
2296 dev_priv->display.get_cdclk = i915gm_get_cdclk;
2297 else if (IS_I915G(dev_priv))
2298 dev_priv->display.get_cdclk = fixed_333mhz_get_cdclk;
2299 else if (IS_I865G(dev_priv))
2300 dev_priv->display.get_cdclk = fixed_266mhz_get_cdclk;
2301 else if (IS_I85X(dev_priv))
2302 dev_priv->display.get_cdclk = i85x_get_cdclk;
2303 else if (IS_I845G(dev_priv))
2304 dev_priv->display.get_cdclk = fixed_200mhz_get_cdclk;
2306 WARN(!IS_I830(dev_priv),
2307 "Unknown platform. Assuming 133 MHz CDCLK\n");
2308 dev_priv->display.get_cdclk = fixed_133mhz_get_cdclk;