2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/kernel.h>
25 #include <linux/component.h>
26 #include <drm/i915_component.h>
27 #include "intel_drv.h"
30 #include <drm/drm_edid.h>
34 * DOC: High Definition Audio over HDMI and Display Port
36 * The graphics and audio drivers together support High Definition Audio over
37 * HDMI and Display Port. The audio programming sequences are divided into audio
38 * codec and controller enable and disable sequences. The graphics driver
39 * handles the audio codec sequences, while the audio driver handles the audio
40 * controller sequences.
42 * The disable sequences must be performed before disabling the transcoder or
43 * port. The enable sequences may only be performed after enabling the
44 * transcoder and port, and after completed link training. Therefore the audio
45 * enable/disable sequences are part of the modeset sequence.
47 * The codec and controller sequences could be done either parallel or serial,
48 * but generally the ELDV/PD change in the codec sequence indicates to the audio
49 * driver that the controller sequence should start. Indeed, most of the
50 * co-operation between the graphics and audio drivers is handled via audio
51 * related registers. (The notable exception is the power management, not
54 * The struct &i915_audio_component is used to interact between the graphics
55 * and audio drivers. The struct &i915_audio_component_ops @ops in it is
56 * defined in graphics driver and called in audio driver. The
57 * struct &i915_audio_component_audio_ops @audio_ops is called from i915 driver.
63 } hdmi_audio_clock[] = {
64 { 25175, AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
65 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
66 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
67 { 27027, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
68 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
69 { 54054, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
70 { 74176, AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
71 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
72 { 148352, AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
73 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
76 /* HDMI N/CTS table */
77 #define TMDS_297M 297000
78 #define TMDS_296M 296703
79 #define TMDS_594M 594000
80 #define TMDS_593M 593407
88 { 44100, TMDS_296M, 4459, 234375 },
89 { 44100, TMDS_297M, 4704, 247500 },
90 { 48000, TMDS_296M, 5824, 281250 },
91 { 48000, TMDS_297M, 5120, 247500 },
92 { 32000, TMDS_296M, 5824, 421875 },
93 { 32000, TMDS_297M, 3072, 222750 },
94 { 88200, TMDS_296M, 8918, 234375 },
95 { 88200, TMDS_297M, 9408, 247500 },
96 { 96000, TMDS_296M, 11648, 281250 },
97 { 96000, TMDS_297M, 10240, 247500 },
98 { 176400, TMDS_296M, 17836, 234375 },
99 { 176400, TMDS_297M, 18816, 247500 },
100 { 192000, TMDS_296M, 23296, 281250 },
101 { 192000, TMDS_297M, 20480, 247500 },
102 { 44100, TMDS_593M, 8918, 937500 },
103 { 44100, TMDS_594M, 9408, 990000 },
104 { 48000, TMDS_593M, 5824, 562500 },
105 { 48000, TMDS_594M, 6144, 594000 },
106 { 32000, TMDS_593M, 5824, 843750 },
107 { 32000, TMDS_594M, 3072, 445500 },
108 { 88200, TMDS_593M, 17836, 937500 },
109 { 88200, TMDS_594M, 18816, 990000 },
110 { 96000, TMDS_593M, 11648, 562500 },
111 { 96000, TMDS_594M, 12288, 594000 },
112 { 176400, TMDS_593M, 35672, 937500 },
113 { 176400, TMDS_594M, 37632, 990000 },
114 { 192000, TMDS_593M, 23296, 562500 },
115 { 192000, TMDS_594M, 24576, 594000 },
118 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
119 static u32 audio_config_hdmi_pixel_clock(const struct drm_display_mode *adjusted_mode)
123 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
124 if (adjusted_mode->crtc_clock == hdmi_audio_clock[i].clock)
128 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
129 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n",
130 adjusted_mode->crtc_clock);
134 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
135 hdmi_audio_clock[i].clock,
136 hdmi_audio_clock[i].config);
138 return hdmi_audio_clock[i].config;
141 static int audio_config_get_n(const struct drm_display_mode *mode, int rate)
145 for (i = 0; i < ARRAY_SIZE(aud_ncts); i++) {
146 if ((rate == aud_ncts[i].sample_rate) &&
147 (mode->clock == aud_ncts[i].clock)) {
148 return aud_ncts[i].n;
154 static uint32_t audio_config_setup_n_reg(int n, uint32_t val)
160 n_up = (n >> 12) & 0xff;
161 tmp &= ~(AUD_CONFIG_UPPER_N_MASK | AUD_CONFIG_LOWER_N_MASK);
162 tmp |= ((n_up << AUD_CONFIG_UPPER_N_SHIFT) |
163 (n_low << AUD_CONFIG_LOWER_N_SHIFT) |
164 AUD_CONFIG_N_PROG_ENABLE);
168 /* check whether N/CTS/M need be set manually */
169 static bool audio_rate_need_prog(struct intel_crtc *crtc,
170 const struct drm_display_mode *mode)
172 if (((mode->clock == TMDS_297M) ||
173 (mode->clock == TMDS_296M)) &&
174 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
180 static bool intel_eld_uptodate(struct drm_connector *connector,
181 i915_reg_t reg_eldv, uint32_t bits_eldv,
182 i915_reg_t reg_elda, uint32_t bits_elda,
185 struct drm_i915_private *dev_priv = to_i915(connector->dev);
186 uint8_t *eld = connector->eld;
190 tmp = I915_READ(reg_eldv);
196 tmp = I915_READ(reg_elda);
198 I915_WRITE(reg_elda, tmp);
200 for (i = 0; i < drm_eld_size(eld) / 4; i++)
201 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
207 static void g4x_audio_codec_disable(struct intel_encoder *encoder)
209 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
212 DRM_DEBUG_KMS("Disable audio codec\n");
214 tmp = I915_READ(G4X_AUD_VID_DID);
215 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
216 eldv = G4X_ELDV_DEVCL_DEVBLC;
218 eldv = G4X_ELDV_DEVCTG;
221 tmp = I915_READ(G4X_AUD_CNTL_ST);
223 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
226 static void g4x_audio_codec_enable(struct drm_connector *connector,
227 struct intel_encoder *encoder,
228 const struct drm_display_mode *adjusted_mode)
230 struct drm_i915_private *dev_priv = to_i915(connector->dev);
231 uint8_t *eld = connector->eld;
236 DRM_DEBUG_KMS("Enable audio codec, %u bytes ELD\n", eld[2]);
238 tmp = I915_READ(G4X_AUD_VID_DID);
239 if (tmp == INTEL_AUDIO_DEVBLC || tmp == INTEL_AUDIO_DEVCL)
240 eldv = G4X_ELDV_DEVCL_DEVBLC;
242 eldv = G4X_ELDV_DEVCTG;
244 if (intel_eld_uptodate(connector,
245 G4X_AUD_CNTL_ST, eldv,
246 G4X_AUD_CNTL_ST, G4X_ELD_ADDR_MASK,
250 tmp = I915_READ(G4X_AUD_CNTL_ST);
251 tmp &= ~(eldv | G4X_ELD_ADDR_MASK);
252 len = (tmp >> 9) & 0x1f; /* ELD buffer size */
253 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
255 len = min(drm_eld_size(eld) / 4, len);
256 DRM_DEBUG_DRIVER("ELD size %d\n", len);
257 for (i = 0; i < len; i++)
258 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
260 tmp = I915_READ(G4X_AUD_CNTL_ST);
262 I915_WRITE(G4X_AUD_CNTL_ST, tmp);
265 static void hsw_audio_codec_disable(struct intel_encoder *encoder)
267 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
268 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
269 enum pipe pipe = intel_crtc->pipe;
272 DRM_DEBUG_KMS("Disable audio codec on pipe %c\n", pipe_name(pipe));
274 mutex_lock(&dev_priv->av_mutex);
276 /* Disable timestamps */
277 tmp = I915_READ(HSW_AUD_CFG(pipe));
278 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
279 tmp |= AUD_CONFIG_N_PROG_ENABLE;
280 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
281 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
282 if (intel_crtc_has_dp_encoder(intel_crtc->config))
283 tmp |= AUD_CONFIG_N_VALUE_INDEX;
284 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
287 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
288 tmp &= ~AUDIO_ELD_VALID(pipe);
289 tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
290 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
292 mutex_unlock(&dev_priv->av_mutex);
295 static void hsw_audio_codec_enable(struct drm_connector *connector,
296 struct intel_encoder *encoder,
297 const struct drm_display_mode *adjusted_mode)
299 struct drm_i915_private *dev_priv = to_i915(connector->dev);
300 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
301 enum pipe pipe = intel_crtc->pipe;
302 struct i915_audio_component *acomp = dev_priv->audio_component;
303 const uint8_t *eld = connector->eld;
304 struct intel_digital_port *intel_dig_port =
305 enc_to_dig_port(&encoder->base);
306 enum port port = intel_dig_port->port;
311 DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
312 pipe_name(pipe), drm_eld_size(eld));
314 mutex_lock(&dev_priv->av_mutex);
316 /* Enable audio presence detect, invalidate ELD */
317 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
318 tmp |= AUDIO_OUTPUT_ENABLE(pipe);
319 tmp &= ~AUDIO_ELD_VALID(pipe);
320 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
323 * FIXME: We're supposed to wait for vblank here, but we have vblanks
324 * disabled during the mode set. The proper fix would be to push the
325 * rest of the setup into a vblank work item, queued here, but the
326 * infrastructure is not there yet.
329 /* Reset ELD write address */
330 tmp = I915_READ(HSW_AUD_DIP_ELD_CTRL(pipe));
331 tmp &= ~IBX_ELD_ADDRESS_MASK;
332 I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
334 /* Up to 84 bytes of hw ELD buffer */
335 len = min(drm_eld_size(eld), 84);
336 for (i = 0; i < len / 4; i++)
337 I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
340 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
341 tmp |= AUDIO_ELD_VALID(pipe);
342 I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
344 /* Enable timestamps */
345 tmp = I915_READ(HSW_AUD_CFG(pipe));
346 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
347 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
348 if (intel_crtc_has_dp_encoder(intel_crtc->config))
349 tmp |= AUD_CONFIG_N_VALUE_INDEX;
351 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
353 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
354 if (audio_rate_need_prog(intel_crtc, adjusted_mode)) {
357 else if (port >= PORT_A && port <= PORT_E)
358 rate = acomp->aud_sample_rate[port];
360 DRM_ERROR("invalid port: %d\n", port);
363 n = audio_config_get_n(adjusted_mode, rate);
365 tmp = audio_config_setup_n_reg(n, tmp);
367 DRM_DEBUG_KMS("no suitable N value is found\n");
370 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
372 mutex_unlock(&dev_priv->av_mutex);
375 static void ilk_audio_codec_disable(struct intel_encoder *encoder)
377 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
378 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
379 enum port port = enc_to_dig_port(&encoder->base)->port;
380 enum pipe pipe = intel_crtc->pipe;
382 i915_reg_t aud_config, aud_cntrl_st2;
384 DRM_DEBUG_KMS("Disable audio codec on port %c, pipe %c\n",
385 port_name(port), pipe_name(pipe));
387 if (WARN_ON(port == PORT_A))
390 if (HAS_PCH_IBX(dev_priv)) {
391 aud_config = IBX_AUD_CFG(pipe);
392 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
393 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
394 aud_config = VLV_AUD_CFG(pipe);
395 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
397 aud_config = CPT_AUD_CFG(pipe);
398 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
401 /* Disable timestamps */
402 tmp = I915_READ(aud_config);
403 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
404 tmp |= AUD_CONFIG_N_PROG_ENABLE;
405 tmp &= ~AUD_CONFIG_UPPER_N_MASK;
406 tmp &= ~AUD_CONFIG_LOWER_N_MASK;
407 if (intel_crtc_has_dp_encoder(intel_crtc->config))
408 tmp |= AUD_CONFIG_N_VALUE_INDEX;
409 I915_WRITE(aud_config, tmp);
411 eldv = IBX_ELD_VALID(port);
414 tmp = I915_READ(aud_cntrl_st2);
416 I915_WRITE(aud_cntrl_st2, tmp);
419 static void ilk_audio_codec_enable(struct drm_connector *connector,
420 struct intel_encoder *encoder,
421 const struct drm_display_mode *adjusted_mode)
423 struct drm_i915_private *dev_priv = to_i915(connector->dev);
424 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
425 enum port port = enc_to_dig_port(&encoder->base)->port;
426 enum pipe pipe = intel_crtc->pipe;
427 uint8_t *eld = connector->eld;
430 i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
432 DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
433 port_name(port), pipe_name(pipe), drm_eld_size(eld));
435 if (WARN_ON(port == PORT_A))
439 * FIXME: We're supposed to wait for vblank here, but we have vblanks
440 * disabled during the mode set. The proper fix would be to push the
441 * rest of the setup into a vblank work item, queued here, but the
442 * infrastructure is not there yet.
445 if (HAS_PCH_IBX(connector->dev)) {
446 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
447 aud_config = IBX_AUD_CFG(pipe);
448 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
449 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
450 } else if (IS_VALLEYVIEW(connector->dev) ||
451 IS_CHERRYVIEW(connector->dev)) {
452 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
453 aud_config = VLV_AUD_CFG(pipe);
454 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
455 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
457 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
458 aud_config = CPT_AUD_CFG(pipe);
459 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
460 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
463 eldv = IBX_ELD_VALID(port);
466 tmp = I915_READ(aud_cntrl_st2);
468 I915_WRITE(aud_cntrl_st2, tmp);
470 /* Reset ELD write address */
471 tmp = I915_READ(aud_cntl_st);
472 tmp &= ~IBX_ELD_ADDRESS_MASK;
473 I915_WRITE(aud_cntl_st, tmp);
475 /* Up to 84 bytes of hw ELD buffer */
476 len = min(drm_eld_size(eld), 84);
477 for (i = 0; i < len / 4; i++)
478 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
481 tmp = I915_READ(aud_cntrl_st2);
483 I915_WRITE(aud_cntrl_st2, tmp);
485 /* Enable timestamps */
486 tmp = I915_READ(aud_config);
487 tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
488 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
489 tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
490 if (intel_crtc_has_dp_encoder(intel_crtc->config))
491 tmp |= AUD_CONFIG_N_VALUE_INDEX;
493 tmp |= audio_config_hdmi_pixel_clock(adjusted_mode);
494 I915_WRITE(aud_config, tmp);
498 * intel_audio_codec_enable - Enable the audio codec for HD audio
499 * @intel_encoder: encoder on which to enable audio
501 * The enable sequences may only be performed after enabling the transcoder and
502 * port, and after completed link training.
504 void intel_audio_codec_enable(struct intel_encoder *intel_encoder)
506 struct drm_encoder *encoder = &intel_encoder->base;
507 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
508 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
509 struct drm_connector *connector;
510 struct drm_device *dev = encoder->dev;
511 struct drm_i915_private *dev_priv = to_i915(dev);
512 struct i915_audio_component *acomp = dev_priv->audio_component;
513 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
514 enum port port = intel_dig_port->port;
516 connector = drm_select_eld(encoder);
520 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
523 connector->encoder->base.id,
524 connector->encoder->name);
527 connector->eld[5] &= ~(3 << 2);
528 if (intel_crtc_has_dp_encoder(crtc->config))
529 connector->eld[5] |= (1 << 2);
531 connector->eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
533 if (dev_priv->display.audio_codec_enable)
534 dev_priv->display.audio_codec_enable(connector, intel_encoder,
537 mutex_lock(&dev_priv->av_mutex);
538 intel_dig_port->audio_connector = connector;
539 /* referred in audio callbacks */
540 dev_priv->dig_port_map[port] = intel_encoder;
541 mutex_unlock(&dev_priv->av_mutex);
543 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
544 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
548 * intel_audio_codec_disable - Disable the audio codec for HD audio
549 * @intel_encoder: encoder on which to disable audio
551 * The disable sequences must be performed before disabling the transcoder or
554 void intel_audio_codec_disable(struct intel_encoder *intel_encoder)
556 struct drm_encoder *encoder = &intel_encoder->base;
557 struct drm_device *dev = encoder->dev;
558 struct drm_i915_private *dev_priv = to_i915(dev);
559 struct i915_audio_component *acomp = dev_priv->audio_component;
560 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
561 enum port port = intel_dig_port->port;
563 if (dev_priv->display.audio_codec_disable)
564 dev_priv->display.audio_codec_disable(intel_encoder);
566 mutex_lock(&dev_priv->av_mutex);
567 intel_dig_port->audio_connector = NULL;
568 dev_priv->dig_port_map[port] = NULL;
569 mutex_unlock(&dev_priv->av_mutex);
571 if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify)
572 acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, (int) port);
576 * intel_init_audio_hooks - Set up chip specific audio hooks
577 * @dev_priv: device private
579 void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
581 if (IS_G4X(dev_priv)) {
582 dev_priv->display.audio_codec_enable = g4x_audio_codec_enable;
583 dev_priv->display.audio_codec_disable = g4x_audio_codec_disable;
584 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
585 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
586 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
587 } else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) {
588 dev_priv->display.audio_codec_enable = hsw_audio_codec_enable;
589 dev_priv->display.audio_codec_disable = hsw_audio_codec_disable;
590 } else if (HAS_PCH_SPLIT(dev_priv)) {
591 dev_priv->display.audio_codec_enable = ilk_audio_codec_enable;
592 dev_priv->display.audio_codec_disable = ilk_audio_codec_disable;
596 static void i915_audio_component_get_power(struct device *kdev)
598 intel_display_power_get(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
601 static void i915_audio_component_put_power(struct device *kdev)
603 intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
606 static void i915_audio_component_codec_wake_override(struct device *kdev,
609 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
612 if (!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv))
615 i915_audio_component_get_power(kdev);
618 * Enable/disable generating the codec wake signal, overriding the
619 * internal logic to generate the codec wake to controller.
621 tmp = I915_READ(HSW_AUD_CHICKENBIT);
622 tmp &= ~SKL_AUD_CODEC_WAKE_SIGNAL;
623 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
624 usleep_range(1000, 1500);
627 tmp = I915_READ(HSW_AUD_CHICKENBIT);
628 tmp |= SKL_AUD_CODEC_WAKE_SIGNAL;
629 I915_WRITE(HSW_AUD_CHICKENBIT, tmp);
630 usleep_range(1000, 1500);
633 i915_audio_component_put_power(kdev);
636 /* Get CDCLK in kHz */
637 static int i915_audio_component_get_cdclk_freq(struct device *kdev)
639 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
641 if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
644 return dev_priv->cdclk_freq;
647 static int i915_audio_component_sync_audio_rate(struct device *kdev,
650 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
651 struct intel_encoder *intel_encoder;
652 struct intel_crtc *crtc;
653 struct drm_display_mode *mode;
654 struct i915_audio_component *acomp = dev_priv->audio_component;
655 enum pipe pipe = INVALID_PIPE;
660 /* HSW, BDW, SKL, KBL need this fix */
661 if (!IS_SKYLAKE(dev_priv) &&
662 !IS_KABYLAKE(dev_priv) &&
663 !IS_BROADWELL(dev_priv) &&
664 !IS_HASWELL(dev_priv))
667 i915_audio_component_get_power(kdev);
668 mutex_lock(&dev_priv->av_mutex);
669 /* 1. get the pipe */
670 intel_encoder = dev_priv->dig_port_map[port];
671 /* intel_encoder might be NULL for DP MST */
672 if (!intel_encoder || !intel_encoder->base.crtc ||
673 intel_encoder->type != INTEL_OUTPUT_HDMI) {
674 DRM_DEBUG_KMS("no valid port %c\n", port_name(port));
678 crtc = to_intel_crtc(intel_encoder->base.crtc);
680 if (pipe == INVALID_PIPE) {
681 DRM_DEBUG_KMS("no pipe for the port %c\n", port_name(port));
686 DRM_DEBUG_KMS("pipe %c connects port %c\n",
687 pipe_name(pipe), port_name(port));
688 mode = &crtc->config->base.adjusted_mode;
690 /* port must be valid now, otherwise the pipe will be invalid */
691 acomp->aud_sample_rate[port] = rate;
693 /* 2. check whether to set the N/CTS/M manually or not */
694 if (!audio_rate_need_prog(crtc, mode)) {
695 tmp = I915_READ(HSW_AUD_CFG(pipe));
696 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
697 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
701 n = audio_config_get_n(mode, rate);
703 DRM_DEBUG_KMS("Using automatic mode for N value on port %c\n",
705 tmp = I915_READ(HSW_AUD_CFG(pipe));
706 tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
707 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
711 /* 3. set the N/CTS/M */
712 tmp = I915_READ(HSW_AUD_CFG(pipe));
713 tmp = audio_config_setup_n_reg(n, tmp);
714 I915_WRITE(HSW_AUD_CFG(pipe), tmp);
717 mutex_unlock(&dev_priv->av_mutex);
718 i915_audio_component_put_power(kdev);
722 static int i915_audio_component_get_eld(struct device *kdev, int port,
724 unsigned char *buf, int max_bytes)
726 struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
727 struct intel_encoder *intel_encoder;
728 struct intel_digital_port *intel_dig_port;
732 mutex_lock(&dev_priv->av_mutex);
733 intel_encoder = dev_priv->dig_port_map[port];
734 /* intel_encoder might be NULL for DP MST */
737 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
738 *enabled = intel_dig_port->audio_connector != NULL;
740 eld = intel_dig_port->audio_connector->eld;
741 ret = drm_eld_size(eld);
742 memcpy(buf, eld, min(max_bytes, ret));
746 mutex_unlock(&dev_priv->av_mutex);
750 static const struct i915_audio_component_ops i915_audio_component_ops = {
751 .owner = THIS_MODULE,
752 .get_power = i915_audio_component_get_power,
753 .put_power = i915_audio_component_put_power,
754 .codec_wake_override = i915_audio_component_codec_wake_override,
755 .get_cdclk_freq = i915_audio_component_get_cdclk_freq,
756 .sync_audio_rate = i915_audio_component_sync_audio_rate,
757 .get_eld = i915_audio_component_get_eld,
760 static int i915_audio_component_bind(struct device *i915_kdev,
761 struct device *hda_kdev, void *data)
763 struct i915_audio_component *acomp = data;
764 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
767 if (WARN_ON(acomp->ops || acomp->dev))
770 drm_modeset_lock_all(&dev_priv->drm);
771 acomp->ops = &i915_audio_component_ops;
772 acomp->dev = i915_kdev;
773 BUILD_BUG_ON(MAX_PORTS != I915_MAX_PORTS);
774 for (i = 0; i < ARRAY_SIZE(acomp->aud_sample_rate); i++)
775 acomp->aud_sample_rate[i] = 0;
776 dev_priv->audio_component = acomp;
777 drm_modeset_unlock_all(&dev_priv->drm);
782 static void i915_audio_component_unbind(struct device *i915_kdev,
783 struct device *hda_kdev, void *data)
785 struct i915_audio_component *acomp = data;
786 struct drm_i915_private *dev_priv = kdev_to_i915(i915_kdev);
788 drm_modeset_lock_all(&dev_priv->drm);
791 dev_priv->audio_component = NULL;
792 drm_modeset_unlock_all(&dev_priv->drm);
795 static const struct component_ops i915_audio_component_bind_ops = {
796 .bind = i915_audio_component_bind,
797 .unbind = i915_audio_component_unbind,
801 * i915_audio_component_init - initialize and register the audio component
802 * @dev_priv: i915 device instance
804 * This will register with the component framework a child component which
805 * will bind dynamically to the snd_hda_intel driver's corresponding master
806 * component when the latter is registered. During binding the child
807 * initializes an instance of struct i915_audio_component which it receives
808 * from the master. The master can then start to use the interface defined by
809 * this struct. Each side can break the binding at any point by deregistering
810 * its own component after which each side's component unbind callback is
813 * We ignore any error during registration and continue with reduced
814 * functionality (i.e. without HDMI audio).
816 void i915_audio_component_init(struct drm_i915_private *dev_priv)
820 ret = component_add(dev_priv->drm.dev, &i915_audio_component_bind_ops);
822 DRM_ERROR("failed to add audio component (%d)\n", ret);
823 /* continue with reduced functionality */
827 dev_priv->audio_component_registered = true;
831 * i915_audio_component_cleanup - deregister the audio component
832 * @dev_priv: i915 device instance
834 * Deregisters the audio component, breaking any existing binding to the
835 * corresponding snd_hda_intel driver's master component.
837 void i915_audio_component_cleanup(struct drm_i915_private *dev_priv)
839 if (!dev_priv->audio_component_registered)
842 component_del(dev_priv->drm.dev, &i915_audio_component_bind_ops);
843 dev_priv->audio_component_registered = false;