drivers/gpu/drm/i915/i915_pmu.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2017-2018 Intel Corporation
   5  */
   6
   7 #include <linux/irq.h>
   8 #include <linux/pm_runtime.h>
   9
  10 #include "gt/intel_engine.h"
  11 #include "gt/intel_engine_pm.h"
  12 #include "gt/intel_engine_user.h"
  13 #include "gt/intel_gt_pm.h"
  14 #include "gt/intel_rc6.h"
  15 #include "gt/intel_rps.h"
  16
  17 #include "i915_drv.h"
  18 #include "i915_pmu.h"
  19 #include "intel_pm.h"
  20
  21 /* Frequency for the sampling timer for events which need it. */
  22 #define FREQUENCY 200
  23 #define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY)
  24
  25 #define ENGINE_SAMPLE_MASK \
  26         (BIT(I915_SAMPLE_BUSY) | \
  27          BIT(I915_SAMPLE_WAIT) | \
  28          BIT(I915_SAMPLE_SEMA))
  29
  30 #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
  31
  32 static cpumask_t i915_pmu_cpumask;
  33
  34 static u8 engine_config_sample(u64 config)
  35 {
  36         return config & I915_PMU_SAMPLE_MASK;
  37 }
  38
  39 static u8 engine_event_sample(struct perf_event *event)
  40 {
  41         return engine_config_sample(event->attr.config);
  42 }
  43
  44 static u8 engine_event_class(struct perf_event *event)
  45 {
  46         return (event->attr.config >> I915_PMU_CLASS_SHIFT) & 0xff;
  47 }
  48
  49 static u8 engine_event_instance(struct perf_event *event)
  50 {
  51         return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
  52 }
  53
  54 static bool is_engine_config(u64 config)
  55 {
  56         return config < __I915_PMU_OTHER(0);
  57 }
  58
  59 static unsigned int config_enabled_bit(u64 config)
  60 {
  61         if (is_engine_config(config))
  62                 return engine_config_sample(config);
  63         else
  64                 return ENGINE_SAMPLE_BITS + (config - __I915_PMU_OTHER(0));
  65 }
  66
  67 static u64 config_enabled_mask(u64 config)
  68 {
  69         return BIT_ULL(config_enabled_bit(config));
  70 }
  71
  72 static bool is_engine_event(struct perf_event *event)
  73 {
  74         return is_engine_config(event->attr.config);
  75 }
  76
  77 static unsigned int event_enabled_bit(struct perf_event *event)
  78 {
  79         return config_enabled_bit(event->attr.config);
  80 }
  81
  82 static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
  83 {
  84         struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
  85         u64 enable;
  86
  87         /*
  88          * Only some counters need the sampling timer.
  89          *
  90          * We start with a bitmask of all currently enabled events.
  91          */
  92         enable = pmu->enable;
  93
  94         /*
  95          * Mask out all the ones which do not need the timer, or in
  96          * other words keep all the ones that could need the timer.
  97          */
  98         enable &= config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY) |
  99                   config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY) |
 100                   ENGINE_SAMPLE_MASK;
 101
 102         /*
 103          * When the GPU is idle per-engine counters do not need to be
 104          * running so clear those bits out.
 105          */
 106         if (!gpu_active)
 107                 enable &= ~ENGINE_SAMPLE_MASK;
 108         /*
 109          * Also there is software busyness tracking available we do not
 110          * need the timer for I915_SAMPLE_BUSY counter.
 111          */
 112         else if (i915->caps.scheduler & I915_SCHEDULER_CAP_ENGINE_BUSY_STATS)
 113                 enable &= ~BIT(I915_SAMPLE_BUSY);
 114
 115         /*
 116          * If some bits remain it means we need the sampling timer running.
 117          */
 118         return enable;
 119 }
 120
 121 static u64 __get_rc6(struct intel_gt *gt)
 122 {
 123         struct drm_i915_private *i915 = gt->i915;
 124         u64 val;
 125
 126         val = intel_rc6_residency_ns(&gt->rc6,
 127                                      IS_VALLEYVIEW(i915) ?
 128                                      VLV_GT_RENDER_RC6 :
 129                                      GEN6_GT_GFX_RC6);
 130
 131         if (HAS_RC6p(i915))
 132                 val += intel_rc6_residency_ns(&gt->rc6, GEN6_GT_GFX_RC6p);
 133
 134         if (HAS_RC6pp(i915))
 135                 val += intel_rc6_residency_ns(&gt->rc6, GEN6_GT_GFX_RC6pp);
 136
 137         return val;
 138 }
 139
 140 #if IS_ENABLED(CONFIG_PM)
 141
 142 static inline s64 ktime_since(const ktime_t kt)
 143 {
 144         return ktime_to_ns(ktime_sub(ktime_get(), kt));
 145 }
 146
 147 static u64 get_rc6(struct intel_gt *gt)
 148 {
 149         struct drm_i915_private *i915 = gt->i915;
 150         struct i915_pmu *pmu = &i915->pmu;
 151         unsigned long flags;
 152         bool awake = false;
 153         u64 val;
 154
 155         if (intel_gt_pm_get_if_awake(gt)) {
 156                 val = __get_rc6(gt);
 157                 intel_gt_pm_put_async(gt);
 158                 awake = true;
 159         }
 160
 161         spin_lock_irqsave(&pmu->lock, flags);
 162
 163         if (awake) {
 164                 pmu->sample[__I915_SAMPLE_RC6].cur = val;
 165         } else {
 166                 /*
 167                  * We think we are runtime suspended.
 168                  *
 169                  * Report the delta from when the device was suspended to now,
 170                  * on top of the last known real value, as the approximated RC6
 171                  * counter value.
 172                  */
 173                 val = ktime_since(pmu->sleep_last);
 174                 val += pmu->sample[__I915_SAMPLE_RC6].cur;
 175         }
 176
 177         if (val < pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur)
 178                 val = pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur;
 179         else
 180                 pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = val;
 181
 182         spin_unlock_irqrestore(&pmu->lock, flags);
 183
 184         return val;
 185 }
 186
 187 static void init_rc6(struct i915_pmu *pmu)
 188 {
 189         struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
 190         intel_wakeref_t wakeref;
 191
 192         with_intel_runtime_pm(i915->gt.uncore->rpm, wakeref) {
 193                 pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(&i915->gt);
 194                 pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur =
 195                                         pmu->sample[__I915_SAMPLE_RC6].cur;
 196                 pmu->sleep_last = ktime_get();
 197         }
 198 }
 199
 200 static void park_rc6(struct drm_i915_private *i915)
 201 {
 202         struct i915_pmu *pmu = &i915->pmu;
 203
 204         pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(&i915->gt);
 205         pmu->sleep_last = ktime_get();
 206 }
 207
 208 #else
 209
 210 static u64 get_rc6(struct intel_gt *gt)
 211 {
 212         return __get_rc6(gt);
 213 }
 214
 215 static void init_rc6(struct i915_pmu *pmu) { }
 216 static void park_rc6(struct drm_i915_private *i915) {}
 217
 218 #endif
 219
 220 static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
 221 {
 222         if (!pmu->timer_enabled && pmu_needs_timer(pmu, true)) {
 223                 pmu->timer_enabled = true;
 224                 pmu->timer_last = ktime_get();
 225                 hrtimer_start_range_ns(&pmu->timer,
 226                                        ns_to_ktime(PERIOD), 0,
 227                                        HRTIMER_MODE_REL_PINNED);
 228         }
 229 }
 230
 231 void i915_pmu_gt_parked(struct drm_i915_private *i915)
 232 {
 233         struct i915_pmu *pmu = &i915->pmu;
 234
 235         if (!pmu->base.event_init)
 236                 return;
 237
 238         spin_lock_irq(&pmu->lock);
 239
 240         park_rc6(i915);
 241
 242         /*
 243          * Signal sampling timer to stop if only engine events are enabled and
 244          * GPU went idle.
 245          */
 246         pmu->timer_enabled = pmu_needs_timer(pmu, false);
 247
 248         spin_unlock_irq(&pmu->lock);
 249 }
 250
 251 void i915_pmu_gt_unparked(struct drm_i915_private *i915)
 252 {
 253         struct i915_pmu *pmu = &i915->pmu;
 254
 255         if (!pmu->base.event_init)
 256                 return;
 257
 258         spin_lock_irq(&pmu->lock);
 259
 260         /*
 261          * Re-enable sampling timer when GPU goes active.
 262          */
 263         __i915_pmu_maybe_start_timer(pmu);
 264
 265         spin_unlock_irq(&pmu->lock);
 266 }
 267
 268 static void
 269 add_sample(struct i915_pmu_sample *sample, u32 val)
 270 {
 271         sample->cur += val;
 272 }
 273
 274 static bool exclusive_mmio_access(const struct drm_i915_private *i915)
 275 {
 276         /*
 277          * We have to avoid concurrent mmio cache line access on gen7 or
 278          * risk a machine hang. For a fun history lesson dig out the old
 279          * userspace intel_gpu_top and run it on Ivybridge or Haswell!
 280          */
 281         return IS_GEN(i915, 7);
 282 }
 283
 284 static void engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)
 285 {
 286         struct intel_engine_pmu *pmu = &engine->pmu;
 287         bool busy;
 288         u32 val;
 289
 290         val = ENGINE_READ_FW(engine, RING_CTL);
 291         if (val == 0) /* powerwell off => engine idle */
 292                 return;
 293
 294         if (val & RING_WAIT)
 295                 add_sample(&pmu->sample[I915_SAMPLE_WAIT], period_ns);
 296         if (val & RING_WAIT_SEMAPHORE)
 297                 add_sample(&pmu->sample[I915_SAMPLE_SEMA], period_ns);
 298
 299         /* No need to sample when busy stats are supported. */
 300         if (intel_engine_supports_stats(engine))
 301                 return;
 302
 303         /*
 304          * While waiting on a semaphore or event, MI_MODE reports the
 305          * ring as idle. However, previously using the seqno, and with
 306          * execlists sampling, we account for the ring waiting as the
 307          * engine being busy. Therefore, we record the sample as being
 308          * busy if either waiting or !idle.
 309          */
 310         busy = val & (RING_WAIT_SEMAPHORE | RING_WAIT);
 311         if (!busy) {
 312                 val = ENGINE_READ_FW(engine, RING_MI_MODE);
 313                 busy = !(val & MODE_IDLE);
 314         }
 315         if (busy)
 316                 add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
 317 }
 318
 319 static void
 320 engines_sample(struct intel_gt *gt, unsigned int period_ns)
 321 {
 322         struct drm_i915_private *i915 = gt->i915;
 323         struct intel_engine_cs *engine;
 324         enum intel_engine_id id;
 325         unsigned long flags;
 326
 327         if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
 328                 return;
 329
 330         if (!intel_gt_pm_is_awake(gt))
 331                 return;
 332
 333         for_each_engine(engine, gt, id) {
 334                 if (!intel_engine_pm_get_if_awake(engine))
 335                         continue;
 336
 337                 if (exclusive_mmio_access(i915)) {
 338                         spin_lock_irqsave(&engine->uncore->lock, flags);
 339                         engine_sample(engine, period_ns);
 340                         spin_unlock_irqrestore(&engine->uncore->lock, flags);
 341                 } else {
 342                         engine_sample(engine, period_ns);
 343                 }
 344
 345                 intel_engine_pm_put_async(engine);
 346         }
 347 }
 348
 349 static void
 350 add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul)
 351 {
 352         sample->cur += mul_u32_u32(val, mul);
 353 }
 354
 355 static bool frequency_sampling_enabled(struct i915_pmu *pmu)
 356 {
 357         return pmu->enable &
 358                (config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY) |
 359                 config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY));
 360 }
 361
 362 static void
 363 frequency_sample(struct intel_gt *gt, unsigned int period_ns)
 364 {
 365         struct drm_i915_private *i915 = gt->i915;
 366         struct intel_uncore *uncore = gt->uncore;
 367         struct i915_pmu *pmu = &i915->pmu;
 368         struct intel_rps *rps = &gt->rps;
 369
 370         if (!frequency_sampling_enabled(pmu))
 371                 return;
 372
 373         /* Report 0/0 (actual/requested) frequency while parked. */
 374         if (!intel_gt_pm_get_if_awake(gt))
 375                 return;
 376
 377         if (pmu->enable & config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) {
 378                 u32 val;
 379
 380                 /*
 381                  * We take a quick peek here without using forcewake
 382                  * so that we don't perturb the system under observation
 383                  * (forcewake => !rc6 => increased power use). We expect
 384                  * that if the read fails because it is outside of the
 385                  * mmio power well, then it will return 0 -- in which
 386                  * case we assume the system is running at the intended
 387                  * frequency. Fortunately, the read should rarely fail!
 388                  */
 389                 val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
 390                 if (val)
 391                         val = intel_rps_get_cagf(rps, val);
 392                 else
 393                         val = rps->cur_freq;
 394
 395                 add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT],
 396                                 intel_gpu_freq(rps, val), period_ns / 1000);
 397         }
 398
 399         if (pmu->enable & config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) {
 400                 add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ],
 401                                 intel_gpu_freq(rps, rps->cur_freq),
 402                                 period_ns / 1000);
 403         }
 404
 405         intel_gt_pm_put_async(gt);
 406 }
 407
 408 static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer)
 409 {
 410         struct drm_i915_private *i915 =
 411                 container_of(hrtimer, struct drm_i915_private, pmu.timer);
 412         struct i915_pmu *pmu = &i915->pmu;
 413         struct intel_gt *gt = &i915->gt;
 414         unsigned int period_ns;
 415         ktime_t now;
 416
 417         if (!READ_ONCE(pmu->timer_enabled))
 418                 return HRTIMER_NORESTART;
 419
 420         now = ktime_get();
 421         period_ns = ktime_to_ns(ktime_sub(now, pmu->timer_last));
 422         pmu->timer_last = now;
 423
 424         /*
 425          * Strictly speaking the passed in period may not be 100% accurate for
 426          * all internal calculation, since some amount of time can be spent on
 427          * grabbing the forcewake. However the potential error from timer call-
 428          * back delay greatly dominates this so we keep it simple.
 429          */
 430         engines_sample(gt, period_ns);
 431         frequency_sample(gt, period_ns);
 432
 433         hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
 434
 435         return HRTIMER_RESTART;
 436 }
 437
 438 static u64 count_interrupts(struct drm_i915_private *i915)
 439 {
 440         /* open-coded kstat_irqs() */
 441         struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
 442         u64 sum = 0;
 443         int cpu;
 444
 445         if (!desc || !desc->kstat_irqs)
 446                 return 0;
 447
 448         for_each_possible_cpu(cpu)
 449                 sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
 450
 451         return sum;
 452 }
 453
 454 static void i915_pmu_event_destroy(struct perf_event *event)
 455 {
 456         struct drm_i915_private *i915 =
 457                 container_of(event->pmu, typeof(*i915), pmu.base);
 458
 459         drm_WARN_ON(&i915->drm, event->parent);
 460 }
 461
 462 static int
 463 engine_event_status(struct intel_engine_cs *engine,
 464                     enum drm_i915_pmu_engine_sample sample)
 465 {
 466         switch (sample) {
 467         case I915_SAMPLE_BUSY:
 468         case I915_SAMPLE_WAIT:
 469                 break;
 470         case I915_SAMPLE_SEMA:
 471                 if (INTEL_GEN(engine->i915) < 6)
 472                         return -ENODEV;
 473                 break;
 474         default:
 475                 return -ENOENT;
 476         }
 477
 478         return 0;
 479 }
 480
 481 static int
 482 config_status(struct drm_i915_private *i915, u64 config)
 483 {
 484         switch (config) {
 485         case I915_PMU_ACTUAL_FREQUENCY:
 486                 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
 487                         /* Requires a mutex for sampling! */
 488                         return -ENODEV;
 489                 fallthrough;
 490         case I915_PMU_REQUESTED_FREQUENCY:
 491                 if (INTEL_GEN(i915) < 6)
 492                         return -ENODEV;
 493                 break;
 494         case I915_PMU_INTERRUPTS:
 495                 break;
 496         case I915_PMU_RC6_RESIDENCY:
 497                 if (!HAS_RC6(i915))
 498                         return -ENODEV;
 499                 break;
 500         default:
 501                 return -ENOENT;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static int engine_event_init(struct perf_event *event)
 508 {
 509         struct drm_i915_private *i915 =
 510                 container_of(event->pmu, typeof(*i915), pmu.base);
 511         struct intel_engine_cs *engine;
 512
 513         engine = intel_engine_lookup_user(i915, engine_event_class(event),
 514                                           engine_event_instance(event));
 515         if (!engine)
 516                 return -ENODEV;
 517
 518         return engine_event_status(engine, engine_event_sample(event));
 519 }
 520
 521 static int i915_pmu_event_init(struct perf_event *event)
 522 {
 523         struct drm_i915_private *i915 =
 524                 container_of(event->pmu, typeof(*i915), pmu.base);
 525         int ret;
 526
 527         if (event->attr.type != event->pmu->type)
 528                 return -ENOENT;
 529
 530         /* unsupported modes and filters */
 531         if (event->attr.sample_period) /* no sampling */
 532                 return -EINVAL;
 533
 534         if (has_branch_stack(event))
 535                 return -EOPNOTSUPP;
 536
 537         if (event->cpu < 0)
 538                 return -EINVAL;
 539
 540         /* only allow running on one cpu at a time */
 541         if (!cpumask_test_cpu(event->cpu, &i915_pmu_cpumask))
 542                 return -EINVAL;
 543
 544         if (is_engine_event(event))
 545                 ret = engine_event_init(event);
 546         else
 547                 ret = config_status(i915, event->attr.config);
 548         if (ret)
 549                 return ret;
 550
 551         if (!event->parent)
 552                 event->destroy = i915_pmu_event_destroy;
 553
 554         return 0;
 555 }
 556
 557 static u64 __i915_pmu_event_read(struct perf_event *event)
 558 {
 559         struct drm_i915_private *i915 =
 560                 container_of(event->pmu, typeof(*i915), pmu.base);
 561         struct i915_pmu *pmu = &i915->pmu;
 562         u64 val = 0;
 563
 564         if (is_engine_event(event)) {
 565                 u8 sample = engine_event_sample(event);
 566                 struct intel_engine_cs *engine;
 567
 568                 engine = intel_engine_lookup_user(i915,
 569                                                   engine_event_class(event),
 570                                                   engine_event_instance(event));
 571
 572                 if (drm_WARN_ON_ONCE(&i915->drm, !engine)) {
 573                         /* Do nothing */
 574                 } else if (sample == I915_SAMPLE_BUSY &&
 575                            intel_engine_supports_stats(engine)) {
 576                         ktime_t unused;
 577
 578                         val = ktime_to_ns(intel_engine_get_busy_time(engine,
 579                                                                      &unused));
 580                 } else {
 581                         val = engine->pmu.sample[sample].cur;
 582                 }
 583         } else {
 584                 switch (event->attr.config) {
 585                 case I915_PMU_ACTUAL_FREQUENCY:
 586                         val =
 587                            div_u64(pmu->sample[__I915_SAMPLE_FREQ_ACT].cur,
 588                                    USEC_PER_SEC /* to MHz */);
 589                         break;
 590                 case I915_PMU_REQUESTED_FREQUENCY:
 591                         val =
 592                            div_u64(pmu->sample[__I915_SAMPLE_FREQ_REQ].cur,
 593                                    USEC_PER_SEC /* to MHz */);
 594                         break;
 595                 case I915_PMU_INTERRUPTS:
 596                         val = count_interrupts(i915);
 597                         break;
 598                 case I915_PMU_RC6_RESIDENCY:
 599                         val = get_rc6(&i915->gt);
 600                         break;
 601                 }
 602         }
 603
 604         return val;
 605 }
 606
 607 static void i915_pmu_event_read(struct perf_event *event)
 608 {
 609         struct hw_perf_event *hwc = &event->hw;
 610         u64 prev, new;
 611
 612 again:
 613         prev = local64_read(&hwc->prev_count);
 614         new = __i915_pmu_event_read(event);
 615
 616         if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
 617                 goto again;
 618
 619         local64_add(new - prev, &event->count);
 620 }
 621
 622 static void i915_pmu_enable(struct perf_event *event)
 623 {
 624         struct drm_i915_private *i915 =
 625                 container_of(event->pmu, typeof(*i915), pmu.base);
 626         unsigned int bit = event_enabled_bit(event);
 627         struct i915_pmu *pmu = &i915->pmu;
 628         unsigned long flags;
 629
 630         spin_lock_irqsave(&pmu->lock, flags);
 631
 632         /*
 633          * Update the bitmask of enabled events and increment
 634          * the event reference counter.
 635          */
 636         BUILD_BUG_ON(ARRAY_SIZE(pmu->enable_count) != I915_PMU_MASK_BITS);
 637         GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
 638         GEM_BUG_ON(pmu->enable_count[bit] == ~0);
 639
 640         pmu->enable |= BIT_ULL(bit);
 641         pmu->enable_count[bit]++;
 642
 643         /*
 644          * Start the sampling timer if needed and not already enabled.
 645          */
 646         __i915_pmu_maybe_start_timer(pmu);
 647
 648         /*
 649          * For per-engine events the bitmask and reference counting
 650          * is stored per engine.
 651          */
 652         if (is_engine_event(event)) {
 653                 u8 sample = engine_event_sample(event);
 654                 struct intel_engine_cs *engine;
 655
 656                 engine = intel_engine_lookup_user(i915,
 657                                                   engine_event_class(event),
 658                                                   engine_event_instance(event));
 659
 660                 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
 661                              I915_ENGINE_SAMPLE_COUNT);
 662                 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
 663                              I915_ENGINE_SAMPLE_COUNT);
 664                 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
 665                 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
 666                 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
 667
 668                 engine->pmu.enable |= BIT(sample);
 669                 engine->pmu.enable_count[sample]++;
 670         }
 671
 672         spin_unlock_irqrestore(&pmu->lock, flags);
 673
 674         /*
 675          * Store the current counter value so we can report the correct delta
 676          * for all listeners. Even when the event was already enabled and has
 677          * an existing non-zero value.
 678          */
 679         local64_set(&event->hw.prev_count, __i915_pmu_event_read(event));
 680 }
 681
 682 static void i915_pmu_disable(struct perf_event *event)
 683 {
 684         struct drm_i915_private *i915 =
 685                 container_of(event->pmu, typeof(*i915), pmu.base);
 686         unsigned int bit = event_enabled_bit(event);
 687         struct i915_pmu *pmu = &i915->pmu;
 688         unsigned long flags;
 689
 690         spin_lock_irqsave(&pmu->lock, flags);
 691
 692         if (is_engine_event(event)) {
 693                 u8 sample = engine_event_sample(event);
 694                 struct intel_engine_cs *engine;
 695
 696                 engine = intel_engine_lookup_user(i915,
 697                                                   engine_event_class(event),
 698                                                   engine_event_instance(event));
 699
 700                 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
 701                 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
 702                 GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
 703
 704                 /*
 705                  * Decrement the reference count and clear the enabled
 706                  * bitmask when the last listener on an event goes away.
 707                  */
 708                 if (--engine->pmu.enable_count[sample] == 0)
 709                         engine->pmu.enable &= ~BIT(sample);
 710         }
 711
 712         GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
 713         GEM_BUG_ON(pmu->enable_count[bit] == 0);
 714         /*
 715          * Decrement the reference count and clear the enabled
 716          * bitmask when the last listener on an event goes away.
 717          */
 718         if (--pmu->enable_count[bit] == 0) {
 719                 pmu->enable &= ~BIT_ULL(bit);
 720                 pmu->timer_enabled &= pmu_needs_timer(pmu, true);
 721         }
 722
 723         spin_unlock_irqrestore(&pmu->lock, flags);
 724 }
 725
 726 static void i915_pmu_event_start(struct perf_event *event, int flags)
 727 {
 728         i915_pmu_enable(event);
 729         event->hw.state = 0;
 730 }
 731
 732 static void i915_pmu_event_stop(struct perf_event *event, int flags)
 733 {
 734         if (flags & PERF_EF_UPDATE)
 735                 i915_pmu_event_read(event);
 736         i915_pmu_disable(event);
 737         event->hw.state = PERF_HES_STOPPED;
 738 }
 739
 740 static int i915_pmu_event_add(struct perf_event *event, int flags)
 741 {
 742         if (flags & PERF_EF_START)
 743                 i915_pmu_event_start(event, flags);
 744
 745         return 0;
 746 }
 747
 748 static void i915_pmu_event_del(struct perf_event *event, int flags)
 749 {
 750         i915_pmu_event_stop(event, PERF_EF_UPDATE);
 751 }
 752
 753 static int i915_pmu_event_event_idx(struct perf_event *event)
 754 {
 755         return 0;
 756 }
 757
 758 struct i915_str_attribute {
 759         struct device_attribute attr;
 760         const char *str;
 761 };
 762
 763 static ssize_t i915_pmu_format_show(struct device *dev,
 764                                     struct device_attribute *attr, char *buf)
 765 {
 766         struct i915_str_attribute *eattr;
 767
 768         eattr = container_of(attr, struct i915_str_attribute, attr);
 769         return sprintf(buf, "%s\n", eattr->str);
 770 }
 771
 772 #define I915_PMU_FORMAT_ATTR(_name, _config) \
 773         (&((struct i915_str_attribute[]) { \
 774                 { .attr = __ATTR(_name, 0444, i915_pmu_format_show, NULL), \
 775                   .str = _config, } \
 776         })[0].attr.attr)
 777
 778 static struct attribute *i915_pmu_format_attrs[] = {
 779         I915_PMU_FORMAT_ATTR(i915_eventid, "config:0-20"),
 780         NULL,
 781 };
 782
 783 static const struct attribute_group i915_pmu_format_attr_group = {
 784         .name = "format",
 785         .attrs = i915_pmu_format_attrs,
 786 };
 787
 788 struct i915_ext_attribute {
 789         struct device_attribute attr;
 790         unsigned long val;
 791 };
 792
 793 static ssize_t i915_pmu_event_show(struct device *dev,
 794                                    struct device_attribute *attr, char *buf)
 795 {
 796         struct i915_ext_attribute *eattr;
 797
 798         eattr = container_of(attr, struct i915_ext_attribute, attr);
 799         return sprintf(buf, "config=0x%lx\n", eattr->val);
 800 }
 801
 802 static ssize_t
 803 i915_pmu_get_attr_cpumask(struct device *dev,
 804                           struct device_attribute *attr,
 805                           char *buf)
 806 {
 807         return cpumap_print_to_pagebuf(true, buf, &i915_pmu_cpumask);
 808 }
 809
 810 static DEVICE_ATTR(cpumask, 0444, i915_pmu_get_attr_cpumask, NULL);
 811
 812 static struct attribute *i915_cpumask_attrs[] = {
 813         &dev_attr_cpumask.attr,
 814         NULL,
 815 };
 816
 817 static const struct attribute_group i915_pmu_cpumask_attr_group = {
 818         .attrs = i915_cpumask_attrs,
 819 };
 820
 821 #define __event(__config, __name, __unit) \
 822 { \
 823         .config = (__config), \
 824         .name = (__name), \
 825         .unit = (__unit), \
 826 }
 827
 828 #define __engine_event(__sample, __name) \
 829 { \
 830         .sample = (__sample), \
 831         .name = (__name), \
 832 }
 833
 834 static struct i915_ext_attribute *
 835 add_i915_attr(struct i915_ext_attribute *attr, const char *name, u64 config)
 836 {
 837         sysfs_attr_init(&attr->attr.attr);
 838         attr->attr.attr.name = name;
 839         attr->attr.attr.mode = 0444;
 840         attr->attr.show = i915_pmu_event_show;
 841         attr->val = config;
 842
 843         return ++attr;
 844 }
 845
 846 static struct perf_pmu_events_attr *
 847 add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
 848              const char *str)
 849 {
 850         sysfs_attr_init(&attr->attr.attr);
 851         attr->attr.attr.name = name;
 852         attr->attr.attr.mode = 0444;
 853         attr->attr.show = perf_event_sysfs_show;
 854         attr->event_str = str;
 855
 856         return ++attr;
 857 }
 858
 859 static struct attribute **
 860 create_event_attributes(struct i915_pmu *pmu)
 861 {
 862         struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
 863         static const struct {
 864                 u64 config;
 865                 const char *name;
 866                 const char *unit;
 867         } events[] = {
 868                 __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),
 869                 __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"),
 870                 __event(I915_PMU_INTERRUPTS, "interrupts", NULL),
 871                 __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
 872         };
 873         static const struct {
 874                 enum drm_i915_pmu_engine_sample sample;
 875                 char *name;
 876         } engine_events[] = {
 877                 __engine_event(I915_SAMPLE_BUSY, "busy"),
 878                 __engine_event(I915_SAMPLE_SEMA, "sema"),
 879                 __engine_event(I915_SAMPLE_WAIT, "wait"),
 880         };
 881         unsigned int count = 0;
 882         struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
 883         struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
 884         struct attribute **attr = NULL, **attr_iter;
 885         struct intel_engine_cs *engine;
 886         unsigned int i;
 887
 888         /* Count how many counters we will be exposing. */
 889         for (i = 0; i < ARRAY_SIZE(events); i++) {
 890                 if (!config_status(i915, events[i].config))
 891                         count++;
 892         }
 893
 894         for_each_uabi_engine(engine, i915) {
 895                 for (i = 0; i < ARRAY_SIZE(engine_events); i++) {
 896                         if (!engine_event_status(engine,
 897                                                  engine_events[i].sample))
 898                                 count++;
 899                 }
 900         }
 901
 902         /* Allocate attribute objects and table. */
 903         i915_attr = kcalloc(count, sizeof(*i915_attr), GFP_KERNEL);
 904         if (!i915_attr)
 905                 goto err_alloc;
 906
 907         pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
 908         if (!pmu_attr)
 909                 goto err_alloc;
 910
 911         /* Max one pointer of each attribute type plus a termination entry. */
 912         attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
 913         if (!attr)
 914                 goto err_alloc;
 915
 916         i915_iter = i915_attr;
 917         pmu_iter = pmu_attr;
 918         attr_iter = attr;
 919
 920         /* Initialize supported non-engine counters. */
 921         for (i = 0; i < ARRAY_SIZE(events); i++) {
 922                 char *str;
 923
 924                 if (config_status(i915, events[i].config))
 925                         continue;
 926
 927                 str = kstrdup(events[i].name, GFP_KERNEL);
 928                 if (!str)
 929                         goto err;
 930
 931                 *attr_iter++ = &i915_iter->attr.attr;
 932                 i915_iter = add_i915_attr(i915_iter, str, events[i].config);
 933
 934                 if (events[i].unit) {
 935                         str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name);
 936                         if (!str)
 937                                 goto err;
 938
 939                         *attr_iter++ = &pmu_iter->attr.attr;
 940                         pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit);
 941                 }
 942         }
 943
 944         /* Initialize supported engine counters. */
 945         for_each_uabi_engine(engine, i915) {
 946                 for (i = 0; i < ARRAY_SIZE(engine_events); i++) {
 947                         char *str;
 948
 949                         if (engine_event_status(engine,
 950                                                 engine_events[i].sample))
 951                                 continue;
 952
 953                         str = kasprintf(GFP_KERNEL, "%s-%s",
 954                                         engine->name, engine_events[i].name);
 955                         if (!str)
 956                                 goto err;
 957
 958                         *attr_iter++ = &i915_iter->attr.attr;
 959                         i915_iter =
 960                                 add_i915_attr(i915_iter, str,
 961                                               __I915_PMU_ENGINE(engine->uabi_class,
 962                                                                 engine->uabi_instance,
 963                                                                 engine_events[i].sample));
 964
 965                         str = kasprintf(GFP_KERNEL, "%s-%s.unit",
 966                                         engine->name, engine_events[i].name);
 967                         if (!str)
 968                                 goto err;
 969
 970                         *attr_iter++ = &pmu_iter->attr.attr;
 971                         pmu_iter = add_pmu_attr(pmu_iter, str, "ns");
 972                 }
 973         }
 974
 975         pmu->i915_attr = i915_attr;
 976         pmu->pmu_attr = pmu_attr;
 977
 978         return attr;
 979
 980 err:;
 981         for (attr_iter = attr; *attr_iter; attr_iter++)
 982                 kfree((*attr_iter)->name);
 983
 984 err_alloc:
 985         kfree(attr);
 986         kfree(i915_attr);
 987         kfree(pmu_attr);
 988
 989         return NULL;
 990 }
 991
 992 static void free_event_attributes(struct i915_pmu *pmu)
 993 {
 994         struct attribute **attr_iter = pmu->events_attr_group.attrs;
 995
 996         for (; *attr_iter; attr_iter++)
 997                 kfree((*attr_iter)->name);
 998
 999         kfree(pmu->events_attr_group.attrs);
1000         kfree(pmu->i915_attr);
1001         kfree(pmu->pmu_attr);
1002
1003         pmu->events_attr_group.attrs = NULL;
1004         pmu->i915_attr = NULL;
1005         pmu->pmu_attr = NULL;
1006 }
1007
1008 static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
1009 {
1010         struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1011
1012         GEM_BUG_ON(!pmu->base.event_init);
1013
1014         /* Select the first online CPU as a designated reader. */
1015         if (!cpumask_weight(&i915_pmu_cpumask))
1016                 cpumask_set_cpu(cpu, &i915_pmu_cpumask);
1017
1018         return 0;
1019 }
1020
1021 static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
1022 {
1023         struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1024         unsigned int target;
1025
1026         GEM_BUG_ON(!pmu->base.event_init);
1027
1028         if (cpumask_test_and_clear_cpu(cpu, &i915_pmu_cpumask)) {
1029                 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
1030                 /* Migrate events if there is a valid target */
1031                 if (target < nr_cpu_ids) {
1032                         cpumask_set_cpu(target, &i915_pmu_cpumask);
1033                         perf_pmu_migrate_context(&pmu->base, cpu, target);
1034                 }
1035         }
1036
1037         return 0;
1038 }
1039
1040 static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu)
1041 {
1042         enum cpuhp_state slot;
1043         int ret;
1044
1045         ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
1046                                       "perf/x86/intel/i915:online",
1047                                       i915_pmu_cpu_online,
1048                                       i915_pmu_cpu_offline);
1049         if (ret < 0)
1050                 return ret;
1051
1052         slot = ret;
1053         ret = cpuhp_state_add_instance(slot, &pmu->cpuhp.node);
1054         if (ret) {
1055                 cpuhp_remove_multi_state(slot);
1056                 return ret;
1057         }
1058
1059         pmu->cpuhp.slot = slot;
1060         return 0;
1061 }
1062
1063 static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
1064 {
1065         struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
1066
1067         drm_WARN_ON(&i915->drm, pmu->cpuhp.slot == CPUHP_INVALID);
1068         drm_WARN_ON(&i915->drm, cpuhp_state_remove_instance(pmu->cpuhp.slot, &pmu->cpuhp.node));
1069         cpuhp_remove_multi_state(pmu->cpuhp.slot);
1070         pmu->cpuhp.slot = CPUHP_INVALID;
1071 }
1072
1073 static bool is_igp(struct drm_i915_private *i915)
1074 {
1075         struct pci_dev *pdev = i915->drm.pdev;
1076
1077         /* IGP is 0000:00:02.0 */
1078         return pci_domain_nr(pdev->bus) == 0 &&
1079                pdev->bus->number == 0 &&
1080                PCI_SLOT(pdev->devfn) == 2 &&
1081                PCI_FUNC(pdev->devfn) == 0;
1082 }
1083
1084 void i915_pmu_register(struct drm_i915_private *i915)
1085 {
1086         struct i915_pmu *pmu = &i915->pmu;
1087         const struct attribute_group *attr_groups[] = {
1088                 &i915_pmu_format_attr_group,
1089                 &pmu->events_attr_group,
1090                 &i915_pmu_cpumask_attr_group,
1091                 NULL
1092         };
1093
1094         int ret = -ENOMEM;
1095
1096         if (INTEL_GEN(i915) <= 2) {
1097                 drm_info(&i915->drm, "PMU not supported for this GPU.");
1098                 return;
1099         }
1100
1101         spin_lock_init(&pmu->lock);
1102         hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1103         pmu->timer.function = i915_sample;
1104         pmu->cpuhp.slot = CPUHP_INVALID;
1105         init_rc6(pmu);
1106
1107         if (!is_igp(i915)) {
1108                 pmu->name = kasprintf(GFP_KERNEL,
1109                                       "i915_%s",
1110                                       dev_name(i915->drm.dev));
1111                 if (pmu->name) {
1112                         /* tools/perf reserves colons as special. */
1113                         strreplace((char *)pmu->name, ':', '_');
1114                 }
1115         } else {
1116                 pmu->name = "i915";
1117         }
1118         if (!pmu->name)
1119                 goto err;
1120
1121         pmu->events_attr_group.name = "events";
1122         pmu->events_attr_group.attrs = create_event_attributes(pmu);
1123         if (!pmu->events_attr_group.attrs)
1124                 goto err_name;
1125
1126         pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
1127                                         GFP_KERNEL);
1128         if (!pmu->base.attr_groups)
1129                 goto err_attr;
1130
1131         pmu->base.module        = THIS_MODULE;
1132         pmu->base.task_ctx_nr   = perf_invalid_context;
1133         pmu->base.event_init    = i915_pmu_event_init;
1134         pmu->base.add           = i915_pmu_event_add;
1135         pmu->base.del           = i915_pmu_event_del;
1136         pmu->base.start         = i915_pmu_event_start;
1137         pmu->base.stop          = i915_pmu_event_stop;
1138         pmu->base.read          = i915_pmu_event_read;
1139         pmu->base.event_idx     = i915_pmu_event_event_idx;
1140
1141         ret = perf_pmu_register(&pmu->base, pmu->name, -1);
1142         if (ret)
1143                 goto err_groups;
1144
1145         ret = i915_pmu_register_cpuhp_state(pmu);
1146         if (ret)
1147                 goto err_unreg;
1148
1149         return;
1150
1151 err_unreg:
1152         perf_pmu_unregister(&pmu->base);
1153 err_groups:
1154         kfree(pmu->base.attr_groups);
1155 err_attr:
1156         pmu->base.event_init = NULL;
1157         free_event_attributes(pmu);
1158 err_name:
1159         if (!is_igp(i915))
1160                 kfree(pmu->name);
1161 err:
1162         drm_notice(&i915->drm, "Failed to register PMU!\n");
1163 }
1164
1165 void i915_pmu_unregister(struct drm_i915_private *i915)
1166 {
1167         struct i915_pmu *pmu = &i915->pmu;
1168
1169         if (!pmu->base.event_init)
1170                 return;
1171
1172         drm_WARN_ON(&i915->drm, pmu->enable);
1173
1174         hrtimer_cancel(&pmu->timer);
1175
1176         i915_pmu_unregister_cpuhp_state(pmu);
1177
1178         perf_pmu_unregister(&pmu->base);
1179         pmu->base.event_init = NULL;
1180         kfree(pmu->base.attr_groups);
1181         if (!is_igp(i915))
1182                 kfree(pmu->name);
1183         free_event_attributes(pmu);
1184 }