2 * SPDX-License-Identifier: MIT
4 * Copyright © 2017-2018 Intel Corporation
8 #include <linux/pm_runtime.h>
10 #include "gt/intel_engine.h"
11 #include "gt/intel_engine_pm.h"
12 #include "gt/intel_engine_user.h"
13 #include "gt/intel_gt_pm.h"
14 #include "gt/intel_rc6.h"
15 #include "gt/intel_rps.h"
21 /* Frequency for the sampling timer for events which need it. */
23 #define PERIOD max_t(u64, 10000, NSEC_PER_SEC / FREQUENCY)
25 #define ENGINE_SAMPLE_MASK \
26 (BIT(I915_SAMPLE_BUSY) | \
27 BIT(I915_SAMPLE_WAIT) | \
28 BIT(I915_SAMPLE_SEMA))
30 #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS)
32 static cpumask_t i915_pmu_cpumask;
34 static u8 engine_config_sample(u64 config)
36 return config & I915_PMU_SAMPLE_MASK;
39 static u8 engine_event_sample(struct perf_event *event)
41 return engine_config_sample(event->attr.config);
44 static u8 engine_event_class(struct perf_event *event)
46 return (event->attr.config >> I915_PMU_CLASS_SHIFT) & 0xff;
49 static u8 engine_event_instance(struct perf_event *event)
51 return (event->attr.config >> I915_PMU_SAMPLE_BITS) & 0xff;
54 static bool is_engine_config(u64 config)
56 return config < __I915_PMU_OTHER(0);
59 static unsigned int config_enabled_bit(u64 config)
61 if (is_engine_config(config))
62 return engine_config_sample(config);
64 return ENGINE_SAMPLE_BITS + (config - __I915_PMU_OTHER(0));
67 static u64 config_enabled_mask(u64 config)
69 return BIT_ULL(config_enabled_bit(config));
72 static bool is_engine_event(struct perf_event *event)
74 return is_engine_config(event->attr.config);
77 static unsigned int event_enabled_bit(struct perf_event *event)
79 return config_enabled_bit(event->attr.config);
82 static bool pmu_needs_timer(struct i915_pmu *pmu, bool gpu_active)
84 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
88 * Only some counters need the sampling timer.
90 * We start with a bitmask of all currently enabled events.
95 * Mask out all the ones which do not need the timer, or in
96 * other words keep all the ones that could need the timer.
98 enable &= config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY) |
99 config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY) |
103 * When the GPU is idle per-engine counters do not need to be
104 * running so clear those bits out.
107 enable &= ~ENGINE_SAMPLE_MASK;
109 * Also there is software busyness tracking available we do not
110 * need the timer for I915_SAMPLE_BUSY counter.
112 else if (i915->caps.scheduler & I915_SCHEDULER_CAP_ENGINE_BUSY_STATS)
113 enable &= ~BIT(I915_SAMPLE_BUSY);
116 * If some bits remain it means we need the sampling timer running.
121 static u64 __get_rc6(struct intel_gt *gt)
123 struct drm_i915_private *i915 = gt->i915;
126 val = intel_rc6_residency_ns(>->rc6,
127 IS_VALLEYVIEW(i915) ?
132 val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6p);
135 val += intel_rc6_residency_ns(>->rc6, GEN6_GT_GFX_RC6pp);
140 #if IS_ENABLED(CONFIG_PM)
142 static inline s64 ktime_since(const ktime_t kt)
144 return ktime_to_ns(ktime_sub(ktime_get(), kt));
147 static u64 get_rc6(struct intel_gt *gt)
149 struct drm_i915_private *i915 = gt->i915;
150 struct i915_pmu *pmu = &i915->pmu;
155 if (intel_gt_pm_get_if_awake(gt)) {
157 intel_gt_pm_put_async(gt);
161 spin_lock_irqsave(&pmu->lock, flags);
164 pmu->sample[__I915_SAMPLE_RC6].cur = val;
167 * We think we are runtime suspended.
169 * Report the delta from when the device was suspended to now,
170 * on top of the last known real value, as the approximated RC6
173 val = ktime_since(pmu->sleep_last);
174 val += pmu->sample[__I915_SAMPLE_RC6].cur;
177 if (val < pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur)
178 val = pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur;
180 pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur = val;
182 spin_unlock_irqrestore(&pmu->lock, flags);
187 static void init_rc6(struct i915_pmu *pmu)
189 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
190 intel_wakeref_t wakeref;
192 with_intel_runtime_pm(i915->gt.uncore->rpm, wakeref) {
193 pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(&i915->gt);
194 pmu->sample[__I915_SAMPLE_RC6_LAST_REPORTED].cur =
195 pmu->sample[__I915_SAMPLE_RC6].cur;
196 pmu->sleep_last = ktime_get();
200 static void park_rc6(struct drm_i915_private *i915)
202 struct i915_pmu *pmu = &i915->pmu;
204 pmu->sample[__I915_SAMPLE_RC6].cur = __get_rc6(&i915->gt);
205 pmu->sleep_last = ktime_get();
210 static u64 get_rc6(struct intel_gt *gt)
212 return __get_rc6(gt);
215 static void init_rc6(struct i915_pmu *pmu) { }
216 static void park_rc6(struct drm_i915_private *i915) {}
220 static void __i915_pmu_maybe_start_timer(struct i915_pmu *pmu)
222 if (!pmu->timer_enabled && pmu_needs_timer(pmu, true)) {
223 pmu->timer_enabled = true;
224 pmu->timer_last = ktime_get();
225 hrtimer_start_range_ns(&pmu->timer,
226 ns_to_ktime(PERIOD), 0,
227 HRTIMER_MODE_REL_PINNED);
231 void i915_pmu_gt_parked(struct drm_i915_private *i915)
233 struct i915_pmu *pmu = &i915->pmu;
235 if (!pmu->base.event_init)
238 spin_lock_irq(&pmu->lock);
243 * Signal sampling timer to stop if only engine events are enabled and
246 pmu->timer_enabled = pmu_needs_timer(pmu, false);
248 spin_unlock_irq(&pmu->lock);
251 void i915_pmu_gt_unparked(struct drm_i915_private *i915)
253 struct i915_pmu *pmu = &i915->pmu;
255 if (!pmu->base.event_init)
258 spin_lock_irq(&pmu->lock);
261 * Re-enable sampling timer when GPU goes active.
263 __i915_pmu_maybe_start_timer(pmu);
265 spin_unlock_irq(&pmu->lock);
269 add_sample(struct i915_pmu_sample *sample, u32 val)
274 static bool exclusive_mmio_access(const struct drm_i915_private *i915)
277 * We have to avoid concurrent mmio cache line access on gen7 or
278 * risk a machine hang. For a fun history lesson dig out the old
279 * userspace intel_gpu_top and run it on Ivybridge or Haswell!
281 return IS_GEN(i915, 7);
284 static void engine_sample(struct intel_engine_cs *engine, unsigned int period_ns)
286 struct intel_engine_pmu *pmu = &engine->pmu;
290 val = ENGINE_READ_FW(engine, RING_CTL);
291 if (val == 0) /* powerwell off => engine idle */
295 add_sample(&pmu->sample[I915_SAMPLE_WAIT], period_ns);
296 if (val & RING_WAIT_SEMAPHORE)
297 add_sample(&pmu->sample[I915_SAMPLE_SEMA], period_ns);
299 /* No need to sample when busy stats are supported. */
300 if (intel_engine_supports_stats(engine))
304 * While waiting on a semaphore or event, MI_MODE reports the
305 * ring as idle. However, previously using the seqno, and with
306 * execlists sampling, we account for the ring waiting as the
307 * engine being busy. Therefore, we record the sample as being
308 * busy if either waiting or !idle.
310 busy = val & (RING_WAIT_SEMAPHORE | RING_WAIT);
312 val = ENGINE_READ_FW(engine, RING_MI_MODE);
313 busy = !(val & MODE_IDLE);
316 add_sample(&pmu->sample[I915_SAMPLE_BUSY], period_ns);
320 engines_sample(struct intel_gt *gt, unsigned int period_ns)
322 struct drm_i915_private *i915 = gt->i915;
323 struct intel_engine_cs *engine;
324 enum intel_engine_id id;
327 if ((i915->pmu.enable & ENGINE_SAMPLE_MASK) == 0)
330 if (!intel_gt_pm_is_awake(gt))
333 for_each_engine(engine, gt, id) {
334 if (!intel_engine_pm_get_if_awake(engine))
337 if (exclusive_mmio_access(i915)) {
338 spin_lock_irqsave(&engine->uncore->lock, flags);
339 engine_sample(engine, period_ns);
340 spin_unlock_irqrestore(&engine->uncore->lock, flags);
342 engine_sample(engine, period_ns);
345 intel_engine_pm_put_async(engine);
350 add_sample_mult(struct i915_pmu_sample *sample, u32 val, u32 mul)
352 sample->cur += mul_u32_u32(val, mul);
355 static bool frequency_sampling_enabled(struct i915_pmu *pmu)
358 (config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY) |
359 config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY));
363 frequency_sample(struct intel_gt *gt, unsigned int period_ns)
365 struct drm_i915_private *i915 = gt->i915;
366 struct intel_uncore *uncore = gt->uncore;
367 struct i915_pmu *pmu = &i915->pmu;
368 struct intel_rps *rps = >->rps;
370 if (!frequency_sampling_enabled(pmu))
373 /* Report 0/0 (actual/requested) frequency while parked. */
374 if (!intel_gt_pm_get_if_awake(gt))
377 if (pmu->enable & config_enabled_mask(I915_PMU_ACTUAL_FREQUENCY)) {
381 * We take a quick peek here without using forcewake
382 * so that we don't perturb the system under observation
383 * (forcewake => !rc6 => increased power use). We expect
384 * that if the read fails because it is outside of the
385 * mmio power well, then it will return 0 -- in which
386 * case we assume the system is running at the intended
387 * frequency. Fortunately, the read should rarely fail!
389 val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
391 val = intel_rps_get_cagf(rps, val);
395 add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_ACT],
396 intel_gpu_freq(rps, val), period_ns / 1000);
399 if (pmu->enable & config_enabled_mask(I915_PMU_REQUESTED_FREQUENCY)) {
400 add_sample_mult(&pmu->sample[__I915_SAMPLE_FREQ_REQ],
401 intel_gpu_freq(rps, rps->cur_freq),
405 intel_gt_pm_put_async(gt);
408 static enum hrtimer_restart i915_sample(struct hrtimer *hrtimer)
410 struct drm_i915_private *i915 =
411 container_of(hrtimer, struct drm_i915_private, pmu.timer);
412 struct i915_pmu *pmu = &i915->pmu;
413 struct intel_gt *gt = &i915->gt;
414 unsigned int period_ns;
417 if (!READ_ONCE(pmu->timer_enabled))
418 return HRTIMER_NORESTART;
421 period_ns = ktime_to_ns(ktime_sub(now, pmu->timer_last));
422 pmu->timer_last = now;
425 * Strictly speaking the passed in period may not be 100% accurate for
426 * all internal calculation, since some amount of time can be spent on
427 * grabbing the forcewake. However the potential error from timer call-
428 * back delay greatly dominates this so we keep it simple.
430 engines_sample(gt, period_ns);
431 frequency_sample(gt, period_ns);
433 hrtimer_forward(hrtimer, now, ns_to_ktime(PERIOD));
435 return HRTIMER_RESTART;
438 static u64 count_interrupts(struct drm_i915_private *i915)
440 /* open-coded kstat_irqs() */
441 struct irq_desc *desc = irq_to_desc(i915->drm.pdev->irq);
445 if (!desc || !desc->kstat_irqs)
448 for_each_possible_cpu(cpu)
449 sum += *per_cpu_ptr(desc->kstat_irqs, cpu);
454 static void i915_pmu_event_destroy(struct perf_event *event)
456 struct drm_i915_private *i915 =
457 container_of(event->pmu, typeof(*i915), pmu.base);
459 drm_WARN_ON(&i915->drm, event->parent);
463 engine_event_status(struct intel_engine_cs *engine,
464 enum drm_i915_pmu_engine_sample sample)
467 case I915_SAMPLE_BUSY:
468 case I915_SAMPLE_WAIT:
470 case I915_SAMPLE_SEMA:
471 if (INTEL_GEN(engine->i915) < 6)
482 config_status(struct drm_i915_private *i915, u64 config)
485 case I915_PMU_ACTUAL_FREQUENCY:
486 if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
487 /* Requires a mutex for sampling! */
490 case I915_PMU_REQUESTED_FREQUENCY:
491 if (INTEL_GEN(i915) < 6)
494 case I915_PMU_INTERRUPTS:
496 case I915_PMU_RC6_RESIDENCY:
507 static int engine_event_init(struct perf_event *event)
509 struct drm_i915_private *i915 =
510 container_of(event->pmu, typeof(*i915), pmu.base);
511 struct intel_engine_cs *engine;
513 engine = intel_engine_lookup_user(i915, engine_event_class(event),
514 engine_event_instance(event));
518 return engine_event_status(engine, engine_event_sample(event));
521 static int i915_pmu_event_init(struct perf_event *event)
523 struct drm_i915_private *i915 =
524 container_of(event->pmu, typeof(*i915), pmu.base);
527 if (event->attr.type != event->pmu->type)
530 /* unsupported modes and filters */
531 if (event->attr.sample_period) /* no sampling */
534 if (has_branch_stack(event))
540 /* only allow running on one cpu at a time */
541 if (!cpumask_test_cpu(event->cpu, &i915_pmu_cpumask))
544 if (is_engine_event(event))
545 ret = engine_event_init(event);
547 ret = config_status(i915, event->attr.config);
552 event->destroy = i915_pmu_event_destroy;
557 static u64 __i915_pmu_event_read(struct perf_event *event)
559 struct drm_i915_private *i915 =
560 container_of(event->pmu, typeof(*i915), pmu.base);
561 struct i915_pmu *pmu = &i915->pmu;
564 if (is_engine_event(event)) {
565 u8 sample = engine_event_sample(event);
566 struct intel_engine_cs *engine;
568 engine = intel_engine_lookup_user(i915,
569 engine_event_class(event),
570 engine_event_instance(event));
572 if (drm_WARN_ON_ONCE(&i915->drm, !engine)) {
574 } else if (sample == I915_SAMPLE_BUSY &&
575 intel_engine_supports_stats(engine)) {
578 val = ktime_to_ns(intel_engine_get_busy_time(engine,
581 val = engine->pmu.sample[sample].cur;
584 switch (event->attr.config) {
585 case I915_PMU_ACTUAL_FREQUENCY:
587 div_u64(pmu->sample[__I915_SAMPLE_FREQ_ACT].cur,
588 USEC_PER_SEC /* to MHz */);
590 case I915_PMU_REQUESTED_FREQUENCY:
592 div_u64(pmu->sample[__I915_SAMPLE_FREQ_REQ].cur,
593 USEC_PER_SEC /* to MHz */);
595 case I915_PMU_INTERRUPTS:
596 val = count_interrupts(i915);
598 case I915_PMU_RC6_RESIDENCY:
599 val = get_rc6(&i915->gt);
607 static void i915_pmu_event_read(struct perf_event *event)
609 struct hw_perf_event *hwc = &event->hw;
613 prev = local64_read(&hwc->prev_count);
614 new = __i915_pmu_event_read(event);
616 if (local64_cmpxchg(&hwc->prev_count, prev, new) != prev)
619 local64_add(new - prev, &event->count);
622 static void i915_pmu_enable(struct perf_event *event)
624 struct drm_i915_private *i915 =
625 container_of(event->pmu, typeof(*i915), pmu.base);
626 unsigned int bit = event_enabled_bit(event);
627 struct i915_pmu *pmu = &i915->pmu;
630 spin_lock_irqsave(&pmu->lock, flags);
633 * Update the bitmask of enabled events and increment
634 * the event reference counter.
636 BUILD_BUG_ON(ARRAY_SIZE(pmu->enable_count) != I915_PMU_MASK_BITS);
637 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
638 GEM_BUG_ON(pmu->enable_count[bit] == ~0);
640 pmu->enable |= BIT_ULL(bit);
641 pmu->enable_count[bit]++;
644 * Start the sampling timer if needed and not already enabled.
646 __i915_pmu_maybe_start_timer(pmu);
649 * For per-engine events the bitmask and reference counting
650 * is stored per engine.
652 if (is_engine_event(event)) {
653 u8 sample = engine_event_sample(event);
654 struct intel_engine_cs *engine;
656 engine = intel_engine_lookup_user(i915,
657 engine_event_class(event),
658 engine_event_instance(event));
660 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.enable_count) !=
661 I915_ENGINE_SAMPLE_COUNT);
662 BUILD_BUG_ON(ARRAY_SIZE(engine->pmu.sample) !=
663 I915_ENGINE_SAMPLE_COUNT);
664 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
665 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
666 GEM_BUG_ON(engine->pmu.enable_count[sample] == ~0);
668 engine->pmu.enable |= BIT(sample);
669 engine->pmu.enable_count[sample]++;
672 spin_unlock_irqrestore(&pmu->lock, flags);
675 * Store the current counter value so we can report the correct delta
676 * for all listeners. Even when the event was already enabled and has
677 * an existing non-zero value.
679 local64_set(&event->hw.prev_count, __i915_pmu_event_read(event));
682 static void i915_pmu_disable(struct perf_event *event)
684 struct drm_i915_private *i915 =
685 container_of(event->pmu, typeof(*i915), pmu.base);
686 unsigned int bit = event_enabled_bit(event);
687 struct i915_pmu *pmu = &i915->pmu;
690 spin_lock_irqsave(&pmu->lock, flags);
692 if (is_engine_event(event)) {
693 u8 sample = engine_event_sample(event);
694 struct intel_engine_cs *engine;
696 engine = intel_engine_lookup_user(i915,
697 engine_event_class(event),
698 engine_event_instance(event));
700 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.enable_count));
701 GEM_BUG_ON(sample >= ARRAY_SIZE(engine->pmu.sample));
702 GEM_BUG_ON(engine->pmu.enable_count[sample] == 0);
705 * Decrement the reference count and clear the enabled
706 * bitmask when the last listener on an event goes away.
708 if (--engine->pmu.enable_count[sample] == 0)
709 engine->pmu.enable &= ~BIT(sample);
712 GEM_BUG_ON(bit >= ARRAY_SIZE(pmu->enable_count));
713 GEM_BUG_ON(pmu->enable_count[bit] == 0);
715 * Decrement the reference count and clear the enabled
716 * bitmask when the last listener on an event goes away.
718 if (--pmu->enable_count[bit] == 0) {
719 pmu->enable &= ~BIT_ULL(bit);
720 pmu->timer_enabled &= pmu_needs_timer(pmu, true);
723 spin_unlock_irqrestore(&pmu->lock, flags);
726 static void i915_pmu_event_start(struct perf_event *event, int flags)
728 i915_pmu_enable(event);
732 static void i915_pmu_event_stop(struct perf_event *event, int flags)
734 if (flags & PERF_EF_UPDATE)
735 i915_pmu_event_read(event);
736 i915_pmu_disable(event);
737 event->hw.state = PERF_HES_STOPPED;
740 static int i915_pmu_event_add(struct perf_event *event, int flags)
742 if (flags & PERF_EF_START)
743 i915_pmu_event_start(event, flags);
748 static void i915_pmu_event_del(struct perf_event *event, int flags)
750 i915_pmu_event_stop(event, PERF_EF_UPDATE);
753 static int i915_pmu_event_event_idx(struct perf_event *event)
758 struct i915_str_attribute {
759 struct device_attribute attr;
763 static ssize_t i915_pmu_format_show(struct device *dev,
764 struct device_attribute *attr, char *buf)
766 struct i915_str_attribute *eattr;
768 eattr = container_of(attr, struct i915_str_attribute, attr);
769 return sprintf(buf, "%s\n", eattr->str);
772 #define I915_PMU_FORMAT_ATTR(_name, _config) \
773 (&((struct i915_str_attribute[]) { \
774 { .attr = __ATTR(_name, 0444, i915_pmu_format_show, NULL), \
778 static struct attribute *i915_pmu_format_attrs[] = {
779 I915_PMU_FORMAT_ATTR(i915_eventid, "config:0-20"),
783 static const struct attribute_group i915_pmu_format_attr_group = {
785 .attrs = i915_pmu_format_attrs,
788 struct i915_ext_attribute {
789 struct device_attribute attr;
793 static ssize_t i915_pmu_event_show(struct device *dev,
794 struct device_attribute *attr, char *buf)
796 struct i915_ext_attribute *eattr;
798 eattr = container_of(attr, struct i915_ext_attribute, attr);
799 return sprintf(buf, "config=0x%lx\n", eattr->val);
803 i915_pmu_get_attr_cpumask(struct device *dev,
804 struct device_attribute *attr,
807 return cpumap_print_to_pagebuf(true, buf, &i915_pmu_cpumask);
810 static DEVICE_ATTR(cpumask, 0444, i915_pmu_get_attr_cpumask, NULL);
812 static struct attribute *i915_cpumask_attrs[] = {
813 &dev_attr_cpumask.attr,
817 static const struct attribute_group i915_pmu_cpumask_attr_group = {
818 .attrs = i915_cpumask_attrs,
821 #define __event(__config, __name, __unit) \
823 .config = (__config), \
828 #define __engine_event(__sample, __name) \
830 .sample = (__sample), \
834 static struct i915_ext_attribute *
835 add_i915_attr(struct i915_ext_attribute *attr, const char *name, u64 config)
837 sysfs_attr_init(&attr->attr.attr);
838 attr->attr.attr.name = name;
839 attr->attr.attr.mode = 0444;
840 attr->attr.show = i915_pmu_event_show;
846 static struct perf_pmu_events_attr *
847 add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name,
850 sysfs_attr_init(&attr->attr.attr);
851 attr->attr.attr.name = name;
852 attr->attr.attr.mode = 0444;
853 attr->attr.show = perf_event_sysfs_show;
854 attr->event_str = str;
859 static struct attribute **
860 create_event_attributes(struct i915_pmu *pmu)
862 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
863 static const struct {
868 __event(I915_PMU_ACTUAL_FREQUENCY, "actual-frequency", "M"),
869 __event(I915_PMU_REQUESTED_FREQUENCY, "requested-frequency", "M"),
870 __event(I915_PMU_INTERRUPTS, "interrupts", NULL),
871 __event(I915_PMU_RC6_RESIDENCY, "rc6-residency", "ns"),
873 static const struct {
874 enum drm_i915_pmu_engine_sample sample;
876 } engine_events[] = {
877 __engine_event(I915_SAMPLE_BUSY, "busy"),
878 __engine_event(I915_SAMPLE_SEMA, "sema"),
879 __engine_event(I915_SAMPLE_WAIT, "wait"),
881 unsigned int count = 0;
882 struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter;
883 struct i915_ext_attribute *i915_attr = NULL, *i915_iter;
884 struct attribute **attr = NULL, **attr_iter;
885 struct intel_engine_cs *engine;
888 /* Count how many counters we will be exposing. */
889 for (i = 0; i < ARRAY_SIZE(events); i++) {
890 if (!config_status(i915, events[i].config))
894 for_each_uabi_engine(engine, i915) {
895 for (i = 0; i < ARRAY_SIZE(engine_events); i++) {
896 if (!engine_event_status(engine,
897 engine_events[i].sample))
902 /* Allocate attribute objects and table. */
903 i915_attr = kcalloc(count, sizeof(*i915_attr), GFP_KERNEL);
907 pmu_attr = kcalloc(count, sizeof(*pmu_attr), GFP_KERNEL);
911 /* Max one pointer of each attribute type plus a termination entry. */
912 attr = kcalloc(count * 2 + 1, sizeof(*attr), GFP_KERNEL);
916 i915_iter = i915_attr;
920 /* Initialize supported non-engine counters. */
921 for (i = 0; i < ARRAY_SIZE(events); i++) {
924 if (config_status(i915, events[i].config))
927 str = kstrdup(events[i].name, GFP_KERNEL);
931 *attr_iter++ = &i915_iter->attr.attr;
932 i915_iter = add_i915_attr(i915_iter, str, events[i].config);
934 if (events[i].unit) {
935 str = kasprintf(GFP_KERNEL, "%s.unit", events[i].name);
939 *attr_iter++ = &pmu_iter->attr.attr;
940 pmu_iter = add_pmu_attr(pmu_iter, str, events[i].unit);
944 /* Initialize supported engine counters. */
945 for_each_uabi_engine(engine, i915) {
946 for (i = 0; i < ARRAY_SIZE(engine_events); i++) {
949 if (engine_event_status(engine,
950 engine_events[i].sample))
953 str = kasprintf(GFP_KERNEL, "%s-%s",
954 engine->name, engine_events[i].name);
958 *attr_iter++ = &i915_iter->attr.attr;
960 add_i915_attr(i915_iter, str,
961 __I915_PMU_ENGINE(engine->uabi_class,
962 engine->uabi_instance,
963 engine_events[i].sample));
965 str = kasprintf(GFP_KERNEL, "%s-%s.unit",
966 engine->name, engine_events[i].name);
970 *attr_iter++ = &pmu_iter->attr.attr;
971 pmu_iter = add_pmu_attr(pmu_iter, str, "ns");
975 pmu->i915_attr = i915_attr;
976 pmu->pmu_attr = pmu_attr;
981 for (attr_iter = attr; *attr_iter; attr_iter++)
982 kfree((*attr_iter)->name);
992 static void free_event_attributes(struct i915_pmu *pmu)
994 struct attribute **attr_iter = pmu->events_attr_group.attrs;
996 for (; *attr_iter; attr_iter++)
997 kfree((*attr_iter)->name);
999 kfree(pmu->events_attr_group.attrs);
1000 kfree(pmu->i915_attr);
1001 kfree(pmu->pmu_attr);
1003 pmu->events_attr_group.attrs = NULL;
1004 pmu->i915_attr = NULL;
1005 pmu->pmu_attr = NULL;
1008 static int i915_pmu_cpu_online(unsigned int cpu, struct hlist_node *node)
1010 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1012 GEM_BUG_ON(!pmu->base.event_init);
1014 /* Select the first online CPU as a designated reader. */
1015 if (!cpumask_weight(&i915_pmu_cpumask))
1016 cpumask_set_cpu(cpu, &i915_pmu_cpumask);
1021 static int i915_pmu_cpu_offline(unsigned int cpu, struct hlist_node *node)
1023 struct i915_pmu *pmu = hlist_entry_safe(node, typeof(*pmu), cpuhp.node);
1024 unsigned int target;
1026 GEM_BUG_ON(!pmu->base.event_init);
1028 if (cpumask_test_and_clear_cpu(cpu, &i915_pmu_cpumask)) {
1029 target = cpumask_any_but(topology_sibling_cpumask(cpu), cpu);
1030 /* Migrate events if there is a valid target */
1031 if (target < nr_cpu_ids) {
1032 cpumask_set_cpu(target, &i915_pmu_cpumask);
1033 perf_pmu_migrate_context(&pmu->base, cpu, target);
1040 static int i915_pmu_register_cpuhp_state(struct i915_pmu *pmu)
1042 enum cpuhp_state slot;
1045 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
1046 "perf/x86/intel/i915:online",
1047 i915_pmu_cpu_online,
1048 i915_pmu_cpu_offline);
1053 ret = cpuhp_state_add_instance(slot, &pmu->cpuhp.node);
1055 cpuhp_remove_multi_state(slot);
1059 pmu->cpuhp.slot = slot;
1063 static void i915_pmu_unregister_cpuhp_state(struct i915_pmu *pmu)
1065 struct drm_i915_private *i915 = container_of(pmu, typeof(*i915), pmu);
1067 drm_WARN_ON(&i915->drm, pmu->cpuhp.slot == CPUHP_INVALID);
1068 drm_WARN_ON(&i915->drm, cpuhp_state_remove_instance(pmu->cpuhp.slot, &pmu->cpuhp.node));
1069 cpuhp_remove_multi_state(pmu->cpuhp.slot);
1070 pmu->cpuhp.slot = CPUHP_INVALID;
1073 static bool is_igp(struct drm_i915_private *i915)
1075 struct pci_dev *pdev = i915->drm.pdev;
1077 /* IGP is 0000:00:02.0 */
1078 return pci_domain_nr(pdev->bus) == 0 &&
1079 pdev->bus->number == 0 &&
1080 PCI_SLOT(pdev->devfn) == 2 &&
1081 PCI_FUNC(pdev->devfn) == 0;
1084 void i915_pmu_register(struct drm_i915_private *i915)
1086 struct i915_pmu *pmu = &i915->pmu;
1087 const struct attribute_group *attr_groups[] = {
1088 &i915_pmu_format_attr_group,
1089 &pmu->events_attr_group,
1090 &i915_pmu_cpumask_attr_group,
1096 if (INTEL_GEN(i915) <= 2) {
1097 drm_info(&i915->drm, "PMU not supported for this GPU.");
1101 spin_lock_init(&pmu->lock);
1102 hrtimer_init(&pmu->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1103 pmu->timer.function = i915_sample;
1104 pmu->cpuhp.slot = CPUHP_INVALID;
1107 if (!is_igp(i915)) {
1108 pmu->name = kasprintf(GFP_KERNEL,
1110 dev_name(i915->drm.dev));
1112 /* tools/perf reserves colons as special. */
1113 strreplace((char *)pmu->name, ':', '_');
1121 pmu->events_attr_group.name = "events";
1122 pmu->events_attr_group.attrs = create_event_attributes(pmu);
1123 if (!pmu->events_attr_group.attrs)
1126 pmu->base.attr_groups = kmemdup(attr_groups, sizeof(attr_groups),
1128 if (!pmu->base.attr_groups)
1131 pmu->base.module = THIS_MODULE;
1132 pmu->base.task_ctx_nr = perf_invalid_context;
1133 pmu->base.event_init = i915_pmu_event_init;
1134 pmu->base.add = i915_pmu_event_add;
1135 pmu->base.del = i915_pmu_event_del;
1136 pmu->base.start = i915_pmu_event_start;
1137 pmu->base.stop = i915_pmu_event_stop;
1138 pmu->base.read = i915_pmu_event_read;
1139 pmu->base.event_idx = i915_pmu_event_event_idx;
1141 ret = perf_pmu_register(&pmu->base, pmu->name, -1);
1145 ret = i915_pmu_register_cpuhp_state(pmu);
1152 perf_pmu_unregister(&pmu->base);
1154 kfree(pmu->base.attr_groups);
1156 pmu->base.event_init = NULL;
1157 free_event_attributes(pmu);
1162 drm_notice(&i915->drm, "Failed to register PMU!\n");
1165 void i915_pmu_unregister(struct drm_i915_private *i915)
1167 struct i915_pmu *pmu = &i915->pmu;
1169 if (!pmu->base.event_init)
1172 drm_WARN_ON(&i915->drm, pmu->enable);
1174 hrtimer_cancel(&pmu->timer);
1176 i915_pmu_unregister_cpuhp_state(pmu);
1178 perf_pmu_unregister(&pmu->base);
1179 pmu->base.event_init = NULL;
1180 kfree(pmu->base.attr_groups);
1183 free_event_attributes(pmu);