2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/console.h>
26 #include <linux/vgaarb.h>
27 #include <linux/vga_switcheroo.h>
30 #include "i915_selftest.h"
32 #define GEN_DEFAULT_PIPEOFFSETS \
33 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
34 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
35 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
36 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
37 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
39 #define GEN_CHV_PIPEOFFSETS \
40 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
41 CHV_PIPE_C_OFFSET }, \
42 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
43 CHV_TRANSCODER_C_OFFSET, }, \
44 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
45 CHV_PALETTE_C_OFFSET }
47 #define CURSOR_OFFSETS \
48 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
50 #define IVB_CURSOR_OFFSETS \
51 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
54 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
56 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
58 /* Keep in gen based order, and chronological order within a gen */
59 #define GEN2_FEATURES \
60 .gen = 2, .num_pipes = 1, \
61 .has_overlay = 1, .overlay_needs_physical = 1, \
62 .has_gmch_display = 1, \
63 .hws_needs_physical = 1, \
64 .unfenced_needs_alignment = 1, \
65 .ring_mask = RENDER_RING, \
66 GEN_DEFAULT_PIPEOFFSETS, \
69 static const struct intel_device_info intel_i830_info = {
71 .platform = INTEL_I830,
72 .is_mobile = 1, .cursor_needs_physical = 1,
73 .num_pipes = 2, /* legal, last one wins */
76 static const struct intel_device_info intel_i845g_info = {
78 .platform = INTEL_I845G,
81 static const struct intel_device_info intel_i85x_info = {
83 .platform = INTEL_I85X, .is_mobile = 1,
84 .num_pipes = 2, /* legal, last one wins */
85 .cursor_needs_physical = 1,
89 static const struct intel_device_info intel_i865g_info = {
91 .platform = INTEL_I865G,
94 #define GEN3_FEATURES \
95 .gen = 3, .num_pipes = 2, \
96 .has_gmch_display = 1, \
97 .ring_mask = RENDER_RING, \
98 GEN_DEFAULT_PIPEOFFSETS, \
101 static const struct intel_device_info intel_i915g_info = {
103 .platform = INTEL_I915G, .cursor_needs_physical = 1,
104 .has_overlay = 1, .overlay_needs_physical = 1,
105 .hws_needs_physical = 1,
106 .unfenced_needs_alignment = 1,
109 static const struct intel_device_info intel_i915gm_info = {
111 .platform = INTEL_I915GM,
113 .cursor_needs_physical = 1,
114 .has_overlay = 1, .overlay_needs_physical = 1,
117 .hws_needs_physical = 1,
118 .unfenced_needs_alignment = 1,
121 static const struct intel_device_info intel_i945g_info = {
123 .platform = INTEL_I945G,
124 .has_hotplug = 1, .cursor_needs_physical = 1,
125 .has_overlay = 1, .overlay_needs_physical = 1,
126 .hws_needs_physical = 1,
127 .unfenced_needs_alignment = 1,
130 static const struct intel_device_info intel_i945gm_info = {
132 .platform = INTEL_I945GM, .is_mobile = 1,
133 .has_hotplug = 1, .cursor_needs_physical = 1,
134 .has_overlay = 1, .overlay_needs_physical = 1,
137 .hws_needs_physical = 1,
138 .unfenced_needs_alignment = 1,
141 static const struct intel_device_info intel_g33_info = {
143 .platform = INTEL_G33,
148 static const struct intel_device_info intel_pineview_info = {
150 .platform = INTEL_PINEVIEW, .is_mobile = 1,
155 #define GEN4_FEATURES \
156 .gen = 4, .num_pipes = 2, \
158 .has_gmch_display = 1, \
159 .ring_mask = RENDER_RING, \
160 GEN_DEFAULT_PIPEOFFSETS, \
163 static const struct intel_device_info intel_i965g_info = {
165 .platform = INTEL_I965G,
167 .hws_needs_physical = 1,
170 static const struct intel_device_info intel_i965gm_info = {
172 .platform = INTEL_I965GM,
173 .is_mobile = 1, .has_fbc = 1,
176 .hws_needs_physical = 1,
179 static const struct intel_device_info intel_g45_info = {
181 .platform = INTEL_G45,
183 .ring_mask = RENDER_RING | BSD_RING,
186 static const struct intel_device_info intel_gm45_info = {
188 .platform = INTEL_GM45,
189 .is_mobile = 1, .has_fbc = 1,
192 .ring_mask = RENDER_RING | BSD_RING,
195 #define GEN5_FEATURES \
196 .gen = 5, .num_pipes = 2, \
198 .has_gmbus_irq = 1, \
199 .ring_mask = RENDER_RING | BSD_RING, \
200 GEN_DEFAULT_PIPEOFFSETS, \
203 static const struct intel_device_info intel_ironlake_d_info = {
205 .platform = INTEL_IRONLAKE,
208 static const struct intel_device_info intel_ironlake_m_info = {
210 .platform = INTEL_IRONLAKE,
211 .is_mobile = 1, .has_fbc = 1,
214 #define GEN6_FEATURES \
215 .gen = 6, .num_pipes = 2, \
218 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
222 .has_gmbus_irq = 1, \
223 .has_aliasing_ppgtt = 1, \
224 GEN_DEFAULT_PIPEOFFSETS, \
227 #define SNB_D_PLATFORM \
229 .platform = INTEL_SANDYBRIDGE
231 static const struct intel_device_info intel_sandybridge_d_gt1_info = {
236 static const struct intel_device_info intel_sandybridge_d_gt2_info = {
241 #define SNB_M_PLATFORM \
243 .platform = INTEL_SANDYBRIDGE, \
247 static const struct intel_device_info intel_sandybridge_m_gt1_info = {
252 static const struct intel_device_info intel_sandybridge_m_gt2_info = {
257 #define GEN7_FEATURES \
258 .gen = 7, .num_pipes = 3, \
261 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
265 .has_gmbus_irq = 1, \
266 .has_aliasing_ppgtt = 1, \
267 .has_full_ppgtt = 1, \
268 GEN_DEFAULT_PIPEOFFSETS, \
271 #define IVB_D_PLATFORM \
273 .platform = INTEL_IVYBRIDGE, \
276 static const struct intel_device_info intel_ivybridge_d_gt1_info = {
281 static const struct intel_device_info intel_ivybridge_d_gt2_info = {
286 #define IVB_M_PLATFORM \
288 .platform = INTEL_IVYBRIDGE, \
292 static const struct intel_device_info intel_ivybridge_m_gt1_info = {
297 static const struct intel_device_info intel_ivybridge_m_gt2_info = {
302 static const struct intel_device_info intel_ivybridge_q_info = {
304 .platform = INTEL_IVYBRIDGE,
306 .num_pipes = 0, /* legal, last one wins */
310 static const struct intel_device_info intel_valleyview_info = {
311 .platform = INTEL_VALLEYVIEW,
319 .has_gmch_display = 1,
321 .has_aliasing_ppgtt = 1,
323 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
324 .display_mmio_offset = VLV_DISPLAY_BASE,
325 GEN_DEFAULT_PIPEOFFSETS,
329 #define HSW_FEATURES \
331 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
335 .has_resource_streamer = 1, \
337 .has_rc6p = 0 /* RC6p removed-by HSW */, \
340 #define HSW_PLATFORM \
342 .platform = INTEL_HASWELL, \
345 static const struct intel_device_info intel_haswell_gt1_info = {
350 static const struct intel_device_info intel_haswell_gt2_info = {
355 static const struct intel_device_info intel_haswell_gt3_info = {
360 #define BDW_FEATURES \
363 .has_logical_ring_contexts = 1, \
364 .has_full_48bit_ppgtt = 1, \
365 .has_64bit_reloc = 1, \
366 .has_reset_engine = 1
368 #define BDW_PLATFORM \
371 .platform = INTEL_BROADWELL
373 static const struct intel_device_info intel_broadwell_gt1_info = {
378 static const struct intel_device_info intel_broadwell_gt2_info = {
383 static const struct intel_device_info intel_broadwell_rsvd_info = {
386 /* According to the device ID those devices are GT3, they were
387 * previously treated as not GT3, keep it like that.
391 static const struct intel_device_info intel_broadwell_gt3_info = {
394 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
397 static const struct intel_device_info intel_cherryview_info = {
398 .gen = 8, .num_pipes = 3,
401 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
402 .platform = INTEL_CHERRYVIEW,
403 .has_64bit_reloc = 1,
406 .has_resource_streamer = 1,
409 .has_logical_ring_contexts = 1,
410 .has_gmch_display = 1,
411 .has_aliasing_ppgtt = 1,
413 .has_reset_engine = 1,
414 .display_mmio_offset = VLV_DISPLAY_BASE,
420 #define SKL_PLATFORM \
423 .platform = INTEL_SKYLAKE, \
428 static const struct intel_device_info intel_skylake_gt1_info = {
433 static const struct intel_device_info intel_skylake_gt2_info = {
438 #define SKL_GT3_PLUS_PLATFORM \
440 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING
443 static const struct intel_device_info intel_skylake_gt3_info = {
444 SKL_GT3_PLUS_PLATFORM,
448 static const struct intel_device_info intel_skylake_gt4_info = {
449 SKL_GT3_PLUS_PLATFORM,
453 #define GEN9_LP_FEATURES \
457 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
459 .has_64bit_reloc = 1, \
463 .has_runtime_pm = 1, \
464 .has_pooled_eu = 0, \
466 .has_resource_streamer = 1, \
469 .has_gmbus_irq = 1, \
470 .has_logical_ring_contexts = 1, \
472 .has_aliasing_ppgtt = 1, \
473 .has_full_ppgtt = 1, \
474 .has_full_48bit_ppgtt = 1, \
475 .has_reset_engine = 1, \
476 GEN_DEFAULT_PIPEOFFSETS, \
477 IVB_CURSOR_OFFSETS, \
480 static const struct intel_device_info intel_broxton_info = {
482 .platform = INTEL_BROXTON,
484 .has_reset_engine = false,
487 static const struct intel_device_info intel_geminilake_info = {
489 .platform = INTEL_GEMINILAKE,
491 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
494 #define KBL_PLATFORM \
497 .platform = INTEL_KABYLAKE, \
502 static const struct intel_device_info intel_kabylake_gt1_info = {
507 static const struct intel_device_info intel_kabylake_gt2_info = {
512 static const struct intel_device_info intel_kabylake_gt3_info = {
515 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
518 #define CFL_PLATFORM \
519 .is_alpha_support = 1, \
522 .platform = INTEL_COFFEELAKE, \
527 static const struct intel_device_info intel_coffeelake_gt1_info = {
532 static const struct intel_device_info intel_coffeelake_gt2_info = {
537 static const struct intel_device_info intel_coffeelake_gt3_info = {
540 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
543 static const struct intel_device_info intel_cannonlake_gt2_info = {
545 .is_alpha_support = 1,
546 .platform = INTEL_CANNONLAKE,
551 .color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
555 * Make sure any device matches here are from most specific to most
556 * general. For example, since the Quanta match is based on the subsystem
557 * and subvendor IDs, we need it to come before the more general IVB
558 * PCI ID matches, otherwise we'll use the wrong info struct above.
560 static const struct pci_device_id pciidlist[] = {
561 INTEL_I830_IDS(&intel_i830_info),
562 INTEL_I845G_IDS(&intel_i845g_info),
563 INTEL_I85X_IDS(&intel_i85x_info),
564 INTEL_I865G_IDS(&intel_i865g_info),
565 INTEL_I915G_IDS(&intel_i915g_info),
566 INTEL_I915GM_IDS(&intel_i915gm_info),
567 INTEL_I945G_IDS(&intel_i945g_info),
568 INTEL_I945GM_IDS(&intel_i945gm_info),
569 INTEL_I965G_IDS(&intel_i965g_info),
570 INTEL_G33_IDS(&intel_g33_info),
571 INTEL_I965GM_IDS(&intel_i965gm_info),
572 INTEL_GM45_IDS(&intel_gm45_info),
573 INTEL_G45_IDS(&intel_g45_info),
574 INTEL_PINEVIEW_IDS(&intel_pineview_info),
575 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info),
576 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info),
577 INTEL_SNB_D_GT1_IDS(&intel_sandybridge_d_gt1_info),
578 INTEL_SNB_D_GT2_IDS(&intel_sandybridge_d_gt2_info),
579 INTEL_SNB_M_GT1_IDS(&intel_sandybridge_m_gt1_info),
580 INTEL_SNB_M_GT2_IDS(&intel_sandybridge_m_gt2_info),
581 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */
582 INTEL_IVB_M_GT1_IDS(&intel_ivybridge_m_gt1_info),
583 INTEL_IVB_M_GT2_IDS(&intel_ivybridge_m_gt2_info),
584 INTEL_IVB_D_GT1_IDS(&intel_ivybridge_d_gt1_info),
585 INTEL_IVB_D_GT2_IDS(&intel_ivybridge_d_gt2_info),
586 INTEL_HSW_GT1_IDS(&intel_haswell_gt1_info),
587 INTEL_HSW_GT2_IDS(&intel_haswell_gt2_info),
588 INTEL_HSW_GT3_IDS(&intel_haswell_gt3_info),
589 INTEL_VLV_IDS(&intel_valleyview_info),
590 INTEL_BDW_GT1_IDS(&intel_broadwell_gt1_info),
591 INTEL_BDW_GT2_IDS(&intel_broadwell_gt2_info),
592 INTEL_BDW_GT3_IDS(&intel_broadwell_gt3_info),
593 INTEL_BDW_RSVD_IDS(&intel_broadwell_rsvd_info),
594 INTEL_CHV_IDS(&intel_cherryview_info),
595 INTEL_SKL_GT1_IDS(&intel_skylake_gt1_info),
596 INTEL_SKL_GT2_IDS(&intel_skylake_gt2_info),
597 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info),
598 INTEL_SKL_GT4_IDS(&intel_skylake_gt4_info),
599 INTEL_BXT_IDS(&intel_broxton_info),
600 INTEL_GLK_IDS(&intel_geminilake_info),
601 INTEL_KBL_GT1_IDS(&intel_kabylake_gt1_info),
602 INTEL_KBL_GT2_IDS(&intel_kabylake_gt2_info),
603 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info),
604 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info),
605 INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
606 INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
607 INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
608 INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
609 INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
610 INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
613 MODULE_DEVICE_TABLE(pci, pciidlist);
615 static void i915_pci_remove(struct pci_dev *pdev)
617 struct drm_device *dev = pci_get_drvdata(pdev);
619 i915_driver_unload(dev);
623 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
625 struct intel_device_info *intel_info =
626 (struct intel_device_info *) ent->driver_data;
629 if (IS_ALPHA_SUPPORT(intel_info) && !i915.alpha_support) {
630 DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
631 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
632 "to enable support in this kernel version, or check for kernel updates.\n");
636 /* Only bind to function 0 of the device. Early generations
637 * used function 1 as a placeholder for multi-head. This causes
638 * us confusion instead, especially on the systems where both
639 * functions have the same PCI-ID!
641 if (PCI_FUNC(pdev->devfn))
645 * apple-gmux is needed on dual GPU MacBook Pro
646 * to probe the panel if we're the inactive GPU.
648 if (vga_switcheroo_client_probe_defer(pdev))
649 return -EPROBE_DEFER;
651 err = i915_driver_load(pdev, ent);
655 err = i915_live_selftests(pdev);
657 i915_pci_remove(pdev);
658 return err > 0 ? -ENOTTY : err;
664 static struct pci_driver i915_pci_driver = {
666 .id_table = pciidlist,
667 .probe = i915_pci_probe,
668 .remove = i915_pci_remove,
669 .driver.pm = &i915_pm_ops,
672 static int __init i915_init(void)
677 err = i915_mock_selftests();
679 return err > 0 ? 0 : err;
682 * Enable KMS by default, unless explicitly overriden by
683 * either the i915.modeset prarameter or by the
684 * vga_text_mode_force boot option.
687 if (i915.modeset == 0)
690 if (vgacon_text_force() && i915.modeset == -1)
694 /* Silently fail loading to not upset userspace. */
695 DRM_DEBUG_DRIVER("KMS disabled.\n");
699 return pci_register_driver(&i915_pci_driver);
702 static void __exit i915_exit(void)
704 if (!i915_pci_driver.driver.owner)
707 pci_unregister_driver(&i915_pci_driver);
710 module_init(i915_init);
711 module_exit(i915_exit);
713 MODULE_AUTHOR("Tungsten Graphics, Inc.");
714 MODULE_AUTHOR("Intel Corporation");
716 MODULE_DESCRIPTION(DRIVER_DESC);
717 MODULE_LICENSE("GPL and additional rights");