drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <linux/circ_buf.h>
  34 #include <drm/drmP.h>
  35 #include <drm/i915_drm.h>
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "intel_drv.h"
  39
  40 /**
  41  * DOC: interrupt handling
  42  *
  43  * These functions provide the basic support for enabling and disabling the
  44  * interrupt handling support. There's a lot more functionality in i915_irq.c
  45  * and related files, but that will be described in separate chapters.
  46  */
  47
  48 static const u32 hpd_ilk[HPD_NUM_PINS] = {
  49         [HPD_PORT_A] = DE_DP_A_HOTPLUG,
  50 };
  51
  52 static const u32 hpd_ivb[HPD_NUM_PINS] = {
  53         [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
  54 };
  55
  56 static const u32 hpd_bdw[HPD_NUM_PINS] = {
  57         [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
  58 };
  59
  60 static const u32 hpd_ibx[HPD_NUM_PINS] = {
  61         [HPD_CRT] = SDE_CRT_HOTPLUG,
  62         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  63         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  64         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  65         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  66 };
  67
  68 static const u32 hpd_cpt[HPD_NUM_PINS] = {
  69         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  70         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  71         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  72         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  73         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  74 };
  75
  76 static const u32 hpd_spt[HPD_NUM_PINS] = {
  77         [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
  78         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  79         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  80         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
  81         [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
  82 };
  83
  84 static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
  85         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  86         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  87         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  88         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  89         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  90         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  91 };
  92
  93 static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
  94         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  95         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  96         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  97         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  98         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  99         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 100 };
 101
 102 static const u32 hpd_status_i915[HPD_NUM_PINS] = {
 103         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
 104         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
 105         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
 106         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
 107         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
 108         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
 109 };
 110
 111 /* BXT hpd list */
 112 static const u32 hpd_bxt[HPD_NUM_PINS] = {
 113         [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
 114         [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
 115         [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
 116 };
 117
 118 /* IIR can theoretically queue up two events. Be paranoid. */
 119 #define GEN8_IRQ_RESET_NDX(type, which) do { \
 120         I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
 121         POSTING_READ(GEN8_##type##_IMR(which)); \
 122         I915_WRITE(GEN8_##type##_IER(which), 0); \
 123         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 124         POSTING_READ(GEN8_##type##_IIR(which)); \
 125         I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
 126         POSTING_READ(GEN8_##type##_IIR(which)); \
 127 } while (0)
 128
 129 #define GEN5_IRQ_RESET(type) do { \
 130         I915_WRITE(type##IMR, 0xffffffff); \
 131         POSTING_READ(type##IMR); \
 132         I915_WRITE(type##IER, 0); \
 133         I915_WRITE(type##IIR, 0xffffffff); \
 134         POSTING_READ(type##IIR); \
 135         I915_WRITE(type##IIR, 0xffffffff); \
 136         POSTING_READ(type##IIR); \
 137 } while (0)
 138
 139 /*
 140  * We should clear IMR at preinstall/uninstall, and just check at postinstall.
 141  */
 142 static void gen5_assert_iir_is_zero(struct drm_i915_private *dev_priv,
 143                                     i915_reg_t reg)
 144 {
 145         u32 val = I915_READ(reg);
 146
 147         if (val == 0)
 148                 return;
 149
 150         WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
 151              i915_mmio_reg_offset(reg), val);
 152         I915_WRITE(reg, 0xffffffff);
 153         POSTING_READ(reg);
 154         I915_WRITE(reg, 0xffffffff);
 155         POSTING_READ(reg);
 156 }
 157
 158 #define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
 159         gen5_assert_iir_is_zero(dev_priv, GEN8_##type##_IIR(which)); \
 160         I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
 161         I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
 162         POSTING_READ(GEN8_##type##_IMR(which)); \
 163 } while (0)
 164
 165 #define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
 166         gen5_assert_iir_is_zero(dev_priv, type##IIR); \
 167         I915_WRITE(type##IER, (ier_val)); \
 168         I915_WRITE(type##IMR, (imr_val)); \
 169         POSTING_READ(type##IMR); \
 170 } while (0)
 171
 172 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
 173
 174 /* For display hotplug interrupt */
 175 static inline void
 176 i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
 177                                      uint32_t mask,
 178                                      uint32_t bits)
 179 {
 180         uint32_t val;
 181
 182         assert_spin_locked(&dev_priv->irq_lock);
 183         WARN_ON(bits & ~mask);
 184
 185         val = I915_READ(PORT_HOTPLUG_EN);
 186         val &= ~mask;
 187         val |= bits;
 188         I915_WRITE(PORT_HOTPLUG_EN, val);
 189 }
 190
 191 /**
 192  * i915_hotplug_interrupt_update - update hotplug interrupt enable
 193  * @dev_priv: driver private
 194  * @mask: bits to update
 195  * @bits: bits to enable
 196  * NOTE: the HPD enable bits are modified both inside and outside
 197  * of an interrupt context. To avoid that read-modify-write cycles
 198  * interfer, these bits are protected by a spinlock. Since this
 199  * function is usually not called from a context where the lock is
 200  * held already, this function acquires the lock itself. A non-locking
 201  * version is also available.
 202  */
 203 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
 204                                    uint32_t mask,
 205                                    uint32_t bits)
 206 {
 207         spin_lock_irq(&dev_priv->irq_lock);
 208         i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
 209         spin_unlock_irq(&dev_priv->irq_lock);
 210 }
 211
 212 /**
 213  * ilk_update_display_irq - update DEIMR
 214  * @dev_priv: driver private
 215  * @interrupt_mask: mask of interrupt bits to update
 216  * @enabled_irq_mask: mask of interrupt bits to enable
 217  */
 218 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
 219                             uint32_t interrupt_mask,
 220                             uint32_t enabled_irq_mask)
 221 {
 222         uint32_t new_val;
 223
 224         assert_spin_locked(&dev_priv->irq_lock);
 225
 226         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 227
 228         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 229                 return;
 230
 231         new_val = dev_priv->irq_mask;
 232         new_val &= ~interrupt_mask;
 233         new_val |= (~enabled_irq_mask & interrupt_mask);
 234
 235         if (new_val != dev_priv->irq_mask) {
 236                 dev_priv->irq_mask = new_val;
 237                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 238                 POSTING_READ(DEIMR);
 239         }
 240 }
 241
 242 /**
 243  * ilk_update_gt_irq - update GTIMR
 244  * @dev_priv: driver private
 245  * @interrupt_mask: mask of interrupt bits to update
 246  * @enabled_irq_mask: mask of interrupt bits to enable
 247  */
 248 static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
 249                               uint32_t interrupt_mask,
 250                               uint32_t enabled_irq_mask)
 251 {
 252         assert_spin_locked(&dev_priv->irq_lock);
 253
 254         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 255
 256         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 257                 return;
 258
 259         dev_priv->gt_irq_mask &= ~interrupt_mask;
 260         dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
 261         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 262 }
 263
 264 void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 265 {
 266         ilk_update_gt_irq(dev_priv, mask, mask);
 267         POSTING_READ_FW(GTIMR);
 268 }
 269
 270 void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 271 {
 272         ilk_update_gt_irq(dev_priv, mask, 0);
 273 }
 274
 275 static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
 276 {
 277         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
 278 }
 279
 280 static i915_reg_t gen6_pm_imr(struct drm_i915_private *dev_priv)
 281 {
 282         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
 283 }
 284
 285 static i915_reg_t gen6_pm_ier(struct drm_i915_private *dev_priv)
 286 {
 287         return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
 288 }
 289
 290 /**
 291  * snb_update_pm_irq - update GEN6_PMIMR
 292  * @dev_priv: driver private
 293  * @interrupt_mask: mask of interrupt bits to update
 294  * @enabled_irq_mask: mask of interrupt bits to enable
 295  */
 296 static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
 297                               uint32_t interrupt_mask,
 298                               uint32_t enabled_irq_mask)
 299 {
 300         uint32_t new_val;
 301
 302         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 303
 304         assert_spin_locked(&dev_priv->irq_lock);
 305
 306         new_val = dev_priv->pm_irq_mask;
 307         new_val &= ~interrupt_mask;
 308         new_val |= (~enabled_irq_mask & interrupt_mask);
 309
 310         if (new_val != dev_priv->pm_irq_mask) {
 311                 dev_priv->pm_irq_mask = new_val;
 312                 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
 313                 POSTING_READ(gen6_pm_imr(dev_priv));
 314         }
 315 }
 316
 317 void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 318 {
 319         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 320                 return;
 321
 322         snb_update_pm_irq(dev_priv, mask, mask);
 323 }
 324
 325 static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
 326                                   uint32_t mask)
 327 {
 328         snb_update_pm_irq(dev_priv, mask, 0);
 329 }
 330
 331 void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
 332 {
 333         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 334                 return;
 335
 336         __gen6_disable_pm_irq(dev_priv, mask);
 337 }
 338
 339 void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
 340 {
 341         i915_reg_t reg = gen6_pm_iir(dev_priv);
 342
 343         spin_lock_irq(&dev_priv->irq_lock);
 344         I915_WRITE(reg, dev_priv->pm_rps_events);
 345         I915_WRITE(reg, dev_priv->pm_rps_events);
 346         POSTING_READ(reg);
 347         dev_priv->rps.pm_iir = 0;
 348         spin_unlock_irq(&dev_priv->irq_lock);
 349 }
 350
 351 void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
 352 {
 353         if (READ_ONCE(dev_priv->rps.interrupts_enabled))
 354                 return;
 355
 356         spin_lock_irq(&dev_priv->irq_lock);
 357         WARN_ON_ONCE(dev_priv->rps.pm_iir);
 358         WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
 359         dev_priv->rps.interrupts_enabled = true;
 360         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
 361                                 dev_priv->pm_rps_events);
 362         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 363
 364         spin_unlock_irq(&dev_priv->irq_lock);
 365 }
 366
 367 u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
 368 {
 369         return (mask & ~dev_priv->rps.pm_intr_keep);
 370 }
 371
 372 void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
 373 {
 374         if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
 375                 return;
 376
 377         spin_lock_irq(&dev_priv->irq_lock);
 378         dev_priv->rps.interrupts_enabled = false;
 379
 380         I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
 381
 382         __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
 383         I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
 384                                 ~dev_priv->pm_rps_events);
 385
 386         spin_unlock_irq(&dev_priv->irq_lock);
 387         synchronize_irq(dev_priv->drm.irq);
 388
 389         /* Now that we will not be generating any more work, flush any
 390          * outsanding tasks. As we are called on the RPS idle path,
 391          * we will reset the GPU to minimum frequencies, so the current
 392          * state of the worker can be discarded.
 393          */
 394         cancel_work_sync(&dev_priv->rps.work);
 395         gen6_reset_rps_interrupts(dev_priv);
 396 }
 397
 398 /**
 399  * bdw_update_port_irq - update DE port interrupt
 400  * @dev_priv: driver private
 401  * @interrupt_mask: mask of interrupt bits to update
 402  * @enabled_irq_mask: mask of interrupt bits to enable
 403  */
 404 static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
 405                                 uint32_t interrupt_mask,
 406                                 uint32_t enabled_irq_mask)
 407 {
 408         uint32_t new_val;
 409         uint32_t old_val;
 410
 411         assert_spin_locked(&dev_priv->irq_lock);
 412
 413         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 414
 415         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 416                 return;
 417
 418         old_val = I915_READ(GEN8_DE_PORT_IMR);
 419
 420         new_val = old_val;
 421         new_val &= ~interrupt_mask;
 422         new_val |= (~enabled_irq_mask & interrupt_mask);
 423
 424         if (new_val != old_val) {
 425                 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
 426                 POSTING_READ(GEN8_DE_PORT_IMR);
 427         }
 428 }
 429
 430 /**
 431  * bdw_update_pipe_irq - update DE pipe interrupt
 432  * @dev_priv: driver private
 433  * @pipe: pipe whose interrupt to update
 434  * @interrupt_mask: mask of interrupt bits to update
 435  * @enabled_irq_mask: mask of interrupt bits to enable
 436  */
 437 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
 438                          enum pipe pipe,
 439                          uint32_t interrupt_mask,
 440                          uint32_t enabled_irq_mask)
 441 {
 442         uint32_t new_val;
 443
 444         assert_spin_locked(&dev_priv->irq_lock);
 445
 446         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 447
 448         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 449                 return;
 450
 451         new_val = dev_priv->de_irq_mask[pipe];
 452         new_val &= ~interrupt_mask;
 453         new_val |= (~enabled_irq_mask & interrupt_mask);
 454
 455         if (new_val != dev_priv->de_irq_mask[pipe]) {
 456                 dev_priv->de_irq_mask[pipe] = new_val;
 457                 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
 458                 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
 459         }
 460 }
 461
 462 /**
 463  * ibx_display_interrupt_update - update SDEIMR
 464  * @dev_priv: driver private
 465  * @interrupt_mask: mask of interrupt bits to update
 466  * @enabled_irq_mask: mask of interrupt bits to enable
 467  */
 468 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
 469                                   uint32_t interrupt_mask,
 470                                   uint32_t enabled_irq_mask)
 471 {
 472         uint32_t sdeimr = I915_READ(SDEIMR);
 473         sdeimr &= ~interrupt_mask;
 474         sdeimr |= (~enabled_irq_mask & interrupt_mask);
 475
 476         WARN_ON(enabled_irq_mask & ~interrupt_mask);
 477
 478         assert_spin_locked(&dev_priv->irq_lock);
 479
 480         if (WARN_ON(!intel_irqs_enabled(dev_priv)))
 481                 return;
 482
 483         I915_WRITE(SDEIMR, sdeimr);
 484         POSTING_READ(SDEIMR);
 485 }
 486
 487 static void
 488 __i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 489                        u32 enable_mask, u32 status_mask)
 490 {
 491         i915_reg_t reg = PIPESTAT(pipe);
 492         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 493
 494         assert_spin_locked(&dev_priv->irq_lock);
 495         WARN_ON(!intel_irqs_enabled(dev_priv));
 496
 497         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 498                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 499                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 500                       pipe_name(pipe), enable_mask, status_mask))
 501                 return;
 502
 503         if ((pipestat & enable_mask) == enable_mask)
 504                 return;
 505
 506         dev_priv->pipestat_irq_mask[pipe] |= status_mask;
 507
 508         /* Enable the interrupt, clear any pending status */
 509         pipestat |= enable_mask | status_mask;
 510         I915_WRITE(reg, pipestat);
 511         POSTING_READ(reg);
 512 }
 513
 514 static void
 515 __i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 516                         u32 enable_mask, u32 status_mask)
 517 {
 518         i915_reg_t reg = PIPESTAT(pipe);
 519         u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
 520
 521         assert_spin_locked(&dev_priv->irq_lock);
 522         WARN_ON(!intel_irqs_enabled(dev_priv));
 523
 524         if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
 525                       status_mask & ~PIPESTAT_INT_STATUS_MASK,
 526                       "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
 527                       pipe_name(pipe), enable_mask, status_mask))
 528                 return;
 529
 530         if ((pipestat & enable_mask) == 0)
 531                 return;
 532
 533         dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
 534
 535         pipestat &= ~enable_mask;
 536         I915_WRITE(reg, pipestat);
 537         POSTING_READ(reg);
 538 }
 539
 540 static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
 541 {
 542         u32 enable_mask = status_mask << 16;
 543
 544         /*
 545          * On pipe A we don't support the PSR interrupt yet,
 546          * on pipe B and C the same bit MBZ.
 547          */
 548         if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
 549                 return 0;
 550         /*
 551          * On pipe B and C we don't support the PSR interrupt yet, on pipe
 552          * A the same bit is for perf counters which we don't use either.
 553          */
 554         if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
 555                 return 0;
 556
 557         enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
 558                          SPRITE0_FLIP_DONE_INT_EN_VLV |
 559                          SPRITE1_FLIP_DONE_INT_EN_VLV);
 560         if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
 561                 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
 562         if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
 563                 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
 564
 565         return enable_mask;
 566 }
 567
 568 void
 569 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 570                      u32 status_mask)
 571 {
 572         u32 enable_mask;
 573
 574         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 575                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 576                                                            status_mask);
 577         else
 578                 enable_mask = status_mask << 16;
 579         __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 580 }
 581
 582 void
 583 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
 584                       u32 status_mask)
 585 {
 586         u32 enable_mask;
 587
 588         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 589                 enable_mask = vlv_get_pipestat_enable_mask(&dev_priv->drm,
 590                                                            status_mask);
 591         else
 592                 enable_mask = status_mask << 16;
 593         __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
 594 }
 595
 596 /**
 597  * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
 598  * @dev_priv: i915 device private
 599  */
 600 static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
 601 {
 602         if (!dev_priv->opregion.asle || !IS_MOBILE(dev_priv))
 603                 return;
 604
 605         spin_lock_irq(&dev_priv->irq_lock);
 606
 607         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
 608         if (INTEL_GEN(dev_priv) >= 4)
 609                 i915_enable_pipestat(dev_priv, PIPE_A,
 610                                      PIPE_LEGACY_BLC_EVENT_STATUS);
 611
 612         spin_unlock_irq(&dev_priv->irq_lock);
 613 }
 614
 615 /*
 616  * This timing diagram depicts the video signal in and
 617  * around the vertical blanking period.
 618  *
 619  * Assumptions about the fictitious mode used in this example:
 620  *  vblank_start >= 3
 621  *  vsync_start = vblank_start + 1
 622  *  vsync_end = vblank_start + 2
 623  *  vtotal = vblank_start + 3
 624  *
 625  *           start of vblank:
 626  *           latch double buffered registers
 627  *           increment frame counter (ctg+)
 628  *           generate start of vblank interrupt (gen4+)
 629  *           |
 630  *           |          frame start:
 631  *           |          generate frame start interrupt (aka. vblank interrupt) (gmch)
 632  *           |          may be shifted forward 1-3 extra lines via PIPECONF
 633  *           |          |
 634  *           |          |  start of vsync:
 635  *           |          |  generate vsync interrupt
 636  *           |          |  |
 637  * ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx___    ___xxxx
 638  *       .   \hs/   .      \hs/          \hs/          \hs/   .      \hs/
 639  * ----va---> <-----------------vb--------------------> <--------va-------------
 640  *       |          |       <----vs----->                     |
 641  * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
 642  * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
 643  * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
 644  *       |          |                                         |
 645  *       last visible pixel                                   first visible pixel
 646  *                  |                                         increment frame counter (gen3/4)
 647  *                  pixel counter = vblank_start * htotal     pixel counter = 0 (gen3/4)
 648  *
 649  * x  = horizontal active
 650  * _  = horizontal blanking
 651  * hs = horizontal sync
 652  * va = vertical active
 653  * vb = vertical blanking
 654  * vs = vertical sync
 655  * vbs = vblank_start (number)
 656  *
 657  * Summary:
 658  * - most events happen at the start of horizontal sync
 659  * - frame start happens at the start of horizontal blank, 1-4 lines
 660  *   (depending on PIPECONF settings) after the start of vblank
 661  * - gen3/4 pixel and frame counter are synchronized with the start
 662  *   of horizontal active on the first line of vertical active
 663  */
 664
 665 /* Called from drm generic code, passed a 'crtc', which
 666  * we use as a pipe index
 667  */
 668 static u32 i915_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 669 {
 670         struct drm_i915_private *dev_priv = to_i915(dev);
 671         i915_reg_t high_frame, low_frame;
 672         u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
 673         struct intel_crtc *intel_crtc =
 674                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
 675         const struct drm_display_mode *mode = &intel_crtc->base.hwmode;
 676
 677         htotal = mode->crtc_htotal;
 678         hsync_start = mode->crtc_hsync_start;
 679         vbl_start = mode->crtc_vblank_start;
 680         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 681                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 682
 683         /* Convert to pixel count */
 684         vbl_start *= htotal;
 685
 686         /* Start of vblank event occurs at start of hsync */
 687         vbl_start -= htotal - hsync_start;
 688
 689         high_frame = PIPEFRAME(pipe);
 690         low_frame = PIPEFRAMEPIXEL(pipe);
 691
 692         /*
 693          * High & low register fields aren't synchronized, so make sure
 694          * we get a low value that's stable across two reads of the high
 695          * register.
 696          */
 697         do {
 698                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 699                 low   = I915_READ(low_frame);
 700                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 701         } while (high1 != high2);
 702
 703         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 704         pixel = low & PIPE_PIXEL_MASK;
 705         low >>= PIPE_FRAME_LOW_SHIFT;
 706
 707         /*
 708          * The frame counter increments at beginning of active.
 709          * Cook up a vblank counter by also checking the pixel
 710          * counter against vblank start.
 711          */
 712         return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
 713 }
 714
 715 static u32 g4x_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
 716 {
 717         struct drm_i915_private *dev_priv = to_i915(dev);
 718
 719         return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
 720 }
 721
 722 /* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
 723 static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 724 {
 725         struct drm_device *dev = crtc->base.dev;
 726         struct drm_i915_private *dev_priv = to_i915(dev);
 727         const struct drm_display_mode *mode = &crtc->base.hwmode;
 728         enum pipe pipe = crtc->pipe;
 729         int position, vtotal;
 730
 731         vtotal = mode->crtc_vtotal;
 732         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 733                 vtotal /= 2;
 734
 735         if (IS_GEN2(dev_priv))
 736                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
 737         else
 738                 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
 739
 740         /*
 741          * On HSW, the DSL reg (0x70000) appears to return 0 if we
 742          * read it just before the start of vblank.  So try it again
 743          * so we don't accidentally end up spanning a vblank frame
 744          * increment, causing the pipe_update_end() code to squak at us.
 745          *
 746          * The nature of this problem means we can't simply check the ISR
 747          * bit and return the vblank start value; nor can we use the scanline
 748          * debug register in the transcoder as it appears to have the same
 749          * problem.  We may need to extend this to include other platforms,
 750          * but so far testing only shows the problem on HSW.
 751          */
 752         if (HAS_DDI(dev_priv) && !position) {
 753                 int i, temp;
 754
 755                 for (i = 0; i < 100; i++) {
 756                         udelay(1);
 757                         temp = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) &
 758                                 DSL_LINEMASK_GEN3;
 759                         if (temp != position) {
 760                                 position = temp;
 761                                 break;
 762                         }
 763                 }
 764         }
 765
 766         /*
 767          * See update_scanline_offset() for the details on the
 768          * scanline_offset adjustment.
 769          */
 770         return (position + crtc->scanline_offset) % vtotal;
 771 }
 772
 773 static int i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
 774                                     unsigned int flags, int *vpos, int *hpos,
 775                                     ktime_t *stime, ktime_t *etime,
 776                                     const struct drm_display_mode *mode)
 777 {
 778         struct drm_i915_private *dev_priv = to_i915(dev);
 779         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 780         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 781         int position;
 782         int vbl_start, vbl_end, hsync_start, htotal, vtotal;
 783         bool in_vbl = true;
 784         int ret = 0;
 785         unsigned long irqflags;
 786
 787         if (WARN_ON(!mode->crtc_clock)) {
 788                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 789                                  "pipe %c\n", pipe_name(pipe));
 790                 return 0;
 791         }
 792
 793         htotal = mode->crtc_htotal;
 794         hsync_start = mode->crtc_hsync_start;
 795         vtotal = mode->crtc_vtotal;
 796         vbl_start = mode->crtc_vblank_start;
 797         vbl_end = mode->crtc_vblank_end;
 798
 799         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 800                 vbl_start = DIV_ROUND_UP(vbl_start, 2);
 801                 vbl_end /= 2;
 802                 vtotal /= 2;
 803         }
 804
 805         ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 806
 807         /*
 808          * Lock uncore.lock, as we will do multiple timing critical raw
 809          * register reads, potentially with preemption disabled, so the
 810          * following code must not block on uncore.lock.
 811          */
 812         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 813
 814         /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
 815
 816         /* Get optional system timestamp before query. */
 817         if (stime)
 818                 *stime = ktime_get();
 819
 820         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 821                 /* No obvious pixelcount register. Only query vertical
 822                  * scanout position from Display scan line register.
 823                  */
 824                 position = __intel_get_crtc_scanline(intel_crtc);
 825         } else {
 826                 /* Have access to pixelcount since start of frame.
 827                  * We can split this into vertical and horizontal
 828                  * scanout position.
 829                  */
 830                 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 831
 832                 /* convert to pixel counts */
 833                 vbl_start *= htotal;
 834                 vbl_end *= htotal;
 835                 vtotal *= htotal;
 836
 837                 /*
 838                  * In interlaced modes, the pixel counter counts all pixels,
 839                  * so one field will have htotal more pixels. In order to avoid
 840                  * the reported position from jumping backwards when the pixel
 841                  * counter is beyond the length of the shorter field, just
 842                  * clamp the position the length of the shorter field. This
 843                  * matches how the scanline counter based position works since
 844                  * the scanline counter doesn't count the two half lines.
 845                  */
 846                 if (position >= vtotal)
 847                         position = vtotal - 1;
 848
 849                 /*
 850                  * Start of vblank interrupt is triggered at start of hsync,
 851                  * just prior to the first active line of vblank. However we
 852                  * consider lines to start at the leading edge of horizontal
 853                  * active. So, should we get here before we've crossed into
 854                  * the horizontal active of the first line in vblank, we would
 855                  * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
 856                  * always add htotal-hsync_start to the current pixel position.
 857                  */
 858                 position = (position + htotal - hsync_start) % vtotal;
 859         }
 860
 861         /* Get optional system timestamp after query. */
 862         if (etime)
 863                 *etime = ktime_get();
 864
 865         /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
 866
 867         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 868
 869         in_vbl = position >= vbl_start && position < vbl_end;
 870
 871         /*
 872          * While in vblank, position will be negative
 873          * counting up towards 0 at vbl_end. And outside
 874          * vblank, position will be positive counting
 875          * up since vbl_end.
 876          */
 877         if (position >= vbl_start)
 878                 position -= vbl_end;
 879         else
 880                 position += vtotal - vbl_end;
 881
 882         if (IS_GEN2(dev_priv) || IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
 883                 *vpos = position;
 884                 *hpos = 0;
 885         } else {
 886                 *vpos = position / htotal;
 887                 *hpos = position - (*vpos * htotal);
 888         }
 889
 890         /* In vblank? */
 891         if (in_vbl)
 892                 ret |= DRM_SCANOUTPOS_IN_VBLANK;
 893
 894         return ret;
 895 }
 896
 897 int intel_get_crtc_scanline(struct intel_crtc *crtc)
 898 {
 899         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 900         unsigned long irqflags;
 901         int position;
 902
 903         spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
 904         position = __intel_get_crtc_scanline(crtc);
 905         spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 906
 907         return position;
 908 }
 909
 910 static int i915_get_vblank_timestamp(struct drm_device *dev, unsigned int pipe,
 911                               int *max_error,
 912                               struct timeval *vblank_time,
 913                               unsigned flags)
 914 {
 915         struct drm_crtc *crtc;
 916
 917         if (pipe >= INTEL_INFO(dev)->num_pipes) {
 918                 DRM_ERROR("Invalid crtc %u\n", pipe);
 919                 return -EINVAL;
 920         }
 921
 922         /* Get drm_crtc to timestamp: */
 923         crtc = intel_get_crtc_for_pipe(dev, pipe);
 924         if (crtc == NULL) {
 925                 DRM_ERROR("Invalid crtc %u\n", pipe);
 926                 return -EINVAL;
 927         }
 928
 929         if (!crtc->hwmode.crtc_clock) {
 930                 DRM_DEBUG_KMS("crtc %u is disabled\n", pipe);
 931                 return -EBUSY;
 932         }
 933
 934         /* Helper routine in DRM core does all the work: */
 935         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 936                                                      vblank_time, flags,
 937                                                      &crtc->hwmode);
 938 }
 939
 940 static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
 941 {
 942         u32 busy_up, busy_down, max_avg, min_avg;
 943         u8 new_delay;
 944
 945         spin_lock(&mchdev_lock);
 946
 947         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 948
 949         new_delay = dev_priv->ips.cur_delay;
 950
 951         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 952         busy_up = I915_READ(RCPREVBSYTUPAVG);
 953         busy_down = I915_READ(RCPREVBSYTDNAVG);
 954         max_avg = I915_READ(RCBMAXAVG);
 955         min_avg = I915_READ(RCBMINAVG);
 956
 957         /* Handle RCS change request from hw */
 958         if (busy_up > max_avg) {
 959                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 960                         new_delay = dev_priv->ips.cur_delay - 1;
 961                 if (new_delay < dev_priv->ips.max_delay)
 962                         new_delay = dev_priv->ips.max_delay;
 963         } else if (busy_down < min_avg) {
 964                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 965                         new_delay = dev_priv->ips.cur_delay + 1;
 966                 if (new_delay > dev_priv->ips.min_delay)
 967                         new_delay = dev_priv->ips.min_delay;
 968         }
 969
 970         if (ironlake_set_drps(dev_priv, new_delay))
 971                 dev_priv->ips.cur_delay = new_delay;
 972
 973         spin_unlock(&mchdev_lock);
 974
 975         return;
 976 }
 977
 978 static void notify_ring(struct intel_engine_cs *engine)
 979 {
 980         smp_store_mb(engine->breadcrumbs.irq_posted, true);
 981         if (intel_engine_wakeup(engine))
 982                 trace_i915_gem_request_notify(engine);
 983 }
 984
 985 static void vlv_c0_read(struct drm_i915_private *dev_priv,
 986                         struct intel_rps_ei *ei)
 987 {
 988         ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
 989         ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
 990         ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
 991 }
 992
 993 void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
 994 {
 995         memset(&dev_priv->rps.ei, 0, sizeof(dev_priv->rps.ei));
 996 }
 997
 998 static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
 999 {
1000         const struct intel_rps_ei *prev = &dev_priv->rps.ei;
1001         struct intel_rps_ei now;
1002         u32 events = 0;
1003
1004         if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1005                 return 0;
1006
1007         vlv_c0_read(dev_priv, &now);
1008         if (now.cz_clock == 0)
1009                 return 0;
1010
1011         if (prev->cz_clock) {
1012                 u64 time, c0;
1013                 unsigned int mul;
1014
1015                 mul = VLV_CZ_CLOCK_TO_MILLI_SEC * 100; /* scale to threshold% */
1016                 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
1017                         mul <<= 8;
1018
1019                 time = now.cz_clock - prev->cz_clock;
1020                 time *= dev_priv->czclk_freq;
1021
1022                 /* Workload can be split between render + media,
1023                  * e.g. SwapBuffers being blitted in X after being rendered in
1024                  * mesa. To account for this we need to combine both engines
1025                  * into our activity counter.
1026                  */
1027                 c0 = now.render_c0 - prev->render_c0;
1028                 c0 += now.media_c0 - prev->media_c0;
1029                 c0 *= mul;
1030
1031                 if (c0 > time * dev_priv->rps.up_threshold)
1032                         events = GEN6_PM_RP_UP_THRESHOLD;
1033                 else if (c0 < time * dev_priv->rps.down_threshold)
1034                         events = GEN6_PM_RP_DOWN_THRESHOLD;
1035         }
1036
1037         dev_priv->rps.ei = now;
1038         return events;
1039 }
1040
1041 static bool any_waiters(struct drm_i915_private *dev_priv)
1042 {
1043         struct intel_engine_cs *engine;
1044
1045         for_each_engine(engine, dev_priv)
1046                 if (intel_engine_has_waiter(engine))
1047                         return true;
1048
1049         return false;
1050 }
1051
1052 static void gen6_pm_rps_work(struct work_struct *work)
1053 {
1054         struct drm_i915_private *dev_priv =
1055                 container_of(work, struct drm_i915_private, rps.work);
1056         bool client_boost;
1057         int new_delay, adj, min, max;
1058         u32 pm_iir;
1059
1060         spin_lock_irq(&dev_priv->irq_lock);
1061         /* Speed up work cancelation during disabling rps interrupts. */
1062         if (!dev_priv->rps.interrupts_enabled) {
1063                 spin_unlock_irq(&dev_priv->irq_lock);
1064                 return;
1065         }
1066
1067         pm_iir = dev_priv->rps.pm_iir;
1068         dev_priv->rps.pm_iir = 0;
1069         /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1070         gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
1071         client_boost = dev_priv->rps.client_boost;
1072         dev_priv->rps.client_boost = false;
1073         spin_unlock_irq(&dev_priv->irq_lock);
1074
1075         /* Make sure we didn't queue anything we're not going to process. */
1076         WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1077
1078         if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1079                 return;
1080
1081         mutex_lock(&dev_priv->rps.hw_lock);
1082
1083         pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1084
1085         adj = dev_priv->rps.last_adj;
1086         new_delay = dev_priv->rps.cur_freq;
1087         min = dev_priv->rps.min_freq_softlimit;
1088         max = dev_priv->rps.max_freq_softlimit;
1089         if (client_boost || any_waiters(dev_priv))
1090                 max = dev_priv->rps.max_freq;
1091         if (client_boost && new_delay < dev_priv->rps.boost_freq) {
1092                 new_delay = dev_priv->rps.boost_freq;
1093                 adj = 0;
1094         } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1095                 if (adj > 0)
1096                         adj *= 2;
1097                 else /* CHV needs even encode values */
1098                         adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1099                 /*
1100                  * For better performance, jump directly
1101                  * to RPe if we're below it.
1102                  */
1103                 if (new_delay < dev_priv->rps.efficient_freq - adj) {
1104                         new_delay = dev_priv->rps.efficient_freq;
1105                         adj = 0;
1106                 }
1107         } else if (client_boost || any_waiters(dev_priv)) {
1108                 adj = 0;
1109         } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1110                 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1111                         new_delay = dev_priv->rps.efficient_freq;
1112                 else
1113                         new_delay = dev_priv->rps.min_freq_softlimit;
1114                 adj = 0;
1115         } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1116                 if (adj < 0)
1117                         adj *= 2;
1118                 else /* CHV needs even encode values */
1119                         adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1120         } else { /* unknown event */
1121                 adj = 0;
1122         }
1123
1124         dev_priv->rps.last_adj = adj;
1125
1126         /* sysfs frequency interfaces may have snuck in while servicing the
1127          * interrupt
1128          */
1129         new_delay += adj;
1130         new_delay = clamp_t(int, new_delay, min, max);
1131
1132         intel_set_rps(dev_priv, new_delay);
1133
1134         mutex_unlock(&dev_priv->rps.hw_lock);
1135 }
1136
1137
1138 /**
1139  * ivybridge_parity_work - Workqueue called when a parity error interrupt
1140  * occurred.
1141  * @work: workqueue struct
1142  *
1143  * Doesn't actually do anything except notify userspace. As a consequence of
1144  * this event, userspace should try to remap the bad rows since statistically
1145  * it is likely the same row is more likely to go bad again.
1146  */
1147 static void ivybridge_parity_work(struct work_struct *work)
1148 {
1149         struct drm_i915_private *dev_priv =
1150                 container_of(work, struct drm_i915_private, l3_parity.error_work);
1151         u32 error_status, row, bank, subbank;
1152         char *parity_event[6];
1153         uint32_t misccpctl;
1154         uint8_t slice = 0;
1155
1156         /* We must turn off DOP level clock gating to access the L3 registers.
1157          * In order to prevent a get/put style interface, acquire struct mutex
1158          * any time we access those registers.
1159          */
1160         mutex_lock(&dev_priv->drm.struct_mutex);
1161
1162         /* If we've screwed up tracking, just let the interrupt fire again */
1163         if (WARN_ON(!dev_priv->l3_parity.which_slice))
1164                 goto out;
1165
1166         misccpctl = I915_READ(GEN7_MISCCPCTL);
1167         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1168         POSTING_READ(GEN7_MISCCPCTL);
1169
1170         while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1171                 i915_reg_t reg;
1172
1173                 slice--;
1174                 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1175                         break;
1176
1177                 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1178
1179                 reg = GEN7_L3CDERRST1(slice);
1180
1181                 error_status = I915_READ(reg);
1182                 row = GEN7_PARITY_ERROR_ROW(error_status);
1183                 bank = GEN7_PARITY_ERROR_BANK(error_status);
1184                 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1185
1186                 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1187                 POSTING_READ(reg);
1188
1189                 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1190                 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1191                 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1192                 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1193                 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1194                 parity_event[5] = NULL;
1195
1196                 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1197                                    KOBJ_CHANGE, parity_event);
1198
1199                 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1200                           slice, row, bank, subbank);
1201
1202                 kfree(parity_event[4]);
1203                 kfree(parity_event[3]);
1204                 kfree(parity_event[2]);
1205                 kfree(parity_event[1]);
1206         }
1207
1208         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1209
1210 out:
1211         WARN_ON(dev_priv->l3_parity.which_slice);
1212         spin_lock_irq(&dev_priv->irq_lock);
1213         gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1214         spin_unlock_irq(&dev_priv->irq_lock);
1215
1216         mutex_unlock(&dev_priv->drm.struct_mutex);
1217 }
1218
1219 static void ivybridge_parity_error_irq_handler(struct drm_i915_private *dev_priv,
1220                                                u32 iir)
1221 {
1222         if (!HAS_L3_DPF(dev_priv))
1223                 return;
1224
1225         spin_lock(&dev_priv->irq_lock);
1226         gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv));
1227         spin_unlock(&dev_priv->irq_lock);
1228
1229         iir &= GT_PARITY_ERROR(dev_priv);
1230         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1231                 dev_priv->l3_parity.which_slice |= 1 << 1;
1232
1233         if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1234                 dev_priv->l3_parity.which_slice |= 1 << 0;
1235
1236         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
1237 }
1238
1239 static void ilk_gt_irq_handler(struct drm_i915_private *dev_priv,
1240                                u32 gt_iir)
1241 {
1242         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1243                 notify_ring(&dev_priv->engine[RCS]);
1244         if (gt_iir & ILK_BSD_USER_INTERRUPT)
1245                 notify_ring(&dev_priv->engine[VCS]);
1246 }
1247
1248 static void snb_gt_irq_handler(struct drm_i915_private *dev_priv,
1249                                u32 gt_iir)
1250 {
1251         if (gt_iir & GT_RENDER_USER_INTERRUPT)
1252                 notify_ring(&dev_priv->engine[RCS]);
1253         if (gt_iir & GT_BSD_USER_INTERRUPT)
1254                 notify_ring(&dev_priv->engine[VCS]);
1255         if (gt_iir & GT_BLT_USER_INTERRUPT)
1256                 notify_ring(&dev_priv->engine[BCS]);
1257
1258         if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1259                       GT_BSD_CS_ERROR_INTERRUPT |
1260                       GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1261                 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
1262
1263         if (gt_iir & GT_PARITY_ERROR(dev_priv))
1264                 ivybridge_parity_error_irq_handler(dev_priv, gt_iir);
1265 }
1266
1267 static __always_inline void
1268 gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift)
1269 {
1270         if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
1271                 notify_ring(engine);
1272         if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
1273                 tasklet_schedule(&engine->irq_tasklet);
1274 }
1275
1276 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
1277                                    u32 master_ctl,
1278                                    u32 gt_iir[4])
1279 {
1280         irqreturn_t ret = IRQ_NONE;
1281
1282         if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
1283                 gt_iir[0] = I915_READ_FW(GEN8_GT_IIR(0));
1284                 if (gt_iir[0]) {
1285                         I915_WRITE_FW(GEN8_GT_IIR(0), gt_iir[0]);
1286                         ret = IRQ_HANDLED;
1287                 } else
1288                         DRM_ERROR("The master control interrupt lied (GT0)!\n");
1289         }
1290
1291         if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
1292                 gt_iir[1] = I915_READ_FW(GEN8_GT_IIR(1));
1293                 if (gt_iir[1]) {
1294                         I915_WRITE_FW(GEN8_GT_IIR(1), gt_iir[1]);
1295                         ret = IRQ_HANDLED;
1296                 } else
1297                         DRM_ERROR("The master control interrupt lied (GT1)!\n");
1298         }
1299
1300         if (master_ctl & GEN8_GT_VECS_IRQ) {
1301                 gt_iir[3] = I915_READ_FW(GEN8_GT_IIR(3));
1302                 if (gt_iir[3]) {
1303                         I915_WRITE_FW(GEN8_GT_IIR(3), gt_iir[3]);
1304                         ret = IRQ_HANDLED;
1305                 } else
1306                         DRM_ERROR("The master control interrupt lied (GT3)!\n");
1307         }
1308
1309         if (master_ctl & GEN8_GT_PM_IRQ) {
1310                 gt_iir[2] = I915_READ_FW(GEN8_GT_IIR(2));
1311                 if (gt_iir[2] & dev_priv->pm_rps_events) {
1312                         I915_WRITE_FW(GEN8_GT_IIR(2),
1313                                       gt_iir[2] & dev_priv->pm_rps_events);
1314                         ret = IRQ_HANDLED;
1315                 } else
1316                         DRM_ERROR("The master control interrupt lied (PM)!\n");
1317         }
1318
1319         return ret;
1320 }
1321
1322 static void gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
1323                                 u32 gt_iir[4])
1324 {
1325         if (gt_iir[0]) {
1326                 gen8_cs_irq_handler(&dev_priv->engine[RCS],
1327                                     gt_iir[0], GEN8_RCS_IRQ_SHIFT);
1328                 gen8_cs_irq_handler(&dev_priv->engine[BCS],
1329                                     gt_iir[0], GEN8_BCS_IRQ_SHIFT);
1330         }
1331
1332         if (gt_iir[1]) {
1333                 gen8_cs_irq_handler(&dev_priv->engine[VCS],
1334                                     gt_iir[1], GEN8_VCS1_IRQ_SHIFT);
1335                 gen8_cs_irq_handler(&dev_priv->engine[VCS2],
1336                                     gt_iir[1], GEN8_VCS2_IRQ_SHIFT);
1337         }
1338
1339         if (gt_iir[3])
1340                 gen8_cs_irq_handler(&dev_priv->engine[VECS],
1341                                     gt_iir[3], GEN8_VECS_IRQ_SHIFT);
1342
1343         if (gt_iir[2] & dev_priv->pm_rps_events)
1344                 gen6_rps_irq_handler(dev_priv, gt_iir[2]);
1345 }
1346
1347 static bool bxt_port_hotplug_long_detect(enum port port, u32 val)
1348 {
1349         switch (port) {
1350         case PORT_A:
1351                 return val & PORTA_HOTPLUG_LONG_DETECT;
1352         case PORT_B:
1353                 return val & PORTB_HOTPLUG_LONG_DETECT;
1354         case PORT_C:
1355                 return val & PORTC_HOTPLUG_LONG_DETECT;
1356         default:
1357                 return false;
1358         }
1359 }
1360
1361 static bool spt_port_hotplug2_long_detect(enum port port, u32 val)
1362 {
1363         switch (port) {
1364         case PORT_E:
1365                 return val & PORTE_HOTPLUG_LONG_DETECT;
1366         default:
1367                 return false;
1368         }
1369 }
1370
1371 static bool spt_port_hotplug_long_detect(enum port port, u32 val)
1372 {
1373         switch (port) {
1374         case PORT_A:
1375                 return val & PORTA_HOTPLUG_LONG_DETECT;
1376         case PORT_B:
1377                 return val & PORTB_HOTPLUG_LONG_DETECT;
1378         case PORT_C:
1379                 return val & PORTC_HOTPLUG_LONG_DETECT;
1380         case PORT_D:
1381                 return val & PORTD_HOTPLUG_LONG_DETECT;
1382         default:
1383                 return false;
1384         }
1385 }
1386
1387 static bool ilk_port_hotplug_long_detect(enum port port, u32 val)
1388 {
1389         switch (port) {
1390         case PORT_A:
1391                 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1392         default:
1393                 return false;
1394         }
1395 }
1396
1397 static bool pch_port_hotplug_long_detect(enum port port, u32 val)
1398 {
1399         switch (port) {
1400         case PORT_B:
1401                 return val & PORTB_HOTPLUG_LONG_DETECT;
1402         case PORT_C:
1403                 return val & PORTC_HOTPLUG_LONG_DETECT;
1404         case PORT_D:
1405                 return val & PORTD_HOTPLUG_LONG_DETECT;
1406         default:
1407                 return false;
1408         }
1409 }
1410
1411 static bool i9xx_port_hotplug_long_detect(enum port port, u32 val)
1412 {
1413         switch (port) {
1414         case PORT_B:
1415                 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1416         case PORT_C:
1417                 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1418         case PORT_D:
1419                 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1420         default:
1421                 return false;
1422         }
1423 }
1424
1425 /*
1426  * Get a bit mask of pins that have triggered, and which ones may be long.
1427  * This can be called multiple times with the same masks to accumulate
1428  * hotplug detection results from several registers.
1429  *
1430  * Note that the caller is expected to zero out the masks initially.
1431  */
1432 static void intel_get_hpd_pins(u32 *pin_mask, u32 *long_mask,
1433                              u32 hotplug_trigger, u32 dig_hotplug_reg,
1434                              const u32 hpd[HPD_NUM_PINS],
1435                              bool long_pulse_detect(enum port port, u32 val))
1436 {
1437         enum port port;
1438         int i;
1439
1440         for_each_hpd_pin(i) {
1441                 if ((hpd[i] & hotplug_trigger) == 0)
1442                         continue;
1443
1444                 *pin_mask |= BIT(i);
1445
1446                 if (!intel_hpd_pin_to_port(i, &port))
1447                         continue;
1448
1449                 if (long_pulse_detect(port, dig_hotplug_reg))
1450                         *long_mask |= BIT(i);
1451         }
1452
1453         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x\n",
1454                          hotplug_trigger, dig_hotplug_reg, *pin_mask);
1455
1456 }
1457
1458 static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1459 {
1460         wake_up_all(&dev_priv->gmbus_wait_queue);
1461 }
1462
1463 static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1464 {
1465         wake_up_all(&dev_priv->gmbus_wait_queue);
1466 }
1467
1468 #if defined(CONFIG_DEBUG_FS)
1469 static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1470                                          enum pipe pipe,
1471                                          uint32_t crc0, uint32_t crc1,
1472                                          uint32_t crc2, uint32_t crc3,
1473                                          uint32_t crc4)
1474 {
1475         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1476         struct intel_pipe_crc_entry *entry;
1477         int head, tail;
1478
1479         spin_lock(&pipe_crc->lock);
1480
1481         if (!pipe_crc->entries) {
1482                 spin_unlock(&pipe_crc->lock);
1483                 DRM_DEBUG_KMS("spurious interrupt\n");
1484                 return;
1485         }
1486
1487         head = pipe_crc->head;
1488         tail = pipe_crc->tail;
1489
1490         if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
1491                 spin_unlock(&pipe_crc->lock);
1492                 DRM_ERROR("CRC buffer overflowing\n");
1493                 return;
1494         }
1495
1496         entry = &pipe_crc->entries[head];
1497
1498         entry->frame = dev_priv->drm.driver->get_vblank_counter(&dev_priv->drm,
1499                                                                  pipe);
1500         entry->crc[0] = crc0;
1501         entry->crc[1] = crc1;
1502         entry->crc[2] = crc2;
1503         entry->crc[3] = crc3;
1504         entry->crc[4] = crc4;
1505
1506         head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
1507         pipe_crc->head = head;
1508
1509         spin_unlock(&pipe_crc->lock);
1510
1511         wake_up_interruptible(&pipe_crc->wq);
1512 }
1513 #else
1514 static inline void
1515 display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1516                              enum pipe pipe,
1517                              uint32_t crc0, uint32_t crc1,
1518                              uint32_t crc2, uint32_t crc3,
1519                              uint32_t crc4) {}
1520 #endif
1521
1522
1523 static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1524                                      enum pipe pipe)
1525 {
1526         display_pipe_crc_irq_handler(dev_priv, pipe,
1527                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1528                                      0, 0, 0, 0);
1529 }
1530
1531 static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1532                                      enum pipe pipe)
1533 {
1534         display_pipe_crc_irq_handler(dev_priv, pipe,
1535                                      I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1536                                      I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1537                                      I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1538                                      I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1539                                      I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1540 }
1541
1542 static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1543                                       enum pipe pipe)
1544 {
1545         uint32_t res1, res2;
1546
1547         if (INTEL_GEN(dev_priv) >= 3)
1548                 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1549         else
1550                 res1 = 0;
1551
1552         if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1553                 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1554         else
1555                 res2 = 0;
1556
1557         display_pipe_crc_irq_handler(dev_priv, pipe,
1558                                      I915_READ(PIPE_CRC_RES_RED(pipe)),
1559                                      I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1560                                      I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1561                                      res1, res2);
1562 }
1563
1564 /* The RPS events need forcewake, so we add them to a work queue and mask their
1565  * IMR bits until the work is done. Other interrupts can be processed without
1566  * the work queue. */
1567 static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1568 {
1569         if (pm_iir & dev_priv->pm_rps_events) {
1570                 spin_lock(&dev_priv->irq_lock);
1571                 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
1572                 if (dev_priv->rps.interrupts_enabled) {
1573                         dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1574                         schedule_work(&dev_priv->rps.work);
1575                 }
1576                 spin_unlock(&dev_priv->irq_lock);
1577         }
1578
1579         if (INTEL_INFO(dev_priv)->gen >= 8)
1580                 return;
1581
1582         if (HAS_VEBOX(dev_priv)) {
1583                 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1584                         notify_ring(&dev_priv->engine[VECS]);
1585
1586                 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1587                         DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1588         }
1589 }
1590
1591 static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv,
1592                                      enum pipe pipe)
1593 {
1594         bool ret;
1595
1596         ret = drm_handle_vblank(&dev_priv->drm, pipe);
1597         if (ret)
1598                 intel_finish_page_flip_mmio(dev_priv, pipe);
1599
1600         return ret;
1601 }
1602
1603 static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1604                                         u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1605 {
1606         int pipe;
1607
1608         spin_lock(&dev_priv->irq_lock);
1609
1610         if (!dev_priv->display_irqs_enabled) {
1611                 spin_unlock(&dev_priv->irq_lock);
1612                 return;
1613         }
1614
1615         for_each_pipe(dev_priv, pipe) {
1616                 i915_reg_t reg;
1617                 u32 mask, iir_bit = 0;
1618
1619                 /*
1620                  * PIPESTAT bits get signalled even when the interrupt is
1621                  * disabled with the mask bits, and some of the status bits do
1622                  * not generate interrupts at all (like the underrun bit). Hence
1623                  * we need to be careful that we only handle what we want to
1624                  * handle.
1625                  */
1626
1627                 /* fifo underruns are filterered in the underrun handler. */
1628                 mask = PIPE_FIFO_UNDERRUN_STATUS;
1629
1630                 switch (pipe) {
1631                 case PIPE_A:
1632                         iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1633                         break;
1634                 case PIPE_B:
1635                         iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1636                         break;
1637                 case PIPE_C:
1638                         iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1639                         break;
1640                 }
1641                 if (iir & iir_bit)
1642                         mask |= dev_priv->pipestat_irq_mask[pipe];
1643
1644                 if (!mask)
1645                         continue;
1646
1647                 reg = PIPESTAT(pipe);
1648                 mask |= PIPESTAT_INT_ENABLE_MASK;
1649                 pipe_stats[pipe] = I915_READ(reg) & mask;
1650
1651                 /*
1652                  * Clear the PIPE*STAT regs before the IIR
1653                  */
1654                 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1655                                         PIPESTAT_INT_STATUS_MASK))
1656                         I915_WRITE(reg, pipe_stats[pipe]);
1657         }
1658         spin_unlock(&dev_priv->irq_lock);
1659 }
1660
1661 static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1662                                             u32 pipe_stats[I915_MAX_PIPES])
1663 {
1664         enum pipe pipe;
1665
1666         for_each_pipe(dev_priv, pipe) {
1667                 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1668                     intel_pipe_handle_vblank(dev_priv, pipe))
1669                         intel_check_page_flip(dev_priv, pipe);
1670
1671                 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV)
1672                         intel_finish_page_flip_cs(dev_priv, pipe);
1673
1674                 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1675                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1676
1677                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1678                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1679         }
1680
1681         if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1682                 gmbus_irq_handler(dev_priv);
1683 }
1684
1685 static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1686 {
1687         u32 hotplug_status = 0, hotplug_status_mask;
1688         int i;
1689
1690         if (IS_G4X(dev_priv) ||
1691             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1692                 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1693                         DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1694         else
1695                 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1696
1697         /*
1698          * We absolutely have to clear all the pending interrupt
1699          * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1700          * interrupt bit won't have an edge, and the i965/g4x
1701          * edge triggered IIR will not notice that an interrupt
1702          * is still pending. We can't use PORT_HOTPLUG_EN to
1703          * guarantee the edge as the act of toggling the enable
1704          * bits can itself generate a new hotplug interrupt :(
1705          */
1706         for (i = 0; i < 10; i++) {
1707                 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1708
1709                 if (tmp == 0)
1710                         return hotplug_status;
1711
1712                 hotplug_status |= tmp;
1713                 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1714         }
1715
1716         WARN_ONCE(1,
1717                   "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1718                   I915_READ(PORT_HOTPLUG_STAT));
1719
1720         return hotplug_status;
1721 }
1722
1723 static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1724                                  u32 hotplug_status)
1725 {
1726         u32 pin_mask = 0, long_mask = 0;
1727
1728         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1729             IS_CHERRYVIEW(dev_priv)) {
1730                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1731
1732                 if (hotplug_trigger) {
1733                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1734                                            hotplug_trigger, hpd_status_g4x,
1735                                            i9xx_port_hotplug_long_detect);
1736
1737                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1738                 }
1739
1740                 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1741                         dp_aux_irq_handler(dev_priv);
1742         } else {
1743                 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1744
1745                 if (hotplug_trigger) {
1746                         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1747                                            hotplug_trigger, hpd_status_i915,
1748                                            i9xx_port_hotplug_long_detect);
1749                         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1750                 }
1751         }
1752 }
1753
1754 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1755 {
1756         struct drm_device *dev = arg;
1757         struct drm_i915_private *dev_priv = to_i915(dev);
1758         irqreturn_t ret = IRQ_NONE;
1759
1760         if (!intel_irqs_enabled(dev_priv))
1761                 return IRQ_NONE;
1762
1763         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1764         disable_rpm_wakeref_asserts(dev_priv);
1765
1766         do {
1767                 u32 iir, gt_iir, pm_iir;
1768                 u32 pipe_stats[I915_MAX_PIPES] = {};
1769                 u32 hotplug_status = 0;
1770                 u32 ier = 0;
1771
1772                 gt_iir = I915_READ(GTIIR);
1773                 pm_iir = I915_READ(GEN6_PMIIR);
1774                 iir = I915_READ(VLV_IIR);
1775
1776                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1777                         break;
1778
1779                 ret = IRQ_HANDLED;
1780
1781                 /*
1782                  * Theory on interrupt generation, based on empirical evidence:
1783                  *
1784                  * x = ((VLV_IIR & VLV_IER) ||
1785                  *      (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1786                  *       (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1787                  *
1788                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1789                  * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1790                  * guarantee the CPU interrupt will be raised again even if we
1791                  * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1792                  * bits this time around.
1793                  */
1794                 I915_WRITE(VLV_MASTER_IER, 0);
1795                 ier = I915_READ(VLV_IER);
1796                 I915_WRITE(VLV_IER, 0);
1797
1798                 if (gt_iir)
1799                         I915_WRITE(GTIIR, gt_iir);
1800                 if (pm_iir)
1801                         I915_WRITE(GEN6_PMIIR, pm_iir);
1802
1803                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1804                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1805
1806                 /* Call regardless, as some status bits might not be
1807                  * signalled in iir */
1808                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1809
1810                 /*
1811                  * VLV_IIR is single buffered, and reflects the level
1812                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1813                  */
1814                 if (iir)
1815                         I915_WRITE(VLV_IIR, iir);
1816
1817                 I915_WRITE(VLV_IER, ier);
1818                 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1819                 POSTING_READ(VLV_MASTER_IER);
1820
1821                 if (gt_iir)
1822                         snb_gt_irq_handler(dev_priv, gt_iir);
1823                 if (pm_iir)
1824                         gen6_rps_irq_handler(dev_priv, pm_iir);
1825
1826                 if (hotplug_status)
1827                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1828
1829                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1830         } while (0);
1831
1832         enable_rpm_wakeref_asserts(dev_priv);
1833
1834         return ret;
1835 }
1836
1837 static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1838 {
1839         struct drm_device *dev = arg;
1840         struct drm_i915_private *dev_priv = to_i915(dev);
1841         irqreturn_t ret = IRQ_NONE;
1842
1843         if (!intel_irqs_enabled(dev_priv))
1844                 return IRQ_NONE;
1845
1846         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1847         disable_rpm_wakeref_asserts(dev_priv);
1848
1849         do {
1850                 u32 master_ctl, iir;
1851                 u32 gt_iir[4] = {};
1852                 u32 pipe_stats[I915_MAX_PIPES] = {};
1853                 u32 hotplug_status = 0;
1854                 u32 ier = 0;
1855
1856                 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1857                 iir = I915_READ(VLV_IIR);
1858
1859                 if (master_ctl == 0 && iir == 0)
1860                         break;
1861
1862                 ret = IRQ_HANDLED;
1863
1864                 /*
1865                  * Theory on interrupt generation, based on empirical evidence:
1866                  *
1867                  * x = ((VLV_IIR & VLV_IER) ||
1868                  *      ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1869                  *       (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1870                  *
1871                  * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1872                  * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1873                  * guarantee the CPU interrupt will be raised again even if we
1874                  * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1875                  * bits this time around.
1876                  */
1877                 I915_WRITE(GEN8_MASTER_IRQ, 0);
1878                 ier = I915_READ(VLV_IER);
1879                 I915_WRITE(VLV_IER, 0);
1880
1881                 gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
1882
1883                 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1884                         hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1885
1886                 /* Call regardless, as some status bits might not be
1887                  * signalled in iir */
1888                 valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1889
1890                 /*
1891                  * VLV_IIR is single buffered, and reflects the level
1892                  * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1893                  */
1894                 if (iir)
1895                         I915_WRITE(VLV_IIR, iir);
1896
1897                 I915_WRITE(VLV_IER, ier);
1898                 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1899                 POSTING_READ(GEN8_MASTER_IRQ);
1900
1901                 gen8_gt_irq_handler(dev_priv, gt_iir);
1902
1903                 if (hotplug_status)
1904                         i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1905
1906                 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1907         } while (0);
1908
1909         enable_rpm_wakeref_asserts(dev_priv);
1910
1911         return ret;
1912 }
1913
1914 static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1915                                 u32 hotplug_trigger,
1916                                 const u32 hpd[HPD_NUM_PINS])
1917 {
1918         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1919
1920         /*
1921          * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1922          * unless we touch the hotplug register, even if hotplug_trigger is
1923          * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1924          * errors.
1925          */
1926         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1927         if (!hotplug_trigger) {
1928                 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1929                         PORTD_HOTPLUG_STATUS_MASK |
1930                         PORTC_HOTPLUG_STATUS_MASK |
1931                         PORTB_HOTPLUG_STATUS_MASK;
1932                 dig_hotplug_reg &= ~mask;
1933         }
1934
1935         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1936         if (!hotplug_trigger)
1937                 return;
1938
1939         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
1940                            dig_hotplug_reg, hpd,
1941                            pch_port_hotplug_long_detect);
1942
1943         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1944 }
1945
1946 static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1947 {
1948         int pipe;
1949         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1950
1951         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
1952
1953         if (pch_iir & SDE_AUDIO_POWER_MASK) {
1954                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1955                                SDE_AUDIO_POWER_SHIFT);
1956                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
1957                                  port_name(port));
1958         }
1959
1960         if (pch_iir & SDE_AUX_MASK)
1961                 dp_aux_irq_handler(dev_priv);
1962
1963         if (pch_iir & SDE_GMBUS)
1964                 gmbus_irq_handler(dev_priv);
1965
1966         if (pch_iir & SDE_AUDIO_HDCP_MASK)
1967                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1968
1969         if (pch_iir & SDE_AUDIO_TRANS_MASK)
1970                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1971
1972         if (pch_iir & SDE_POISON)
1973                 DRM_ERROR("PCH poison interrupt\n");
1974
1975         if (pch_iir & SDE_FDI_MASK)
1976                 for_each_pipe(dev_priv, pipe)
1977                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
1978                                          pipe_name(pipe),
1979                                          I915_READ(FDI_RX_IIR(pipe)));
1980
1981         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1982                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1983
1984         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1985                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1986
1987         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1988                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1989
1990         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1991                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1992 }
1993
1994 static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1995 {
1996         u32 err_int = I915_READ(GEN7_ERR_INT);
1997         enum pipe pipe;
1998
1999         if (err_int & ERR_INT_POISON)
2000                 DRM_ERROR("Poison interrupt\n");
2001
2002         for_each_pipe(dev_priv, pipe) {
2003                 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2004                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2005
2006                 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2007                         if (IS_IVYBRIDGE(dev_priv))
2008                                 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2009                         else
2010                                 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2011                 }
2012         }
2013
2014         I915_WRITE(GEN7_ERR_INT, err_int);
2015 }
2016
2017 static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2018 {
2019         u32 serr_int = I915_READ(SERR_INT);
2020
2021         if (serr_int & SERR_INT_POISON)
2022                 DRM_ERROR("PCH poison interrupt\n");
2023
2024         if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
2025                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2026
2027         if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
2028                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2029
2030         if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
2031                 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_C);
2032
2033         I915_WRITE(SERR_INT, serr_int);
2034 }
2035
2036 static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2037 {
2038         int pipe;
2039         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2040
2041         ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2042
2043         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2044                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2045                                SDE_AUDIO_POWER_SHIFT_CPT);
2046                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2047                                  port_name(port));
2048         }
2049
2050         if (pch_iir & SDE_AUX_MASK_CPT)
2051                 dp_aux_irq_handler(dev_priv);
2052
2053         if (pch_iir & SDE_GMBUS_CPT)
2054                 gmbus_irq_handler(dev_priv);
2055
2056         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2057                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2058
2059         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2060                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2061
2062         if (pch_iir & SDE_FDI_MASK_CPT)
2063                 for_each_pipe(dev_priv, pipe)
2064                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
2065                                          pipe_name(pipe),
2066                                          I915_READ(FDI_RX_IIR(pipe)));
2067
2068         if (pch_iir & SDE_ERROR_CPT)
2069                 cpt_serr_int_handler(dev_priv);
2070 }
2071
2072 static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2073 {
2074         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2075                 ~SDE_PORTE_HOTPLUG_SPT;
2076         u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2077         u32 pin_mask = 0, long_mask = 0;
2078
2079         if (hotplug_trigger) {
2080                 u32 dig_hotplug_reg;
2081
2082                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2083                 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2084
2085                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2086                                    dig_hotplug_reg, hpd_spt,
2087                                    spt_port_hotplug_long_detect);
2088         }
2089
2090         if (hotplug2_trigger) {
2091                 u32 dig_hotplug_reg;
2092
2093                 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2094                 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2095
2096                 intel_get_hpd_pins(&pin_mask, &long_mask, hotplug2_trigger,
2097                                    dig_hotplug_reg, hpd_spt,
2098                                    spt_port_hotplug2_long_detect);
2099         }
2100
2101         if (pin_mask)
2102                 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2103
2104         if (pch_iir & SDE_GMBUS_CPT)
2105                 gmbus_irq_handler(dev_priv);
2106 }
2107
2108 static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2109                                 u32 hotplug_trigger,
2110                                 const u32 hpd[HPD_NUM_PINS])
2111 {
2112         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2113
2114         dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2115         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2116
2117         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2118                            dig_hotplug_reg, hpd,
2119                            ilk_port_hotplug_long_detect);
2120
2121         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2122 }
2123
2124 static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2125                                     u32 de_iir)
2126 {
2127         enum pipe pipe;
2128         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2129
2130         if (hotplug_trigger)
2131                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2132
2133         if (de_iir & DE_AUX_CHANNEL_A)
2134                 dp_aux_irq_handler(dev_priv);
2135
2136         if (de_iir & DE_GSE)
2137                 intel_opregion_asle_intr(dev_priv);
2138
2139         if (de_iir & DE_POISON)
2140                 DRM_ERROR("Poison interrupt\n");
2141
2142         for_each_pipe(dev_priv, pipe) {
2143                 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2144                     intel_pipe_handle_vblank(dev_priv, pipe))
2145                         intel_check_page_flip(dev_priv, pipe);
2146
2147                 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2148                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2149
2150                 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2151                         i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2152
2153                 /* plane/pipes map 1:1 on ilk+ */
2154                 if (de_iir & DE_PLANE_FLIP_DONE(pipe))
2155                         intel_finish_page_flip_cs(dev_priv, pipe);
2156         }
2157
2158         /* check event from PCH */
2159         if (de_iir & DE_PCH_EVENT) {
2160                 u32 pch_iir = I915_READ(SDEIIR);
2161
2162                 if (HAS_PCH_CPT(dev_priv))
2163                         cpt_irq_handler(dev_priv, pch_iir);
2164                 else
2165                         ibx_irq_handler(dev_priv, pch_iir);
2166
2167                 /* should clear PCH hotplug event before clear CPU irq */
2168                 I915_WRITE(SDEIIR, pch_iir);
2169         }
2170
2171         if (IS_GEN5(dev_priv) && de_iir & DE_PCU_EVENT)
2172                 ironlake_rps_change_irq_handler(dev_priv);
2173 }
2174
2175 static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2176                                     u32 de_iir)
2177 {
2178         enum pipe pipe;
2179         u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2180
2181         if (hotplug_trigger)
2182                 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2183
2184         if (de_iir & DE_ERR_INT_IVB)
2185                 ivb_err_int_handler(dev_priv);
2186
2187         if (de_iir & DE_AUX_CHANNEL_A_IVB)
2188                 dp_aux_irq_handler(dev_priv);
2189
2190         if (de_iir & DE_GSE_IVB)
2191                 intel_opregion_asle_intr(dev_priv);
2192
2193         for_each_pipe(dev_priv, pipe) {
2194                 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2195                     intel_pipe_handle_vblank(dev_priv, pipe))
2196                         intel_check_page_flip(dev_priv, pipe);
2197
2198                 /* plane/pipes map 1:1 on ilk+ */
2199                 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe))
2200                         intel_finish_page_flip_cs(dev_priv, pipe);
2201         }
2202
2203         /* check event from PCH */
2204         if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2205                 u32 pch_iir = I915_READ(SDEIIR);
2206
2207                 cpt_irq_handler(dev_priv, pch_iir);
2208
2209                 /* clear PCH hotplug event before clear CPU irq */
2210                 I915_WRITE(SDEIIR, pch_iir);
2211         }
2212 }
2213
2214 /*
2215  * To handle irqs with the minimum potential races with fresh interrupts, we:
2216  * 1 - Disable Master Interrupt Control.
2217  * 2 - Find the source(s) of the interrupt.
2218  * 3 - Clear the Interrupt Identity bits (IIR).
2219  * 4 - Process the interrupt(s) that had bits set in the IIRs.
2220  * 5 - Re-enable Master Interrupt Control.
2221  */
2222 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2223 {
2224         struct drm_device *dev = arg;
2225         struct drm_i915_private *dev_priv = to_i915(dev);
2226         u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2227         irqreturn_t ret = IRQ_NONE;
2228
2229         if (!intel_irqs_enabled(dev_priv))
2230                 return IRQ_NONE;
2231
2232         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2233         disable_rpm_wakeref_asserts(dev_priv);
2234
2235         /* disable master interrupt before clearing iir  */
2236         de_ier = I915_READ(DEIER);
2237         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2238         POSTING_READ(DEIER);
2239
2240         /* Disable south interrupts. We'll only write to SDEIIR once, so further
2241          * interrupts will will be stored on its back queue, and then we'll be
2242          * able to process them after we restore SDEIER (as soon as we restore
2243          * it, we'll get an interrupt if SDEIIR still has something to process
2244          * due to its back queue). */
2245         if (!HAS_PCH_NOP(dev_priv)) {
2246                 sde_ier = I915_READ(SDEIER);
2247                 I915_WRITE(SDEIER, 0);
2248                 POSTING_READ(SDEIER);
2249         }
2250
2251         /* Find, clear, then process each source of interrupt */
2252
2253         gt_iir = I915_READ(GTIIR);
2254         if (gt_iir) {
2255                 I915_WRITE(GTIIR, gt_iir);
2256                 ret = IRQ_HANDLED;
2257                 if (INTEL_GEN(dev_priv) >= 6)
2258                         snb_gt_irq_handler(dev_priv, gt_iir);
2259                 else
2260                         ilk_gt_irq_handler(dev_priv, gt_iir);
2261         }
2262
2263         de_iir = I915_READ(DEIIR);
2264         if (de_iir) {
2265                 I915_WRITE(DEIIR, de_iir);
2266                 ret = IRQ_HANDLED;
2267                 if (INTEL_GEN(dev_priv) >= 7)
2268                         ivb_display_irq_handler(dev_priv, de_iir);
2269                 else
2270                         ilk_display_irq_handler(dev_priv, de_iir);
2271         }
2272
2273         if (INTEL_GEN(dev_priv) >= 6) {
2274                 u32 pm_iir = I915_READ(GEN6_PMIIR);
2275                 if (pm_iir) {
2276                         I915_WRITE(GEN6_PMIIR, pm_iir);
2277                         ret = IRQ_HANDLED;
2278                         gen6_rps_irq_handler(dev_priv, pm_iir);
2279                 }
2280         }
2281
2282         I915_WRITE(DEIER, de_ier);
2283         POSTING_READ(DEIER);
2284         if (!HAS_PCH_NOP(dev_priv)) {
2285                 I915_WRITE(SDEIER, sde_ier);
2286                 POSTING_READ(SDEIER);
2287         }
2288
2289         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2290         enable_rpm_wakeref_asserts(dev_priv);
2291
2292         return ret;
2293 }
2294
2295 static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2296                                 u32 hotplug_trigger,
2297                                 const u32 hpd[HPD_NUM_PINS])
2298 {
2299         u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2300
2301         dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2302         I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2303
2304         intel_get_hpd_pins(&pin_mask, &long_mask, hotplug_trigger,
2305                            dig_hotplug_reg, hpd,
2306                            bxt_port_hotplug_long_detect);
2307
2308         intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2309 }
2310
2311 static irqreturn_t
2312 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2313 {
2314         irqreturn_t ret = IRQ_NONE;
2315         u32 iir;
2316         enum pipe pipe;
2317
2318         if (master_ctl & GEN8_DE_MISC_IRQ) {
2319                 iir = I915_READ(GEN8_DE_MISC_IIR);
2320                 if (iir) {
2321                         I915_WRITE(GEN8_DE_MISC_IIR, iir);
2322                         ret = IRQ_HANDLED;
2323                         if (iir & GEN8_DE_MISC_GSE)
2324                                 intel_opregion_asle_intr(dev_priv);
2325                         else
2326                                 DRM_ERROR("Unexpected DE Misc interrupt\n");
2327                 }
2328                 else
2329                         DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2330         }
2331
2332         if (master_ctl & GEN8_DE_PORT_IRQ) {
2333                 iir = I915_READ(GEN8_DE_PORT_IIR);
2334                 if (iir) {
2335                         u32 tmp_mask;
2336                         bool found = false;
2337
2338                         I915_WRITE(GEN8_DE_PORT_IIR, iir);
2339                         ret = IRQ_HANDLED;
2340
2341                         tmp_mask = GEN8_AUX_CHANNEL_A;
2342                         if (INTEL_INFO(dev_priv)->gen >= 9)
2343                                 tmp_mask |= GEN9_AUX_CHANNEL_B |
2344                                             GEN9_AUX_CHANNEL_C |
2345                                             GEN9_AUX_CHANNEL_D;
2346
2347                         if (iir & tmp_mask) {
2348                                 dp_aux_irq_handler(dev_priv);
2349                                 found = true;
2350                         }
2351
2352                         if (IS_BROXTON(dev_priv)) {
2353                                 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2354                                 if (tmp_mask) {
2355                                         bxt_hpd_irq_handler(dev_priv, tmp_mask,
2356                                                             hpd_bxt);
2357                                         found = true;
2358                                 }
2359                         } else if (IS_BROADWELL(dev_priv)) {
2360                                 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2361                                 if (tmp_mask) {
2362                                         ilk_hpd_irq_handler(dev_priv,
2363                                                             tmp_mask, hpd_bdw);
2364                                         found = true;
2365                                 }
2366                         }
2367
2368                         if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2369                                 gmbus_irq_handler(dev_priv);
2370                                 found = true;
2371                         }
2372
2373                         if (!found)
2374                                 DRM_ERROR("Unexpected DE Port interrupt\n");
2375                 }
2376                 else
2377                         DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2378         }
2379
2380         for_each_pipe(dev_priv, pipe) {
2381                 u32 flip_done, fault_errors;
2382
2383                 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2384                         continue;
2385
2386                 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2387                 if (!iir) {
2388                         DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2389                         continue;
2390                 }
2391
2392                 ret = IRQ_HANDLED;
2393                 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2394
2395                 if (iir & GEN8_PIPE_VBLANK &&
2396                     intel_pipe_handle_vblank(dev_priv, pipe))
2397                         intel_check_page_flip(dev_priv, pipe);
2398
2399                 flip_done = iir;
2400                 if (INTEL_INFO(dev_priv)->gen >= 9)
2401                         flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
2402                 else
2403                         flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
2404
2405                 if (flip_done)
2406                         intel_finish_page_flip_cs(dev_priv, pipe);
2407
2408                 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2409                         hsw_pipe_crc_irq_handler(dev_priv, pipe);
2410
2411                 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2412                         intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2413
2414                 fault_errors = iir;
2415                 if (INTEL_INFO(dev_priv)->gen >= 9)
2416                         fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2417                 else
2418                         fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2419
2420                 if (fault_errors)
2421                         DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2422                                   pipe_name(pipe),
2423                                   fault_errors);
2424         }
2425
2426         if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2427             master_ctl & GEN8_DE_PCH_IRQ) {
2428                 /*
2429                  * FIXME(BDW): Assume for now that the new interrupt handling
2430                  * scheme also closed the SDE interrupt handling race we've seen
2431                  * on older pch-split platforms. But this needs testing.
2432                  */
2433                 iir = I915_READ(SDEIIR);
2434                 if (iir) {
2435                         I915_WRITE(SDEIIR, iir);
2436                         ret = IRQ_HANDLED;
2437
2438                         if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
2439                                 spt_irq_handler(dev_priv, iir);
2440                         else
2441                                 cpt_irq_handler(dev_priv, iir);
2442                 } else {
2443                         /*
2444                          * Like on previous PCH there seems to be something
2445                          * fishy going on with forwarding PCH interrupts.
2446                          */
2447                         DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2448                 }
2449         }
2450
2451         return ret;
2452 }
2453
2454 static irqreturn_t gen8_irq_handler(int irq, void *arg)
2455 {
2456         struct drm_device *dev = arg;
2457         struct drm_i915_private *dev_priv = to_i915(dev);
2458         u32 master_ctl;
2459         u32 gt_iir[4] = {};
2460         irqreturn_t ret;
2461
2462         if (!intel_irqs_enabled(dev_priv))
2463                 return IRQ_NONE;
2464
2465         master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
2466         master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2467         if (!master_ctl)
2468                 return IRQ_NONE;
2469
2470         I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
2471
2472         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2473         disable_rpm_wakeref_asserts(dev_priv);
2474
2475         /* Find, clear, then process each source of interrupt */
2476         ret = gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
2477         gen8_gt_irq_handler(dev_priv, gt_iir);
2478         ret |= gen8_de_irq_handler(dev_priv, master_ctl);
2479
2480         I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2481         POSTING_READ_FW(GEN8_MASTER_IRQ);
2482
2483         enable_rpm_wakeref_asserts(dev_priv);
2484
2485         return ret;
2486 }
2487
2488 static void i915_error_wake_up(struct drm_i915_private *dev_priv)
2489 {
2490         /*
2491          * Notify all waiters for GPU completion events that reset state has
2492          * been changed, and that they need to restart their wait after
2493          * checking for potential errors (and bail out to drop locks if there is
2494          * a gpu reset pending so that i915_error_work_func can acquire them).
2495          */
2496
2497         /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2498         wake_up_all(&dev_priv->gpu_error.wait_queue);
2499
2500         /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2501         wake_up_all(&dev_priv->pending_flip_queue);
2502 }
2503
2504 /**
2505  * i915_reset_and_wakeup - do process context error handling work
2506  * @dev_priv: i915 device private
2507  *
2508  * Fire an error uevent so userspace can see that a hang or error
2509  * was detected.
2510  */
2511 static void i915_reset_and_wakeup(struct drm_i915_private *dev_priv)
2512 {
2513         struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
2514         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2515         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2516         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
2517
2518         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
2519
2520         DRM_DEBUG_DRIVER("resetting chip\n");
2521         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
2522
2523         /*
2524          * In most cases it's guaranteed that we get here with an RPM
2525          * reference held, for example because there is a pending GPU
2526          * request that won't finish until the reset is done. This
2527          * isn't the case at least when we get here by doing a
2528          * simulated reset via debugs, so get an RPM reference.
2529          */
2530         intel_runtime_pm_get(dev_priv);
2531         intel_prepare_reset(dev_priv);
2532
2533         do {
2534                 /*
2535                  * All state reset _must_ be completed before we update the
2536                  * reset counter, for otherwise waiters might miss the reset
2537                  * pending state and not properly drop locks, resulting in
2538                  * deadlocks with the reset work.
2539                  */
2540                 if (mutex_trylock(&dev_priv->drm.struct_mutex)) {
2541                         i915_reset(dev_priv);
2542                         mutex_unlock(&dev_priv->drm.struct_mutex);
2543                 }
2544
2545                 /* We need to wait for anyone holding the lock to wakeup */
2546         } while (wait_on_bit_timeout(&dev_priv->gpu_error.flags,
2547                                      I915_RESET_IN_PROGRESS,
2548                                      TASK_UNINTERRUPTIBLE,
2549                                      HZ));
2550
2551         intel_finish_reset(dev_priv);
2552         intel_runtime_pm_put(dev_priv);
2553
2554         if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
2555                 kobject_uevent_env(kobj,
2556                                    KOBJ_CHANGE, reset_done_event);
2557
2558         /*
2559          * Note: The wake_up also serves as a memory barrier so that
2560          * waiters see the updated value of the dev_priv->gpu_error.
2561          */
2562         wake_up_all(&dev_priv->gpu_error.reset_queue);
2563 }
2564
2565 static void i915_report_and_clear_eir(struct drm_i915_private *dev_priv)
2566 {
2567         uint32_t instdone[I915_NUM_INSTDONE_REG];
2568         u32 eir = I915_READ(EIR);
2569         int pipe, i;
2570
2571         if (!eir)
2572                 return;
2573
2574         pr_err("render error detected, EIR: 0x%08x\n", eir);
2575
2576         i915_get_extra_instdone(dev_priv, instdone);
2577
2578         if (IS_G4X(dev_priv)) {
2579                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2580                         u32 ipeir = I915_READ(IPEIR_I965);
2581
2582                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2583                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2584                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
2585                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2586                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2587                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2588                         I915_WRITE(IPEIR_I965, ipeir);
2589                         POSTING_READ(IPEIR_I965);
2590                 }
2591                 if (eir & GM45_ERROR_PAGE_TABLE) {
2592                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2593                         pr_err("page table error\n");
2594                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2595                         I915_WRITE(PGTBL_ER, pgtbl_err);
2596                         POSTING_READ(PGTBL_ER);
2597                 }
2598         }
2599
2600         if (!IS_GEN2(dev_priv)) {
2601                 if (eir & I915_ERROR_PAGE_TABLE) {
2602                         u32 pgtbl_err = I915_READ(PGTBL_ER);
2603                         pr_err("page table error\n");
2604                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
2605                         I915_WRITE(PGTBL_ER, pgtbl_err);
2606                         POSTING_READ(PGTBL_ER);
2607                 }
2608         }
2609
2610         if (eir & I915_ERROR_MEMORY_REFRESH) {
2611                 pr_err("memory refresh error:\n");
2612                 for_each_pipe(dev_priv, pipe)
2613                         pr_err("pipe %c stat: 0x%08x\n",
2614                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
2615                 /* pipestat has already been acked */
2616         }
2617         if (eir & I915_ERROR_INSTRUCTION) {
2618                 pr_err("instruction error\n");
2619                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
2620                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2621                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
2622                 if (INTEL_GEN(dev_priv) < 4) {
2623                         u32 ipeir = I915_READ(IPEIR);
2624
2625                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
2626                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
2627                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
2628                         I915_WRITE(IPEIR, ipeir);
2629                         POSTING_READ(IPEIR);
2630                 } else {
2631                         u32 ipeir = I915_READ(IPEIR_I965);
2632
2633                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2634                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
2635                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
2636                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
2637                         I915_WRITE(IPEIR_I965, ipeir);
2638                         POSTING_READ(IPEIR_I965);
2639                 }
2640         }
2641
2642         I915_WRITE(EIR, eir);
2643         POSTING_READ(EIR);
2644         eir = I915_READ(EIR);
2645         if (eir) {
2646                 /*
2647                  * some errors might have become stuck,
2648                  * mask them.
2649                  */
2650                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2651                 I915_WRITE(EMR, I915_READ(EMR) | eir);
2652                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2653         }
2654 }
2655
2656 /**
2657  * i915_handle_error - handle a gpu error
2658  * @dev_priv: i915 device private
2659  * @engine_mask: mask representing engines that are hung
2660  * Do some basic checking of register state at error time and
2661  * dump it to the syslog.  Also call i915_capture_error_state() to make
2662  * sure we get a record and make it available in debugfs.  Fire a uevent
2663  * so userspace knows something bad happened (should trigger collection
2664  * of a ring dump etc.).
2665  * @fmt: Error message format string
2666  */
2667 void i915_handle_error(struct drm_i915_private *dev_priv,
2668                        u32 engine_mask,
2669                        const char *fmt, ...)
2670 {
2671         va_list args;
2672         char error_msg[80];
2673
2674         va_start(args, fmt);
2675         vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2676         va_end(args);
2677
2678         i915_capture_error_state(dev_priv, engine_mask, error_msg);
2679         i915_report_and_clear_eir(dev_priv);
2680
2681         if (!engine_mask)
2682                 return;
2683
2684         if (test_and_set_bit(I915_RESET_IN_PROGRESS,
2685                              &dev_priv->gpu_error.flags))
2686                 return;
2687
2688         /*
2689          * Wakeup waiting processes so that the reset function
2690          * i915_reset_and_wakeup doesn't deadlock trying to grab
2691          * various locks. By bumping the reset counter first, the woken
2692          * processes will see a reset in progress and back off,
2693          * releasing their locks and then wait for the reset completion.
2694          * We must do this for _all_ gpu waiters that might hold locks
2695          * that the reset work needs to acquire.
2696          *
2697          * Note: The wake_up also provides a memory barrier to ensure that the
2698          * waiters see the updated value of the reset flags.
2699          */
2700         i915_error_wake_up(dev_priv);
2701
2702         i915_reset_and_wakeup(dev_priv);
2703 }
2704
2705 /* Called from drm generic code, passed 'crtc' which
2706  * we use as a pipe index
2707  */
2708 static int i915_enable_vblank(struct drm_device *dev, unsigned int pipe)
2709 {
2710         struct drm_i915_private *dev_priv = to_i915(dev);
2711         unsigned long irqflags;
2712
2713         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2714         if (INTEL_INFO(dev)->gen >= 4)
2715                 i915_enable_pipestat(dev_priv, pipe,
2716                                      PIPE_START_VBLANK_INTERRUPT_STATUS);
2717         else
2718                 i915_enable_pipestat(dev_priv, pipe,
2719                                      PIPE_VBLANK_INTERRUPT_STATUS);
2720         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2721
2722         return 0;
2723 }
2724
2725 static int ironlake_enable_vblank(struct drm_device *dev, unsigned int pipe)
2726 {
2727         struct drm_i915_private *dev_priv = to_i915(dev);
2728         unsigned long irqflags;
2729         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2730                                                      DE_PIPE_VBLANK(pipe);
2731
2732         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2733         ilk_enable_display_irq(dev_priv, bit);
2734         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2735
2736         return 0;
2737 }
2738
2739 static int valleyview_enable_vblank(struct drm_device *dev, unsigned int pipe)
2740 {
2741         struct drm_i915_private *dev_priv = to_i915(dev);
2742         unsigned long irqflags;
2743
2744         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2745         i915_enable_pipestat(dev_priv, pipe,
2746                              PIPE_START_VBLANK_INTERRUPT_STATUS);
2747         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2748
2749         return 0;
2750 }
2751
2752 static int gen8_enable_vblank(struct drm_device *dev, unsigned int pipe)
2753 {
2754         struct drm_i915_private *dev_priv = to_i915(dev);
2755         unsigned long irqflags;
2756
2757         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2758         bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2759         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2760
2761         return 0;
2762 }
2763
2764 /* Called from drm generic code, passed 'crtc' which
2765  * we use as a pipe index
2766  */
2767 static void i915_disable_vblank(struct drm_device *dev, unsigned int pipe)
2768 {
2769         struct drm_i915_private *dev_priv = to_i915(dev);
2770         unsigned long irqflags;
2771
2772         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2773         i915_disable_pipestat(dev_priv, pipe,
2774                               PIPE_VBLANK_INTERRUPT_STATUS |
2775                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2776         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2777 }
2778
2779 static void ironlake_disable_vblank(struct drm_device *dev, unsigned int pipe)
2780 {
2781         struct drm_i915_private *dev_priv = to_i915(dev);
2782         unsigned long irqflags;
2783         uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
2784                                                      DE_PIPE_VBLANK(pipe);
2785
2786         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2787         ilk_disable_display_irq(dev_priv, bit);
2788         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2789 }
2790
2791 static void valleyview_disable_vblank(struct drm_device *dev, unsigned int pipe)
2792 {
2793         struct drm_i915_private *dev_priv = to_i915(dev);
2794         unsigned long irqflags;
2795
2796         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2797         i915_disable_pipestat(dev_priv, pipe,
2798                               PIPE_START_VBLANK_INTERRUPT_STATUS);
2799         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2800 }
2801
2802 static void gen8_disable_vblank(struct drm_device *dev, unsigned int pipe)
2803 {
2804         struct drm_i915_private *dev_priv = to_i915(dev);
2805         unsigned long irqflags;
2806
2807         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2808         bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2809         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2810 }
2811
2812 static bool
2813 ipehr_is_semaphore_wait(struct intel_engine_cs *engine, u32 ipehr)
2814 {
2815         if (INTEL_GEN(engine->i915) >= 8) {
2816                 return (ipehr >> 23) == 0x1c;
2817         } else {
2818                 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2819                 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2820                                  MI_SEMAPHORE_REGISTER);
2821         }
2822 }
2823
2824 static struct intel_engine_cs *
2825 semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
2826                                  u64 offset)
2827 {
2828         struct drm_i915_private *dev_priv = engine->i915;
2829         struct intel_engine_cs *signaller;
2830
2831         if (INTEL_GEN(dev_priv) >= 8) {
2832                 for_each_engine(signaller, dev_priv) {
2833                         if (engine == signaller)
2834                                 continue;
2835
2836                         if (offset == signaller->semaphore.signal_ggtt[engine->hw_id])
2837                                 return signaller;
2838                 }
2839         } else {
2840                 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2841
2842                 for_each_engine(signaller, dev_priv) {
2843                         if(engine == signaller)
2844                                 continue;
2845
2846                         if (sync_bits == signaller->semaphore.mbox.wait[engine->hw_id])
2847                                 return signaller;
2848                 }
2849         }
2850
2851         DRM_DEBUG_DRIVER("No signaller ring found for %s, ipehr 0x%08x, offset 0x%016llx\n",
2852                          engine->name, ipehr, offset);
2853
2854         return ERR_PTR(-ENODEV);
2855 }
2856
2857 static struct intel_engine_cs *
2858 semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
2859 {
2860         struct drm_i915_private *dev_priv = engine->i915;
2861         void __iomem *vaddr;
2862         u32 cmd, ipehr, head;
2863         u64 offset = 0;
2864         int i, backwards;
2865
2866         /*
2867          * This function does not support execlist mode - any attempt to
2868          * proceed further into this function will result in a kernel panic
2869          * when dereferencing ring->buffer, which is not set up in execlist
2870          * mode.
2871          *
2872          * The correct way of doing it would be to derive the currently
2873          * executing ring buffer from the current context, which is derived
2874          * from the currently running request. Unfortunately, to get the
2875          * current request we would have to grab the struct_mutex before doing
2876          * anything else, which would be ill-advised since some other thread
2877          * might have grabbed it already and managed to hang itself, causing
2878          * the hang checker to deadlock.
2879          *
2880          * Therefore, this function does not support execlist mode in its
2881          * current form. Just return NULL and move on.
2882          */
2883         if (engine->buffer == NULL)
2884                 return NULL;
2885
2886         ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
2887         if (!ipehr_is_semaphore_wait(engine, ipehr))
2888                 return NULL;
2889
2890         /*
2891          * HEAD is likely pointing to the dword after the actual command,
2892          * so scan backwards until we find the MBOX. But limit it to just 3
2893          * or 4 dwords depending on the semaphore wait command size.
2894          * Note that we don't care about ACTHD here since that might
2895          * point at at batch, and semaphores are always emitted into the
2896          * ringbuffer itself.
2897          */
2898         head = I915_READ_HEAD(engine) & HEAD_ADDR;
2899         backwards = (INTEL_GEN(dev_priv) >= 8) ? 5 : 4;
2900         vaddr = (void __iomem *)engine->buffer->vaddr;
2901
2902         for (i = backwards; i; --i) {
2903                 /*
2904                  * Be paranoid and presume the hw has gone off into the wild -
2905                  * our ring is smaller than what the hardware (and hence
2906                  * HEAD_ADDR) allows. Also handles wrap-around.
2907                  */
2908                 head &= engine->buffer->size - 1;
2909
2910                 /* This here seems to blow up */
2911                 cmd = ioread32(vaddr + head);
2912                 if (cmd == ipehr)
2913                         break;
2914
2915                 head -= 4;
2916         }
2917
2918         if (!i)
2919                 return NULL;
2920
2921         *seqno = ioread32(vaddr + head + 4) + 1;
2922         if (INTEL_GEN(dev_priv) >= 8) {
2923                 offset = ioread32(vaddr + head + 12);
2924                 offset <<= 32;
2925                 offset |= ioread32(vaddr + head + 8);
2926         }
2927         return semaphore_wait_to_signaller_ring(engine, ipehr, offset);
2928 }
2929
2930 static int semaphore_passed(struct intel_engine_cs *engine)
2931 {
2932         struct drm_i915_private *dev_priv = engine->i915;
2933         struct intel_engine_cs *signaller;
2934         u32 seqno;
2935
2936         engine->hangcheck.deadlock++;
2937
2938         signaller = semaphore_waits_for(engine, &seqno);
2939         if (signaller == NULL)
2940                 return -1;
2941
2942         if (IS_ERR(signaller))
2943                 return 0;
2944
2945         /* Prevent pathological recursion due to driver bugs */
2946         if (signaller->hangcheck.deadlock >= I915_NUM_ENGINES)
2947                 return -1;
2948
2949         if (i915_seqno_passed(intel_engine_get_seqno(signaller), seqno))
2950                 return 1;
2951
2952         /* cursory check for an unkickable deadlock */
2953         if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2954             semaphore_passed(signaller) < 0)
2955                 return -1;
2956
2957         return 0;
2958 }
2959
2960 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2961 {
2962         struct intel_engine_cs *engine;
2963
2964         for_each_engine(engine, dev_priv)
2965                 engine->hangcheck.deadlock = 0;
2966 }
2967
2968 static bool subunits_stuck(struct intel_engine_cs *engine)
2969 {
2970         u32 instdone[I915_NUM_INSTDONE_REG];
2971         bool stuck;
2972         int i;
2973
2974         if (engine->id != RCS)
2975                 return true;
2976
2977         i915_get_extra_instdone(engine->i915, instdone);
2978
2979         /* There might be unstable subunit states even when
2980          * actual head is not moving. Filter out the unstable ones by
2981          * accumulating the undone -> done transitions and only
2982          * consider those as progress.
2983          */
2984         stuck = true;
2985         for (i = 0; i < I915_NUM_INSTDONE_REG; i++) {
2986                 const u32 tmp = instdone[i] | engine->hangcheck.instdone[i];
2987
2988                 if (tmp != engine->hangcheck.instdone[i])
2989                         stuck = false;
2990
2991                 engine->hangcheck.instdone[i] |= tmp;
2992         }
2993
2994         return stuck;
2995 }
2996
2997 static enum intel_engine_hangcheck_action
2998 head_stuck(struct intel_engine_cs *engine, u64 acthd)
2999 {
3000         if (acthd != engine->hangcheck.acthd) {
3001
3002                 /* Clear subunit states on head movement */
3003                 memset(engine->hangcheck.instdone, 0,
3004                        sizeof(engine->hangcheck.instdone));
3005
3006                 return HANGCHECK_ACTIVE;
3007         }
3008
3009         if (!subunits_stuck(engine))
3010                 return HANGCHECK_ACTIVE;
3011
3012         return HANGCHECK_HUNG;
3013 }
3014
3015 static enum intel_engine_hangcheck_action
3016 engine_stuck(struct intel_engine_cs *engine, u64 acthd)
3017 {
3018         struct drm_i915_private *dev_priv = engine->i915;
3019         enum intel_engine_hangcheck_action ha;
3020         u32 tmp;
3021
3022         ha = head_stuck(engine, acthd);
3023         if (ha != HANGCHECK_HUNG)
3024                 return ha;
3025
3026         if (IS_GEN2(dev_priv))
3027                 return HANGCHECK_HUNG;
3028
3029         /* Is the chip hanging on a WAIT_FOR_EVENT?
3030          * If so we can simply poke the RB_WAIT bit
3031          * and break the hang. This should work on
3032          * all but the second generation chipsets.
3033          */
3034         tmp = I915_READ_CTL(engine);
3035         if (tmp & RING_WAIT) {
3036                 i915_handle_error(dev_priv, 0,
3037                                   "Kicking stuck wait on %s",
3038                                   engine->name);
3039                 I915_WRITE_CTL(engine, tmp);
3040                 return HANGCHECK_KICK;
3041         }
3042
3043         if (INTEL_GEN(dev_priv) >= 6 && tmp & RING_WAIT_SEMAPHORE) {
3044                 switch (semaphore_passed(engine)) {
3045                 default:
3046                         return HANGCHECK_HUNG;
3047                 case 1:
3048                         i915_handle_error(dev_priv, 0,
3049                                           "Kicking stuck semaphore on %s",
3050                                           engine->name);
3051                         I915_WRITE_CTL(engine, tmp);
3052                         return HANGCHECK_KICK;
3053                 case 0:
3054                         return HANGCHECK_WAIT;
3055                 }
3056         }
3057
3058         return HANGCHECK_HUNG;
3059 }
3060
3061 /*
3062  * This is called when the chip hasn't reported back with completed
3063  * batchbuffers in a long time. We keep track per ring seqno progress and
3064  * if there are no progress, hangcheck score for that ring is increased.
3065  * Further, acthd is inspected to see if the ring is stuck. On stuck case
3066  * we kick the ring. If we see no progress on three subsequent calls
3067  * we assume chip is wedged and try to fix it by resetting the chip.
3068  */
3069 static void i915_hangcheck_elapsed(struct work_struct *work)
3070 {
3071         struct drm_i915_private *dev_priv =
3072                 container_of(work, typeof(*dev_priv),
3073                              gpu_error.hangcheck_work.work);
3074         struct intel_engine_cs *engine;
3075         unsigned int hung = 0, stuck = 0;
3076         int busy_count = 0;
3077 #define BUSY 1
3078 #define KICK 5
3079 #define HUNG 20
3080 #define ACTIVE_DECAY 15
3081
3082         if (!i915.enable_hangcheck)
3083                 return;
3084
3085         if (!READ_ONCE(dev_priv->gt.awake))
3086                 return;
3087
3088         /* As enabling the GPU requires fairly extensive mmio access,
3089          * periodically arm the mmio checker to see if we are triggering
3090          * any invalid access.
3091          */
3092         intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
3093
3094         for_each_engine(engine, dev_priv) {
3095                 bool busy = intel_engine_has_waiter(engine);
3096                 u64 acthd;
3097                 u32 seqno;
3098                 u32 submit;
3099
3100                 semaphore_clear_deadlocks(dev_priv);
3101
3102                 /* We don't strictly need an irq-barrier here, as we are not
3103                  * serving an interrupt request, be paranoid in case the
3104                  * barrier has side-effects (such as preventing a broken
3105                  * cacheline snoop) and so be sure that we can see the seqno
3106                  * advance. If the seqno should stick, due to a stale
3107                  * cacheline, we would erroneously declare the GPU hung.
3108                  */
3109                 if (engine->irq_seqno_barrier)
3110                         engine->irq_seqno_barrier(engine);
3111
3112                 acthd = intel_engine_get_active_head(engine);
3113                 seqno = intel_engine_get_seqno(engine);
3114                 submit = READ_ONCE(engine->last_submitted_seqno);
3115
3116                 if (engine->hangcheck.seqno == seqno) {
3117                         if (i915_seqno_passed(seqno, submit)) {
3118                                 engine->hangcheck.action = HANGCHECK_IDLE;
3119                         } else {
3120                                 /* We always increment the hangcheck score
3121                                  * if the engine is busy and still processing
3122                                  * the same request, so that no single request
3123                                  * can run indefinitely (such as a chain of
3124                                  * batches). The only time we do not increment
3125                                  * the hangcheck score on this ring, if this
3126                                  * engine is in a legitimate wait for another
3127                                  * engine. In that case the waiting engine is a
3128                                  * victim and we want to be sure we catch the
3129                                  * right culprit. Then every time we do kick
3130                                  * the ring, add a small increment to the
3131                                  * score so that we can catch a batch that is
3132                                  * being repeatedly kicked and so responsible
3133                                  * for stalling the machine.
3134                                  */
3135                                 engine->hangcheck.action =
3136                                         engine_stuck(engine, acthd);
3137
3138                                 switch (engine->hangcheck.action) {
3139                                 case HANGCHECK_IDLE:
3140                                 case HANGCHECK_WAIT:
3141                                         break;
3142                                 case HANGCHECK_ACTIVE:
3143                                         engine->hangcheck.score += BUSY;
3144                                         break;
3145                                 case HANGCHECK_KICK:
3146                                         engine->hangcheck.score += KICK;
3147                                         break;
3148                                 case HANGCHECK_HUNG:
3149                                         engine->hangcheck.score += HUNG;
3150                                         break;
3151                                 }
3152                         }
3153
3154                         if (engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
3155                                 hung |= intel_engine_flag(engine);
3156                                 if (engine->hangcheck.action != HANGCHECK_HUNG)
3157                                         stuck |= intel_engine_flag(engine);
3158                         }
3159                 } else {
3160                         engine->hangcheck.action = HANGCHECK_ACTIVE;
3161
3162                         /* Gradually reduce the count so that we catch DoS
3163                          * attempts across multiple batches.
3164                          */
3165                         if (engine->hangcheck.score > 0)
3166                                 engine->hangcheck.score -= ACTIVE_DECAY;
3167                         if (engine->hangcheck.score < 0)
3168                                 engine->hangcheck.score = 0;
3169
3170                         /* Clear head and subunit states on seqno movement */
3171                         acthd = 0;
3172
3173                         memset(engine->hangcheck.instdone, 0,
3174                                sizeof(engine->hangcheck.instdone));
3175                 }
3176
3177                 engine->hangcheck.seqno = seqno;
3178                 engine->hangcheck.acthd = acthd;
3179                 busy_count += busy;
3180         }
3181
3182         if (hung) {
3183                 char msg[80];
3184                 unsigned int tmp;
3185                 int len;
3186
3187                 /* If some rings hung but others were still busy, only
3188                  * blame the hanging rings in the synopsis.
3189                  */
3190                 if (stuck != hung)
3191                         hung &= ~stuck;
3192                 len = scnprintf(msg, sizeof(msg),
3193                                 "%s on ", stuck == hung ? "No progress" : "Hang");
3194                 for_each_engine_masked(engine, dev_priv, hung, tmp)
3195                         len += scnprintf(msg + len, sizeof(msg) - len,
3196                                          "%s, ", engine->name);
3197                 msg[len-2] = '\0';
3198
3199                 return i915_handle_error(dev_priv, hung, msg);
3200         }
3201
3202         /* Reset timer in case GPU hangs without another request being added */
3203         if (busy_count)
3204                 i915_queue_hangcheck(dev_priv);
3205 }
3206
3207 static void ibx_irq_reset(struct drm_device *dev)
3208 {
3209         struct drm_i915_private *dev_priv = to_i915(dev);
3210
3211         if (HAS_PCH_NOP(dev))
3212                 return;
3213
3214         GEN5_IRQ_RESET(SDE);
3215
3216         if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3217                 I915_WRITE(SERR_INT, 0xffffffff);
3218 }
3219
3220 /*
3221  * SDEIER is also touched by the interrupt handler to work around missed PCH
3222  * interrupts. Hence we can't update it after the interrupt handler is enabled -
3223  * instead we unconditionally enable all PCH interrupt sources here, but then
3224  * only unmask them as needed with SDEIMR.
3225  *
3226  * This function needs to be called before interrupts are enabled.
3227  */
3228 static void ibx_irq_pre_postinstall(struct drm_device *dev)
3229 {
3230         struct drm_i915_private *dev_priv = to_i915(dev);
3231
3232         if (HAS_PCH_NOP(dev))
3233                 return;
3234
3235         WARN_ON(I915_READ(SDEIER) != 0);
3236         I915_WRITE(SDEIER, 0xffffffff);
3237         POSTING_READ(SDEIER);
3238 }
3239
3240 static void gen5_gt_irq_reset(struct drm_device *dev)
3241 {
3242         struct drm_i915_private *dev_priv = to_i915(dev);
3243
3244         GEN5_IRQ_RESET(GT);
3245         if (INTEL_INFO(dev)->gen >= 6)
3246                 GEN5_IRQ_RESET(GEN6_PM);
3247 }
3248
3249 static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3250 {
3251         enum pipe pipe;
3252
3253         if (IS_CHERRYVIEW(dev_priv))
3254                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3255         else
3256                 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3257
3258         i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3259         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3260
3261         for_each_pipe(dev_priv, pipe) {
3262                 I915_WRITE(PIPESTAT(pipe),
3263                            PIPE_FIFO_UNDERRUN_STATUS |
3264                            PIPESTAT_INT_STATUS_MASK);
3265                 dev_priv->pipestat_irq_mask[pipe] = 0;
3266         }
3267
3268         GEN5_IRQ_RESET(VLV_);
3269         dev_priv->irq_mask = ~0;
3270 }
3271
3272 static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3273 {
3274         u32 pipestat_mask;
3275         u32 enable_mask;
3276         enum pipe pipe;
3277
3278         pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3279                         PIPE_CRC_DONE_INTERRUPT_STATUS;
3280
3281         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3282         for_each_pipe(dev_priv, pipe)
3283                 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3284
3285         enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3286                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3287                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
3288         if (IS_CHERRYVIEW(dev_priv))
3289                 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
3290
3291         WARN_ON(dev_priv->irq_mask != ~0);
3292
3293         dev_priv->irq_mask = ~enable_mask;
3294
3295         GEN5_IRQ_INIT(VLV_, dev_priv->irq_mask, enable_mask);
3296 }
3297
3298 /* drm_dma.h hooks
3299 */
3300 static void ironlake_irq_reset(struct drm_device *dev)
3301 {
3302         struct drm_i915_private *dev_priv = to_i915(dev);
3303
3304         I915_WRITE(HWSTAM, 0xffffffff);
3305
3306         GEN5_IRQ_RESET(DE);
3307         if (IS_GEN7(dev))
3308                 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
3309
3310         gen5_gt_irq_reset(dev);
3311
3312         ibx_irq_reset(dev);
3313 }
3314
3315 static void valleyview_irq_preinstall(struct drm_device *dev)
3316 {
3317         struct drm_i915_private *dev_priv = to_i915(dev);
3318
3319         I915_WRITE(VLV_MASTER_IER, 0);
3320         POSTING_READ(VLV_MASTER_IER);
3321
3322         gen5_gt_irq_reset(dev);
3323
3324         spin_lock_irq(&dev_priv->irq_lock);
3325         if (dev_priv->display_irqs_enabled)
3326                 vlv_display_irq_reset(dev_priv);
3327         spin_unlock_irq(&dev_priv->irq_lock);
3328 }
3329
3330 static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3331 {
3332         GEN8_IRQ_RESET_NDX(GT, 0);
3333         GEN8_IRQ_RESET_NDX(GT, 1);
3334         GEN8_IRQ_RESET_NDX(GT, 2);
3335         GEN8_IRQ_RESET_NDX(GT, 3);
3336 }
3337
3338 static void gen8_irq_reset(struct drm_device *dev)
3339 {
3340         struct drm_i915_private *dev_priv = to_i915(dev);
3341         int pipe;
3342
3343         I915_WRITE(GEN8_MASTER_IRQ, 0);
3344         POSTING_READ(GEN8_MASTER_IRQ);
3345
3346         gen8_gt_irq_reset(dev_priv);
3347
3348         for_each_pipe(dev_priv, pipe)
3349                 if (intel_display_power_is_enabled(dev_priv,
3350                                                    POWER_DOMAIN_PIPE(pipe)))
3351                         GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3352
3353         GEN5_IRQ_RESET(GEN8_DE_PORT_);
3354         GEN5_IRQ_RESET(GEN8_DE_MISC_);
3355         GEN5_IRQ_RESET(GEN8_PCU_);
3356
3357         if (HAS_PCH_SPLIT(dev))
3358                 ibx_irq_reset(dev);
3359 }
3360
3361 void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3362                                      unsigned int pipe_mask)
3363 {
3364         uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3365         enum pipe pipe;
3366
3367         spin_lock_irq(&dev_priv->irq_lock);
3368         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3369                 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3370                                   dev_priv->de_irq_mask[pipe],
3371                                   ~dev_priv->de_irq_mask[pipe] | extra_ier);
3372         spin_unlock_irq(&dev_priv->irq_lock);
3373 }
3374
3375 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3376                                      unsigned int pipe_mask)
3377 {
3378         enum pipe pipe;
3379
3380         spin_lock_irq(&dev_priv->irq_lock);
3381         for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3382                 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
3383         spin_unlock_irq(&dev_priv->irq_lock);
3384
3385         /* make sure we're done processing display irqs */
3386         synchronize_irq(dev_priv->drm.irq);
3387 }
3388
3389 static void cherryview_irq_preinstall(struct drm_device *dev)
3390 {
3391         struct drm_i915_private *dev_priv = to_i915(dev);
3392
3393         I915_WRITE(GEN8_MASTER_IRQ, 0);
3394         POSTING_READ(GEN8_MASTER_IRQ);
3395
3396         gen8_gt_irq_reset(dev_priv);
3397
3398         GEN5_IRQ_RESET(GEN8_PCU_);
3399
3400         spin_lock_irq(&dev_priv->irq_lock);
3401         if (dev_priv->display_irqs_enabled)
3402                 vlv_display_irq_reset(dev_priv);
3403         spin_unlock_irq(&dev_priv->irq_lock);
3404 }
3405
3406 static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3407                                   const u32 hpd[HPD_NUM_PINS])
3408 {
3409         struct intel_encoder *encoder;
3410         u32 enabled_irqs = 0;
3411
3412         for_each_intel_encoder(&dev_priv->drm, encoder)
3413                 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3414                         enabled_irqs |= hpd[encoder->hpd_pin];
3415
3416         return enabled_irqs;
3417 }
3418
3419 static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3420 {
3421         u32 hotplug_irqs, hotplug, enabled_irqs;
3422
3423         if (HAS_PCH_IBX(dev_priv)) {
3424                 hotplug_irqs = SDE_HOTPLUG_MASK;
3425                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3426         } else {
3427                 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3428                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3429         }
3430
3431         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3432
3433         /*
3434          * Enable digital hotplug on the PCH, and configure the DP short pulse
3435          * duration to 2ms (which is the minimum in the Display Port spec).
3436          * The pulse duration bits are reserved on LPT+.
3437          */
3438         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3439         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3440         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3441         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3442         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3443         /*
3444          * When CPU and PCH are on the same package, port A
3445          * HPD must be enabled in both north and south.
3446          */
3447         if (HAS_PCH_LPT_LP(dev_priv))
3448                 hotplug |= PORTA_HOTPLUG_ENABLE;
3449         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3450 }
3451
3452 static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3453 {
3454         u32 hotplug_irqs, hotplug, enabled_irqs;
3455
3456         hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3457         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3458
3459         ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3460
3461         /* Enable digital hotplug on the PCH */
3462         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3463         hotplug |= PORTD_HOTPLUG_ENABLE | PORTC_HOTPLUG_ENABLE |
3464                 PORTB_HOTPLUG_ENABLE | PORTA_HOTPLUG_ENABLE;
3465         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3466
3467         hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3468         hotplug |= PORTE_HOTPLUG_ENABLE;
3469         I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3470 }
3471
3472 static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3473 {
3474         u32 hotplug_irqs, hotplug, enabled_irqs;
3475
3476         if (INTEL_GEN(dev_priv) >= 8) {
3477                 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3478                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3479
3480                 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3481         } else if (INTEL_GEN(dev_priv) >= 7) {
3482                 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3483                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3484
3485                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3486         } else {
3487                 hotplug_irqs = DE_DP_A_HOTPLUG;
3488                 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3489
3490                 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3491         }
3492
3493         /*
3494          * Enable digital hotplug on the CPU, and configure the DP short pulse
3495          * duration to 2ms (which is the minimum in the Display Port spec)
3496          * The pulse duration bits are reserved on HSW+.
3497          */
3498         hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3499         hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3500         hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE | DIGITAL_PORTA_PULSE_DURATION_2ms;
3501         I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3502
3503         ibx_hpd_irq_setup(dev_priv);
3504 }
3505
3506 static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3507 {
3508         u32 hotplug_irqs, hotplug, enabled_irqs;
3509
3510         enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3511         hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3512
3513         bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3514
3515         hotplug = I915_READ(PCH_PORT_HOTPLUG);
3516         hotplug |= PORTC_HOTPLUG_ENABLE | PORTB_HOTPLUG_ENABLE |
3517                 PORTA_HOTPLUG_ENABLE;
3518
3519         DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3520                       hotplug, enabled_irqs);
3521         hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3522
3523         /*
3524          * For BXT invert bit has to be set based on AOB design
3525          * for HPD detection logic, update it based on VBT fields.
3526          */
3527
3528         if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3529             intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3530                 hotplug |= BXT_DDIA_HPD_INVERT;
3531         if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3532             intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3533                 hotplug |= BXT_DDIB_HPD_INVERT;
3534         if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3535             intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3536                 hotplug |= BXT_DDIC_HPD_INVERT;
3537
3538         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3539 }
3540
3541 static void ibx_irq_postinstall(struct drm_device *dev)
3542 {
3543         struct drm_i915_private *dev_priv = to_i915(dev);
3544         u32 mask;
3545
3546         if (HAS_PCH_NOP(dev))
3547                 return;
3548
3549         if (HAS_PCH_IBX(dev))
3550                 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3551         else
3552                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3553
3554         gen5_assert_iir_is_zero(dev_priv, SDEIIR);
3555         I915_WRITE(SDEIMR, ~mask);
3556 }
3557
3558 static void gen5_gt_irq_postinstall(struct drm_device *dev)
3559 {
3560         struct drm_i915_private *dev_priv = to_i915(dev);
3561         u32 pm_irqs, gt_irqs;
3562
3563         pm_irqs = gt_irqs = 0;
3564
3565         dev_priv->gt_irq_mask = ~0;
3566         if (HAS_L3_DPF(dev)) {
3567                 /* L3 parity interrupt is always unmasked. */
3568                 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3569                 gt_irqs |= GT_PARITY_ERROR(dev);
3570         }
3571
3572         gt_irqs |= GT_RENDER_USER_INTERRUPT;
3573         if (IS_GEN5(dev)) {
3574                 gt_irqs |= ILK_BSD_USER_INTERRUPT;
3575         } else {
3576                 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3577         }
3578
3579         GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
3580
3581         if (INTEL_INFO(dev)->gen >= 6) {
3582                 /*
3583                  * RPS interrupts will get enabled/disabled on demand when RPS
3584                  * itself is enabled/disabled.
3585                  */
3586                 if (HAS_VEBOX(dev))
3587                         pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3588
3589                 dev_priv->pm_irq_mask = 0xffffffff;
3590                 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
3591         }
3592 }
3593
3594 static int ironlake_irq_postinstall(struct drm_device *dev)
3595 {
3596         struct drm_i915_private *dev_priv = to_i915(dev);
3597         u32 display_mask, extra_mask;
3598
3599         if (INTEL_INFO(dev)->gen >= 7) {
3600                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3601                                 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3602                                 DE_PLANEB_FLIP_DONE_IVB |
3603                                 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
3604                 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3605                               DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3606                               DE_DP_A_HOTPLUG_IVB);
3607         } else {
3608                 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3609                                 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
3610                                 DE_AUX_CHANNEL_A |
3611                                 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3612                                 DE_POISON);
3613                 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3614                               DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3615                               DE_DP_A_HOTPLUG);
3616         }
3617
3618         dev_priv->irq_mask = ~display_mask;
3619
3620         I915_WRITE(HWSTAM, 0xeffe);
3621
3622         ibx_irq_pre_postinstall(dev);
3623
3624         GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
3625
3626         gen5_gt_irq_postinstall(dev);
3627
3628         ibx_irq_postinstall(dev);
3629
3630         if (IS_IRONLAKE_M(dev)) {
3631                 /* Enable PCU event interrupts
3632                  *
3633                  * spinlocking not required here for correctness since interrupt
3634                  * setup is guaranteed to run in single-threaded context. But we
3635                  * need it to make the assert_spin_locked happy. */
3636                 spin_lock_irq(&dev_priv->irq_lock);
3637                 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3638                 spin_unlock_irq(&dev_priv->irq_lock);
3639         }
3640
3641         return 0;
3642 }
3643
3644 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3645 {
3646         assert_spin_locked(&dev_priv->irq_lock);
3647
3648         if (dev_priv->display_irqs_enabled)
3649                 return;
3650
3651         dev_priv->display_irqs_enabled = true;
3652
3653         if (intel_irqs_enabled(dev_priv)) {
3654                 vlv_display_irq_reset(dev_priv);
3655                 vlv_display_irq_postinstall(dev_priv);
3656         }
3657 }
3658
3659 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3660 {
3661         assert_spin_locked(&dev_priv->irq_lock);
3662
3663         if (!dev_priv->display_irqs_enabled)
3664                 return;
3665
3666         dev_priv->display_irqs_enabled = false;
3667
3668         if (intel_irqs_enabled(dev_priv))
3669                 vlv_display_irq_reset(dev_priv);
3670 }
3671
3672
3673 static int valleyview_irq_postinstall(struct drm_device *dev)
3674 {
3675         struct drm_i915_private *dev_priv = to_i915(dev);
3676
3677         gen5_gt_irq_postinstall(dev);
3678
3679         spin_lock_irq(&dev_priv->irq_lock);
3680         if (dev_priv->display_irqs_enabled)
3681                 vlv_display_irq_postinstall(dev_priv);
3682         spin_unlock_irq(&dev_priv->irq_lock);
3683
3684         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3685         POSTING_READ(VLV_MASTER_IER);
3686
3687         return 0;
3688 }
3689
3690 static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3691 {
3692         /* These are interrupts we'll toggle with the ring mask register */
3693         uint32_t gt_interrupts[] = {
3694                 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3695                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
3696                         GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3697                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
3698                 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3699                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3700                         GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3701                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
3702                 0,
3703                 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3704                         GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
3705                 };
3706
3707         if (HAS_L3_DPF(dev_priv))
3708                 gt_interrupts[0] |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
3709
3710         dev_priv->pm_irq_mask = 0xffffffff;
3711         GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3712         GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
3713         /*
3714          * RPS interrupts will get enabled/disabled on demand when RPS itself
3715          * is enabled/disabled.
3716          */
3717         GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
3718         GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
3719 }
3720
3721 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3722 {
3723         uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3724         uint32_t de_pipe_enables;
3725         u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3726         u32 de_port_enables;
3727         u32 de_misc_masked = GEN8_DE_MISC_GSE;
3728         enum pipe pipe;
3729
3730         if (INTEL_INFO(dev_priv)->gen >= 9) {
3731                 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3732                                   GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3733                 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3734                                   GEN9_AUX_CHANNEL_D;
3735                 if (IS_BROXTON(dev_priv))
3736                         de_port_masked |= BXT_DE_PORT_GMBUS;
3737         } else {
3738                 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3739                                   GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3740         }
3741
3742         de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3743                                            GEN8_PIPE_FIFO_UNDERRUN;
3744
3745         de_port_enables = de_port_masked;
3746         if (IS_BROXTON(dev_priv))
3747                 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3748         else if (IS_BROADWELL(dev_priv))
3749                 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3750
3751         dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3752         dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3753         dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
3754
3755         for_each_pipe(dev_priv, pipe)
3756                 if (intel_display_power_is_enabled(dev_priv,
3757                                 POWER_DOMAIN_PIPE(pipe)))
3758                         GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3759                                           dev_priv->de_irq_mask[pipe],
3760                                           de_pipe_enables);
3761
3762         GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3763         GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3764 }
3765
3766 static int gen8_irq_postinstall(struct drm_device *dev)
3767 {
3768         struct drm_i915_private *dev_priv = to_i915(dev);
3769
3770         if (HAS_PCH_SPLIT(dev))
3771                 ibx_irq_pre_postinstall(dev);
3772
3773         gen8_gt_irq_postinstall(dev_priv);
3774         gen8_de_irq_postinstall(dev_priv);
3775
3776         if (HAS_PCH_SPLIT(dev))
3777                 ibx_irq_postinstall(dev);
3778
3779         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3780         POSTING_READ(GEN8_MASTER_IRQ);
3781
3782         return 0;
3783 }
3784
3785 static int cherryview_irq_postinstall(struct drm_device *dev)
3786 {
3787         struct drm_i915_private *dev_priv = to_i915(dev);
3788
3789         gen8_gt_irq_postinstall(dev_priv);
3790
3791         spin_lock_irq(&dev_priv->irq_lock);
3792         if (dev_priv->display_irqs_enabled)
3793                 vlv_display_irq_postinstall(dev_priv);
3794         spin_unlock_irq(&dev_priv->irq_lock);
3795
3796         I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3797         POSTING_READ(GEN8_MASTER_IRQ);
3798
3799         return 0;
3800 }
3801
3802 static void gen8_irq_uninstall(struct drm_device *dev)
3803 {
3804         struct drm_i915_private *dev_priv = to_i915(dev);
3805
3806         if (!dev_priv)
3807                 return;
3808
3809         gen8_irq_reset(dev);
3810 }
3811
3812 static void valleyview_irq_uninstall(struct drm_device *dev)
3813 {
3814         struct drm_i915_private *dev_priv = to_i915(dev);
3815
3816         if (!dev_priv)
3817                 return;
3818
3819         I915_WRITE(VLV_MASTER_IER, 0);
3820         POSTING_READ(VLV_MASTER_IER);
3821
3822         gen5_gt_irq_reset(dev);
3823
3824         I915_WRITE(HWSTAM, 0xffffffff);
3825
3826         spin_lock_irq(&dev_priv->irq_lock);
3827         if (dev_priv->display_irqs_enabled)
3828                 vlv_display_irq_reset(dev_priv);
3829         spin_unlock_irq(&dev_priv->irq_lock);
3830 }
3831
3832 static void cherryview_irq_uninstall(struct drm_device *dev)
3833 {
3834         struct drm_i915_private *dev_priv = to_i915(dev);
3835
3836         if (!dev_priv)
3837                 return;
3838
3839         I915_WRITE(GEN8_MASTER_IRQ, 0);
3840         POSTING_READ(GEN8_MASTER_IRQ);
3841
3842         gen8_gt_irq_reset(dev_priv);
3843
3844         GEN5_IRQ_RESET(GEN8_PCU_);
3845
3846         spin_lock_irq(&dev_priv->irq_lock);
3847         if (dev_priv->display_irqs_enabled)
3848                 vlv_display_irq_reset(dev_priv);
3849         spin_unlock_irq(&dev_priv->irq_lock);
3850 }
3851
3852 static void ironlake_irq_uninstall(struct drm_device *dev)
3853 {
3854         struct drm_i915_private *dev_priv = to_i915(dev);
3855
3856         if (!dev_priv)
3857                 return;
3858
3859         ironlake_irq_reset(dev);
3860 }
3861
3862 static void i8xx_irq_preinstall(struct drm_device * dev)
3863 {
3864         struct drm_i915_private *dev_priv = to_i915(dev);
3865         int pipe;
3866
3867         for_each_pipe(dev_priv, pipe)
3868                 I915_WRITE(PIPESTAT(pipe), 0);
3869         I915_WRITE16(IMR, 0xffff);
3870         I915_WRITE16(IER, 0x0);
3871         POSTING_READ16(IER);
3872 }
3873
3874 static int i8xx_irq_postinstall(struct drm_device *dev)
3875 {
3876         struct drm_i915_private *dev_priv = to_i915(dev);
3877
3878         I915_WRITE16(EMR,
3879                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3880
3881         /* Unmask the interrupts that we always want on. */
3882         dev_priv->irq_mask =
3883                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3884                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3885                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3886                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
3887         I915_WRITE16(IMR, dev_priv->irq_mask);
3888
3889         I915_WRITE16(IER,
3890                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3891                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3892                      I915_USER_INTERRUPT);
3893         POSTING_READ16(IER);
3894
3895         /* Interrupt setup is already guaranteed to be single-threaded, this is
3896          * just to make the assert_spin_locked check happy. */
3897         spin_lock_irq(&dev_priv->irq_lock);
3898         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3899         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3900         spin_unlock_irq(&dev_priv->irq_lock);
3901
3902         return 0;
3903 }
3904
3905 /*
3906  * Returns true when a page flip has completed.
3907  */
3908 static bool i8xx_handle_vblank(struct drm_i915_private *dev_priv,
3909                                int plane, int pipe, u32 iir)
3910 {
3911         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3912
3913         if (!intel_pipe_handle_vblank(dev_priv, pipe))
3914                 return false;
3915
3916         if ((iir & flip_pending) == 0)
3917                 goto check_page_flip;
3918
3919         /* We detect FlipDone by looking for the change in PendingFlip from '1'
3920          * to '0' on the following vblank, i.e. IIR has the Pendingflip
3921          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3922          * the flip is completed (no longer pending). Since this doesn't raise
3923          * an interrupt per se, we watch for the change at vblank.
3924          */
3925         if (I915_READ16(ISR) & flip_pending)
3926                 goto check_page_flip;
3927
3928         intel_finish_page_flip_cs(dev_priv, pipe);
3929         return true;
3930
3931 check_page_flip:
3932         intel_check_page_flip(dev_priv, pipe);
3933         return false;
3934 }
3935
3936 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3937 {
3938         struct drm_device *dev = arg;
3939         struct drm_i915_private *dev_priv = to_i915(dev);
3940         u16 iir, new_iir;
3941         u32 pipe_stats[2];
3942         int pipe;
3943         u16 flip_mask =
3944                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3945                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3946         irqreturn_t ret;
3947
3948         if (!intel_irqs_enabled(dev_priv))
3949                 return IRQ_NONE;
3950
3951         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3952         disable_rpm_wakeref_asserts(dev_priv);
3953
3954         ret = IRQ_NONE;
3955         iir = I915_READ16(IIR);
3956         if (iir == 0)
3957                 goto out;
3958
3959         while (iir & ~flip_mask) {
3960                 /* Can't rely on pipestat interrupt bit in iir as it might
3961                  * have been cleared after the pipestat interrupt was received.
3962                  * It doesn't set the bit in iir again, but it still produces
3963                  * interrupts (for non-MSI).
3964                  */
3965                 spin_lock(&dev_priv->irq_lock);
3966                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
3967                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
3968
3969                 for_each_pipe(dev_priv, pipe) {
3970                         i915_reg_t reg = PIPESTAT(pipe);
3971                         pipe_stats[pipe] = I915_READ(reg);
3972
3973                         /*
3974                          * Clear the PIPE*STAT regs before the IIR
3975                          */
3976                         if (pipe_stats[pipe] & 0x8000ffff)
3977                                 I915_WRITE(reg, pipe_stats[pipe]);
3978                 }
3979                 spin_unlock(&dev_priv->irq_lock);
3980
3981                 I915_WRITE16(IIR, iir & ~flip_mask);
3982                 new_iir = I915_READ16(IIR); /* Flush posted writes */
3983
3984                 if (iir & I915_USER_INTERRUPT)
3985                         notify_ring(&dev_priv->engine[RCS]);
3986
3987                 for_each_pipe(dev_priv, pipe) {
3988                         int plane = pipe;
3989                         if (HAS_FBC(dev_priv))
3990                                 plane = !plane;
3991
3992                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3993                             i8xx_handle_vblank(dev_priv, plane, pipe, iir))
3994                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
3995
3996                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
3997                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
3998
3999                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4000                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4001                                                                     pipe);
4002                 }
4003
4004                 iir = new_iir;
4005         }
4006         ret = IRQ_HANDLED;
4007
4008 out:
4009         enable_rpm_wakeref_asserts(dev_priv);
4010
4011         return ret;
4012 }
4013
4014 static void i8xx_irq_uninstall(struct drm_device * dev)
4015 {
4016         struct drm_i915_private *dev_priv = to_i915(dev);
4017         int pipe;
4018
4019         for_each_pipe(dev_priv, pipe) {
4020                 /* Clear enable bits; then clear status bits */
4021                 I915_WRITE(PIPESTAT(pipe), 0);
4022                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4023         }
4024         I915_WRITE16(IMR, 0xffff);
4025         I915_WRITE16(IER, 0x0);
4026         I915_WRITE16(IIR, I915_READ16(IIR));
4027 }
4028
4029 static void i915_irq_preinstall(struct drm_device * dev)
4030 {
4031         struct drm_i915_private *dev_priv = to_i915(dev);
4032         int pipe;
4033
4034         if (I915_HAS_HOTPLUG(dev)) {
4035                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4036                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4037         }
4038
4039         I915_WRITE16(HWSTAM, 0xeffe);
4040         for_each_pipe(dev_priv, pipe)
4041                 I915_WRITE(PIPESTAT(pipe), 0);
4042         I915_WRITE(IMR, 0xffffffff);
4043         I915_WRITE(IER, 0x0);
4044         POSTING_READ(IER);
4045 }
4046
4047 static int i915_irq_postinstall(struct drm_device *dev)
4048 {
4049         struct drm_i915_private *dev_priv = to_i915(dev);
4050         u32 enable_mask;
4051
4052         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
4053
4054         /* Unmask the interrupts that we always want on. */
4055         dev_priv->irq_mask =
4056                 ~(I915_ASLE_INTERRUPT |
4057                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4058                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4059                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4060                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4061
4062         enable_mask =
4063                 I915_ASLE_INTERRUPT |
4064                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4065                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4066                 I915_USER_INTERRUPT;
4067
4068         if (I915_HAS_HOTPLUG(dev)) {
4069                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4070                 POSTING_READ(PORT_HOTPLUG_EN);
4071
4072                 /* Enable in IER... */
4073                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4074                 /* and unmask in IMR */
4075                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4076         }
4077
4078         I915_WRITE(IMR, dev_priv->irq_mask);
4079         I915_WRITE(IER, enable_mask);
4080         POSTING_READ(IER);
4081
4082         i915_enable_asle_pipestat(dev_priv);
4083
4084         /* Interrupt setup is already guaranteed to be single-threaded, this is
4085          * just to make the assert_spin_locked check happy. */
4086         spin_lock_irq(&dev_priv->irq_lock);
4087         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4088         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4089         spin_unlock_irq(&dev_priv->irq_lock);
4090
4091         return 0;
4092 }
4093
4094 /*
4095  * Returns true when a page flip has completed.
4096  */
4097 static bool i915_handle_vblank(struct drm_i915_private *dev_priv,
4098                                int plane, int pipe, u32 iir)
4099 {
4100         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
4101
4102         if (!intel_pipe_handle_vblank(dev_priv, pipe))
4103                 return false;
4104
4105         if ((iir & flip_pending) == 0)
4106                 goto check_page_flip;
4107
4108         /* We detect FlipDone by looking for the change in PendingFlip from '1'
4109          * to '0' on the following vblank, i.e. IIR has the Pendingflip
4110          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
4111          * the flip is completed (no longer pending). Since this doesn't raise
4112          * an interrupt per se, we watch for the change at vblank.
4113          */
4114         if (I915_READ(ISR) & flip_pending)
4115                 goto check_page_flip;
4116
4117         intel_finish_page_flip_cs(dev_priv, pipe);
4118         return true;
4119
4120 check_page_flip:
4121         intel_check_page_flip(dev_priv, pipe);
4122         return false;
4123 }
4124
4125 static irqreturn_t i915_irq_handler(int irq, void *arg)
4126 {
4127         struct drm_device *dev = arg;
4128         struct drm_i915_private *dev_priv = to_i915(dev);
4129         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
4130         u32 flip_mask =
4131                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4132                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4133         int pipe, ret = IRQ_NONE;
4134
4135         if (!intel_irqs_enabled(dev_priv))
4136                 return IRQ_NONE;
4137
4138         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4139         disable_rpm_wakeref_asserts(dev_priv);
4140
4141         iir = I915_READ(IIR);
4142         do {
4143                 bool irq_received = (iir & ~flip_mask) != 0;
4144                 bool blc_event = false;
4145
4146                 /* Can't rely on pipestat interrupt bit in iir as it might
4147                  * have been cleared after the pipestat interrupt was received.
4148                  * It doesn't set the bit in iir again, but it still produces
4149                  * interrupts (for non-MSI).
4150                  */
4151                 spin_lock(&dev_priv->irq_lock);
4152                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4153                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4154
4155                 for_each_pipe(dev_priv, pipe) {
4156                         i915_reg_t reg = PIPESTAT(pipe);
4157                         pipe_stats[pipe] = I915_READ(reg);
4158
4159                         /* Clear the PIPE*STAT regs before the IIR */
4160                         if (pipe_stats[pipe] & 0x8000ffff) {
4161                                 I915_WRITE(reg, pipe_stats[pipe]);
4162                                 irq_received = true;
4163                         }
4164                 }
4165                 spin_unlock(&dev_priv->irq_lock);
4166
4167                 if (!irq_received)
4168                         break;
4169
4170                 /* Consume port.  Then clear IIR or we'll miss events */
4171                 if (I915_HAS_HOTPLUG(dev_priv) &&
4172                     iir & I915_DISPLAY_PORT_INTERRUPT) {
4173                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4174                         if (hotplug_status)
4175                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4176                 }
4177
4178                 I915_WRITE(IIR, iir & ~flip_mask);
4179                 new_iir = I915_READ(IIR); /* Flush posted writes */
4180
4181                 if (iir & I915_USER_INTERRUPT)
4182                         notify_ring(&dev_priv->engine[RCS]);
4183
4184                 for_each_pipe(dev_priv, pipe) {
4185                         int plane = pipe;
4186                         if (HAS_FBC(dev_priv))
4187                                 plane = !plane;
4188
4189                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
4190                             i915_handle_vblank(dev_priv, plane, pipe, iir))
4191                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
4192
4193                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4194                                 blc_event = true;
4195
4196                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4197                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4198
4199                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4200                                 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4201                                                                     pipe);
4202                 }
4203
4204                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4205                         intel_opregion_asle_intr(dev_priv);
4206
4207                 /* With MSI, interrupts are only generated when iir
4208                  * transitions from zero to nonzero.  If another bit got
4209                  * set while we were handling the existing iir bits, then
4210                  * we would never get another interrupt.
4211                  *
4212                  * This is fine on non-MSI as well, as if we hit this path
4213                  * we avoid exiting the interrupt handler only to generate
4214                  * another one.
4215                  *
4216                  * Note that for MSI this could cause a stray interrupt report
4217                  * if an interrupt landed in the time between writing IIR and
4218                  * the posting read.  This should be rare enough to never
4219                  * trigger the 99% of 100,000 interrupts test for disabling
4220                  * stray interrupts.
4221                  */
4222                 ret = IRQ_HANDLED;
4223                 iir = new_iir;
4224         } while (iir & ~flip_mask);
4225
4226         enable_rpm_wakeref_asserts(dev_priv);
4227
4228         return ret;
4229 }
4230
4231 static void i915_irq_uninstall(struct drm_device * dev)
4232 {
4233         struct drm_i915_private *dev_priv = to_i915(dev);
4234         int pipe;
4235
4236         if (I915_HAS_HOTPLUG(dev)) {
4237                 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4238                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4239         }
4240
4241         I915_WRITE16(HWSTAM, 0xffff);
4242         for_each_pipe(dev_priv, pipe) {
4243                 /* Clear enable bits; then clear status bits */
4244                 I915_WRITE(PIPESTAT(pipe), 0);
4245                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4246         }
4247         I915_WRITE(IMR, 0xffffffff);
4248         I915_WRITE(IER, 0x0);
4249
4250         I915_WRITE(IIR, I915_READ(IIR));
4251 }
4252
4253 static void i965_irq_preinstall(struct drm_device * dev)
4254 {
4255         struct drm_i915_private *dev_priv = to_i915(dev);
4256         int pipe;
4257
4258         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4259         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4260
4261         I915_WRITE(HWSTAM, 0xeffe);
4262         for_each_pipe(dev_priv, pipe)
4263                 I915_WRITE(PIPESTAT(pipe), 0);
4264         I915_WRITE(IMR, 0xffffffff);
4265         I915_WRITE(IER, 0x0);
4266         POSTING_READ(IER);
4267 }
4268
4269 static int i965_irq_postinstall(struct drm_device *dev)
4270 {
4271         struct drm_i915_private *dev_priv = to_i915(dev);
4272         u32 enable_mask;
4273         u32 error_mask;
4274
4275         /* Unmask the interrupts that we always want on. */
4276         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
4277                                I915_DISPLAY_PORT_INTERRUPT |
4278                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4279                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4280                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4281                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4282                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4283
4284         enable_mask = ~dev_priv->irq_mask;
4285         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4286                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
4287         enable_mask |= I915_USER_INTERRUPT;
4288
4289         if (IS_G4X(dev_priv))
4290                 enable_mask |= I915_BSD_USER_INTERRUPT;
4291
4292         /* Interrupt setup is already guaranteed to be single-threaded, this is
4293          * just to make the assert_spin_locked check happy. */
4294         spin_lock_irq(&dev_priv->irq_lock);
4295         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4296         i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4297         i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4298         spin_unlock_irq(&dev_priv->irq_lock);
4299
4300         /*
4301          * Enable some error detection, note the instruction error mask
4302          * bit is reserved, so we leave it masked.
4303          */
4304         if (IS_G4X(dev_priv)) {
4305                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4306                                GM45_ERROR_MEM_PRIV |
4307                                GM45_ERROR_CP_PRIV |
4308                                I915_ERROR_MEMORY_REFRESH);
4309         } else {
4310                 error_mask = ~(I915_ERROR_PAGE_TABLE |
4311                                I915_ERROR_MEMORY_REFRESH);
4312         }
4313         I915_WRITE(EMR, error_mask);
4314
4315         I915_WRITE(IMR, dev_priv->irq_mask);
4316         I915_WRITE(IER, enable_mask);
4317         POSTING_READ(IER);
4318
4319         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4320         POSTING_READ(PORT_HOTPLUG_EN);
4321
4322         i915_enable_asle_pipestat(dev_priv);
4323
4324         return 0;
4325 }
4326
4327 static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4328 {
4329         u32 hotplug_en;
4330
4331         assert_spin_locked(&dev_priv->irq_lock);
4332
4333         /* Note HDMI and DP share hotplug bits */
4334         /* enable bits are the same for all generations */
4335         hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4336         /* Programming the CRT detection parameters tends
4337            to generate a spurious hotplug event about three
4338            seconds later.  So just do it once.
4339         */
4340         if (IS_G4X(dev_priv))
4341                 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4342         hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4343
4344         /* Ignore TV since it's buggy */
4345         i915_hotplug_interrupt_update_locked(dev_priv,
4346                                              HOTPLUG_INT_EN_MASK |
4347                                              CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4348                                              CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4349                                              hotplug_en);
4350 }
4351
4352 static irqreturn_t i965_irq_handler(int irq, void *arg)
4353 {
4354         struct drm_device *dev = arg;
4355         struct drm_i915_private *dev_priv = to_i915(dev);
4356         u32 iir, new_iir;
4357         u32 pipe_stats[I915_MAX_PIPES];
4358         int ret = IRQ_NONE, pipe;
4359         u32 flip_mask =
4360                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4361                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4362
4363         if (!intel_irqs_enabled(dev_priv))
4364                 return IRQ_NONE;
4365
4366         /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4367         disable_rpm_wakeref_asserts(dev_priv);
4368
4369         iir = I915_READ(IIR);
4370
4371         for (;;) {
4372                 bool irq_received = (iir & ~flip_mask) != 0;
4373                 bool blc_event = false;
4374
4375                 /* Can't rely on pipestat interrupt bit in iir as it might
4376                  * have been cleared after the pipestat interrupt was received.
4377                  * It doesn't set the bit in iir again, but it still produces
4378                  * interrupts (for non-MSI).
4379                  */
4380                 spin_lock(&dev_priv->irq_lock);
4381                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
4382                         DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
4383
4384                 for_each_pipe(dev_priv, pipe) {
4385                         i915_reg_t reg = PIPESTAT(pipe);
4386                         pipe_stats[pipe] = I915_READ(reg);
4387
4388                         /*
4389                          * Clear the PIPE*STAT regs before the IIR
4390                          */
4391                         if (pipe_stats[pipe] & 0x8000ffff) {
4392                                 I915_WRITE(reg, pipe_stats[pipe]);
4393                                 irq_received = true;
4394                         }
4395                 }
4396                 spin_unlock(&dev_priv->irq_lock);
4397
4398                 if (!irq_received)
4399                         break;
4400
4401                 ret = IRQ_HANDLED;
4402
4403                 /* Consume port.  Then clear IIR or we'll miss events */
4404                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
4405                         u32 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4406                         if (hotplug_status)
4407                                 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4408                 }
4409
4410                 I915_WRITE(IIR, iir & ~flip_mask);
4411                 new_iir = I915_READ(IIR); /* Flush posted writes */
4412
4413                 if (iir & I915_USER_INTERRUPT)
4414                         notify_ring(&dev_priv->engine[RCS]);
4415                 if (iir & I915_BSD_USER_INTERRUPT)
4416                         notify_ring(&dev_priv->engine[VCS]);
4417
4418                 for_each_pipe(dev_priv, pipe) {
4419                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
4420                             i915_handle_vblank(dev_priv, pipe, pipe, iir))
4421                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
4422
4423                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4424                                 blc_event = true;
4425
4426                         if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
4427                                 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
4428
4429                         if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4430                                 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
4431                 }
4432
4433                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4434                         intel_opregion_asle_intr(dev_priv);
4435
4436                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4437                         gmbus_irq_handler(dev_priv);
4438
4439                 /* With MSI, interrupts are only generated when iir
4440                  * transitions from zero to nonzero.  If another bit got
4441                  * set while we were handling the existing iir bits, then
4442                  * we would never get another interrupt.
4443                  *
4444                  * This is fine on non-MSI as well, as if we hit this path
4445                  * we avoid exiting the interrupt handler only to generate
4446                  * another one.
4447                  *
4448                  * Note that for MSI this could cause a stray interrupt report
4449                  * if an interrupt landed in the time between writing IIR and
4450                  * the posting read.  This should be rare enough to never
4451                  * trigger the 99% of 100,000 interrupts test for disabling
4452                  * stray interrupts.
4453                  */
4454                 iir = new_iir;
4455         }
4456
4457         enable_rpm_wakeref_asserts(dev_priv);
4458
4459         return ret;
4460 }
4461
4462 static void i965_irq_uninstall(struct drm_device * dev)
4463 {
4464         struct drm_i915_private *dev_priv = to_i915(dev);
4465         int pipe;
4466
4467         if (!dev_priv)
4468                 return;
4469
4470         i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4471         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4472
4473         I915_WRITE(HWSTAM, 0xffffffff);
4474         for_each_pipe(dev_priv, pipe)
4475                 I915_WRITE(PIPESTAT(pipe), 0);
4476         I915_WRITE(IMR, 0xffffffff);
4477         I915_WRITE(IER, 0x0);
4478
4479         for_each_pipe(dev_priv, pipe)
4480                 I915_WRITE(PIPESTAT(pipe),
4481                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4482         I915_WRITE(IIR, I915_READ(IIR));
4483 }
4484
4485 /**
4486  * intel_irq_init - initializes irq support
4487  * @dev_priv: i915 device instance
4488  *
4489  * This function initializes all the irq support including work items, timers
4490  * and all the vtables. It does not setup the interrupt itself though.
4491  */
4492 void intel_irq_init(struct drm_i915_private *dev_priv)
4493 {
4494         struct drm_device *dev = &dev_priv->drm;
4495
4496         intel_hpd_init_work(dev_priv);
4497
4498         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
4499         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4500
4501         /* Let's track the enabled rps events */
4502         if (IS_VALLEYVIEW(dev_priv))
4503                 /* WaGsvRC0ResidencyMethod:vlv */
4504                 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4505         else
4506                 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
4507
4508         dev_priv->rps.pm_intr_keep = 0;
4509
4510         /*
4511          * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
4512          * if GEN6_PM_UP_EI_EXPIRED is masked.
4513          *
4514          * TODO: verify if this can be reproduced on VLV,CHV.
4515          */
4516         if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
4517                 dev_priv->rps.pm_intr_keep |= GEN6_PM_RP_UP_EI_EXPIRED;
4518
4519         if (INTEL_INFO(dev_priv)->gen >= 8)
4520                 dev_priv->rps.pm_intr_keep |= GEN8_PMINTR_REDIRECT_TO_GUC;
4521
4522         INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4523                           i915_hangcheck_elapsed);
4524
4525         if (IS_GEN2(dev_priv)) {
4526                 /* Gen2 doesn't have a hardware frame counter */
4527                 dev->max_vblank_count = 0;
4528                 dev->driver->get_vblank_counter = drm_vblank_no_hw_counter;
4529         } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
4530                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4531                 dev->driver->get_vblank_counter = g4x_get_vblank_counter;
4532         } else {
4533                 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4534                 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
4535         }
4536
4537         /*
4538          * Opt out of the vblank disable timer on everything except gen2.
4539          * Gen2 doesn't have a hardware frame counter and so depends on
4540          * vblank interrupts to produce sane vblank seuquence numbers.
4541          */
4542         if (!IS_GEN2(dev_priv))
4543                 dev->vblank_disable_immediate = true;
4544
4545         /* Most platforms treat the display irq block as an always-on
4546          * power domain. vlv/chv can disable it at runtime and need
4547          * special care to avoid writing any of the display block registers
4548          * outside of the power domain. We defer setting up the display irqs
4549          * in this case to the runtime pm.
4550          */
4551         dev_priv->display_irqs_enabled = true;
4552         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4553                 dev_priv->display_irqs_enabled = false;
4554
4555         dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4556         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
4557
4558         if (IS_CHERRYVIEW(dev_priv)) {
4559                 dev->driver->irq_handler = cherryview_irq_handler;
4560                 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4561                 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4562                 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4563                 dev->driver->enable_vblank = valleyview_enable_vblank;
4564                 dev->driver->disable_vblank = valleyview_disable_vblank;
4565                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4566         } else if (IS_VALLEYVIEW(dev_priv)) {
4567                 dev->driver->irq_handler = valleyview_irq_handler;
4568                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4569                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4570                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4571                 dev->driver->enable_vblank = valleyview_enable_vblank;
4572                 dev->driver->disable_vblank = valleyview_disable_vblank;
4573                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4574         } else if (INTEL_INFO(dev_priv)->gen >= 8) {
4575                 dev->driver->irq_handler = gen8_irq_handler;
4576                 dev->driver->irq_preinstall = gen8_irq_reset;
4577                 dev->driver->irq_postinstall = gen8_irq_postinstall;
4578                 dev->driver->irq_uninstall = gen8_irq_uninstall;
4579                 dev->driver->enable_vblank = gen8_enable_vblank;
4580                 dev->driver->disable_vblank = gen8_disable_vblank;
4581                 if (IS_BROXTON(dev))
4582                         dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4583                 else if (HAS_PCH_SPT(dev) || HAS_PCH_KBP(dev))
4584                         dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4585                 else
4586                         dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4587         } else if (HAS_PCH_SPLIT(dev)) {
4588                 dev->driver->irq_handler = ironlake_irq_handler;
4589                 dev->driver->irq_preinstall = ironlake_irq_reset;
4590                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4591                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4592                 dev->driver->enable_vblank = ironlake_enable_vblank;
4593                 dev->driver->disable_vblank = ironlake_disable_vblank;
4594                 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4595         } else {
4596                 if (IS_GEN2(dev_priv)) {
4597                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
4598                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
4599                         dev->driver->irq_handler = i8xx_irq_handler;
4600                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
4601                 } else if (IS_GEN3(dev_priv)) {
4602                         dev->driver->irq_preinstall = i915_irq_preinstall;
4603                         dev->driver->irq_postinstall = i915_irq_postinstall;
4604                         dev->driver->irq_uninstall = i915_irq_uninstall;
4605                         dev->driver->irq_handler = i915_irq_handler;
4606                 } else {
4607                         dev->driver->irq_preinstall = i965_irq_preinstall;
4608                         dev->driver->irq_postinstall = i965_irq_postinstall;
4609                         dev->driver->irq_uninstall = i965_irq_uninstall;
4610                         dev->driver->irq_handler = i965_irq_handler;
4611                 }
4612                 if (I915_HAS_HOTPLUG(dev_priv))
4613                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4614                 dev->driver->enable_vblank = i915_enable_vblank;
4615                 dev->driver->disable_vblank = i915_disable_vblank;
4616         }
4617 }
4618
4619 /**
4620  * intel_irq_install - enables the hardware interrupt
4621  * @dev_priv: i915 device instance
4622  *
4623  * This function enables the hardware interrupt handling, but leaves the hotplug
4624  * handling still disabled. It is called after intel_irq_init().
4625  *
4626  * In the driver load and resume code we need working interrupts in a few places
4627  * but don't want to deal with the hassle of concurrent probe and hotplug
4628  * workers. Hence the split into this two-stage approach.
4629  */
4630 int intel_irq_install(struct drm_i915_private *dev_priv)
4631 {
4632         /*
4633          * We enable some interrupt sources in our postinstall hooks, so mark
4634          * interrupts as enabled _before_ actually enabling them to avoid
4635          * special cases in our ordering checks.
4636          */
4637         dev_priv->pm.irqs_enabled = true;
4638
4639         return drm_irq_install(&dev_priv->drm, dev_priv->drm.pdev->irq);
4640 }
4641
4642 /**
4643  * intel_irq_uninstall - finilizes all irq handling
4644  * @dev_priv: i915 device instance
4645  *
4646  * This stops interrupt and hotplug handling and unregisters and frees all
4647  * resources acquired in the init functions.
4648  */
4649 void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4650 {
4651         drm_irq_uninstall(&dev_priv->drm);
4652         intel_hpd_cancel_work(dev_priv);
4653         dev_priv->pm.irqs_enabled = false;
4654 }
4655
4656 /**
4657  * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4658  * @dev_priv: i915 device instance
4659  *
4660  * This function is used to disable interrupts at runtime, both in the runtime
4661  * pm and the system suspend/resume code.
4662  */
4663 void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4664 {
4665         dev_priv->drm.driver->irq_uninstall(&dev_priv->drm);
4666         dev_priv->pm.irqs_enabled = false;
4667         synchronize_irq(dev_priv->drm.irq);
4668 }
4669
4670 /**
4671  * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4672  * @dev_priv: i915 device instance
4673  *
4674  * This function is used to enable interrupts at runtime, both in the runtime
4675  * pm and the system suspend/resume code.
4676  */
4677 void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4678 {
4679         dev_priv->pm.irqs_enabled = true;
4680         dev_priv->drm.driver->irq_preinstall(&dev_priv->drm);
4681         dev_priv->drm.driver->irq_postinstall(&dev_priv->drm);
4682 }