2 * SPDX-License-Identifier: MIT
4 * Copyright � 2008-2018 Intel Corporation
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
10 #include <linux/atomic.h>
11 #include <linux/kref.h>
12 #include <linux/ktime.h>
13 #include <linux/sched.h>
15 #include <drm/drm_mm.h>
17 #include "gt/intel_engine.h"
18 #include "gt/intel_gt_types.h"
19 #include "gt/uc/intel_uc_fw.h"
21 #include "intel_device_info.h"
24 #include "i915_gem_gtt.h"
25 #include "i915_params.h"
26 #include "i915_scheduler.h"
28 struct drm_i915_private;
29 struct i915_vma_compress;
30 struct intel_engine_capture_vma;
31 struct intel_overlay_error_state;
32 struct intel_display_error_state;
34 struct i915_vma_coredump {
35 struct i915_vma_coredump *next;
49 struct i915_request_coredump {
56 struct i915_sched_attr sched_attr;
59 struct intel_engine_coredump {
60 const struct intel_engine_cs *engine;
65 /* position of active request inside the ring */
66 u32 rq_head, rq_post, rq_tail;
86 u32 rc_psmi; /* sleep state */
87 struct intel_instdone instdone;
89 struct i915_gem_context_coredump {
90 char comm[TASK_COMM_LEN];
98 struct i915_sched_attr sched_attr;
101 struct i915_vma_coredump *vma;
103 struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
104 unsigned int num_ports;
114 struct intel_engine_coredump *next;
117 struct intel_gt_coredump {
118 const struct intel_gt *_gt;
122 struct intel_gt_info info;
124 /* Generic register state */
128 u32 gtier[6], ngtier;
131 u32 error; /* gen6+ */
132 u32 err_int; /* gen7 */
133 u32 fault_data0; /* gen8, gen9 */
134 u32 fault_data1; /* gen8, gen9 */
141 u32 aux_err; /* gen12 */
142 u32 sfc_done[GEN12_SFC_DONE_MAX]; /* gen12 */
143 u32 gam_done; /* gen12 */
146 u64 fence[I915_MAX_NUM_FENCES];
148 struct intel_engine_coredump *engine;
150 struct intel_uc_coredump {
151 struct intel_uc_fw guc_fw;
152 struct intel_uc_fw huc_fw;
153 struct i915_vma_coredump *guc_log;
156 struct intel_gt_coredump *next;
159 struct i915_gpu_coredump {
164 unsigned long capture;
166 struct drm_i915_private *i915;
168 struct intel_gt_coredump *gt;
178 struct intel_device_info device_info;
179 struct intel_runtime_info runtime_info;
180 struct intel_driver_caps driver_caps;
181 struct i915_params params;
183 struct intel_overlay_error_state *overlay;
184 struct intel_display_error_state *display;
186 struct scatterlist *sgl, *fit;
189 struct i915_gpu_error {
190 /* For reset and error_state handling. */
192 /* Protected by the above dev->gpu_error.lock. */
193 struct i915_gpu_coredump *first_error;
195 atomic_t pending_fb_pin;
197 /** Number of times the device has been reset (global) */
198 atomic_t reset_count;
200 /** Number of times an engine has been reset */
201 atomic_t reset_engine_count[I915_NUM_ENGINES];
204 struct drm_i915_error_state_buf {
205 struct drm_i915_private *i915;
206 struct scatterlist *sgl, *cur, *end;
216 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
219 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
221 struct i915_gpu_coredump *i915_gpu_coredump(struct drm_i915_private *i915);
222 void i915_capture_error_state(struct drm_i915_private *i915);
224 struct i915_gpu_coredump *
225 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
227 struct intel_gt_coredump *
228 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp);
230 struct intel_engine_coredump *
231 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp);
233 struct intel_engine_capture_vma *
234 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
235 struct i915_request *rq,
238 void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
239 struct intel_engine_capture_vma *capture,
240 struct i915_vma_compress *compress);
242 struct i915_vma_compress *
243 i915_vma_capture_prepare(struct intel_gt_coredump *gt);
245 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
246 struct i915_vma_compress *compress);
248 void i915_error_state_store(struct i915_gpu_coredump *error);
250 static inline struct i915_gpu_coredump *
251 i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
258 i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
259 char *buf, loff_t offset, size_t count);
261 void __i915_gpu_coredump_free(struct kref *kref);
262 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
265 kref_put(&gpu->ref, __i915_gpu_coredump_free);
268 struct i915_gpu_coredump *i915_first_error_state(struct drm_i915_private *i915);
269 void i915_reset_error_state(struct drm_i915_private *i915);
270 void i915_disable_error_state(struct drm_i915_private *i915, int err);
274 static inline void i915_capture_error_state(struct drm_i915_private *i915)
278 static inline struct i915_gpu_coredump *
279 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
284 static inline struct intel_gt_coredump *
285 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp)
290 static inline struct intel_engine_coredump *
291 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp)
296 static inline struct intel_engine_capture_vma *
297 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
298 struct i915_request *rq,
305 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
306 struct intel_engine_capture_vma *capture,
307 struct i915_vma_compress *compress)
311 static inline struct i915_vma_compress *
312 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
318 i915_vma_capture_finish(struct intel_gt_coredump *gt,
319 struct i915_vma_compress *compress)
324 i915_error_state_store(struct i915_gpu_coredump *error)
328 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
332 static inline struct i915_gpu_coredump *
333 i915_first_error_state(struct drm_i915_private *i915)
335 return ERR_PTR(-ENODEV);
338 static inline void i915_reset_error_state(struct drm_i915_private *i915)
342 static inline void i915_disable_error_state(struct drm_i915_private *i915,
347 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
349 #endif /* _I915_GPU_ERROR_H_ */