2 * Copyright (c) 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
30 #include <generated/utsrelease.h>
31 #include <linux/stop_machine.h>
32 #include <linux/zlib.h>
33 #include <drm/drm_print.h>
34 #include <linux/ascii85.h>
36 #include "i915_gpu_error.h"
39 static inline const struct intel_engine_cs *
40 engine_lookup(const struct drm_i915_private *i915, unsigned int id)
42 if (id >= I915_NUM_ENGINES)
45 return i915->engine[id];
48 static inline const char *
49 __engine_name(const struct intel_engine_cs *engine)
51 return engine ? engine->name : "";
55 engine_name(const struct drm_i915_private *i915, unsigned int id)
57 return __engine_name(engine_lookup(i915, id));
60 static const char *tiling_flag(int tiling)
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
70 static const char *dirty_flag(int dirty)
72 return dirty ? " dirty" : "";
75 static const char *purgeable_flag(int purgeable)
77 return purgeable ? " purgeable" : "";
80 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
88 if (e->bytes == e->size - 1 || e->err)
94 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
97 if (e->pos + len <= e->start) {
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
111 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
138 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
139 const char *f, va_list args)
143 if (!__i915_error_ok(e))
146 /* Seek the first printf which is hits start position */
147 if (e->pos < e->start) {
151 len = vsnprintf(NULL, 0, f, tmp);
154 if (!__i915_error_seek(e, len))
158 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
159 if (len >= e->size - e->bytes)
160 len = e->size - e->bytes - 1;
162 __i915_error_advance(e, len);
165 static void i915_error_puts(struct drm_i915_error_state_buf *e,
170 if (!__i915_error_ok(e))
175 /* Seek the first printf which is hits start position */
176 if (e->pos < e->start) {
177 if (!__i915_error_seek(e, len))
181 if (len >= e->size - e->bytes)
182 len = e->size - e->bytes - 1;
183 memcpy(e->buf + e->bytes, str, len);
185 __i915_error_advance(e, len);
188 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
189 #define err_puts(e, s) i915_error_puts(e, s)
191 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
193 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
196 static inline struct drm_printer
197 i915_error_printer(struct drm_i915_error_state_buf *e)
199 struct drm_printer p = {
200 .printfn = __i915_printfn_error,
206 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
209 struct z_stream_s zstream;
213 static bool compress_init(struct compress *c)
215 struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
218 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
219 GFP_ATOMIC | __GFP_NOWARN);
220 if (!zstream->workspace)
223 if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
224 kfree(zstream->workspace);
229 if (i915_has_memcpy_from_wc())
230 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
235 static void *compress_next_page(struct drm_i915_error_object *dst)
239 if (dst->page_count >= dst->num_pages)
240 return ERR_PTR(-ENOSPC);
242 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
244 return ERR_PTR(-ENOMEM);
246 return dst->pages[dst->page_count++] = (void *)page;
249 static int compress_page(struct compress *c,
251 struct drm_i915_error_object *dst)
253 struct z_stream_s *zstream = &c->zstream;
255 zstream->next_in = src;
256 if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
257 zstream->next_in = c->tmp;
258 zstream->avail_in = PAGE_SIZE;
261 if (zstream->avail_out == 0) {
262 zstream->next_out = compress_next_page(dst);
263 if (IS_ERR(zstream->next_out))
264 return PTR_ERR(zstream->next_out);
266 zstream->avail_out = PAGE_SIZE;
269 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
273 } while (zstream->avail_in);
275 /* Fallback to uncompressed if we increase size? */
276 if (0 && zstream->total_out > zstream->total_in)
282 static int compress_flush(struct compress *c,
283 struct drm_i915_error_object *dst)
285 struct z_stream_s *zstream = &c->zstream;
288 switch (zlib_deflate(zstream, Z_FINISH)) {
289 case Z_OK: /* more space requested */
290 zstream->next_out = compress_next_page(dst);
291 if (IS_ERR(zstream->next_out))
292 return PTR_ERR(zstream->next_out);
294 zstream->avail_out = PAGE_SIZE;
300 default: /* any error */
306 memset(zstream->next_out, 0, zstream->avail_out);
307 dst->unused = zstream->avail_out;
311 static void compress_fini(struct compress *c,
312 struct drm_i915_error_object *dst)
314 struct z_stream_s *zstream = &c->zstream;
316 zlib_deflateEnd(zstream);
317 kfree(zstream->workspace);
319 free_page((unsigned long)c->tmp);
322 static void err_compression_marker(struct drm_i915_error_state_buf *m)
332 static bool compress_init(struct compress *c)
337 static int compress_page(struct compress *c,
339 struct drm_i915_error_object *dst)
344 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
349 if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
350 memcpy(ptr, src, PAGE_SIZE);
351 dst->pages[dst->page_count++] = ptr;
357 static int compress_flush(struct compress *c,
358 struct drm_i915_error_object *dst)
363 static void compress_fini(struct compress *c,
364 struct drm_i915_error_object *dst)
368 static void err_compression_marker(struct drm_i915_error_state_buf *m)
375 static void print_error_buffers(struct drm_i915_error_state_buf *m,
377 struct drm_i915_error_buffer *err,
380 err_printf(m, "%s [%d]:\n", name, count);
383 err_printf(m, " %08x_%08x %8u %02x %02x %02x",
384 upper_32_bits(err->gtt_offset),
385 lower_32_bits(err->gtt_offset),
390 err_puts(m, tiling_flag(err->tiling));
391 err_puts(m, dirty_flag(err->dirty));
392 err_puts(m, purgeable_flag(err->purgeable));
393 err_puts(m, err->userptr ? " userptr" : "");
394 err_puts(m, err->engine != -1 ? " " : "");
395 err_puts(m, engine_name(m->i915, err->engine));
396 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
399 err_printf(m, " (name: %d)", err->name);
400 if (err->fence_reg != I915_FENCE_REG_NONE)
401 err_printf(m, " (fence: %d)", err->fence_reg);
408 static void error_print_instdone(struct drm_i915_error_state_buf *m,
409 const struct drm_i915_error_engine *ee)
414 err_printf(m, " INSTDONE: 0x%08x\n",
415 ee->instdone.instdone);
417 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
420 err_printf(m, " SC_INSTDONE: 0x%08x\n",
421 ee->instdone.slice_common);
423 if (INTEL_GEN(m->i915) <= 6)
426 for_each_instdone_slice_subslice(m->i915, slice, subslice)
427 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
429 ee->instdone.sampler[slice][subslice]);
431 for_each_instdone_slice_subslice(m->i915, slice, subslice)
432 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
434 ee->instdone.row[slice][subslice]);
437 static const char *bannable(const struct drm_i915_error_context *ctx)
439 return ctx->bannable ? "" : " (unbannable)";
442 static void error_print_request(struct drm_i915_error_state_buf *m,
444 const struct drm_i915_error_request *erq,
445 const unsigned long epoch)
450 err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n",
451 prefix, erq->pid, erq->ban_score,
452 erq->context, erq->seqno, erq->sched_attr.priority,
453 jiffies_to_msecs(erq->jiffies - epoch),
454 erq->start, erq->head, erq->tail);
457 static void error_print_context(struct drm_i915_error_state_buf *m,
459 const struct drm_i915_error_context *ctx)
461 err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, ban score %d%s guilty %d active %d\n",
462 header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
463 ctx->sched_attr.priority, ctx->ban_score, bannable(ctx),
464 ctx->guilty, ctx->active);
467 static void error_print_engine(struct drm_i915_error_state_buf *m,
468 const struct drm_i915_error_engine *ee,
469 const unsigned long epoch)
473 err_printf(m, "%s command stream:\n",
474 engine_name(m->i915, ee->engine_id));
475 err_printf(m, " IDLE?: %s\n", yesno(ee->idle));
476 err_printf(m, " START: 0x%08x\n", ee->start);
477 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
478 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
479 ee->tail, ee->rq_post, ee->rq_tail);
480 err_printf(m, " CTL: 0x%08x\n", ee->ctl);
481 err_printf(m, " MODE: 0x%08x\n", ee->mode);
482 err_printf(m, " HWS: 0x%08x\n", ee->hws);
483 err_printf(m, " ACTHD: 0x%08x %08x\n",
484 (u32)(ee->acthd>>32), (u32)ee->acthd);
485 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
486 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
488 error_print_instdone(m, ee);
490 if (ee->batchbuffer) {
491 u64 start = ee->batchbuffer->gtt_offset;
492 u64 end = start + ee->batchbuffer->gtt_size;
494 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
495 upper_32_bits(start), lower_32_bits(start),
496 upper_32_bits(end), lower_32_bits(end));
498 if (INTEL_GEN(m->i915) >= 4) {
499 err_printf(m, " BBADDR: 0x%08x_%08x\n",
500 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
501 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
502 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
504 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
505 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
506 lower_32_bits(ee->faddr));
507 if (INTEL_GEN(m->i915) >= 6) {
508 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
509 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
510 err_printf(m, " SYNC_0: 0x%08x\n",
511 ee->semaphore_mboxes[0]);
512 err_printf(m, " SYNC_1: 0x%08x\n",
513 ee->semaphore_mboxes[1]);
514 if (HAS_VEBOX(m->i915))
515 err_printf(m, " SYNC_2: 0x%08x\n",
516 ee->semaphore_mboxes[2]);
518 if (USES_PPGTT(m->i915)) {
519 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
521 if (INTEL_GEN(m->i915) >= 8) {
523 for (i = 0; i < 4; i++)
524 err_printf(m, " PDP%d: 0x%016llx\n",
525 i, ee->vm_info.pdp[i]);
527 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
528 ee->vm_info.pp_dir_base);
531 err_printf(m, " seqno: 0x%08x\n", ee->seqno);
532 err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno);
533 err_printf(m, " waiting: %s\n", yesno(ee->waiting));
534 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
535 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
536 err_printf(m, " hangcheck stall: %s\n", yesno(ee->hangcheck_stalled));
537 err_printf(m, " hangcheck action: %s\n",
538 hangcheck_action_to_str(ee->hangcheck_action));
539 err_printf(m, " hangcheck action timestamp: %dms (%lu%s)\n",
540 jiffies_to_msecs(ee->hangcheck_timestamp - epoch),
541 ee->hangcheck_timestamp,
542 ee->hangcheck_timestamp == epoch ? "; epoch" : "");
543 err_printf(m, " engine reset count: %u\n", ee->reset_count);
545 for (n = 0; n < ee->num_ports; n++) {
546 err_printf(m, " ELSP[%d]:", n);
547 error_print_request(m, " ", &ee->execlist[n], epoch);
550 error_print_context(m, " Active context: ", &ee->context);
553 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
558 i915_error_vprintf(e, f, args);
562 static void print_error_obj(struct drm_i915_error_state_buf *m,
563 struct intel_engine_cs *engine,
565 struct drm_i915_error_object *obj)
567 char out[ASCII85_BUFSZ];
574 err_printf(m, "%s --- %s = 0x%08x %08x\n",
575 engine ? engine->name : "global", name,
576 upper_32_bits(obj->gtt_offset),
577 lower_32_bits(obj->gtt_offset));
580 err_compression_marker(m);
581 for (page = 0; page < obj->page_count; page++) {
585 if (page == obj->page_count - 1)
587 len = ascii85_encode_len(len);
589 for (i = 0; i < len; i++)
590 err_puts(m, ascii85_encode(obj->pages[page][i], out));
595 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
596 const struct intel_device_info *info,
597 const struct intel_driver_caps *caps)
599 struct drm_printer p = i915_error_printer(m);
601 intel_device_info_dump_flags(info, &p);
602 intel_driver_caps_print(caps, &p);
603 intel_device_info_dump_topology(&info->sseu, &p);
606 static void err_print_params(struct drm_i915_error_state_buf *m,
607 const struct i915_params *params)
609 struct drm_printer p = i915_error_printer(m);
611 i915_params_dump(params, &p);
614 static void err_print_pciid(struct drm_i915_error_state_buf *m,
615 struct drm_i915_private *i915)
617 struct pci_dev *pdev = i915->drm.pdev;
619 err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
620 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
621 err_printf(m, "PCI Subsystem: %04x:%04x\n",
622 pdev->subsystem_vendor,
623 pdev->subsystem_device);
626 static void err_print_uc(struct drm_i915_error_state_buf *m,
627 const struct i915_error_uc *error_uc)
629 struct drm_printer p = i915_error_printer(m);
630 const struct i915_gpu_state *error =
631 container_of(error_uc, typeof(*error), uc);
633 if (!error->device_info.has_guc)
636 intel_uc_fw_dump(&error_uc->guc_fw, &p);
637 intel_uc_fw_dump(&error_uc->huc_fw, &p);
638 print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
641 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
642 const struct i915_gpu_state *error)
644 struct drm_i915_private *dev_priv = m->i915;
645 struct drm_i915_error_object *obj;
646 struct timespec64 ts;
650 err_printf(m, "No error state collected\n");
654 if (*error->error_msg)
655 err_printf(m, "%s\n", error->error_msg);
656 err_printf(m, "Kernel: " UTS_RELEASE "\n");
657 ts = ktime_to_timespec64(error->time);
658 err_printf(m, "Time: %lld s %ld us\n",
659 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
660 ts = ktime_to_timespec64(error->boottime);
661 err_printf(m, "Boottime: %lld s %ld us\n",
662 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
663 ts = ktime_to_timespec64(error->uptime);
664 err_printf(m, "Uptime: %lld s %ld us\n",
665 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
666 err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ);
667 err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n",
669 jiffies_to_msecs(jiffies - error->capture),
670 jiffies_to_msecs(error->capture - error->epoch));
672 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
673 if (error->engine[i].hangcheck_stalled &&
674 error->engine[i].context.pid) {
675 err_printf(m, "Active process (on ring %s): %s [%d], score %d%s\n",
676 engine_name(m->i915, i),
677 error->engine[i].context.comm,
678 error->engine[i].context.pid,
679 error->engine[i].context.ban_score,
680 bannable(&error->engine[i].context));
683 err_printf(m, "Reset count: %u\n", error->reset_count);
684 err_printf(m, "Suspend count: %u\n", error->suspend_count);
685 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
686 err_print_pciid(m, error->i915);
688 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
690 if (HAS_CSR(dev_priv)) {
691 struct intel_csr *csr = &dev_priv->csr;
693 err_printf(m, "DMC loaded: %s\n",
694 yesno(csr->dmc_payload != NULL));
695 err_printf(m, "DMC fw version: %d.%d\n",
696 CSR_VERSION_MAJOR(csr->version),
697 CSR_VERSION_MINOR(csr->version));
700 err_printf(m, "GT awake: %s\n", yesno(error->awake));
701 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
702 err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
703 err_printf(m, "EIR: 0x%08x\n", error->eir);
704 err_printf(m, "IER: 0x%08x\n", error->ier);
705 for (i = 0; i < error->ngtier; i++)
706 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
707 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
708 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
709 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
710 err_printf(m, "CCID: 0x%08x\n", error->ccid);
711 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
713 for (i = 0; i < error->nfence; i++)
714 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
716 if (INTEL_GEN(dev_priv) >= 6) {
717 err_printf(m, "ERROR: 0x%08x\n", error->error);
719 if (INTEL_GEN(dev_priv) >= 8)
720 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
721 error->fault_data1, error->fault_data0);
723 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
726 if (IS_GEN7(dev_priv))
727 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
729 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
730 if (error->engine[i].engine_id != -1)
731 error_print_engine(m, &error->engine[i], error->epoch);
734 for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
738 if (!error->active_vm[i])
741 len = scnprintf(buf, sizeof(buf), "Active (");
742 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
743 if (error->engine[j].vm != error->active_vm[i])
746 len += scnprintf(buf + len, sizeof(buf), "%s%s",
748 dev_priv->engine[j]->name);
751 scnprintf(buf + len, sizeof(buf), ")");
752 print_error_buffers(m, buf,
754 error->active_bo_count[i]);
757 print_error_buffers(m, "Pinned (global)",
759 error->pinned_bo_count);
761 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
762 const struct drm_i915_error_engine *ee = &error->engine[i];
764 obj = ee->batchbuffer;
766 err_puts(m, dev_priv->engine[i]->name);
768 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d%s)",
773 ee->context.ban_score,
774 bannable(&ee->context));
775 err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
776 upper_32_bits(obj->gtt_offset),
777 lower_32_bits(obj->gtt_offset));
778 print_error_obj(m, dev_priv->engine[i], NULL, obj);
781 for (j = 0; j < ee->user_bo_count; j++)
782 print_error_obj(m, dev_priv->engine[i],
783 "user", ee->user_bo[j]);
785 if (ee->num_requests) {
786 err_printf(m, "%s --- %d requests\n",
787 dev_priv->engine[i]->name,
789 for (j = 0; j < ee->num_requests; j++)
790 error_print_request(m, " ",
795 if (IS_ERR(ee->waiters)) {
796 err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
797 dev_priv->engine[i]->name);
798 } else if (ee->num_waiters) {
799 err_printf(m, "%s --- %d waiters\n",
800 dev_priv->engine[i]->name,
802 for (j = 0; j < ee->num_waiters; j++) {
803 err_printf(m, " seqno 0x%08x for %s [%d]\n",
804 ee->waiters[j].seqno,
810 print_error_obj(m, dev_priv->engine[i],
811 "ringbuffer", ee->ringbuffer);
813 print_error_obj(m, dev_priv->engine[i],
814 "HW Status", ee->hws_page);
816 print_error_obj(m, dev_priv->engine[i],
817 "HW context", ee->ctx);
819 print_error_obj(m, dev_priv->engine[i],
820 "WA context", ee->wa_ctx);
822 print_error_obj(m, dev_priv->engine[i],
823 "WA batchbuffer", ee->wa_batchbuffer);
825 print_error_obj(m, dev_priv->engine[i],
826 "NULL context", ee->default_state);
830 intel_overlay_print_error_state(m, error->overlay);
833 intel_display_print_error_state(m, error->display);
835 err_print_capabilities(m, &error->device_info, &error->driver_caps);
836 err_print_params(m, &error->params);
837 err_print_uc(m, &error->uc);
839 if (m->bytes == 0 && m->err)
845 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
846 struct drm_i915_private *i915,
847 size_t count, loff_t pos)
849 memset(ebuf, 0, sizeof(*ebuf));
852 /* We need to have enough room to store any i915_error_state printf
853 * so that we can move it to start position.
855 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
856 ebuf->buf = kmalloc(ebuf->size,
857 GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);
859 if (ebuf->buf == NULL) {
860 ebuf->size = PAGE_SIZE;
861 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
864 if (ebuf->buf == NULL) {
866 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
869 if (ebuf->buf == NULL)
877 static void i915_error_object_free(struct drm_i915_error_object *obj)
884 for (page = 0; page < obj->page_count; page++)
885 free_page((unsigned long)obj->pages[page]);
890 static __always_inline void free_param(const char *type, void *x)
892 if (!__builtin_strcmp(type, "char *"))
896 static void cleanup_params(struct i915_gpu_state *error)
898 #define FREE(T, x, ...) free_param(#T, &error->params.x);
899 I915_PARAMS_FOR_EACH(FREE);
903 static void cleanup_uc_state(struct i915_gpu_state *error)
905 struct i915_error_uc *error_uc = &error->uc;
907 kfree(error_uc->guc_fw.path);
908 kfree(error_uc->huc_fw.path);
909 i915_error_object_free(error_uc->guc_log);
912 void __i915_gpu_state_free(struct kref *error_ref)
914 struct i915_gpu_state *error =
915 container_of(error_ref, typeof(*error), ref);
918 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
919 struct drm_i915_error_engine *ee = &error->engine[i];
921 for (j = 0; j < ee->user_bo_count; j++)
922 i915_error_object_free(ee->user_bo[j]);
925 i915_error_object_free(ee->batchbuffer);
926 i915_error_object_free(ee->wa_batchbuffer);
927 i915_error_object_free(ee->ringbuffer);
928 i915_error_object_free(ee->hws_page);
929 i915_error_object_free(ee->ctx);
930 i915_error_object_free(ee->wa_ctx);
933 if (!IS_ERR_OR_NULL(ee->waiters))
937 for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
938 kfree(error->active_bo[i]);
939 kfree(error->pinned_bo);
941 kfree(error->overlay);
942 kfree(error->display);
944 cleanup_params(error);
945 cleanup_uc_state(error);
950 static struct drm_i915_error_object *
951 i915_error_object_create(struct drm_i915_private *i915,
952 struct i915_vma *vma)
954 struct i915_ggtt *ggtt = &i915->ggtt;
955 const u64 slot = ggtt->error_capture.start;
956 struct drm_i915_error_object *dst;
957 struct compress compress;
958 unsigned long num_pages;
959 struct sgt_iter iter;
966 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
967 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
968 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
969 GFP_ATOMIC | __GFP_NOWARN);
973 dst->gtt_offset = vma->node.start;
974 dst->gtt_size = vma->node.size;
975 dst->num_pages = num_pages;
979 if (!compress_init(&compress)) {
985 for_each_sgt_dma(dma, iter, vma->pages) {
988 ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
990 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
991 ret = compress_page(&compress, (void __force *)s, dst);
992 io_mapping_unmap_atomic(s);
997 if (ret || compress_flush(&compress, dst)) {
998 while (dst->page_count--)
999 free_page((unsigned long)dst->pages[dst->page_count]);
1004 compress_fini(&compress, dst);
1005 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1009 /* The error capture is special as tries to run underneath the normal
1010 * locking rules - so we use the raw version of the i915_gem_active lookup.
1012 static inline uint32_t
1013 __active_get_seqno(struct i915_gem_active *active)
1015 struct i915_request *request;
1017 request = __i915_gem_active_peek(active);
1018 return request ? request->global_seqno : 0;
1022 __active_get_engine_id(struct i915_gem_active *active)
1024 struct i915_request *request;
1026 request = __i915_gem_active_peek(active);
1027 return request ? request->engine->id : -1;
1030 static void capture_bo(struct drm_i915_error_buffer *err,
1031 struct i915_vma *vma)
1033 struct drm_i915_gem_object *obj = vma->obj;
1035 err->size = obj->base.size;
1036 err->name = obj->base.name;
1038 err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
1039 err->engine = __active_get_engine_id(&obj->frontbuffer_write);
1041 err->gtt_offset = vma->node.start;
1042 err->read_domains = obj->read_domains;
1043 err->write_domain = obj->write_domain;
1044 err->fence_reg = vma->fence ? vma->fence->id : -1;
1045 err->tiling = i915_gem_object_get_tiling(obj);
1046 err->dirty = obj->mm.dirty;
1047 err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
1048 err->userptr = obj->userptr.mm != NULL;
1049 err->cache_level = obj->cache_level;
1052 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
1053 int count, struct list_head *head,
1056 struct i915_vma *vma;
1059 list_for_each_entry(vma, head, vm_link) {
1063 if (pinned_only && !i915_vma_is_pinned(vma))
1066 capture_bo(err++, vma);
1074 /* Generate a semi-unique error code. The code is not meant to have meaning, The
1075 * code's only purpose is to try to prevent false duplicated bug reports by
1076 * grossly estimating a GPU error state.
1078 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1079 * the hang if we could strip the GTT offset information from it.
1081 * It's only a small step better than a random number in its current form.
1083 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
1084 struct i915_gpu_state *error,
1087 uint32_t error_code = 0;
1090 /* IPEHR would be an ideal way to detect errors, as it's the gross
1091 * measure of "the command that hung." However, has some very common
1092 * synchronization commands which almost always appear in the case
1093 * strictly a client bug. Use instdone to differentiate those some.
1095 for (i = 0; i < I915_NUM_ENGINES; i++) {
1096 if (error->engine[i].hangcheck_stalled) {
1100 return error->engine[i].ipehr ^
1101 error->engine[i].instdone.instdone;
1108 static void gem_record_fences(struct i915_gpu_state *error)
1110 struct drm_i915_private *dev_priv = error->i915;
1113 if (INTEL_GEN(dev_priv) >= 6) {
1114 for (i = 0; i < dev_priv->num_fence_regs; i++)
1115 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
1116 } else if (INTEL_GEN(dev_priv) >= 4) {
1117 for (i = 0; i < dev_priv->num_fence_regs; i++)
1118 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
1120 for (i = 0; i < dev_priv->num_fence_regs; i++)
1121 error->fence[i] = I915_READ(FENCE_REG(i));
1126 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1127 struct drm_i915_error_engine *ee)
1129 struct drm_i915_private *dev_priv = engine->i915;
1131 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1132 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1133 if (HAS_VEBOX(dev_priv))
1134 ee->semaphore_mboxes[2] =
1135 I915_READ(RING_SYNC_2(engine->mmio_base));
1138 static void error_record_engine_waiters(struct intel_engine_cs *engine,
1139 struct drm_i915_error_engine *ee)
1141 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1142 struct drm_i915_error_waiter *waiter;
1146 ee->num_waiters = 0;
1149 if (RB_EMPTY_ROOT(&b->waiters))
1152 if (!spin_trylock_irq(&b->rb_lock)) {
1153 ee->waiters = ERR_PTR(-EDEADLK);
1158 for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
1160 spin_unlock_irq(&b->rb_lock);
1164 waiter = kmalloc_array(count,
1165 sizeof(struct drm_i915_error_waiter),
1170 if (!spin_trylock_irq(&b->rb_lock)) {
1172 ee->waiters = ERR_PTR(-EDEADLK);
1176 ee->waiters = waiter;
1177 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1178 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1180 strcpy(waiter->comm, w->tsk->comm);
1181 waiter->pid = w->tsk->pid;
1182 waiter->seqno = w->seqno;
1185 if (++ee->num_waiters == count)
1188 spin_unlock_irq(&b->rb_lock);
1191 static void error_record_engine_registers(struct i915_gpu_state *error,
1192 struct intel_engine_cs *engine,
1193 struct drm_i915_error_engine *ee)
1195 struct drm_i915_private *dev_priv = engine->i915;
1197 if (INTEL_GEN(dev_priv) >= 6) {
1198 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1199 if (INTEL_GEN(dev_priv) >= 8) {
1200 ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
1202 gen6_record_semaphore_state(engine, ee);
1203 ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1207 if (INTEL_GEN(dev_priv) >= 4) {
1208 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1209 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1210 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1211 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1212 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1213 if (INTEL_GEN(dev_priv) >= 8) {
1214 ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1215 ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1217 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1219 ee->faddr = I915_READ(DMA_FADD_I8XX);
1220 ee->ipeir = I915_READ(IPEIR);
1221 ee->ipehr = I915_READ(IPEHR);
1224 intel_engine_get_instdone(engine, &ee->instdone);
1226 ee->waiting = intel_engine_has_waiter(engine);
1227 ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1228 ee->acthd = intel_engine_get_active_head(engine);
1229 ee->seqno = intel_engine_get_seqno(engine);
1230 ee->last_seqno = intel_engine_last_submit(engine);
1231 ee->start = I915_READ_START(engine);
1232 ee->head = I915_READ_HEAD(engine);
1233 ee->tail = I915_READ_TAIL(engine);
1234 ee->ctl = I915_READ_CTL(engine);
1235 if (INTEL_GEN(dev_priv) > 2)
1236 ee->mode = I915_READ_MODE(engine);
1238 if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1241 if (IS_GEN7(dev_priv)) {
1242 switch (engine->id) {
1245 mmio = RENDER_HWS_PGA_GEN7;
1248 mmio = BLT_HWS_PGA_GEN7;
1251 mmio = BSD_HWS_PGA_GEN7;
1254 mmio = VEBOX_HWS_PGA_GEN7;
1257 } else if (IS_GEN6(engine->i915)) {
1258 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1260 /* XXX: gen8 returns to sanity */
1261 mmio = RING_HWS_PGA(engine->mmio_base);
1264 ee->hws = I915_READ(mmio);
1267 ee->idle = intel_engine_is_idle(engine);
1268 ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1269 ee->hangcheck_action = engine->hangcheck.action;
1270 ee->hangcheck_stalled = engine->hangcheck.stalled;
1271 ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1274 if (USES_PPGTT(dev_priv)) {
1277 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1279 if (IS_GEN6(dev_priv))
1280 ee->vm_info.pp_dir_base =
1281 I915_READ(RING_PP_DIR_BASE_READ(engine));
1282 else if (IS_GEN7(dev_priv))
1283 ee->vm_info.pp_dir_base =
1284 I915_READ(RING_PP_DIR_BASE(engine));
1285 else if (INTEL_GEN(dev_priv) >= 8)
1286 for (i = 0; i < 4; i++) {
1287 ee->vm_info.pdp[i] =
1288 I915_READ(GEN8_RING_PDP_UDW(engine, i));
1289 ee->vm_info.pdp[i] <<= 32;
1290 ee->vm_info.pdp[i] |=
1291 I915_READ(GEN8_RING_PDP_LDW(engine, i));
1296 static void record_request(struct i915_request *request,
1297 struct drm_i915_error_request *erq)
1299 struct i915_gem_context *ctx = request->gem_context;
1301 erq->context = ctx->hw_id;
1302 erq->sched_attr = request->sched.attr;
1303 erq->ban_score = atomic_read(&ctx->ban_score);
1304 erq->seqno = request->global_seqno;
1305 erq->jiffies = request->emitted_jiffies;
1306 erq->start = i915_ggtt_offset(request->ring->vma);
1307 erq->head = request->head;
1308 erq->tail = request->tail;
1311 erq->pid = ctx->pid ? pid_nr(ctx->pid) : 0;
1315 static void engine_record_requests(struct intel_engine_cs *engine,
1316 struct i915_request *first,
1317 struct drm_i915_error_engine *ee)
1319 struct i915_request *request;
1324 list_for_each_entry_from(request, &engine->timeline.requests, link)
1329 ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1333 ee->num_requests = count;
1337 list_for_each_entry_from(request, &engine->timeline.requests, link) {
1338 if (count >= ee->num_requests) {
1340 * If the ring request list was changed in
1341 * between the point where the error request
1342 * list was created and dimensioned and this
1343 * point then just exit early to avoid crashes.
1345 * We don't need to communicate that the
1346 * request list changed state during error
1347 * state capture and that the error state is
1348 * slightly incorrect as a consequence since we
1349 * are typically only interested in the request
1350 * list state at the point of error state
1351 * capture, not in any changes happening during
1357 record_request(request, &ee->requests[count++]);
1359 ee->num_requests = count;
1362 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1363 struct drm_i915_error_engine *ee)
1365 const struct intel_engine_execlists * const execlists = &engine->execlists;
1368 for (n = 0; n < execlists_num_ports(execlists); n++) {
1369 struct i915_request *rq = port_request(&execlists->port[n]);
1374 record_request(rq, &ee->execlist[n]);
1380 static void record_context(struct drm_i915_error_context *e,
1381 struct i915_gem_context *ctx)
1384 struct task_struct *task;
1387 task = pid_task(ctx->pid, PIDTYPE_PID);
1389 strcpy(e->comm, task->comm);
1395 e->handle = ctx->user_handle;
1396 e->hw_id = ctx->hw_id;
1397 e->sched_attr = ctx->sched;
1398 e->ban_score = atomic_read(&ctx->ban_score);
1399 e->bannable = i915_gem_context_is_bannable(ctx);
1400 e->guilty = atomic_read(&ctx->guilty_count);
1401 e->active = atomic_read(&ctx->active_count);
1404 static void request_record_user_bo(struct i915_request *request,
1405 struct drm_i915_error_engine *ee)
1407 struct i915_capture_list *c;
1408 struct drm_i915_error_object **bo;
1412 for (c = request->capture_list; c; c = c->next)
1417 bo = kcalloc(count, sizeof(*bo), GFP_ATOMIC);
1422 for (c = request->capture_list; c; c = c->next) {
1423 bo[count] = i915_error_object_create(request->i915, c->vma);
1430 ee->user_bo_count = count;
1433 static struct drm_i915_error_object *
1434 capture_object(struct drm_i915_private *dev_priv,
1435 struct drm_i915_gem_object *obj)
1437 if (obj && i915_gem_object_has_pages(obj)) {
1438 struct i915_vma fake = {
1439 .node = { .start = U64_MAX, .size = obj->base.size },
1440 .size = obj->base.size,
1441 .pages = obj->mm.pages,
1445 return i915_error_object_create(dev_priv, &fake);
1451 static void gem_record_rings(struct i915_gpu_state *error)
1453 struct drm_i915_private *i915 = error->i915;
1454 struct i915_ggtt *ggtt = &i915->ggtt;
1457 for (i = 0; i < I915_NUM_ENGINES; i++) {
1458 struct intel_engine_cs *engine = i915->engine[i];
1459 struct drm_i915_error_engine *ee = &error->engine[i];
1460 struct i915_request *request;
1469 error_record_engine_registers(error, engine, ee);
1470 error_record_engine_waiters(engine, ee);
1471 error_record_engine_execlists(engine, ee);
1473 request = i915_gem_find_active_request(engine);
1475 struct i915_gem_context *ctx = request->gem_context;
1476 struct intel_ring *ring;
1478 ee->vm = ctx->ppgtt ? &ctx->ppgtt->vm : &ggtt->vm;
1480 record_context(&ee->context, ctx);
1482 /* We need to copy these to an anonymous buffer
1483 * as the simplest method to avoid being overwritten
1487 i915_error_object_create(i915, request->batch);
1489 if (HAS_BROKEN_CS_TLB(i915))
1490 ee->wa_batchbuffer =
1491 i915_error_object_create(i915,
1493 request_record_user_bo(request, ee);
1496 i915_error_object_create(i915,
1497 request->hw_context->state);
1500 i915_gem_context_no_error_capture(ctx);
1502 ee->rq_head = request->head;
1503 ee->rq_post = request->postfix;
1504 ee->rq_tail = request->tail;
1506 ring = request->ring;
1507 ee->cpu_ring_head = ring->head;
1508 ee->cpu_ring_tail = ring->tail;
1510 i915_error_object_create(i915, ring->vma);
1512 engine_record_requests(engine, request, ee);
1516 i915_error_object_create(i915,
1517 engine->status_page.vma);
1519 ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma);
1521 ee->default_state = capture_object(i915, engine->default_state);
1525 static void gem_capture_vm(struct i915_gpu_state *error,
1526 struct i915_address_space *vm,
1529 struct drm_i915_error_buffer *active_bo;
1530 struct i915_vma *vma;
1534 list_for_each_entry(vma, &vm->active_list, vm_link)
1539 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1541 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1545 error->active_vm[idx] = vm;
1546 error->active_bo[idx] = active_bo;
1547 error->active_bo_count[idx] = count;
1550 static void capture_active_buffers(struct i915_gpu_state *error)
1554 BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1555 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1556 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1558 /* Scan each engine looking for unique active contexts/vm */
1559 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1560 struct drm_i915_error_engine *ee = &error->engine[i];
1567 for (j = 0; j < i && !found; j++)
1568 found = error->engine[j].vm == ee->vm;
1570 gem_capture_vm(error, ee->vm, cnt++);
1574 static void capture_pinned_buffers(struct i915_gpu_state *error)
1576 struct i915_address_space *vm = &error->i915->ggtt.vm;
1577 struct drm_i915_error_buffer *bo;
1578 struct i915_vma *vma;
1579 int count_inactive, count_active;
1582 list_for_each_entry(vma, &vm->inactive_list, vm_link)
1586 list_for_each_entry(vma, &vm->active_list, vm_link)
1590 if (count_inactive + count_active)
1591 bo = kcalloc(count_inactive + count_active,
1592 sizeof(*bo), GFP_ATOMIC);
1596 count_inactive = capture_error_bo(bo, count_inactive,
1597 &vm->active_list, true);
1598 count_active = capture_error_bo(bo + count_inactive, count_active,
1599 &vm->inactive_list, true);
1600 error->pinned_bo_count = count_inactive + count_active;
1601 error->pinned_bo = bo;
1604 static void capture_uc_state(struct i915_gpu_state *error)
1606 struct drm_i915_private *i915 = error->i915;
1607 struct i915_error_uc *error_uc = &error->uc;
1609 /* Capturing uC state won't be useful if there is no GuC */
1610 if (!error->device_info.has_guc)
1613 error_uc->guc_fw = i915->guc.fw;
1614 error_uc->huc_fw = i915->huc.fw;
1616 /* Non-default firmware paths will be specified by the modparam.
1617 * As modparams are generally accesible from the userspace make
1618 * explicit copies of the firmware paths.
1620 error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
1621 error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
1622 error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
1625 /* Capture all registers which don't fit into another category. */
1626 static void capture_reg_state(struct i915_gpu_state *error)
1628 struct drm_i915_private *dev_priv = error->i915;
1631 /* General organization
1632 * 1. Registers specific to a single generation
1633 * 2. Registers which belong to multiple generations
1634 * 3. Feature specific registers.
1635 * 4. Everything else
1636 * Please try to follow the order.
1639 /* 1: Registers specific to a single generation */
1640 if (IS_VALLEYVIEW(dev_priv)) {
1641 error->gtier[0] = I915_READ(GTIER);
1642 error->ier = I915_READ(VLV_IER);
1643 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1646 if (IS_GEN7(dev_priv))
1647 error->err_int = I915_READ(GEN7_ERR_INT);
1649 if (INTEL_GEN(dev_priv) >= 8) {
1650 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1651 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1654 if (IS_GEN6(dev_priv)) {
1655 error->forcewake = I915_READ_FW(FORCEWAKE);
1656 error->gab_ctl = I915_READ(GAB_CTL);
1657 error->gfx_mode = I915_READ(GFX_MODE);
1660 /* 2: Registers which belong to multiple generations */
1661 if (INTEL_GEN(dev_priv) >= 7)
1662 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1664 if (INTEL_GEN(dev_priv) >= 6) {
1665 error->derrmr = I915_READ(DERRMR);
1666 error->error = I915_READ(ERROR_GEN6);
1667 error->done_reg = I915_READ(DONE_REG);
1670 if (INTEL_GEN(dev_priv) >= 5)
1671 error->ccid = I915_READ(CCID);
1673 /* 3: Feature specific registers */
1674 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1675 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1676 error->gac_eco = I915_READ(GAC_ECO_BITS);
1679 /* 4: Everything else */
1680 if (INTEL_GEN(dev_priv) >= 11) {
1681 error->ier = I915_READ(GEN8_DE_MISC_IER);
1682 error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
1683 error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
1684 error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE);
1685 error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1686 error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);
1687 error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);
1689 } else if (INTEL_GEN(dev_priv) >= 8) {
1690 error->ier = I915_READ(GEN8_DE_MISC_IER);
1691 for (i = 0; i < 4; i++)
1692 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1694 } else if (HAS_PCH_SPLIT(dev_priv)) {
1695 error->ier = I915_READ(DEIER);
1696 error->gtier[0] = I915_READ(GTIER);
1698 } else if (IS_GEN2(dev_priv)) {
1699 error->ier = I915_READ16(IER);
1700 } else if (!IS_VALLEYVIEW(dev_priv)) {
1701 error->ier = I915_READ(IER);
1703 error->eir = I915_READ(EIR);
1704 error->pgtbl_er = I915_READ(PGTBL_ER);
1707 static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1708 struct i915_gpu_state *error,
1710 const char *error_msg)
1713 int engine_id = -1, len;
1715 ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1717 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1718 "GPU HANG: ecode %d:%d:0x%08x",
1719 INTEL_GEN(dev_priv), engine_id, ecode);
1721 if (engine_id != -1 && error->engine[engine_id].context.pid)
1722 len += scnprintf(error->error_msg + len,
1723 sizeof(error->error_msg) - len,
1725 error->engine[engine_id].context.comm,
1726 error->engine[engine_id].context.pid);
1728 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1729 ", reason: %s, action: %s",
1731 engine_mask ? "reset" : "continue");
1734 static void capture_gen_state(struct i915_gpu_state *error)
1736 struct drm_i915_private *i915 = error->i915;
1738 error->awake = i915->gt.awake;
1739 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1740 error->suspended = i915->runtime_pm.suspended;
1743 #ifdef CONFIG_INTEL_IOMMU
1744 error->iommu = intel_iommu_gfx_mapped;
1746 error->reset_count = i915_reset_count(&i915->gpu_error);
1747 error->suspend_count = i915->suspend_count;
1749 memcpy(&error->device_info,
1751 sizeof(error->device_info));
1752 error->driver_caps = i915->caps;
1755 static __always_inline void dup_param(const char *type, void *x)
1757 if (!__builtin_strcmp(type, "char *"))
1758 *(void **)x = kstrdup(*(void **)x, GFP_ATOMIC);
1761 static void capture_params(struct i915_gpu_state *error)
1763 error->params = i915_modparams;
1764 #define DUP(T, x, ...) dup_param(#T, &error->params.x);
1765 I915_PARAMS_FOR_EACH(DUP);
1769 static unsigned long capture_find_epoch(const struct i915_gpu_state *error)
1771 unsigned long epoch = error->capture;
1774 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1775 const struct drm_i915_error_engine *ee = &error->engine[i];
1777 if (ee->hangcheck_stalled &&
1778 time_before(ee->hangcheck_timestamp, epoch))
1779 epoch = ee->hangcheck_timestamp;
1785 static int capture(void *data)
1787 struct i915_gpu_state *error = data;
1789 error->time = ktime_get_real();
1790 error->boottime = ktime_get_boottime();
1791 error->uptime = ktime_sub(ktime_get(),
1792 error->i915->gt.last_init_time);
1793 error->capture = jiffies;
1795 capture_params(error);
1796 capture_gen_state(error);
1797 capture_uc_state(error);
1798 capture_reg_state(error);
1799 gem_record_fences(error);
1800 gem_record_rings(error);
1801 capture_active_buffers(error);
1802 capture_pinned_buffers(error);
1804 error->overlay = intel_overlay_capture_error_state(error->i915);
1805 error->display = intel_display_capture_error_state(error->i915);
1807 error->epoch = capture_find_epoch(error);
1812 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1814 struct i915_gpu_state *
1815 i915_capture_gpu_state(struct drm_i915_private *i915)
1817 struct i915_gpu_state *error;
1819 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1823 kref_init(&error->ref);
1826 stop_machine(capture, error, NULL);
1832 * i915_capture_error_state - capture an error record for later analysis
1833 * @i915: i915 device
1834 * @engine_mask: the mask of engines triggering the hang
1835 * @error_msg: a message to insert into the error capture header
1837 * Should be called when an error is detected (either a hang or an error
1838 * interrupt) to capture error state from the time of the error. Fills
1839 * out a structure which becomes available in debugfs for user level tools
1842 void i915_capture_error_state(struct drm_i915_private *i915,
1844 const char *error_msg)
1847 struct i915_gpu_state *error;
1848 unsigned long flags;
1850 if (!i915_modparams.error_capture)
1853 if (READ_ONCE(i915->gpu_error.first_error))
1856 error = i915_capture_gpu_state(i915);
1858 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1862 i915_error_capture_msg(i915, error, engine_mask, error_msg);
1863 DRM_INFO("%s\n", error->error_msg);
1865 if (!error->simulated) {
1866 spin_lock_irqsave(&i915->gpu_error.lock, flags);
1867 if (!i915->gpu_error.first_error) {
1868 i915->gpu_error.first_error = error;
1871 spin_unlock_irqrestore(&i915->gpu_error.lock, flags);
1875 __i915_gpu_state_free(&error->ref);
1880 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1881 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1882 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1883 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1884 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1885 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1886 i915->drm.primary->index);
1891 struct i915_gpu_state *
1892 i915_first_error_state(struct drm_i915_private *i915)
1894 struct i915_gpu_state *error;
1896 spin_lock_irq(&i915->gpu_error.lock);
1897 error = i915->gpu_error.first_error;
1899 i915_gpu_state_get(error);
1900 spin_unlock_irq(&i915->gpu_error.lock);
1905 void i915_reset_error_state(struct drm_i915_private *i915)
1907 struct i915_gpu_state *error;
1909 spin_lock_irq(&i915->gpu_error.lock);
1910 error = i915->gpu_error.first_error;
1911 i915->gpu_error.first_error = NULL;
1912 spin_unlock_irq(&i915->gpu_error.lock);
1914 i915_gpu_state_put(error);