2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include <linux/string.h>
29 #include <linux/bitops.h>
31 #include <drm/i915_drm.h>
35 * DOC: buffer object tiling
37 * i915_gem_set_tiling() and i915_gem_get_tiling() is the userspace interface to
38 * declare fence register requirements.
40 * In principle GEM doesn't care at all about the internal data layout of an
41 * object, and hence it also doesn't care about tiling or swizzling. There's two
44 * - For X and Y tiling the hardware provides detilers for CPU access, so called
45 * fences. Since there's only a limited amount of them the kernel must manage
46 * these, and therefore userspace must tell the kernel the object tiling if it
47 * wants to use fences for detiling.
48 * - On gen3 and gen4 platforms have a swizzling pattern for tiled objects which
49 * depends upon the physical page frame number. When swapping such objects the
50 * page frame number might change and the kernel must be able to fix this up
51 * and hence now the tiling. Note that on a subset of platforms with
52 * asymmetric memory channel population the swizzling pattern changes in an
53 * unknown way, and for those the kernel simply forbids swapping completely.
55 * Since neither of this applies for new tiling layouts on modern platforms like
56 * W, Ys and Yf tiling GEM only allows object tiling to be set to X or Y tiled.
57 * Anything else can be handled in userspace entirely without the kernel's
61 /* Check pitch constriants for all chips & tiling formats */
63 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
67 /* Linear is always fine */
68 if (tiling_mode == I915_TILING_NONE)
71 if (tiling_mode > I915_TILING_LAST)
75 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
80 /* check maximum stride & object size */
81 /* i965+ stores the end address of the gtt mapping in the fence
82 * reg, so dont bother to check the size */
83 if (INTEL_INFO(dev)->gen >= 7) {
84 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
86 } else if (INTEL_INFO(dev)->gen >= 4) {
87 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
94 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
97 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
102 if (stride < tile_width)
105 /* 965+ just needs multiples of tile width */
106 if (INTEL_INFO(dev)->gen >= 4) {
107 if (stride & (tile_width - 1))
112 /* Pre-965 needs power of two tile widths */
113 if (stride & (stride - 1))
119 static bool i915_vma_fence_prepare(struct i915_vma *vma, int tiling_mode)
121 struct drm_i915_private *dev_priv = to_i915(vma->vm->dev);
124 if (!i915_vma_is_map_and_fenceable(vma))
127 if (INTEL_GEN(dev_priv) == 3) {
128 if (vma->node.start & ~I915_FENCE_START_MASK)
131 if (vma->node.start & ~I830_FENCE_START_MASK)
135 size = i915_gem_get_ggtt_size(dev_priv, vma->size, tiling_mode);
136 if (vma->node.size < size)
139 if (vma->node.start & (size - 1))
145 /* Make the current GTT allocation valid for the change in tiling. */
147 i915_gem_object_fence_prepare(struct drm_i915_gem_object *obj, int tiling_mode)
149 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
150 struct i915_vma *vma;
153 if (tiling_mode == I915_TILING_NONE)
156 if (INTEL_GEN(dev_priv) >= 4)
159 list_for_each_entry(vma, &obj->vma_list, obj_link) {
160 if (i915_vma_fence_prepare(vma, tiling_mode))
163 ret = i915_vma_unbind(vma);
172 * i915_gem_set_tiling - IOCTL handler to set tiling mode
174 * @data: data pointer for the ioctl
175 * @file: DRM file for the ioctl call
177 * Sets the tiling mode of an object, returning the required swizzling of
178 * bit 6 of addresses in the object.
180 * Called by the user via ioctl.
183 * Zero on success, negative errno on failure.
186 i915_gem_set_tiling(struct drm_device *dev, void *data,
187 struct drm_file *file)
189 struct drm_i915_gem_set_tiling *args = data;
190 struct drm_i915_private *dev_priv = to_i915(dev);
191 struct drm_i915_gem_object *obj;
194 /* Make sure we don't cross-contaminate obj->tiling_and_stride */
195 BUILD_BUG_ON(I915_TILING_LAST & STRIDE_MASK);
197 obj = i915_gem_object_lookup(file, args->handle);
201 if (!i915_tiling_ok(dev,
202 args->stride, obj->base.size, args->tiling_mode)) {
203 i915_gem_object_put_unlocked(obj);
207 intel_runtime_pm_get(dev_priv);
209 mutex_lock(&dev->struct_mutex);
210 if (obj->pin_display || obj->framebuffer_references) {
215 if (args->tiling_mode == I915_TILING_NONE) {
216 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
219 if (args->tiling_mode == I915_TILING_X)
220 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
222 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
224 /* Hide bit 17 swizzling from the user. This prevents old Mesa
225 * from aborting the application on sw fallbacks to bit 17,
226 * and we use the pread/pwrite bit17 paths to swizzle for it.
227 * If there was a user that was relying on the swizzle
228 * information for drm_intel_bo_map()ed reads/writes this would
229 * break it, but we don't have any of those.
231 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
232 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
233 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
234 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
236 /* If we can't handle the swizzling, make it untiled. */
237 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
238 args->tiling_mode = I915_TILING_NONE;
239 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
244 if (args->tiling_mode != i915_gem_object_get_tiling(obj) ||
245 args->stride != i915_gem_object_get_stride(obj)) {
246 /* We need to rebind the object if its current allocation
247 * no longer meets the alignment restrictions for its new
248 * tiling mode. Otherwise we can just leave it alone, but
249 * need to ensure that any fence register is updated before
250 * the next fenced (either through the GTT or by the BLT unit
251 * on older GPUs) access.
253 * After updating the tiling parameters, we then flag whether
254 * we need to update an associated fence register. Note this
255 * has to also include the unfenced register the GPU uses
256 * whilst executing a fenced command for an untiled object.
259 err = i915_gem_object_fence_prepare(obj, args->tiling_mode);
261 struct i915_vma *vma;
264 obj->madv == I915_MADV_WILLNEED &&
265 dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
266 if (args->tiling_mode == I915_TILING_NONE)
267 i915_gem_object_unpin_pages(obj);
268 if (!i915_gem_object_is_tiled(obj))
269 i915_gem_object_pin_pages(obj);
272 list_for_each_entry(vma, &obj->vma_list, obj_link) {
276 vma->fence->dirty = true;
278 obj->tiling_and_stride =
279 args->stride | args->tiling_mode;
281 /* Force the fence to be reacquired for GTT access */
282 i915_gem_release_mmap(obj);
285 /* we have to maintain this existing ABI... */
286 args->stride = i915_gem_object_get_stride(obj);
287 args->tiling_mode = i915_gem_object_get_tiling(obj);
289 /* Try to preallocate memory required to save swizzling on put-pages */
290 if (i915_gem_object_needs_bit17_swizzle(obj)) {
291 if (obj->bit_17 == NULL) {
292 obj->bit_17 = kcalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT),
293 sizeof(long), GFP_KERNEL);
301 i915_gem_object_put(obj);
302 mutex_unlock(&dev->struct_mutex);
304 intel_runtime_pm_put(dev_priv);
310 * i915_gem_get_tiling - IOCTL handler to get tiling mode
312 * @data: data pointer for the ioctl
313 * @file: DRM file for the ioctl call
315 * Returns the current tiling mode and required bit 6 swizzling for the object.
317 * Called by the user via ioctl.
320 * Zero on success, negative errno on failure.
323 i915_gem_get_tiling(struct drm_device *dev, void *data,
324 struct drm_file *file)
326 struct drm_i915_gem_get_tiling *args = data;
327 struct drm_i915_private *dev_priv = to_i915(dev);
328 struct drm_i915_gem_object *obj;
330 obj = i915_gem_object_lookup(file, args->handle);
334 args->tiling_mode = READ_ONCE(obj->tiling_and_stride) & TILING_MASK;
335 switch (args->tiling_mode) {
337 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
340 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
342 case I915_TILING_NONE:
343 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
346 DRM_ERROR("unknown tiling mode\n");
349 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
350 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
351 args->phys_swizzle_mode = I915_BIT_6_SWIZZLE_UNKNOWN;
353 args->phys_swizzle_mode = args->swizzle_mode;
354 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
355 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
356 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
357 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
359 i915_gem_object_put_unlocked(obj);