2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/seq_file.h>
28 #include <drm/i915_drm.h>
30 #include "i915_vgpu.h"
31 #include "i915_trace.h"
32 #include "intel_drv.h"
35 * DOC: Global GTT views
37 * Background and previous state
39 * Historically objects could exists (be bound) in global GTT space only as
40 * singular instances with a view representing all of the object's backing pages
41 * in a linear fashion. This view will be called a normal view.
43 * To support multiple views of the same object, where the number of mapped
44 * pages is not equal to the backing store, or where the layout of the pages
45 * is not linear, concept of a GGTT view was added.
47 * One example of an alternative view is a stereo display driven by a single
48 * image. In this case we would have a framebuffer looking like this
54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
55 * rendering. In contrast, fed to the display engine would be an alternative
56 * view which could look something like this:
61 * In this example both the size and layout of pages in the alternative view is
62 * different from the normal view.
64 * Implementation and usage
66 * GGTT views are implemented using VMAs and are distinguished via enum
67 * i915_ggtt_view_type and struct i915_ggtt_view.
69 * A new flavour of core GEM functions which work with GGTT bound objects were
70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
71 * renaming in large amounts of code. They take the struct i915_ggtt_view
72 * parameter encapsulating all metadata required to implement a view.
74 * As a helper for callers which are only interested in the normal view,
75 * globally const i915_ggtt_view_normal singleton instance exists. All old core
76 * GEM API functions, the ones not taking the view parameter, are operating on,
77 * or with the normal GGTT view.
79 * Code wanting to add or use a new GGTT view needs to:
81 * 1. Add a new enum with a suitable name.
82 * 2. Extend the metadata in the i915_ggtt_view structure if required.
83 * 3. Add support to i915_get_vma_pages().
85 * New views are required to build a scatter-gather table from within the
86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
87 * exists for the lifetime of an VMA.
89 * Core API is designed to have copy semantics which means that passed in
90 * struct i915_ggtt_view does not need to be persistent (left around after
91 * calling the core API functions).
96 i915_get_ggtt_vma_pages(struct i915_vma *vma);
98 const struct i915_ggtt_view i915_ggtt_view_normal;
99 const struct i915_ggtt_view i915_ggtt_view_rotated = {
100 .type = I915_GGTT_VIEW_ROTATED
103 static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
105 bool has_aliasing_ppgtt;
108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6;
109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7;
111 if (intel_vgpu_active(dev))
112 has_full_ppgtt = false; /* emulation is too hard */
115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
116 * execlists, the sole mechanism available to submit work.
118 if (INTEL_INFO(dev)->gen < 9 &&
119 (enable_ppgtt == 0 || !has_aliasing_ppgtt))
122 /* Full PPGTT is required by the Gen9 cmdparser */
123 if (enable_ppgtt == 1 && INTEL_INFO(dev)->gen != 9)
126 if (enable_ppgtt == 2 && has_full_ppgtt)
129 #ifdef CONFIG_INTEL_IOMMU
130 /* Disable ppgtt on SNB if VT-d is on. */
131 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) {
132 DRM_INFO("Disabling PPGTT because VT-d is on\n");
137 /* Early VLV doesn't have this */
138 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
139 dev->pdev->revision < 0xb) {
140 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
144 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists)
147 return has_aliasing_ppgtt ? 1 : 0;
150 static int ppgtt_bind_vma(struct i915_vma *vma,
151 enum i915_cache_level cache_level,
156 /* Applicable to VLV, and gen8+ */
159 pte_flags |= PTE_READ_ONLY;
161 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start,
162 cache_level, pte_flags);
167 static void ppgtt_unbind_vma(struct i915_vma *vma)
169 vma->vm->clear_range(vma->vm,
175 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
176 enum i915_cache_level level,
177 bool valid, u32 flags)
179 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0;
182 if (unlikely(flags & PTE_READ_ONLY))
186 case I915_CACHE_NONE:
187 pte |= PPAT_UNCACHED_INDEX;
190 pte |= PPAT_DISPLAY_ELLC_INDEX;
193 pte |= PPAT_CACHED_INDEX;
200 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
201 const enum i915_cache_level level)
203 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
205 if (level != I915_CACHE_NONE)
206 pde |= PPAT_CACHED_PDE_INDEX;
208 pde |= PPAT_UNCACHED_INDEX;
212 #define gen8_pdpe_encode gen8_pde_encode
213 #define gen8_pml4e_encode gen8_pde_encode
215 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
216 enum i915_cache_level level,
217 bool valid, u32 unused)
219 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
220 pte |= GEN6_PTE_ADDR_ENCODE(addr);
223 case I915_CACHE_L3_LLC:
225 pte |= GEN6_PTE_CACHE_LLC;
227 case I915_CACHE_NONE:
228 pte |= GEN6_PTE_UNCACHED;
237 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
238 enum i915_cache_level level,
239 bool valid, u32 unused)
241 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
242 pte |= GEN6_PTE_ADDR_ENCODE(addr);
245 case I915_CACHE_L3_LLC:
246 pte |= GEN7_PTE_CACHE_L3_LLC;
249 pte |= GEN6_PTE_CACHE_LLC;
251 case I915_CACHE_NONE:
252 pte |= GEN6_PTE_UNCACHED;
261 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
262 enum i915_cache_level level,
263 bool valid, u32 flags)
265 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
266 pte |= GEN6_PTE_ADDR_ENCODE(addr);
268 if (!(flags & PTE_READ_ONLY))
269 pte |= BYT_PTE_WRITEABLE;
271 if (level != I915_CACHE_NONE)
272 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
277 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
278 enum i915_cache_level level,
279 bool valid, u32 unused)
281 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
282 pte |= HSW_PTE_ADDR_ENCODE(addr);
284 if (level != I915_CACHE_NONE)
285 pte |= HSW_WB_LLC_AGE3;
290 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
291 enum i915_cache_level level,
292 bool valid, u32 unused)
294 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0;
295 pte |= HSW_PTE_ADDR_ENCODE(addr);
298 case I915_CACHE_NONE:
301 pte |= HSW_WT_ELLC_LLC_AGE3;
304 pte |= HSW_WB_ELLC_LLC_AGE3;
311 static int __setup_page_dma(struct drm_device *dev,
312 struct i915_page_dma *p, gfp_t flags)
314 struct device *device = &dev->pdev->dev;
316 p->page = alloc_page(flags);
320 p->daddr = dma_map_page(device,
321 p->page, 0, 4096, PCI_DMA_BIDIRECTIONAL);
323 if (dma_mapping_error(device, p->daddr)) {
324 __free_page(p->page);
331 static int setup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
333 return __setup_page_dma(dev, p, GFP_KERNEL);
336 static void cleanup_page_dma(struct drm_device *dev, struct i915_page_dma *p)
338 if (WARN_ON(!p->page))
341 dma_unmap_page(&dev->pdev->dev, p->daddr, 4096, PCI_DMA_BIDIRECTIONAL);
342 __free_page(p->page);
343 memset(p, 0, sizeof(*p));
346 static void *kmap_page_dma(struct i915_page_dma *p)
348 return kmap_atomic(p->page);
351 /* We use the flushing unmap only with ppgtt structures:
352 * page directories, page tables and scratch pages.
354 static void kunmap_page_dma(struct drm_device *dev, void *vaddr)
356 /* There are only few exceptions for gen >=6. chv and bxt.
357 * And we are not sure about the latter so play safe for now.
359 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
360 drm_clflush_virt_range(vaddr, PAGE_SIZE);
362 kunmap_atomic(vaddr);
365 #define kmap_px(px) kmap_page_dma(px_base(px))
366 #define kunmap_px(ppgtt, vaddr) kunmap_page_dma((ppgtt)->base.dev, (vaddr))
368 #define setup_px(dev, px) setup_page_dma((dev), px_base(px))
369 #define cleanup_px(dev, px) cleanup_page_dma((dev), px_base(px))
370 #define fill_px(dev, px, v) fill_page_dma((dev), px_base(px), (v))
371 #define fill32_px(dev, px, v) fill_page_dma_32((dev), px_base(px), (v))
373 static void fill_page_dma(struct drm_device *dev, struct i915_page_dma *p,
377 uint64_t * const vaddr = kmap_page_dma(p);
379 for (i = 0; i < 512; i++)
382 kunmap_page_dma(dev, vaddr);
385 static void fill_page_dma_32(struct drm_device *dev, struct i915_page_dma *p,
386 const uint32_t val32)
392 fill_page_dma(dev, p, v);
395 static struct i915_page_scratch *alloc_scratch_page(struct drm_device *dev)
397 struct i915_page_scratch *sp;
400 sp = kzalloc(sizeof(*sp), GFP_KERNEL);
402 return ERR_PTR(-ENOMEM);
404 ret = __setup_page_dma(dev, px_base(sp), GFP_DMA32 | __GFP_ZERO);
410 set_pages_uc(px_page(sp), 1);
415 static void free_scratch_page(struct drm_device *dev,
416 struct i915_page_scratch *sp)
418 set_pages_wb(px_page(sp), 1);
424 static struct i915_page_table *alloc_pt(struct drm_device *dev)
426 struct i915_page_table *pt;
427 const size_t count = INTEL_INFO(dev)->gen >= 8 ?
428 GEN8_PTES : GEN6_PTES;
431 pt = kzalloc(sizeof(*pt), GFP_KERNEL);
433 return ERR_PTR(-ENOMEM);
435 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes),
441 ret = setup_px(dev, pt);
448 kfree(pt->used_ptes);
455 static void free_pt(struct drm_device *dev, struct i915_page_table *pt)
458 kfree(pt->used_ptes);
462 static void gen8_initialize_pt(struct i915_address_space *vm,
463 struct i915_page_table *pt)
465 gen8_pte_t scratch_pte;
467 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
468 I915_CACHE_LLC, true, 0);
470 fill_px(vm->dev, pt, scratch_pte);
473 static void gen6_initialize_pt(struct i915_address_space *vm,
474 struct i915_page_table *pt)
476 gen6_pte_t scratch_pte;
478 WARN_ON(px_dma(vm->scratch_page) == 0);
480 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
481 I915_CACHE_LLC, true, 0);
483 fill32_px(vm->dev, pt, scratch_pte);
486 static struct i915_page_directory *alloc_pd(struct drm_device *dev)
488 struct i915_page_directory *pd;
491 pd = kzalloc(sizeof(*pd), GFP_KERNEL);
493 return ERR_PTR(-ENOMEM);
495 pd->used_pdes = kcalloc(BITS_TO_LONGS(I915_PDES),
496 sizeof(*pd->used_pdes), GFP_KERNEL);
500 ret = setup_px(dev, pd);
507 kfree(pd->used_pdes);
514 static void free_pd(struct drm_device *dev, struct i915_page_directory *pd)
518 kfree(pd->used_pdes);
523 static void gen8_initialize_pd(struct i915_address_space *vm,
524 struct i915_page_directory *pd)
526 gen8_pde_t scratch_pde;
528 scratch_pde = gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC);
530 fill_px(vm->dev, pd, scratch_pde);
533 static int __pdp_init(struct drm_device *dev,
534 struct i915_page_directory_pointer *pdp)
536 size_t pdpes = I915_PDPES_PER_PDP(dev);
538 pdp->used_pdpes = kcalloc(BITS_TO_LONGS(pdpes),
539 sizeof(unsigned long),
541 if (!pdp->used_pdpes)
544 pdp->page_directory = kcalloc(pdpes, sizeof(*pdp->page_directory),
546 if (!pdp->page_directory) {
547 kfree(pdp->used_pdpes);
548 /* the PDP might be the statically allocated top level. Keep it
549 * as clean as possible */
550 pdp->used_pdpes = NULL;
557 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
559 kfree(pdp->used_pdpes);
560 kfree(pdp->page_directory);
561 pdp->page_directory = NULL;
565 i915_page_directory_pointer *alloc_pdp(struct drm_device *dev)
567 struct i915_page_directory_pointer *pdp;
570 WARN_ON(!USES_FULL_48BIT_PPGTT(dev));
572 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
574 return ERR_PTR(-ENOMEM);
576 ret = __pdp_init(dev, pdp);
580 ret = setup_px(dev, pdp);
594 static void free_pdp(struct drm_device *dev,
595 struct i915_page_directory_pointer *pdp)
598 if (USES_FULL_48BIT_PPGTT(dev)) {
599 cleanup_px(dev, pdp);
604 static void gen8_initialize_pdp(struct i915_address_space *vm,
605 struct i915_page_directory_pointer *pdp)
607 gen8_ppgtt_pdpe_t scratch_pdpe;
609 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
611 fill_px(vm->dev, pdp, scratch_pdpe);
614 static void gen8_initialize_pml4(struct i915_address_space *vm,
615 struct i915_pml4 *pml4)
617 gen8_ppgtt_pml4e_t scratch_pml4e;
619 scratch_pml4e = gen8_pml4e_encode(px_dma(vm->scratch_pdp),
622 fill_px(vm->dev, pml4, scratch_pml4e);
626 gen8_setup_page_directory(struct i915_hw_ppgtt *ppgtt,
627 struct i915_page_directory_pointer *pdp,
628 struct i915_page_directory *pd,
631 gen8_ppgtt_pdpe_t *page_directorypo;
633 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
636 page_directorypo = kmap_px(pdp);
637 page_directorypo[index] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
638 kunmap_px(ppgtt, page_directorypo);
642 gen8_setup_page_directory_pointer(struct i915_hw_ppgtt *ppgtt,
643 struct i915_pml4 *pml4,
644 struct i915_page_directory_pointer *pdp,
647 gen8_ppgtt_pml4e_t *pagemap = kmap_px(pml4);
649 WARN_ON(!USES_FULL_48BIT_PPGTT(ppgtt->base.dev));
650 pagemap[index] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
651 kunmap_px(ppgtt, pagemap);
654 /* Broadwell Page Directory Pointer Descriptors */
655 static int gen8_write_pdp(struct drm_i915_gem_request *req,
659 struct intel_engine_cs *ring = req->ring;
664 ret = intel_ring_begin(req, 6);
668 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
669 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry));
670 intel_ring_emit(ring, upper_32_bits(addr));
671 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
672 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry));
673 intel_ring_emit(ring, lower_32_bits(addr));
674 intel_ring_advance(ring);
679 static int gen8_legacy_mm_switch(struct i915_hw_ppgtt *ppgtt,
680 struct drm_i915_gem_request *req)
684 for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
685 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
687 ret = gen8_write_pdp(req, i, pd_daddr);
695 static int gen8_48b_mm_switch(struct i915_hw_ppgtt *ppgtt,
696 struct drm_i915_gem_request *req)
698 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
701 static void gen8_ppgtt_clear_pte_range(struct i915_address_space *vm,
702 struct i915_page_directory_pointer *pdp,
705 gen8_pte_t scratch_pte)
707 struct i915_hw_ppgtt *ppgtt =
708 container_of(vm, struct i915_hw_ppgtt, base);
709 gen8_pte_t *pt_vaddr;
710 unsigned pdpe = gen8_pdpe_index(start);
711 unsigned pde = gen8_pde_index(start);
712 unsigned pte = gen8_pte_index(start);
713 unsigned num_entries = length >> PAGE_SHIFT;
714 unsigned last_pte, i;
719 while (num_entries) {
720 struct i915_page_directory *pd;
721 struct i915_page_table *pt;
723 if (WARN_ON(!pdp->page_directory[pdpe]))
726 pd = pdp->page_directory[pdpe];
728 if (WARN_ON(!pd->page_table[pde]))
731 pt = pd->page_table[pde];
733 if (WARN_ON(!px_page(pt)))
736 last_pte = pte + num_entries;
737 if (last_pte > GEN8_PTES)
738 last_pte = GEN8_PTES;
740 pt_vaddr = kmap_px(pt);
742 for (i = pte; i < last_pte; i++) {
743 pt_vaddr[i] = scratch_pte;
747 kunmap_px(ppgtt, pt);
750 if (++pde == I915_PDES) {
751 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
758 static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
763 struct i915_hw_ppgtt *ppgtt =
764 container_of(vm, struct i915_hw_ppgtt, base);
765 gen8_pte_t scratch_pte =
766 gen8_pte_encode(px_dma(vm->scratch_page),
767 I915_CACHE_LLC, use_scratch, 0);
769 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
770 gen8_ppgtt_clear_pte_range(vm, &ppgtt->pdp, start, length,
773 uint64_t templ4, pml4e;
774 struct i915_page_directory_pointer *pdp;
776 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
777 gen8_ppgtt_clear_pte_range(vm, pdp, start, length,
784 gen8_ppgtt_insert_pte_entries(struct i915_address_space *vm,
785 struct i915_page_directory_pointer *pdp,
786 struct sg_page_iter *sg_iter,
788 enum i915_cache_level cache_level,
791 struct i915_hw_ppgtt *ppgtt =
792 container_of(vm, struct i915_hw_ppgtt, base);
793 gen8_pte_t *pt_vaddr;
794 unsigned pdpe = gen8_pdpe_index(start);
795 unsigned pde = gen8_pde_index(start);
796 unsigned pte = gen8_pte_index(start);
800 while (__sg_page_iter_next(sg_iter)) {
801 if (pt_vaddr == NULL) {
802 struct i915_page_directory *pd = pdp->page_directory[pdpe];
803 struct i915_page_table *pt = pd->page_table[pde];
804 pt_vaddr = kmap_px(pt);
808 gen8_pte_encode(sg_page_iter_dma_address(sg_iter),
809 cache_level, true, flags);
810 if (++pte == GEN8_PTES) {
811 kunmap_px(ppgtt, pt_vaddr);
813 if (++pde == I915_PDES) {
814 if (++pdpe == I915_PDPES_PER_PDP(vm->dev))
823 kunmap_px(ppgtt, pt_vaddr);
826 static void gen8_ppgtt_insert_entries(struct i915_address_space *vm,
827 struct sg_table *pages,
829 enum i915_cache_level cache_level,
832 struct i915_hw_ppgtt *ppgtt =
833 container_of(vm, struct i915_hw_ppgtt, base);
834 struct sg_page_iter sg_iter;
836 __sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
838 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
839 gen8_ppgtt_insert_pte_entries(vm, &ppgtt->pdp, &sg_iter, start,
842 struct i915_page_directory_pointer *pdp;
843 uint64_t templ4, pml4e;
844 uint64_t length = (uint64_t)pages->orig_nents << PAGE_SHIFT;
846 gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4, pml4e) {
847 gen8_ppgtt_insert_pte_entries(vm, pdp, &sg_iter,
848 start, cache_level, flags);
853 static void gen8_free_page_tables(struct drm_device *dev,
854 struct i915_page_directory *pd)
861 for_each_set_bit(i, pd->used_pdes, I915_PDES) {
862 if (WARN_ON(!pd->page_table[i]))
865 free_pt(dev, pd->page_table[i]);
866 pd->page_table[i] = NULL;
870 static int gen8_init_scratch(struct i915_address_space *vm)
872 struct drm_device *dev = vm->dev;
874 vm->scratch_page = alloc_scratch_page(dev);
875 if (IS_ERR(vm->scratch_page))
876 return PTR_ERR(vm->scratch_page);
878 vm->scratch_pt = alloc_pt(dev);
879 if (IS_ERR(vm->scratch_pt)) {
880 free_scratch_page(dev, vm->scratch_page);
881 return PTR_ERR(vm->scratch_pt);
884 vm->scratch_pd = alloc_pd(dev);
885 if (IS_ERR(vm->scratch_pd)) {
886 free_pt(dev, vm->scratch_pt);
887 free_scratch_page(dev, vm->scratch_page);
888 return PTR_ERR(vm->scratch_pd);
891 if (USES_FULL_48BIT_PPGTT(dev)) {
892 vm->scratch_pdp = alloc_pdp(dev);
893 if (IS_ERR(vm->scratch_pdp)) {
894 free_pd(dev, vm->scratch_pd);
895 free_pt(dev, vm->scratch_pt);
896 free_scratch_page(dev, vm->scratch_page);
897 return PTR_ERR(vm->scratch_pdp);
901 gen8_initialize_pt(vm, vm->scratch_pt);
902 gen8_initialize_pd(vm, vm->scratch_pd);
903 if (USES_FULL_48BIT_PPGTT(dev))
904 gen8_initialize_pdp(vm, vm->scratch_pdp);
909 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
911 enum vgt_g2v_type msg;
912 struct drm_device *dev = ppgtt->base.dev;
913 struct drm_i915_private *dev_priv = dev->dev_private;
914 unsigned int offset = vgtif_reg(pdp0_lo);
917 if (USES_FULL_48BIT_PPGTT(dev)) {
918 u64 daddr = px_dma(&ppgtt->pml4);
920 I915_WRITE(offset, lower_32_bits(daddr));
921 I915_WRITE(offset + 4, upper_32_bits(daddr));
923 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
924 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
926 for (i = 0; i < GEN8_LEGACY_PDPES; i++) {
927 u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
929 I915_WRITE(offset, lower_32_bits(daddr));
930 I915_WRITE(offset + 4, upper_32_bits(daddr));
935 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
936 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
939 I915_WRITE(vgtif_reg(g2v_notify), msg);
944 static void gen8_free_scratch(struct i915_address_space *vm)
946 struct drm_device *dev = vm->dev;
948 if (USES_FULL_48BIT_PPGTT(dev))
949 free_pdp(dev, vm->scratch_pdp);
950 free_pd(dev, vm->scratch_pd);
951 free_pt(dev, vm->scratch_pt);
952 free_scratch_page(dev, vm->scratch_page);
955 static void gen8_ppgtt_cleanup_3lvl(struct drm_device *dev,
956 struct i915_page_directory_pointer *pdp)
960 for_each_set_bit(i, pdp->used_pdpes, I915_PDPES_PER_PDP(dev)) {
961 if (WARN_ON(!pdp->page_directory[i]))
964 gen8_free_page_tables(dev, pdp->page_directory[i]);
965 free_pd(dev, pdp->page_directory[i]);
971 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
975 for_each_set_bit(i, ppgtt->pml4.used_pml4es, GEN8_PML4ES_PER_PML4) {
976 if (WARN_ON(!ppgtt->pml4.pdps[i]))
979 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, ppgtt->pml4.pdps[i]);
982 cleanup_px(ppgtt->base.dev, &ppgtt->pml4);
985 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
987 struct i915_hw_ppgtt *ppgtt =
988 container_of(vm, struct i915_hw_ppgtt, base);
990 if (intel_vgpu_active(vm->dev))
991 gen8_ppgtt_notify_vgt(ppgtt, false);
993 if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
994 gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp);
996 gen8_ppgtt_cleanup_4lvl(ppgtt);
998 gen8_free_scratch(vm);
1002 * gen8_ppgtt_alloc_pagetabs() - Allocate page tables for VA range.
1003 * @vm: Master vm structure.
1004 * @pd: Page directory for this address range.
1005 * @start: Starting virtual address to begin allocations.
1006 * @length: Size of the allocations.
1007 * @new_pts: Bitmap set by function with new allocations. Likely used by the
1008 * caller to free on error.
1010 * Allocate the required number of page tables. Extremely similar to
1011 * gen8_ppgtt_alloc_page_directories(). The main difference is here we are limited by
1012 * the page directory boundary (instead of the page directory pointer). That
1013 * boundary is 1GB virtual. Therefore, unlike gen8_ppgtt_alloc_page_directories(), it is
1014 * possible, and likely that the caller will need to use multiple calls of this
1015 * function to achieve the appropriate allocation.
1017 * Return: 0 if success; negative error code otherwise.
1019 static int gen8_ppgtt_alloc_pagetabs(struct i915_address_space *vm,
1020 struct i915_page_directory *pd,
1023 unsigned long *new_pts)
1025 struct drm_device *dev = vm->dev;
1026 struct i915_page_table *pt;
1030 gen8_for_each_pde(pt, pd, start, length, temp, pde) {
1031 /* Don't reallocate page tables */
1032 if (test_bit(pde, pd->used_pdes)) {
1033 /* Scratch is never allocated this way */
1034 WARN_ON(pt == vm->scratch_pt);
1042 gen8_initialize_pt(vm, pt);
1043 pd->page_table[pde] = pt;
1044 __set_bit(pde, new_pts);
1045 trace_i915_page_table_entry_alloc(vm, pde, start, GEN8_PDE_SHIFT);
1051 for_each_set_bit(pde, new_pts, I915_PDES)
1052 free_pt(dev, pd->page_table[pde]);
1058 * gen8_ppgtt_alloc_page_directories() - Allocate page directories for VA range.
1059 * @vm: Master vm structure.
1060 * @pdp: Page directory pointer for this address range.
1061 * @start: Starting virtual address to begin allocations.
1062 * @length: Size of the allocations.
1063 * @new_pds: Bitmap set by function with new allocations. Likely used by the
1064 * caller to free on error.
1066 * Allocate the required number of page directories starting at the pde index of
1067 * @start, and ending at the pde index @start + @length. This function will skip
1068 * over already allocated page directories within the range, and only allocate
1069 * new ones, setting the appropriate pointer within the pdp as well as the
1070 * correct position in the bitmap @new_pds.
1072 * The function will only allocate the pages within the range for a give page
1073 * directory pointer. In other words, if @start + @length straddles a virtually
1074 * addressed PDP boundary (512GB for 4k pages), there will be more allocations
1075 * required by the caller, This is not currently possible, and the BUG in the
1076 * code will prevent it.
1078 * Return: 0 if success; negative error code otherwise.
1081 gen8_ppgtt_alloc_page_directories(struct i915_address_space *vm,
1082 struct i915_page_directory_pointer *pdp,
1085 unsigned long *new_pds)
1087 struct drm_device *dev = vm->dev;
1088 struct i915_page_directory *pd;
1091 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1093 WARN_ON(!bitmap_empty(new_pds, pdpes));
1095 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1096 if (test_bit(pdpe, pdp->used_pdpes))
1103 gen8_initialize_pd(vm, pd);
1104 pdp->page_directory[pdpe] = pd;
1105 __set_bit(pdpe, new_pds);
1106 trace_i915_page_directory_entry_alloc(vm, pdpe, start, GEN8_PDPE_SHIFT);
1112 for_each_set_bit(pdpe, new_pds, pdpes)
1113 free_pd(dev, pdp->page_directory[pdpe]);
1119 * gen8_ppgtt_alloc_page_dirpointers() - Allocate pdps for VA range.
1120 * @vm: Master vm structure.
1121 * @pml4: Page map level 4 for this address range.
1122 * @start: Starting virtual address to begin allocations.
1123 * @length: Size of the allocations.
1124 * @new_pdps: Bitmap set by function with new allocations. Likely used by the
1125 * caller to free on error.
1127 * Allocate the required number of page directory pointers. Extremely similar to
1128 * gen8_ppgtt_alloc_page_directories() and gen8_ppgtt_alloc_pagetabs().
1129 * The main difference is here we are limited by the pml4 boundary (instead of
1130 * the page directory pointer).
1132 * Return: 0 if success; negative error code otherwise.
1135 gen8_ppgtt_alloc_page_dirpointers(struct i915_address_space *vm,
1136 struct i915_pml4 *pml4,
1139 unsigned long *new_pdps)
1141 struct drm_device *dev = vm->dev;
1142 struct i915_page_directory_pointer *pdp;
1146 WARN_ON(!bitmap_empty(new_pdps, GEN8_PML4ES_PER_PML4));
1148 gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1149 if (!test_bit(pml4e, pml4->used_pml4es)) {
1150 pdp = alloc_pdp(dev);
1154 gen8_initialize_pdp(vm, pdp);
1155 pml4->pdps[pml4e] = pdp;
1156 __set_bit(pml4e, new_pdps);
1157 trace_i915_page_directory_pointer_entry_alloc(vm,
1167 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1168 free_pdp(dev, pml4->pdps[pml4e]);
1174 free_gen8_temp_bitmaps(unsigned long *new_pds, unsigned long *new_pts)
1180 /* Fills in the page directory bitmap, and the array of page tables bitmap. Both
1181 * of these are based on the number of PDPEs in the system.
1184 int __must_check alloc_gen8_temp_bitmaps(unsigned long **new_pds,
1185 unsigned long **new_pts,
1191 pds = kcalloc(BITS_TO_LONGS(pdpes), sizeof(unsigned long), GFP_TEMPORARY);
1195 pts = kcalloc(pdpes, BITS_TO_LONGS(I915_PDES) * sizeof(unsigned long),
1206 free_gen8_temp_bitmaps(pds, pts);
1210 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
1211 * the page table structures, we mark them dirty so that
1212 * context switching/execlist queuing code takes extra steps
1213 * to ensure that tlbs are flushed.
1215 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
1217 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask;
1220 static int gen8_alloc_va_range_3lvl(struct i915_address_space *vm,
1221 struct i915_page_directory_pointer *pdp,
1225 struct i915_hw_ppgtt *ppgtt =
1226 container_of(vm, struct i915_hw_ppgtt, base);
1227 unsigned long *new_page_dirs, *new_page_tables;
1228 struct drm_device *dev = vm->dev;
1229 struct i915_page_directory *pd;
1230 const uint64_t orig_start = start;
1231 const uint64_t orig_length = length;
1234 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1237 /* Wrap is never okay since we can only represent 48b, and we don't
1238 * actually use the other side of the canonical address space.
1240 if (WARN_ON(start + length < start))
1243 if (WARN_ON(start + length > vm->total))
1246 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1250 /* Do the allocations first so we can easily bail out */
1251 ret = gen8_ppgtt_alloc_page_directories(vm, pdp, start, length,
1254 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1258 /* For every page directory referenced, allocate page tables */
1259 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1260 ret = gen8_ppgtt_alloc_pagetabs(vm, pd, start, length,
1261 new_page_tables + pdpe * BITS_TO_LONGS(I915_PDES));
1267 length = orig_length;
1269 /* Allocations have completed successfully, so set the bitmaps, and do
1271 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1272 gen8_pde_t *const page_directory = kmap_px(pd);
1273 struct i915_page_table *pt;
1274 uint64_t pd_len = length;
1275 uint64_t pd_start = start;
1278 /* Every pd should be allocated, we just did that above. */
1281 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1282 /* Same reasoning as pd */
1285 WARN_ON(!gen8_pte_count(pd_start, pd_len));
1287 /* Set our used ptes within the page table */
1288 bitmap_set(pt->used_ptes,
1289 gen8_pte_index(pd_start),
1290 gen8_pte_count(pd_start, pd_len));
1292 /* Our pde is now pointing to the pagetable, pt */
1293 __set_bit(pde, pd->used_pdes);
1295 /* Map the PDE to the page table */
1296 page_directory[pde] = gen8_pde_encode(px_dma(pt),
1298 trace_i915_page_table_entry_map(&ppgtt->base, pde, pt,
1299 gen8_pte_index(start),
1300 gen8_pte_count(start, length),
1303 /* NB: We haven't yet mapped ptes to pages. At this
1304 * point we're still relying on insert_entries() */
1307 kunmap_px(ppgtt, page_directory);
1308 __set_bit(pdpe, pdp->used_pdpes);
1309 gen8_setup_page_directory(ppgtt, pdp, pd, pdpe);
1312 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1313 mark_tlbs_dirty(ppgtt);
1318 for_each_set_bit(temp, new_page_tables + pdpe *
1319 BITS_TO_LONGS(I915_PDES), I915_PDES)
1320 free_pt(dev, pdp->page_directory[pdpe]->page_table[temp]);
1323 for_each_set_bit(pdpe, new_page_dirs, pdpes)
1324 free_pd(dev, pdp->page_directory[pdpe]);
1326 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1327 mark_tlbs_dirty(ppgtt);
1331 static int gen8_alloc_va_range_4lvl(struct i915_address_space *vm,
1332 struct i915_pml4 *pml4,
1336 DECLARE_BITMAP(new_pdps, GEN8_PML4ES_PER_PML4);
1337 struct i915_hw_ppgtt *ppgtt =
1338 container_of(vm, struct i915_hw_ppgtt, base);
1339 struct i915_page_directory_pointer *pdp;
1340 uint64_t temp, pml4e;
1343 /* Do the pml4 allocations first, so we don't need to track the newly
1344 * allocated tables below the pdp */
1345 bitmap_zero(new_pdps, GEN8_PML4ES_PER_PML4);
1347 /* The pagedirectory and pagetable allocations are done in the shared 3
1348 * and 4 level code. Just allocate the pdps.
1350 ret = gen8_ppgtt_alloc_page_dirpointers(vm, pml4, start, length,
1355 WARN(bitmap_weight(new_pdps, GEN8_PML4ES_PER_PML4) > 2,
1356 "The allocation has spanned more than 512GB. "
1357 "It is highly likely this is incorrect.");
1359 gen8_for_each_pml4e(pdp, pml4, start, length, temp, pml4e) {
1362 ret = gen8_alloc_va_range_3lvl(vm, pdp, start, length);
1366 gen8_setup_page_directory_pointer(ppgtt, pml4, pdp, pml4e);
1369 bitmap_or(pml4->used_pml4es, new_pdps, pml4->used_pml4es,
1370 GEN8_PML4ES_PER_PML4);
1375 for_each_set_bit(pml4e, new_pdps, GEN8_PML4ES_PER_PML4)
1376 gen8_ppgtt_cleanup_3lvl(vm->dev, pml4->pdps[pml4e]);
1381 static int gen8_alloc_va_range(struct i915_address_space *vm,
1382 uint64_t start, uint64_t length)
1384 struct i915_hw_ppgtt *ppgtt =
1385 container_of(vm, struct i915_hw_ppgtt, base);
1387 if (USES_FULL_48BIT_PPGTT(vm->dev))
1388 return gen8_alloc_va_range_4lvl(vm, &ppgtt->pml4, start, length);
1390 return gen8_alloc_va_range_3lvl(vm, &ppgtt->pdp, start, length);
1393 static void gen8_dump_pdp(struct i915_page_directory_pointer *pdp,
1394 uint64_t start, uint64_t length,
1395 gen8_pte_t scratch_pte,
1398 struct i915_page_directory *pd;
1402 gen8_for_each_pdpe(pd, pdp, start, length, temp, pdpe) {
1403 struct i915_page_table *pt;
1404 uint64_t pd_len = length;
1405 uint64_t pd_start = start;
1408 if (!test_bit(pdpe, pdp->used_pdpes))
1411 seq_printf(m, "\tPDPE #%d\n", pdpe);
1412 gen8_for_each_pde(pt, pd, pd_start, pd_len, temp, pde) {
1414 gen8_pte_t *pt_vaddr;
1416 if (!test_bit(pde, pd->used_pdes))
1419 pt_vaddr = kmap_px(pt);
1420 for (pte = 0; pte < GEN8_PTES; pte += 4) {
1422 (pdpe << GEN8_PDPE_SHIFT) |
1423 (pde << GEN8_PDE_SHIFT) |
1424 (pte << GEN8_PTE_SHIFT);
1428 for (i = 0; i < 4; i++)
1429 if (pt_vaddr[pte + i] != scratch_pte)
1434 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1435 for (i = 0; i < 4; i++) {
1436 if (pt_vaddr[pte + i] != scratch_pte)
1437 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1439 seq_puts(m, " SCRATCH ");
1443 /* don't use kunmap_px, it could trigger
1444 * an unnecessary flush.
1446 kunmap_atomic(pt_vaddr);
1451 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1453 struct i915_address_space *vm = &ppgtt->base;
1454 uint64_t start = ppgtt->base.start;
1455 uint64_t length = ppgtt->base.total;
1456 gen8_pte_t scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
1457 I915_CACHE_LLC, true, 0);
1459 if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
1460 gen8_dump_pdp(&ppgtt->pdp, start, length, scratch_pte, m);
1462 uint64_t templ4, pml4e;
1463 struct i915_pml4 *pml4 = &ppgtt->pml4;
1464 struct i915_page_directory_pointer *pdp;
1466 gen8_for_each_pml4e(pdp, pml4, start, length, templ4, pml4e) {
1467 if (!test_bit(pml4e, pml4->used_pml4es))
1470 seq_printf(m, " PML4E #%llu\n", pml4e);
1471 gen8_dump_pdp(pdp, start, length, scratch_pte, m);
1476 static int gen8_preallocate_top_level_pdps(struct i915_hw_ppgtt *ppgtt)
1478 unsigned long *new_page_dirs, *new_page_tables;
1479 uint32_t pdpes = I915_PDPES_PER_PDP(dev);
1482 /* We allocate temp bitmap for page tables for no gain
1483 * but as this is for init only, lets keep the things simple
1485 ret = alloc_gen8_temp_bitmaps(&new_page_dirs, &new_page_tables, pdpes);
1489 /* Allocate for all pdps regardless of how the ppgtt
1492 ret = gen8_ppgtt_alloc_page_directories(&ppgtt->base, &ppgtt->pdp,
1496 *ppgtt->pdp.used_pdpes = *new_page_dirs;
1498 free_gen8_temp_bitmaps(new_page_dirs, new_page_tables);
1504 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1505 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1506 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1510 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1514 ret = gen8_init_scratch(&ppgtt->base);
1518 ppgtt->base.start = 0;
1519 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1520 ppgtt->base.allocate_va_range = gen8_alloc_va_range;
1521 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
1522 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
1523 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1524 ppgtt->base.bind_vma = ppgtt_bind_vma;
1527 * From bdw, there is support for read-only pages in the PPGTT.
1529 * XXX GVT is not honouring the lack of RW in the PTE bits.
1531 ppgtt->base.has_read_only = !intel_vgpu_active(ppgtt->base.dev);
1533 ppgtt->debug_dump = gen8_dump_ppgtt;
1535 if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
1536 ret = setup_px(ppgtt->base.dev, &ppgtt->pml4);
1540 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1542 ppgtt->base.total = 1ULL << 48;
1543 ppgtt->switch_mm = gen8_48b_mm_switch;
1545 ret = __pdp_init(ppgtt->base.dev, &ppgtt->pdp);
1549 ppgtt->base.total = 1ULL << 32;
1550 ppgtt->switch_mm = gen8_legacy_mm_switch;
1551 trace_i915_page_directory_pointer_entry_alloc(&ppgtt->base,
1555 if (intel_vgpu_active(ppgtt->base.dev)) {
1556 ret = gen8_preallocate_top_level_pdps(ppgtt);
1562 if (intel_vgpu_active(ppgtt->base.dev))
1563 gen8_ppgtt_notify_vgt(ppgtt, true);
1568 gen8_free_scratch(&ppgtt->base);
1572 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1574 struct i915_address_space *vm = &ppgtt->base;
1575 struct i915_page_table *unused;
1576 gen6_pte_t scratch_pte;
1578 uint32_t pte, pde, temp;
1579 uint32_t start = ppgtt->base.start, length = ppgtt->base.total;
1581 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1582 I915_CACHE_LLC, true, 0);
1584 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) {
1586 gen6_pte_t *pt_vaddr;
1587 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1588 pd_entry = readl(ppgtt->pd_addr + pde);
1589 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1591 if (pd_entry != expected)
1592 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1596 seq_printf(m, "\tPDE: %x\n", pd_entry);
1598 pt_vaddr = kmap_px(ppgtt->pd.page_table[pde]);
1600 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1602 (pde * PAGE_SIZE * GEN6_PTES) +
1606 for (i = 0; i < 4; i++)
1607 if (pt_vaddr[pte + i] != scratch_pte)
1612 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1613 for (i = 0; i < 4; i++) {
1614 if (pt_vaddr[pte + i] != scratch_pte)
1615 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1617 seq_puts(m, " SCRATCH ");
1621 kunmap_px(ppgtt, pt_vaddr);
1625 /* Write pde (index) from the page directory @pd to the page table @pt */
1626 static void gen6_write_pde(struct i915_page_directory *pd,
1627 const int pde, struct i915_page_table *pt)
1629 /* Caller needs to make sure the write completes if necessary */
1630 struct i915_hw_ppgtt *ppgtt =
1631 container_of(pd, struct i915_hw_ppgtt, pd);
1634 pd_entry = GEN6_PDE_ADDR_ENCODE(px_dma(pt));
1635 pd_entry |= GEN6_PDE_VALID;
1637 writel(pd_entry, ppgtt->pd_addr + pde);
1640 /* Write all the page tables found in the ppgtt structure to incrementing page
1642 static void gen6_write_page_range(struct drm_i915_private *dev_priv,
1643 struct i915_page_directory *pd,
1644 uint32_t start, uint32_t length)
1646 struct i915_page_table *pt;
1649 gen6_for_each_pde(pt, pd, start, length, temp, pde)
1650 gen6_write_pde(pd, pde, pt);
1652 /* Make sure write is complete before other code can use this page
1653 * table. Also require for WC mapped PTEs */
1654 readl(dev_priv->gtt.gsm);
1657 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1659 BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1661 return (ppgtt->pd.base.ggtt_offset / 64) << 16;
1664 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1665 struct drm_i915_gem_request *req)
1667 struct intel_engine_cs *ring = req->ring;
1670 /* NB: TLBs must be flushed and invalidated before a switch */
1671 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1675 ret = intel_ring_begin(req, 6);
1679 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1680 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1681 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1682 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1683 intel_ring_emit(ring, get_pd_offset(ppgtt));
1684 intel_ring_emit(ring, MI_NOOP);
1685 intel_ring_advance(ring);
1690 static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt,
1691 struct drm_i915_gem_request *req)
1693 struct intel_engine_cs *ring = req->ring;
1694 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev);
1696 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1697 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1701 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1702 struct drm_i915_gem_request *req)
1704 struct intel_engine_cs *ring = req->ring;
1707 /* NB: TLBs must be flushed and invalidated before a switch */
1708 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1712 ret = intel_ring_begin(req, 6);
1716 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2));
1717 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring));
1718 intel_ring_emit(ring, PP_DIR_DCLV_2G);
1719 intel_ring_emit(ring, RING_PP_DIR_BASE(ring));
1720 intel_ring_emit(ring, get_pd_offset(ppgtt));
1721 intel_ring_emit(ring, MI_NOOP);
1722 intel_ring_advance(ring);
1724 /* XXX: RCS is the only one to auto invalidate the TLBs? */
1725 if (ring->id != RCS) {
1726 ret = ring->flush(req, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
1734 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1735 struct drm_i915_gem_request *req)
1737 struct intel_engine_cs *ring = req->ring;
1738 struct drm_device *dev = ppgtt->base.dev;
1739 struct drm_i915_private *dev_priv = dev->dev_private;
1742 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G);
1743 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt));
1745 POSTING_READ(RING_PP_DIR_DCLV(ring));
1750 static void gen8_ppgtt_enable(struct drm_device *dev)
1752 struct drm_i915_private *dev_priv = dev->dev_private;
1753 struct intel_engine_cs *ring;
1756 for_each_ring(ring, dev_priv, j) {
1757 u32 four_level = USES_FULL_48BIT_PPGTT(dev) ? GEN8_GFX_PPGTT_48B : 0;
1758 I915_WRITE(RING_MODE_GEN7(ring),
1759 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1763 static void gen7_ppgtt_enable(struct drm_device *dev)
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 struct intel_engine_cs *ring;
1767 uint32_t ecochk, ecobits;
1770 ecobits = I915_READ(GAC_ECO_BITS);
1771 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1773 ecochk = I915_READ(GAM_ECOCHK);
1774 if (IS_HASWELL(dev)) {
1775 ecochk |= ECOCHK_PPGTT_WB_HSW;
1777 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1778 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1780 I915_WRITE(GAM_ECOCHK, ecochk);
1782 for_each_ring(ring, dev_priv, i) {
1783 /* GFX_MODE is per-ring on gen7+ */
1784 I915_WRITE(RING_MODE_GEN7(ring),
1785 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1789 static void gen6_ppgtt_enable(struct drm_device *dev)
1791 struct drm_i915_private *dev_priv = dev->dev_private;
1792 uint32_t ecochk, gab_ctl, ecobits;
1794 ecobits = I915_READ(GAC_ECO_BITS);
1795 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1796 ECOBITS_PPGTT_CACHE64B);
1798 gab_ctl = I915_READ(GAB_CTL);
1799 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1801 ecochk = I915_READ(GAM_ECOCHK);
1802 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1804 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1807 /* PPGTT support for Sandybdrige/Gen6 and later */
1808 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1813 struct i915_hw_ppgtt *ppgtt =
1814 container_of(vm, struct i915_hw_ppgtt, base);
1815 gen6_pte_t *pt_vaddr, scratch_pte;
1816 unsigned first_entry = start >> PAGE_SHIFT;
1817 unsigned num_entries = length >> PAGE_SHIFT;
1818 unsigned act_pt = first_entry / GEN6_PTES;
1819 unsigned first_pte = first_entry % GEN6_PTES;
1820 unsigned last_pte, i;
1822 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
1823 I915_CACHE_LLC, true, 0);
1825 while (num_entries) {
1826 last_pte = first_pte + num_entries;
1827 if (last_pte > GEN6_PTES)
1828 last_pte = GEN6_PTES;
1830 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1832 for (i = first_pte; i < last_pte; i++)
1833 pt_vaddr[i] = scratch_pte;
1835 kunmap_px(ppgtt, pt_vaddr);
1837 num_entries -= last_pte - first_pte;
1843 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1844 struct sg_table *pages,
1846 enum i915_cache_level cache_level, u32 flags)
1848 struct i915_hw_ppgtt *ppgtt =
1849 container_of(vm, struct i915_hw_ppgtt, base);
1850 gen6_pte_t *pt_vaddr;
1851 unsigned first_entry = start >> PAGE_SHIFT;
1852 unsigned act_pt = first_entry / GEN6_PTES;
1853 unsigned act_pte = first_entry % GEN6_PTES;
1854 struct sg_page_iter sg_iter;
1857 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) {
1858 if (pt_vaddr == NULL)
1859 pt_vaddr = kmap_px(ppgtt->pd.page_table[act_pt]);
1862 vm->pte_encode(sg_page_iter_dma_address(&sg_iter),
1863 cache_level, true, flags);
1865 if (++act_pte == GEN6_PTES) {
1866 kunmap_px(ppgtt, pt_vaddr);
1873 kunmap_px(ppgtt, pt_vaddr);
1876 static int gen6_alloc_va_range(struct i915_address_space *vm,
1877 uint64_t start_in, uint64_t length_in)
1879 DECLARE_BITMAP(new_page_tables, I915_PDES);
1880 struct drm_device *dev = vm->dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
1882 struct i915_hw_ppgtt *ppgtt =
1883 container_of(vm, struct i915_hw_ppgtt, base);
1884 struct i915_page_table *pt;
1885 uint32_t start, length, start_save, length_save;
1889 if (WARN_ON(start_in + length_in > ppgtt->base.total))
1892 start = start_save = start_in;
1893 length = length_save = length_in;
1895 bitmap_zero(new_page_tables, I915_PDES);
1897 /* The allocation is done in two stages so that we can bail out with
1898 * minimal amount of pain. The first stage finds new page tables that
1899 * need allocation. The second stage marks use ptes within the page
1902 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1903 if (pt != vm->scratch_pt) {
1904 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES));
1908 /* We've already allocated a page table */
1909 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES));
1917 gen6_initialize_pt(vm, pt);
1919 ppgtt->pd.page_table[pde] = pt;
1920 __set_bit(pde, new_page_tables);
1921 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT);
1925 length = length_save;
1927 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) {
1928 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES);
1930 bitmap_zero(tmp_bitmap, GEN6_PTES);
1931 bitmap_set(tmp_bitmap, gen6_pte_index(start),
1932 gen6_pte_count(start, length));
1934 if (__test_and_clear_bit(pde, new_page_tables))
1935 gen6_write_pde(&ppgtt->pd, pde, pt);
1937 trace_i915_page_table_entry_map(vm, pde, pt,
1938 gen6_pte_index(start),
1939 gen6_pte_count(start, length),
1941 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes,
1945 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES));
1947 /* Make sure write is complete before other code can use this page
1948 * table. Also require for WC mapped PTEs */
1949 readl(dev_priv->gtt.gsm);
1951 mark_tlbs_dirty(ppgtt);
1955 for_each_set_bit(pde, new_page_tables, I915_PDES) {
1956 struct i915_page_table *pt = ppgtt->pd.page_table[pde];
1958 ppgtt->pd.page_table[pde] = vm->scratch_pt;
1959 free_pt(vm->dev, pt);
1962 mark_tlbs_dirty(ppgtt);
1966 static int gen6_init_scratch(struct i915_address_space *vm)
1968 struct drm_device *dev = vm->dev;
1970 vm->scratch_page = alloc_scratch_page(dev);
1971 if (IS_ERR(vm->scratch_page))
1972 return PTR_ERR(vm->scratch_page);
1974 vm->scratch_pt = alloc_pt(dev);
1975 if (IS_ERR(vm->scratch_pt)) {
1976 free_scratch_page(dev, vm->scratch_page);
1977 return PTR_ERR(vm->scratch_pt);
1980 gen6_initialize_pt(vm, vm->scratch_pt);
1985 static void gen6_free_scratch(struct i915_address_space *vm)
1987 struct drm_device *dev = vm->dev;
1989 free_pt(dev, vm->scratch_pt);
1990 free_scratch_page(dev, vm->scratch_page);
1993 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1995 struct i915_hw_ppgtt *ppgtt =
1996 container_of(vm, struct i915_hw_ppgtt, base);
1997 struct i915_page_table *pt;
2000 drm_mm_remove_node(&ppgtt->node);
2002 gen6_for_all_pdes(pt, ppgtt, pde) {
2003 if (pt != vm->scratch_pt)
2004 free_pt(ppgtt->base.dev, pt);
2007 gen6_free_scratch(vm);
2010 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
2012 struct i915_address_space *vm = &ppgtt->base;
2013 struct drm_device *dev = ppgtt->base.dev;
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 bool retried = false;
2018 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
2019 * allocator works in address space sizes, so it's multiplied by page
2020 * size. We allocate at the top of the GTT to avoid fragmentation.
2022 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm));
2024 ret = gen6_init_scratch(vm);
2029 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm,
2030 &ppgtt->node, GEN6_PD_SIZE,
2032 0, dev_priv->gtt.base.total,
2034 if (ret == -ENOSPC && !retried) {
2035 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base,
2036 GEN6_PD_SIZE, GEN6_PD_ALIGN,
2038 0, dev_priv->gtt.base.total,
2051 if (ppgtt->node.start < dev_priv->gtt.mappable_end)
2052 DRM_DEBUG("Forced to use aperture for PDEs\n");
2057 gen6_free_scratch(vm);
2061 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
2063 return gen6_ppgtt_allocate_page_directories(ppgtt);
2066 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
2067 uint64_t start, uint64_t length)
2069 struct i915_page_table *unused;
2072 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde)
2073 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
2076 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
2078 struct drm_device *dev = ppgtt->base.dev;
2079 struct drm_i915_private *dev_priv = dev->dev_private;
2082 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode;
2084 ppgtt->switch_mm = gen6_mm_switch;
2085 } else if (IS_HASWELL(dev)) {
2086 ppgtt->switch_mm = hsw_mm_switch;
2087 } else if (IS_GEN7(dev)) {
2088 ppgtt->switch_mm = gen7_mm_switch;
2092 if (intel_vgpu_active(dev))
2093 ppgtt->switch_mm = vgpu_mm_switch;
2095 ret = gen6_ppgtt_alloc(ppgtt);
2099 ppgtt->base.allocate_va_range = gen6_alloc_va_range;
2100 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
2101 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
2102 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
2103 ppgtt->base.bind_vma = ppgtt_bind_vma;
2104 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
2105 ppgtt->base.start = 0;
2106 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
2107 ppgtt->debug_dump = gen6_dump_ppgtt;
2109 ppgtt->pd.base.ggtt_offset =
2110 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
2112 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm +
2113 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
2115 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
2117 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
2119 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2120 ppgtt->node.size >> 20,
2121 ppgtt->node.start / PAGE_SIZE);
2123 DRM_DEBUG("Adding PPGTT at offset %x\n",
2124 ppgtt->pd.base.ggtt_offset << 10);
2129 static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2131 ppgtt->base.dev = dev;
2133 if (INTEL_INFO(dev)->gen < 8)
2134 return gen6_ppgtt_init(ppgtt);
2136 return gen8_ppgtt_init(ppgtt);
2139 static void i915_address_space_init(struct i915_address_space *vm,
2140 struct drm_i915_private *dev_priv)
2142 drm_mm_init(&vm->mm, vm->start, vm->total);
2143 vm->dev = dev_priv->dev;
2144 INIT_LIST_HEAD(&vm->active_list);
2145 INIT_LIST_HEAD(&vm->inactive_list);
2146 list_add_tail(&vm->global_link, &dev_priv->vm_list);
2149 int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
2151 struct drm_i915_private *dev_priv = dev->dev_private;
2154 ret = __hw_ppgtt_init(dev, ppgtt);
2156 kref_init(&ppgtt->ref);
2157 i915_address_space_init(&ppgtt->base, dev_priv);
2163 int i915_ppgtt_init_hw(struct drm_device *dev)
2165 /* In the case of execlists, PPGTT is enabled by the context descriptor
2166 * and the PDPs are contained within the context itself. We don't
2167 * need to do anything here. */
2168 if (i915.enable_execlists)
2171 if (!USES_PPGTT(dev))
2175 gen6_ppgtt_enable(dev);
2176 else if (IS_GEN7(dev))
2177 gen7_ppgtt_enable(dev);
2178 else if (INTEL_INFO(dev)->gen >= 8)
2179 gen8_ppgtt_enable(dev);
2181 MISSING_CASE(INTEL_INFO(dev)->gen);
2186 int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
2188 struct drm_i915_private *dev_priv = req->ring->dev->dev_private;
2189 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2191 if (i915.enable_execlists)
2197 return ppgtt->switch_mm(ppgtt, req);
2200 struct i915_hw_ppgtt *
2201 i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
2203 struct i915_hw_ppgtt *ppgtt;
2206 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2208 return ERR_PTR(-ENOMEM);
2210 ret = i915_ppgtt_init(dev, ppgtt);
2213 return ERR_PTR(ret);
2216 ppgtt->file_priv = fpriv;
2218 trace_i915_ppgtt_create(&ppgtt->base);
2223 void i915_ppgtt_release(struct kref *kref)
2225 struct i915_hw_ppgtt *ppgtt =
2226 container_of(kref, struct i915_hw_ppgtt, ref);
2228 trace_i915_ppgtt_release(&ppgtt->base);
2230 /* vmas should already be unbound */
2231 WARN_ON(!list_empty(&ppgtt->base.active_list));
2232 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
2234 list_del(&ppgtt->base.global_link);
2235 drm_mm_takedown(&ppgtt->base.mm);
2237 ppgtt->base.cleanup(&ppgtt->base);
2241 extern int intel_iommu_gfx_mapped;
2242 /* Certain Gen5 chipsets require require idling the GPU before
2243 * unmapping anything from the GTT when VT-d is enabled.
2245 static bool needs_idle_maps(struct drm_device *dev)
2247 #ifdef CONFIG_INTEL_IOMMU
2248 /* Query intel_iommu to see if we need the workaround. Presumably that
2251 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped)
2257 static bool do_idling(struct drm_i915_private *dev_priv)
2259 bool ret = dev_priv->mm.interruptible;
2261 if (unlikely(dev_priv->gtt.do_idle_maps)) {
2262 dev_priv->mm.interruptible = false;
2263 if (i915_gpu_idle(dev_priv->dev)) {
2264 DRM_ERROR("Couldn't idle GPU\n");
2265 /* Wait a bit, in hopes it avoids the hang */
2273 static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
2275 if (unlikely(dev_priv->gtt.do_idle_maps))
2276 dev_priv->mm.interruptible = interruptible;
2279 void i915_check_and_clear_faults(struct drm_device *dev)
2281 struct drm_i915_private *dev_priv = dev->dev_private;
2282 struct intel_engine_cs *ring;
2285 if (INTEL_INFO(dev)->gen < 6)
2288 for_each_ring(ring, dev_priv, i) {
2290 fault_reg = I915_READ(RING_FAULT_REG(ring));
2291 if (fault_reg & RING_FAULT_VALID) {
2292 DRM_DEBUG_DRIVER("Unexpected fault\n"
2294 "\tAddress space: %s\n"
2297 fault_reg & PAGE_MASK,
2298 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2299 RING_FAULT_SRCID(fault_reg),
2300 RING_FAULT_FAULT_TYPE(fault_reg));
2301 I915_WRITE(RING_FAULT_REG(ring),
2302 fault_reg & ~RING_FAULT_VALID);
2305 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
2308 static void i915_ggtt_flush(struct drm_i915_private *dev_priv)
2310 if (INTEL_INFO(dev_priv->dev)->gen < 6) {
2311 intel_gtt_chipset_flush();
2313 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2314 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2318 void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
2320 struct drm_i915_private *dev_priv = dev->dev_private;
2322 /* Don't bother messing with faults pre GEN6 as we have little
2323 * documentation supporting that it's a good idea.
2325 if (INTEL_INFO(dev)->gen < 6)
2328 i915_check_and_clear_faults(dev);
2330 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
2331 dev_priv->gtt.base.start,
2332 dev_priv->gtt.base.total,
2335 i915_ggtt_flush(dev_priv);
2338 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
2340 if (!dma_map_sg(&obj->base.dev->pdev->dev,
2341 obj->pages->sgl, obj->pages->nents,
2342 PCI_DMA_BIDIRECTIONAL))
2348 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2353 iowrite32((u32)pte, addr);
2354 iowrite32(pte >> 32, addr + 4);
2358 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2359 struct sg_table *st,
2361 enum i915_cache_level level, u32 flags)
2363 struct drm_i915_private *dev_priv = vm->dev->dev_private;
2364 unsigned first_entry = start >> PAGE_SHIFT;
2365 gen8_pte_t __iomem *gtt_entries =
2366 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2368 struct sg_page_iter sg_iter;
2369 dma_addr_t addr = 0; /* shut up gcc */
2371 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2372 addr = sg_dma_address(sg_iter.sg) +
2373 (sg_iter.sg_pgoffset << PAGE_SHIFT);
2374 gen8_set_pte(>t_entries[i],
2375 gen8_pte_encode(addr, level, true, flags));
2380 * XXX: This serves as a posting read to make sure that the PTE has
2381 * actually been updated. There is some concern that even though
2382 * registers and PTEs are within the same BAR that they are potentially
2383 * of NUMA access patterns. Therefore, even with the way we assume
2384 * hardware should work, we must keep this posting read for paranoia.
2387 WARN_ON(readq(>t_entries[i-1])
2388 != gen8_pte_encode(addr, level, true, flags));
2390 /* This next bit makes the above posting read even more important. We
2391 * want to flush the TLBs only after we're certain all the PTE updates
2394 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2395 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2399 * Binds an object into the global gtt with the specified cache level. The object
2400 * will be accessible to the GPU via commands whose operands reference offsets
2401 * within the global GTT as well as accessible by the GPU through the GMADR
2402 * mapped BAR (dev_priv->mm.gtt->gtt).
2404 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2405 struct sg_table *st,
2407 enum i915_cache_level level, u32 flags)
2409 struct drm_i915_private *dev_priv = vm->dev->dev_private;
2410 unsigned first_entry = start >> PAGE_SHIFT;
2411 gen6_pte_t __iomem *gtt_entries =
2412 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry;
2414 struct sg_page_iter sg_iter;
2415 dma_addr_t addr = 0;
2417 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
2418 addr = sg_page_iter_dma_address(&sg_iter);
2419 iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]);
2423 /* XXX: This serves as a posting read to make sure that the PTE has
2424 * actually been updated. There is some concern that even though
2425 * registers and PTEs are within the same BAR that they are potentially
2426 * of NUMA access patterns. Therefore, even with the way we assume
2427 * hardware should work, we must keep this posting read for paranoia.
2430 unsigned long gtt = readl(>t_entries[i-1]);
2431 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags));
2434 /* This next bit makes the above posting read even more important. We
2435 * want to flush the TLBs only after we're certain all the PTE updates
2438 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
2439 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2442 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2447 struct drm_i915_private *dev_priv = vm->dev->dev_private;
2448 unsigned first_entry = start >> PAGE_SHIFT;
2449 unsigned num_entries = length >> PAGE_SHIFT;
2450 gen8_pte_t scratch_pte, __iomem *gtt_base =
2451 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2452 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2455 if (WARN(num_entries > max_entries,
2456 "First entry = %d; Num entries = %d (max=%d)\n",
2457 first_entry, num_entries, max_entries))
2458 num_entries = max_entries;
2460 scratch_pte = gen8_pte_encode(px_dma(vm->scratch_page),
2463 for (i = 0; i < num_entries; i++)
2464 gen8_set_pte(>t_base[i], scratch_pte);
2468 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2473 struct drm_i915_private *dev_priv = vm->dev->dev_private;
2474 unsigned first_entry = start >> PAGE_SHIFT;
2475 unsigned num_entries = length >> PAGE_SHIFT;
2476 gen6_pte_t scratch_pte, __iomem *gtt_base =
2477 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry;
2478 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry;
2481 if (WARN(num_entries > max_entries,
2482 "First entry = %d; Num entries = %d (max=%d)\n",
2483 first_entry, num_entries, max_entries))
2484 num_entries = max_entries;
2486 scratch_pte = vm->pte_encode(px_dma(vm->scratch_page),
2487 I915_CACHE_LLC, use_scratch, 0);
2489 for (i = 0; i < num_entries; i++)
2490 iowrite32(scratch_pte, >t_base[i]);
2494 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2495 struct sg_table *pages,
2497 enum i915_cache_level cache_level, u32 unused)
2499 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2500 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2502 intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
2506 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2511 unsigned first_entry = start >> PAGE_SHIFT;
2512 unsigned num_entries = length >> PAGE_SHIFT;
2513 intel_gtt_clear_range(first_entry, num_entries);
2516 static int ggtt_bind_vma(struct i915_vma *vma,
2517 enum i915_cache_level cache_level,
2520 struct drm_i915_gem_object *obj = vma->obj;
2524 ret = i915_get_ggtt_vma_pages(vma);
2528 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
2531 pte_flags |= PTE_READ_ONLY;
2533 vma->vm->insert_entries(vma->vm, vma->ggtt_view.pages,
2535 cache_level, pte_flags);
2538 * Without aliasing PPGTT there's no difference between
2539 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2540 * upgrade to both bound if we bind either to avoid double-binding.
2542 vma->bound |= GLOBAL_BIND | LOCAL_BIND;
2547 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2548 enum i915_cache_level cache_level,
2551 struct drm_device *dev = vma->vm->dev;
2552 struct drm_i915_private *dev_priv = dev->dev_private;
2553 struct drm_i915_gem_object *obj = vma->obj;
2554 struct sg_table *pages = obj->pages;
2558 ret = i915_get_ggtt_vma_pages(vma);
2561 pages = vma->ggtt_view.pages;
2563 /* Currently applicable only to VLV */
2565 pte_flags |= PTE_READ_ONLY;
2568 if (flags & GLOBAL_BIND) {
2569 vma->vm->insert_entries(vma->vm, pages,
2571 cache_level, pte_flags);
2574 if (flags & LOCAL_BIND) {
2575 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2576 appgtt->base.insert_entries(&appgtt->base, pages,
2578 cache_level, pte_flags);
2584 static void ggtt_unbind_vma(struct i915_vma *vma)
2586 struct drm_device *dev = vma->vm->dev;
2587 struct drm_i915_private *dev_priv = dev->dev_private;
2588 struct drm_i915_gem_object *obj = vma->obj;
2589 const uint64_t size = min_t(uint64_t,
2593 if (vma->bound & GLOBAL_BIND) {
2594 vma->vm->clear_range(vma->vm,
2600 if (dev_priv->mm.aliasing_ppgtt && vma->bound & LOCAL_BIND) {
2601 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt;
2603 appgtt->base.clear_range(&appgtt->base,
2610 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj)
2612 struct drm_device *dev = obj->base.dev;
2613 struct drm_i915_private *dev_priv = dev->dev_private;
2616 interruptible = do_idling(dev_priv);
2618 dma_unmap_sg(&dev->pdev->dev, obj->pages->sgl, obj->pages->nents,
2619 PCI_DMA_BIDIRECTIONAL);
2621 undo_idling(dev_priv, interruptible);
2624 static void i915_gtt_color_adjust(struct drm_mm_node *node,
2625 unsigned long color,
2629 if (node->color != color)
2632 if (!list_empty(&node->node_list)) {
2633 node = list_entry(node->node_list.next,
2636 if (node->allocated && node->color != color)
2641 static int i915_gem_setup_global_gtt(struct drm_device *dev,
2646 /* Let GEM Manage all of the aperture.
2648 * However, leave one page at the end still bound to the scratch page.
2649 * There are a number of places where the hardware apparently prefetches
2650 * past the end of the object, and we've seen multiple hangs with the
2651 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2652 * aperture. One page should be enough to keep any prefetching inside
2655 struct drm_i915_private *dev_priv = dev->dev_private;
2656 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base;
2657 struct drm_mm_node *entry;
2658 struct drm_i915_gem_object *obj;
2659 unsigned long hole_start, hole_end;
2662 BUG_ON(mappable_end > end);
2664 ggtt_vm->start = start;
2666 /* Subtract the guard page before address space initialization to
2667 * shrink the range used by drm_mm */
2668 ggtt_vm->total = end - start - PAGE_SIZE;
2669 i915_address_space_init(ggtt_vm, dev_priv);
2670 ggtt_vm->total += PAGE_SIZE;
2672 /* Only VLV supports read-only GGTT mappings */
2673 ggtt_vm->has_read_only = IS_VALLEYVIEW(dev_priv);
2675 if (intel_vgpu_active(dev)) {
2676 ret = intel_vgt_balloon(dev);
2682 ggtt_vm->mm.color_adjust = i915_gtt_color_adjust;
2684 /* Mark any preallocated objects as occupied */
2685 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
2686 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm);
2688 DRM_DEBUG_KMS("reserving preallocated space: %llx + %zx\n",
2689 i915_gem_obj_ggtt_offset(obj), obj->base.size);
2691 WARN_ON(i915_gem_obj_ggtt_bound(obj));
2692 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node);
2694 DRM_DEBUG_KMS("Reservation failed: %i\n", ret);
2697 vma->bound |= GLOBAL_BIND;
2698 __i915_vma_set_map_and_fenceable(vma);
2699 list_add_tail(&vma->mm_list, &ggtt_vm->inactive_list);
2702 /* Clear any non-preallocated blocks */
2703 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) {
2704 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2705 hole_start, hole_end);
2706 ggtt_vm->clear_range(ggtt_vm, hole_start,
2707 hole_end - hole_start, true);
2710 /* And finally clear the reserved guard page */
2711 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true);
2713 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) {
2714 struct i915_hw_ppgtt *ppgtt;
2716 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
2720 ret = __hw_ppgtt_init(dev, ppgtt);
2722 ppgtt->base.cleanup(&ppgtt->base);
2727 if (ppgtt->base.allocate_va_range)
2728 ret = ppgtt->base.allocate_va_range(&ppgtt->base, 0,
2731 ppgtt->base.cleanup(&ppgtt->base);
2736 ppgtt->base.clear_range(&ppgtt->base,
2741 dev_priv->mm.aliasing_ppgtt = ppgtt;
2742 WARN_ON(dev_priv->gtt.base.bind_vma != ggtt_bind_vma);
2743 dev_priv->gtt.base.bind_vma = aliasing_gtt_bind_vma;
2749 void i915_gem_init_global_gtt(struct drm_device *dev)
2751 struct drm_i915_private *dev_priv = dev->dev_private;
2752 u64 gtt_size, mappable_size;
2754 gtt_size = dev_priv->gtt.base.total;
2755 mappable_size = dev_priv->gtt.mappable_end;
2757 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size);
2760 void i915_global_gtt_cleanup(struct drm_device *dev)
2762 struct drm_i915_private *dev_priv = dev->dev_private;
2763 struct i915_address_space *vm = &dev_priv->gtt.base;
2765 if (dev_priv->mm.aliasing_ppgtt) {
2766 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2768 ppgtt->base.cleanup(&ppgtt->base);
2772 if (drm_mm_initialized(&vm->mm)) {
2773 if (intel_vgpu_active(dev))
2774 intel_vgt_deballoon();
2776 drm_mm_takedown(&vm->mm);
2777 list_del(&vm->global_link);
2783 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2785 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2786 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2787 return snb_gmch_ctl << 20;
2790 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2792 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2793 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2795 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2797 #ifdef CONFIG_X86_32
2798 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2799 if (bdw_gmch_ctl > 4)
2803 return bdw_gmch_ctl << 20;
2806 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2808 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2809 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2812 return 1 << (20 + gmch_ctrl);
2817 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2819 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2820 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2821 return snb_gmch_ctl << 25; /* 32 MB units */
2824 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2826 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2827 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2828 return bdw_gmch_ctl << 25; /* 32 MB units */
2831 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2833 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2834 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2837 * 0x0 to 0x10: 32MB increments starting at 0MB
2838 * 0x11 to 0x16: 4MB increments starting at 8MB
2839 * 0x17 to 0x1d: 4MB increments start at 36MB
2841 if (gmch_ctrl < 0x11)
2842 return gmch_ctrl << 25;
2843 else if (gmch_ctrl < 0x17)
2844 return (gmch_ctrl - 0x11 + 2) << 22;
2846 return (gmch_ctrl - 0x17 + 9) << 22;
2849 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2851 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2852 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2854 if (gen9_gmch_ctl < 0xf0)
2855 return gen9_gmch_ctl << 25; /* 32 MB units */
2857 /* 4MB increments starting at 0xf0 for 4MB */
2858 return (gen9_gmch_ctl - 0xf0 + 1) << 22;
2861 static int ggtt_probe_common(struct drm_device *dev,
2864 struct drm_i915_private *dev_priv = dev->dev_private;
2865 struct i915_page_scratch *scratch_page;
2866 phys_addr_t gtt_phys_addr;
2868 /* For Modern GENs the PTEs and register space are split in the BAR */
2869 gtt_phys_addr = pci_resource_start(dev->pdev, 0) +
2870 (pci_resource_len(dev->pdev, 0) / 2);
2873 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2874 * dropped. For WC mappings in general we have 64 byte burst writes
2875 * when the WC buffer is flushed, so we can't use it, but have to
2876 * resort to an uncached mapping. The WC issue is easily caught by the
2877 * readback check when writing GTT PTE entries.
2879 if (IS_BROXTON(dev))
2880 dev_priv->gtt.gsm = ioremap_nocache(gtt_phys_addr, gtt_size);
2882 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size);
2883 if (!dev_priv->gtt.gsm) {
2884 DRM_ERROR("Failed to map the gtt page table\n");
2888 scratch_page = alloc_scratch_page(dev);
2889 if (IS_ERR(scratch_page)) {
2890 DRM_ERROR("Scratch setup failed\n");
2891 /* iounmap will also get called at remove, but meh */
2892 iounmap(dev_priv->gtt.gsm);
2893 return PTR_ERR(scratch_page);
2896 dev_priv->gtt.base.scratch_page = scratch_page;
2901 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2902 * bits. When using advanced contexts each context stores its own PAT, but
2903 * writing this data shouldn't be harmful even in those cases. */
2904 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2908 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2909 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2910 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2911 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2912 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2913 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2914 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2915 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2917 if (!USES_PPGTT(dev_priv->dev))
2918 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2919 * so RTL will always use the value corresponding to
2921 * So let's disable cache for GGTT to avoid screen corruptions.
2922 * MOCS still can be used though.
2923 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2924 * before this patch, i.e. the same uncached + snooping access
2925 * like on gen6/7 seems to be in effect.
2926 * - So this just fixes blitter/render access. Again it looks
2927 * like it's not just uncached access, but uncached + snooping.
2928 * So we can still hold onto all our assumptions wrt cpu
2929 * clflushing on LLC machines.
2931 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2933 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2934 * write would work. */
2935 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2936 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2939 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2944 * Map WB on BDW to snooped on CHV.
2946 * Only the snoop bit has meaning for CHV, the rest is
2949 * The hardware will never snoop for certain types of accesses:
2950 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2951 * - PPGTT page tables
2952 * - some other special cycles
2954 * As with BDW, we also need to consider the following for GT accesses:
2955 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2956 * so RTL will always use the value corresponding to
2958 * Which means we must set the snoop bit in PAT entry 0
2959 * in order to keep the global status page working.
2961 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2965 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2966 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2967 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2968 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2970 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2971 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2974 static int gen8_gmch_probe(struct drm_device *dev,
2977 phys_addr_t *mappable_base,
2980 struct drm_i915_private *dev_priv = dev->dev_private;
2985 /* TODO: We're not aware of mappable constraints on gen8 yet */
2986 *mappable_base = pci_resource_start(dev->pdev, 2);
2987 *mappable_end = pci_resource_len(dev->pdev, 2);
2989 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39)))
2990 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39));
2992 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2994 if (INTEL_INFO(dev)->gen >= 9) {
2995 *stolen = gen9_get_stolen_size(snb_gmch_ctl);
2996 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
2997 } else if (IS_CHERRYVIEW(dev)) {
2998 *stolen = chv_get_stolen_size(snb_gmch_ctl);
2999 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl);
3001 *stolen = gen8_get_stolen_size(snb_gmch_ctl);
3002 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl);
3005 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
3007 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3008 chv_setup_private_ppat(dev_priv);
3010 bdw_setup_private_ppat(dev_priv);
3012 ret = ggtt_probe_common(dev, gtt_size);
3014 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range;
3015 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries;
3016 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3017 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3022 static int gen6_gmch_probe(struct drm_device *dev,
3025 phys_addr_t *mappable_base,
3028 struct drm_i915_private *dev_priv = dev->dev_private;
3029 unsigned int gtt_size;
3033 *mappable_base = pci_resource_start(dev->pdev, 2);
3034 *mappable_end = pci_resource_len(dev->pdev, 2);
3036 /* 64/512MB is the current min/max we actually know of, but this is just
3037 * a coarse sanity check.
3039 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) {
3040 DRM_ERROR("Unknown GMADR size (%llx)\n",
3041 dev_priv->gtt.mappable_end);
3045 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40)))
3046 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40));
3047 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
3049 *stolen = gen6_get_stolen_size(snb_gmch_ctl);
3051 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl);
3052 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
3054 ret = ggtt_probe_common(dev, gtt_size);
3056 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range;
3057 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries;
3058 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3059 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3064 static void gen6_gmch_remove(struct i915_address_space *vm)
3067 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
3070 free_scratch_page(vm->dev, vm->scratch_page);
3073 static int i915_gmch_probe(struct drm_device *dev,
3076 phys_addr_t *mappable_base,
3079 struct drm_i915_private *dev_priv = dev->dev_private;
3082 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL);
3084 DRM_ERROR("failed to set up gmch\n");
3088 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end);
3090 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev);
3091 dev_priv->gtt.base.insert_entries = i915_ggtt_insert_entries;
3092 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range;
3093 dev_priv->gtt.base.bind_vma = ggtt_bind_vma;
3094 dev_priv->gtt.base.unbind_vma = ggtt_unbind_vma;
3096 if (unlikely(dev_priv->gtt.do_idle_maps))
3097 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3102 static void i915_gmch_remove(struct i915_address_space *vm)
3104 intel_gmch_remove();
3107 int i915_gem_gtt_init(struct drm_device *dev)
3109 struct drm_i915_private *dev_priv = dev->dev_private;
3110 struct i915_gtt *gtt = &dev_priv->gtt;
3113 if (INTEL_INFO(dev)->gen <= 5) {
3114 gtt->gtt_probe = i915_gmch_probe;
3115 gtt->base.cleanup = i915_gmch_remove;
3116 } else if (INTEL_INFO(dev)->gen < 8) {
3117 gtt->gtt_probe = gen6_gmch_probe;
3118 gtt->base.cleanup = gen6_gmch_remove;
3119 if (IS_HASWELL(dev) && dev_priv->ellc_size)
3120 gtt->base.pte_encode = iris_pte_encode;
3121 else if (IS_HASWELL(dev))
3122 gtt->base.pte_encode = hsw_pte_encode;
3123 else if (IS_VALLEYVIEW(dev))
3124 gtt->base.pte_encode = byt_pte_encode;
3125 else if (INTEL_INFO(dev)->gen >= 7)
3126 gtt->base.pte_encode = ivb_pte_encode;
3128 gtt->base.pte_encode = snb_pte_encode;
3130 dev_priv->gtt.gtt_probe = gen8_gmch_probe;
3131 dev_priv->gtt.base.cleanup = gen6_gmch_remove;
3134 gtt->base.dev = dev;
3136 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size,
3137 >t->mappable_base, >t->mappable_end);
3141 /* GMADR is the PCI mmio aperture into the global GTT. */
3142 DRM_INFO("Memory usable by graphics device = %lluM\n",
3143 gtt->base.total >> 20);
3144 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", gtt->mappable_end >> 20);
3145 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20);
3146 #ifdef CONFIG_INTEL_IOMMU
3147 if (intel_iommu_gfx_mapped)
3148 DRM_INFO("VT-d active for gfx access\n");
3151 * i915.enable_ppgtt is read-only, so do an early pass to validate the
3152 * user's requested state against the hardware/driver capabilities. We
3153 * do this now so that we can print out any log messages once rather
3154 * than every time we check intel_enable_ppgtt().
3156 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt);
3157 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt);
3162 void i915_gem_restore_gtt_mappings(struct drm_device *dev)
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 struct drm_i915_gem_object *obj;
3166 struct i915_address_space *vm;
3167 struct i915_vma *vma;
3170 i915_check_and_clear_faults(dev);
3172 /* First fill our portion of the GTT with scratch pages */
3173 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
3174 dev_priv->gtt.base.start,
3175 dev_priv->gtt.base.total,
3178 /* Cache flush objects bound into GGTT and rebind them. */
3179 vm = &dev_priv->gtt.base;
3180 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
3182 list_for_each_entry(vma, &obj->vma_list, vma_link) {
3186 WARN_ON(i915_vma_bind(vma, obj->cache_level,
3193 i915_gem_clflush_object(obj, obj->pin_display);
3196 if (INTEL_INFO(dev)->gen >= 8) {
3197 if (IS_CHERRYVIEW(dev) || IS_BROXTON(dev))
3198 chv_setup_private_ppat(dev_priv);
3200 bdw_setup_private_ppat(dev_priv);
3205 if (USES_PPGTT(dev)) {
3206 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3207 /* TODO: Perhaps it shouldn't be gen6 specific */
3209 struct i915_hw_ppgtt *ppgtt =
3210 container_of(vm, struct i915_hw_ppgtt,
3213 if (i915_is_ggtt(vm))
3214 ppgtt = dev_priv->mm.aliasing_ppgtt;
3216 gen6_write_page_range(dev_priv, &ppgtt->pd,
3217 0, ppgtt->base.total);
3221 i915_ggtt_flush(dev_priv);
3224 static struct i915_vma *
3225 __i915_gem_vma_create(struct drm_i915_gem_object *obj,
3226 struct i915_address_space *vm,
3227 const struct i915_ggtt_view *ggtt_view)
3229 struct i915_vma *vma;
3231 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
3232 return ERR_PTR(-EINVAL);
3234 vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
3236 return ERR_PTR(-ENOMEM);
3238 INIT_LIST_HEAD(&vma->vma_link);
3239 INIT_LIST_HEAD(&vma->mm_list);
3240 INIT_LIST_HEAD(&vma->exec_list);
3244 if (i915_is_ggtt(vm))
3245 vma->ggtt_view = *ggtt_view;
3247 list_add_tail(&vma->vma_link, &obj->vma_list);
3248 if (!i915_is_ggtt(vm))
3249 i915_ppgtt_get(i915_vm_to_ppgtt(vm));
3255 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3256 struct i915_address_space *vm)
3258 struct i915_vma *vma;
3260 vma = i915_gem_obj_to_vma(obj, vm);
3262 vma = __i915_gem_vma_create(obj, vm,
3263 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL);
3269 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3270 const struct i915_ggtt_view *view)
3272 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj);
3273 struct i915_vma *vma;
3276 return ERR_PTR(-EINVAL);
3278 vma = i915_gem_obj_to_ggtt_view(obj, view);
3284 vma = __i915_gem_vma_create(obj, ggtt, view);
3290 static struct scatterlist *
3291 rotate_pages(dma_addr_t *in, unsigned int offset,
3292 unsigned int width, unsigned int height,
3293 struct sg_table *st, struct scatterlist *sg)
3295 unsigned int column, row;
3296 unsigned int src_idx;
3303 for (column = 0; column < width; column++) {
3304 src_idx = width * (height - 1) + column;
3305 for (row = 0; row < height; row++) {
3307 /* We don't need the pages, but need to initialize
3308 * the entries so the sg list can be happily traversed.
3309 * The only thing we need are DMA addresses.
3311 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3312 sg_dma_address(sg) = in[offset + src_idx];
3313 sg_dma_len(sg) = PAGE_SIZE;
3322 static struct sg_table *
3323 intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view,
3324 struct drm_i915_gem_object *obj)
3326 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info;
3327 unsigned int size_pages = rot_info->size >> PAGE_SHIFT;
3328 unsigned int size_pages_uv;
3329 struct sg_page_iter sg_iter;
3331 dma_addr_t *page_addr_list;
3332 struct sg_table *st;
3333 unsigned int uv_start_page;
3334 struct scatterlist *sg;
3337 /* Allocate a temporary list of source pages for random access. */
3338 page_addr_list = drm_malloc_ab(obj->base.size / PAGE_SIZE,
3339 sizeof(dma_addr_t));
3340 if (!page_addr_list)
3341 return ERR_PTR(ret);
3343 /* Account for UV plane with NV12. */
3344 if (rot_info->pixel_format == DRM_FORMAT_NV12)
3345 size_pages_uv = rot_info->size_uv >> PAGE_SHIFT;
3349 /* Allocate target SG list. */
3350 st = kmalloc(sizeof(*st), GFP_KERNEL);
3354 ret = sg_alloc_table(st, size_pages + size_pages_uv, GFP_KERNEL);
3358 /* Populate source page list from the object. */
3360 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) {
3361 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter);
3365 /* Rotate the pages. */
3366 sg = rotate_pages(page_addr_list, 0,
3367 rot_info->width_pages, rot_info->height_pages,
3370 /* Append the UV plane if NV12. */
3371 if (rot_info->pixel_format == DRM_FORMAT_NV12) {
3372 uv_start_page = size_pages;
3374 /* Check for tile-row un-alignment. */
3375 if (offset_in_page(rot_info->uv_offset))
3378 rot_info->uv_start_page = uv_start_page;
3380 rotate_pages(page_addr_list, uv_start_page,
3381 rot_info->width_pages_uv,
3382 rot_info->height_pages_uv,
3387 "Created rotated page mapping for object size %zu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0)).\n",
3388 obj->base.size, rot_info->pitch, rot_info->height,
3389 rot_info->pixel_format, rot_info->width_pages,
3390 rot_info->height_pages, size_pages + size_pages_uv,
3393 drm_free_large(page_addr_list);
3400 drm_free_large(page_addr_list);
3403 "Failed to create rotated mapping for object size %zu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %u pages (%u plane 0))\n",
3404 obj->base.size, ret, rot_info->pitch, rot_info->height,
3405 rot_info->pixel_format, rot_info->width_pages,
3406 rot_info->height_pages, size_pages + size_pages_uv,
3408 return ERR_PTR(ret);
3411 static struct sg_table *
3412 intel_partial_pages(const struct i915_ggtt_view *view,
3413 struct drm_i915_gem_object *obj)
3415 struct sg_table *st;
3416 struct scatterlist *sg;
3417 struct sg_page_iter obj_sg_iter;
3420 st = kmalloc(sizeof(*st), GFP_KERNEL);
3424 ret = sg_alloc_table(st, view->params.partial.size, GFP_KERNEL);
3430 for_each_sg_page(obj->pages->sgl, &obj_sg_iter, obj->pages->nents,
3431 view->params.partial.offset)
3433 if (st->nents >= view->params.partial.size)
3436 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3437 sg_dma_address(sg) = sg_page_iter_dma_address(&obj_sg_iter);
3438 sg_dma_len(sg) = PAGE_SIZE;
3449 return ERR_PTR(ret);
3453 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3457 if (vma->ggtt_view.pages)
3460 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL)
3461 vma->ggtt_view.pages = vma->obj->pages;
3462 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
3463 vma->ggtt_view.pages =
3464 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj);
3465 else if (vma->ggtt_view.type == I915_GGTT_VIEW_PARTIAL)
3466 vma->ggtt_view.pages =
3467 intel_partial_pages(&vma->ggtt_view, vma->obj);
3469 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3470 vma->ggtt_view.type);
3472 if (!vma->ggtt_view.pages) {
3473 DRM_ERROR("Failed to get pages for GGTT view type %u!\n",
3474 vma->ggtt_view.type);
3476 } else if (IS_ERR(vma->ggtt_view.pages)) {
3477 ret = PTR_ERR(vma->ggtt_view.pages);
3478 vma->ggtt_view.pages = NULL;
3479 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3480 vma->ggtt_view.type, ret);
3487 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space.
3489 * @cache_level: mapping cache level
3490 * @flags: flags like global or local mapping
3492 * DMA addresses are taken from the scatter-gather table of this object (or of
3493 * this VMA in case of non-default GGTT views) and PTE entries set up.
3494 * Note that DMA addresses are also the only part of the SG table we care about.
3496 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
3502 if (WARN_ON(flags == 0))
3506 if (flags & PIN_GLOBAL)
3507 bind_flags |= GLOBAL_BIND;
3508 if (flags & PIN_USER)
3509 bind_flags |= LOCAL_BIND;
3511 if (flags & PIN_UPDATE)
3512 bind_flags |= vma->bound;
3514 bind_flags &= ~vma->bound;
3516 if (bind_flags == 0)
3519 if (vma->bound == 0 && vma->vm->allocate_va_range) {
3520 trace_i915_va_alloc(vma->vm,
3523 VM_TO_TRACE_NAME(vma->vm));
3525 /* XXX: i915_vma_pin() will fix this +- hack */
3527 ret = vma->vm->allocate_va_range(vma->vm,
3535 ret = vma->vm->bind_vma(vma, cache_level, bind_flags);
3539 vma->bound |= bind_flags;
3545 * i915_ggtt_view_size - Get the size of a GGTT view.
3546 * @obj: Object the view is of.
3547 * @view: The view in question.
3549 * @return The size of the GGTT view in bytes.
3552 i915_ggtt_view_size(struct drm_i915_gem_object *obj,
3553 const struct i915_ggtt_view *view)
3555 if (view->type == I915_GGTT_VIEW_NORMAL) {
3556 return obj->base.size;
3557 } else if (view->type == I915_GGTT_VIEW_ROTATED) {
3558 return view->rotation_info.size;
3559 } else if (view->type == I915_GGTT_VIEW_PARTIAL) {
3560 return view->params.partial.size << PAGE_SHIFT;
3562 WARN_ONCE(1, "GGTT view %u not implemented!\n", view->type);
3563 return obj->base.size;