2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/slab.h> /* fault-inject.h is not standalone! */
28 #include <linux/fault-inject.h>
29 #include <linux/log2.h>
30 #include <linux/random.h>
31 #include <linux/seq_file.h>
32 #include <linux/stop_machine.h>
34 #include <asm/set_memory.h>
37 #include <drm/i915_drm.h>
40 #include "i915_vgpu.h"
41 #include "i915_trace.h"
42 #include "intel_drv.h"
43 #include "intel_frontbuffer.h"
45 #define I915_GFP_DMA (GFP_KERNEL | __GFP_HIGHMEM)
48 * DOC: Global GTT views
50 * Background and previous state
52 * Historically objects could exists (be bound) in global GTT space only as
53 * singular instances with a view representing all of the object's backing pages
54 * in a linear fashion. This view will be called a normal view.
56 * To support multiple views of the same object, where the number of mapped
57 * pages is not equal to the backing store, or where the layout of the pages
58 * is not linear, concept of a GGTT view was added.
60 * One example of an alternative view is a stereo display driven by a single
61 * image. In this case we would have a framebuffer looking like this
67 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
68 * rendering. In contrast, fed to the display engine would be an alternative
69 * view which could look something like this:
74 * In this example both the size and layout of pages in the alternative view is
75 * different from the normal view.
77 * Implementation and usage
79 * GGTT views are implemented using VMAs and are distinguished via enum
80 * i915_ggtt_view_type and struct i915_ggtt_view.
82 * A new flavour of core GEM functions which work with GGTT bound objects were
83 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
84 * renaming in large amounts of code. They take the struct i915_ggtt_view
85 * parameter encapsulating all metadata required to implement a view.
87 * As a helper for callers which are only interested in the normal view,
88 * globally const i915_ggtt_view_normal singleton instance exists. All old core
89 * GEM API functions, the ones not taking the view parameter, are operating on,
90 * or with the normal GGTT view.
92 * Code wanting to add or use a new GGTT view needs to:
94 * 1. Add a new enum with a suitable name.
95 * 2. Extend the metadata in the i915_ggtt_view structure if required.
96 * 3. Add support to i915_get_vma_pages().
98 * New views are required to build a scatter-gather table from within the
99 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
100 * exists for the lifetime of an VMA.
102 * Core API is designed to have copy semantics which means that passed in
103 * struct i915_ggtt_view does not need to be persistent (left around after
104 * calling the core API functions).
109 i915_get_ggtt_vma_pages(struct i915_vma *vma);
111 static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
113 /* Note that as an uncached mmio write, this should flush the
114 * WCB of the writes into the GGTT before it triggers the invalidate.
116 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
119 static void guc_ggtt_invalidate(struct drm_i915_private *dev_priv)
121 gen6_ggtt_invalidate(dev_priv);
122 I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
125 static void gmch_ggtt_invalidate(struct drm_i915_private *dev_priv)
127 intel_gtt_chipset_flush();
130 static inline void i915_ggtt_invalidate(struct drm_i915_private *i915)
132 i915->ggtt.invalidate(i915);
135 int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
138 bool has_aliasing_ppgtt;
140 bool has_full_48bit_ppgtt;
142 has_aliasing_ppgtt = dev_priv->info.has_aliasing_ppgtt;
143 has_full_ppgtt = dev_priv->info.has_full_ppgtt;
144 has_full_48bit_ppgtt = dev_priv->info.has_full_48bit_ppgtt;
146 if (intel_vgpu_active(dev_priv)) {
147 /* GVT-g has no support for 32bit ppgtt */
148 has_full_ppgtt = false;
149 has_full_48bit_ppgtt = intel_vgpu_has_full_48bit_ppgtt(dev_priv);
152 if (!has_aliasing_ppgtt)
156 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
157 * execlists, the sole mechanism available to submit work.
159 if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)
162 /* Full PPGTT is required by the Gen9 cmdparser */
163 if (enable_ppgtt == 1 && INTEL_GEN(dev_priv) != 9)
166 if (enable_ppgtt == 2 && has_full_ppgtt)
169 if (enable_ppgtt == 3 && has_full_48bit_ppgtt)
172 /* Disable ppgtt on SNB if VT-d is on. */
173 if (IS_GEN6(dev_priv) && intel_vtd_active()) {
174 DRM_INFO("Disabling PPGTT because VT-d is on\n");
178 /* Early VLV doesn't have this */
179 if (IS_VALLEYVIEW(dev_priv) && dev_priv->drm.pdev->revision < 0xb) {
180 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
184 if (INTEL_GEN(dev_priv) >= 8 && i915.enable_execlists) {
185 if (has_full_48bit_ppgtt)
192 return has_aliasing_ppgtt ? 1 : 0;
195 static int ppgtt_bind_vma(struct i915_vma *vma,
196 enum i915_cache_level cache_level,
202 if (!(vma->flags & I915_VMA_LOCAL_BIND)) {
203 ret = vma->vm->allocate_va_range(vma->vm, vma->node.start,
209 vma->pages = vma->obj->mm.pages;
211 /* Applicable to VLV, and gen8+ */
213 if (i915_gem_object_is_readonly(vma->obj))
214 pte_flags |= PTE_READ_ONLY;
216 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
221 static void ppgtt_unbind_vma(struct i915_vma *vma)
223 vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
226 static gen8_pte_t gen8_pte_encode(dma_addr_t addr,
227 enum i915_cache_level level,
230 gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
232 if (unlikely(flags & PTE_READ_ONLY))
236 case I915_CACHE_NONE:
237 pte |= PPAT_UNCACHED_INDEX;
240 pte |= PPAT_DISPLAY_ELLC_INDEX;
243 pte |= PPAT_CACHED_INDEX;
250 static gen8_pde_t gen8_pde_encode(const dma_addr_t addr,
251 const enum i915_cache_level level)
253 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW;
255 if (level != I915_CACHE_NONE)
256 pde |= PPAT_CACHED_PDE_INDEX;
258 pde |= PPAT_UNCACHED_INDEX;
262 #define gen8_pdpe_encode gen8_pde_encode
263 #define gen8_pml4e_encode gen8_pde_encode
265 static gen6_pte_t snb_pte_encode(dma_addr_t addr,
266 enum i915_cache_level level,
269 gen6_pte_t pte = GEN6_PTE_VALID;
270 pte |= GEN6_PTE_ADDR_ENCODE(addr);
273 case I915_CACHE_L3_LLC:
275 pte |= GEN6_PTE_CACHE_LLC;
277 case I915_CACHE_NONE:
278 pte |= GEN6_PTE_UNCACHED;
287 static gen6_pte_t ivb_pte_encode(dma_addr_t addr,
288 enum i915_cache_level level,
291 gen6_pte_t pte = GEN6_PTE_VALID;
292 pte |= GEN6_PTE_ADDR_ENCODE(addr);
295 case I915_CACHE_L3_LLC:
296 pte |= GEN7_PTE_CACHE_L3_LLC;
299 pte |= GEN6_PTE_CACHE_LLC;
301 case I915_CACHE_NONE:
302 pte |= GEN6_PTE_UNCACHED;
311 static gen6_pte_t byt_pte_encode(dma_addr_t addr,
312 enum i915_cache_level level,
315 gen6_pte_t pte = GEN6_PTE_VALID;
316 pte |= GEN6_PTE_ADDR_ENCODE(addr);
318 if (!(flags & PTE_READ_ONLY))
319 pte |= BYT_PTE_WRITEABLE;
321 if (level != I915_CACHE_NONE)
322 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
327 static gen6_pte_t hsw_pte_encode(dma_addr_t addr,
328 enum i915_cache_level level,
331 gen6_pte_t pte = GEN6_PTE_VALID;
332 pte |= HSW_PTE_ADDR_ENCODE(addr);
334 if (level != I915_CACHE_NONE)
335 pte |= HSW_WB_LLC_AGE3;
340 static gen6_pte_t iris_pte_encode(dma_addr_t addr,
341 enum i915_cache_level level,
344 gen6_pte_t pte = GEN6_PTE_VALID;
345 pte |= HSW_PTE_ADDR_ENCODE(addr);
348 case I915_CACHE_NONE:
351 pte |= HSW_WT_ELLC_LLC_AGE3;
354 pte |= HSW_WB_ELLC_LLC_AGE3;
361 static struct page *vm_alloc_page(struct i915_address_space *vm, gfp_t gfp)
365 if (I915_SELFTEST_ONLY(should_fail(&vm->fault_attr, 1)))
366 i915_gem_shrink_all(vm->i915);
368 if (vm->free_pages.nr)
369 return vm->free_pages.pages[--vm->free_pages.nr];
371 page = alloc_page(gfp);
376 set_pages_array_wc(&page, 1);
381 static void vm_free_pages_release(struct i915_address_space *vm)
383 GEM_BUG_ON(!pagevec_count(&vm->free_pages));
386 set_pages_array_wb(vm->free_pages.pages,
387 pagevec_count(&vm->free_pages));
389 __pagevec_release(&vm->free_pages);
392 static void vm_free_page(struct i915_address_space *vm, struct page *page)
394 if (!pagevec_add(&vm->free_pages, page))
395 vm_free_pages_release(vm);
398 static int __setup_page_dma(struct i915_address_space *vm,
399 struct i915_page_dma *p,
402 p->page = vm_alloc_page(vm, gfp | __GFP_NOWARN | __GFP_NORETRY);
403 if (unlikely(!p->page))
406 p->daddr = dma_map_page(vm->dma, p->page, 0, PAGE_SIZE,
407 PCI_DMA_BIDIRECTIONAL);
408 if (unlikely(dma_mapping_error(vm->dma, p->daddr))) {
409 vm_free_page(vm, p->page);
416 static int setup_page_dma(struct i915_address_space *vm,
417 struct i915_page_dma *p)
419 return __setup_page_dma(vm, p, I915_GFP_DMA);
422 static void cleanup_page_dma(struct i915_address_space *vm,
423 struct i915_page_dma *p)
425 dma_unmap_page(vm->dma, p->daddr, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
426 vm_free_page(vm, p->page);
429 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
431 #define setup_px(vm, px) setup_page_dma((vm), px_base(px))
432 #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
433 #define fill_px(ppgtt, px, v) fill_page_dma((vm), px_base(px), (v))
434 #define fill32_px(ppgtt, px, v) fill_page_dma_32((vm), px_base(px), (v))
436 static void fill_page_dma(struct i915_address_space *vm,
437 struct i915_page_dma *p,
440 u64 * const vaddr = kmap_atomic(p->page);
443 for (i = 0; i < 512; i++)
446 kunmap_atomic(vaddr);
449 static void fill_page_dma_32(struct i915_address_space *vm,
450 struct i915_page_dma *p,
453 fill_page_dma(vm, p, (u64)v << 32 | v);
457 setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
459 return __setup_page_dma(vm, &vm->scratch_page, gfp | __GFP_ZERO);
462 static void cleanup_scratch_page(struct i915_address_space *vm)
464 cleanup_page_dma(vm, &vm->scratch_page);
467 static struct i915_page_table *alloc_pt(struct i915_address_space *vm)
469 struct i915_page_table *pt;
471 pt = kmalloc(sizeof(*pt), GFP_KERNEL | __GFP_NOWARN);
473 return ERR_PTR(-ENOMEM);
475 if (unlikely(setup_px(vm, pt))) {
477 return ERR_PTR(-ENOMEM);
484 static void free_pt(struct i915_address_space *vm, struct i915_page_table *pt)
490 static void gen8_initialize_pt(struct i915_address_space *vm,
491 struct i915_page_table *pt)
494 gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0));
497 static void gen6_initialize_pt(struct i915_address_space *vm,
498 struct i915_page_table *pt)
501 vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0));
504 static struct i915_page_directory *alloc_pd(struct i915_address_space *vm)
506 struct i915_page_directory *pd;
508 pd = kzalloc(sizeof(*pd), GFP_KERNEL | __GFP_NOWARN);
510 return ERR_PTR(-ENOMEM);
512 if (unlikely(setup_px(vm, pd))) {
514 return ERR_PTR(-ENOMEM);
521 static void free_pd(struct i915_address_space *vm,
522 struct i915_page_directory *pd)
528 static void gen8_initialize_pd(struct i915_address_space *vm,
529 struct i915_page_directory *pd)
534 gen8_pde_encode(px_dma(vm->scratch_pt), I915_CACHE_LLC));
535 for (i = 0; i < I915_PDES; i++)
536 pd->page_table[i] = vm->scratch_pt;
539 static int __pdp_init(struct i915_address_space *vm,
540 struct i915_page_directory_pointer *pdp)
542 const unsigned int pdpes = i915_pdpes_per_pdp(vm);
545 pdp->page_directory = kmalloc_array(pdpes, sizeof(*pdp->page_directory),
546 GFP_KERNEL | __GFP_NOWARN);
547 if (unlikely(!pdp->page_directory))
550 for (i = 0; i < pdpes; i++)
551 pdp->page_directory[i] = vm->scratch_pd;
556 static void __pdp_fini(struct i915_page_directory_pointer *pdp)
558 kfree(pdp->page_directory);
559 pdp->page_directory = NULL;
562 static inline bool use_4lvl(const struct i915_address_space *vm)
564 return i915_vm_is_48bit(vm);
567 static struct i915_page_directory_pointer *
568 alloc_pdp(struct i915_address_space *vm)
570 struct i915_page_directory_pointer *pdp;
573 WARN_ON(!use_4lvl(vm));
575 pdp = kzalloc(sizeof(*pdp), GFP_KERNEL);
577 return ERR_PTR(-ENOMEM);
579 ret = __pdp_init(vm, pdp);
583 ret = setup_px(vm, pdp);
597 static void free_pdp(struct i915_address_space *vm,
598 struct i915_page_directory_pointer *pdp)
609 static void gen8_initialize_pdp(struct i915_address_space *vm,
610 struct i915_page_directory_pointer *pdp)
612 gen8_ppgtt_pdpe_t scratch_pdpe;
614 scratch_pdpe = gen8_pdpe_encode(px_dma(vm->scratch_pd), I915_CACHE_LLC);
616 fill_px(vm, pdp, scratch_pdpe);
619 static void gen8_initialize_pml4(struct i915_address_space *vm,
620 struct i915_pml4 *pml4)
625 gen8_pml4e_encode(px_dma(vm->scratch_pdp), I915_CACHE_LLC));
626 for (i = 0; i < GEN8_PML4ES_PER_PML4; i++)
627 pml4->pdps[i] = vm->scratch_pdp;
630 /* Broadwell Page Directory Pointer Descriptors */
631 static int gen8_write_pdp(struct drm_i915_gem_request *req,
635 struct intel_engine_cs *engine = req->engine;
640 cs = intel_ring_begin(req, 6);
644 *cs++ = MI_LOAD_REGISTER_IMM(1);
645 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, entry));
646 *cs++ = upper_32_bits(addr);
647 *cs++ = MI_LOAD_REGISTER_IMM(1);
648 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, entry));
649 *cs++ = lower_32_bits(addr);
650 intel_ring_advance(req, cs);
655 static int gen8_mm_switch_3lvl(struct i915_hw_ppgtt *ppgtt,
656 struct drm_i915_gem_request *req)
660 for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) {
661 const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);
663 ret = gen8_write_pdp(req, i, pd_daddr);
671 static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt *ppgtt,
672 struct drm_i915_gem_request *req)
674 return gen8_write_pdp(req, 0, px_dma(&ppgtt->pml4));
677 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
678 * the page table structures, we mark them dirty so that
679 * context switching/execlist queuing code takes extra steps
680 * to ensure that tlbs are flushed.
682 static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
684 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask;
687 /* Removes entries from a single page table, releasing it if it's empty.
688 * Caller can use the return value to update higher-level entries.
690 static bool gen8_ppgtt_clear_pt(struct i915_address_space *vm,
691 struct i915_page_table *pt,
692 u64 start, u64 length)
694 unsigned int num_entries = gen8_pte_count(start, length);
695 unsigned int pte = gen8_pte_index(start);
696 unsigned int pte_end = pte + num_entries;
697 const gen8_pte_t scratch_pte =
698 gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
701 GEM_BUG_ON(num_entries > pt->used_ptes);
703 pt->used_ptes -= num_entries;
707 vaddr = kmap_atomic_px(pt);
708 while (pte < pte_end)
709 vaddr[pte++] = scratch_pte;
710 kunmap_atomic(vaddr);
715 static void gen8_ppgtt_set_pde(struct i915_address_space *vm,
716 struct i915_page_directory *pd,
717 struct i915_page_table *pt,
722 pd->page_table[pde] = pt;
724 vaddr = kmap_atomic_px(pd);
725 vaddr[pde] = gen8_pde_encode(px_dma(pt), I915_CACHE_LLC);
726 kunmap_atomic(vaddr);
729 static bool gen8_ppgtt_clear_pd(struct i915_address_space *vm,
730 struct i915_page_directory *pd,
731 u64 start, u64 length)
733 struct i915_page_table *pt;
736 gen8_for_each_pde(pt, pd, start, length, pde) {
737 GEM_BUG_ON(pt == vm->scratch_pt);
739 if (!gen8_ppgtt_clear_pt(vm, pt, start, length))
742 gen8_ppgtt_set_pde(vm, pd, vm->scratch_pt, pde);
743 GEM_BUG_ON(!pd->used_pdes);
749 return !pd->used_pdes;
752 static void gen8_ppgtt_set_pdpe(struct i915_address_space *vm,
753 struct i915_page_directory_pointer *pdp,
754 struct i915_page_directory *pd,
757 gen8_ppgtt_pdpe_t *vaddr;
759 pdp->page_directory[pdpe] = pd;
763 vaddr = kmap_atomic_px(pdp);
764 vaddr[pdpe] = gen8_pdpe_encode(px_dma(pd), I915_CACHE_LLC);
765 kunmap_atomic(vaddr);
768 /* Removes entries from a single page dir pointer, releasing it if it's empty.
769 * Caller can use the return value to update higher-level entries
771 static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
772 struct i915_page_directory_pointer *pdp,
773 u64 start, u64 length)
775 struct i915_page_directory *pd;
778 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
779 GEM_BUG_ON(pd == vm->scratch_pd);
781 if (!gen8_ppgtt_clear_pd(vm, pd, start, length))
784 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
785 GEM_BUG_ON(!pdp->used_pdpes);
791 return !pdp->used_pdpes;
794 static void gen8_ppgtt_clear_3lvl(struct i915_address_space *vm,
795 u64 start, u64 length)
797 gen8_ppgtt_clear_pdp(vm, &i915_vm_to_ppgtt(vm)->pdp, start, length);
800 static void gen8_ppgtt_set_pml4e(struct i915_pml4 *pml4,
801 struct i915_page_directory_pointer *pdp,
804 gen8_ppgtt_pml4e_t *vaddr;
806 pml4->pdps[pml4e] = pdp;
808 vaddr = kmap_atomic_px(pml4);
809 vaddr[pml4e] = gen8_pml4e_encode(px_dma(pdp), I915_CACHE_LLC);
810 kunmap_atomic(vaddr);
813 /* Removes entries from a single pml4.
814 * This is the top-level structure in 4-level page tables used on gen8+.
815 * Empty entries are always scratch pml4e.
817 static void gen8_ppgtt_clear_4lvl(struct i915_address_space *vm,
818 u64 start, u64 length)
820 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
821 struct i915_pml4 *pml4 = &ppgtt->pml4;
822 struct i915_page_directory_pointer *pdp;
825 GEM_BUG_ON(!use_4lvl(vm));
827 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
828 GEM_BUG_ON(pdp == vm->scratch_pdp);
830 if (!gen8_ppgtt_clear_pdp(vm, pdp, start, length))
833 gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
839 static inline struct sgt_dma {
840 struct scatterlist *sg;
842 } sgt_dma(struct i915_vma *vma) {
843 struct scatterlist *sg = vma->pages->sgl;
844 dma_addr_t addr = sg_dma_address(sg);
845 return (struct sgt_dma) { sg, addr, addr + sg->length };
848 struct gen8_insert_pte {
855 static __always_inline struct gen8_insert_pte gen8_insert_pte(u64 start)
857 return (struct gen8_insert_pte) {
858 gen8_pml4e_index(start),
859 gen8_pdpe_index(start),
860 gen8_pde_index(start),
861 gen8_pte_index(start),
865 static __always_inline bool
866 gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt *ppgtt,
867 struct i915_page_directory_pointer *pdp,
868 struct sgt_dma *iter,
869 struct gen8_insert_pte *idx,
870 enum i915_cache_level cache_level,
873 struct i915_page_directory *pd;
874 const gen8_pte_t pte_encode = gen8_pte_encode(0, cache_level, flags);
878 GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base));
879 pd = pdp->page_directory[idx->pdpe];
880 vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
882 vaddr[idx->pte] = pte_encode | iter->dma;
884 iter->dma += PAGE_SIZE;
885 if (iter->dma >= iter->max) {
886 iter->sg = __sg_next(iter->sg);
892 iter->dma = sg_dma_address(iter->sg);
893 iter->max = iter->dma + iter->sg->length;
896 if (++idx->pte == GEN8_PTES) {
899 if (++idx->pde == I915_PDES) {
902 /* Limited by sg length for 3lvl */
903 if (++idx->pdpe == GEN8_PML4ES_PER_PML4) {
909 GEM_BUG_ON(idx->pdpe >= i915_pdpes_per_pdp(&ppgtt->base));
910 pd = pdp->page_directory[idx->pdpe];
913 kunmap_atomic(vaddr);
914 vaddr = kmap_atomic_px(pd->page_table[idx->pde]);
917 kunmap_atomic(vaddr);
922 static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm,
923 struct i915_vma *vma,
924 enum i915_cache_level cache_level,
927 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
928 struct sgt_dma iter = sgt_dma(vma);
929 struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
931 gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx,
935 static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm,
936 struct i915_vma *vma,
937 enum i915_cache_level cache_level,
940 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
941 struct sgt_dma iter = sgt_dma(vma);
942 struct i915_page_directory_pointer **pdps = ppgtt->pml4.pdps;
943 struct gen8_insert_pte idx = gen8_insert_pte(vma->node.start);
945 while (gen8_ppgtt_insert_pte_entries(ppgtt, pdps[idx.pml4e++], &iter,
946 &idx, cache_level, flags))
947 GEM_BUG_ON(idx.pml4e >= GEN8_PML4ES_PER_PML4);
950 static void gen8_free_page_tables(struct i915_address_space *vm,
951 struct i915_page_directory *pd)
958 for (i = 0; i < I915_PDES; i++) {
959 if (pd->page_table[i] != vm->scratch_pt)
960 free_pt(vm, pd->page_table[i]);
964 static int gen8_init_scratch(struct i915_address_space *vm)
968 ret = setup_scratch_page(vm, I915_GFP_DMA);
972 vm->scratch_pt = alloc_pt(vm);
973 if (IS_ERR(vm->scratch_pt)) {
974 ret = PTR_ERR(vm->scratch_pt);
975 goto free_scratch_page;
978 vm->scratch_pd = alloc_pd(vm);
979 if (IS_ERR(vm->scratch_pd)) {
980 ret = PTR_ERR(vm->scratch_pd);
985 vm->scratch_pdp = alloc_pdp(vm);
986 if (IS_ERR(vm->scratch_pdp)) {
987 ret = PTR_ERR(vm->scratch_pdp);
992 gen8_initialize_pt(vm, vm->scratch_pt);
993 gen8_initialize_pd(vm, vm->scratch_pd);
995 gen8_initialize_pdp(vm, vm->scratch_pdp);
1000 free_pd(vm, vm->scratch_pd);
1002 free_pt(vm, vm->scratch_pt);
1004 cleanup_scratch_page(vm);
1009 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create)
1011 struct i915_address_space *vm = &ppgtt->base;
1012 struct drm_i915_private *dev_priv = vm->i915;
1013 enum vgt_g2v_type msg;
1017 const u64 daddr = px_dma(&ppgtt->pml4);
1019 I915_WRITE(vgtif_reg(pdp[0].lo), lower_32_bits(daddr));
1020 I915_WRITE(vgtif_reg(pdp[0].hi), upper_32_bits(daddr));
1022 msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE :
1023 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY);
1025 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1026 const u64 daddr = i915_page_dir_dma_addr(ppgtt, i);
1028 I915_WRITE(vgtif_reg(pdp[i].lo), lower_32_bits(daddr));
1029 I915_WRITE(vgtif_reg(pdp[i].hi), upper_32_bits(daddr));
1032 msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE :
1033 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY);
1036 I915_WRITE(vgtif_reg(g2v_notify), msg);
1041 static void gen8_free_scratch(struct i915_address_space *vm)
1044 free_pdp(vm, vm->scratch_pdp);
1045 free_pd(vm, vm->scratch_pd);
1046 free_pt(vm, vm->scratch_pt);
1047 cleanup_scratch_page(vm);
1050 static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space *vm,
1051 struct i915_page_directory_pointer *pdp)
1053 const unsigned int pdpes = i915_pdpes_per_pdp(vm);
1056 for (i = 0; i < pdpes; i++) {
1057 if (pdp->page_directory[i] == vm->scratch_pd)
1060 gen8_free_page_tables(vm, pdp->page_directory[i]);
1061 free_pd(vm, pdp->page_directory[i]);
1067 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt *ppgtt)
1071 for (i = 0; i < GEN8_PML4ES_PER_PML4; i++) {
1072 if (ppgtt->pml4.pdps[i] == ppgtt->base.scratch_pdp)
1075 gen8_ppgtt_cleanup_3lvl(&ppgtt->base, ppgtt->pml4.pdps[i]);
1078 cleanup_px(&ppgtt->base, &ppgtt->pml4);
1081 static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
1083 struct drm_i915_private *dev_priv = vm->i915;
1084 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1086 if (intel_vgpu_active(dev_priv))
1087 gen8_ppgtt_notify_vgt(ppgtt, false);
1090 gen8_ppgtt_cleanup_4lvl(ppgtt);
1092 gen8_ppgtt_cleanup_3lvl(&ppgtt->base, &ppgtt->pdp);
1094 gen8_free_scratch(vm);
1097 static int gen8_ppgtt_alloc_pd(struct i915_address_space *vm,
1098 struct i915_page_directory *pd,
1099 u64 start, u64 length)
1101 struct i915_page_table *pt;
1105 gen8_for_each_pde(pt, pd, start, length, pde) {
1106 if (pt == vm->scratch_pt) {
1111 gen8_initialize_pt(vm, pt);
1113 gen8_ppgtt_set_pde(vm, pd, pt, pde);
1115 GEM_BUG_ON(pd->used_pdes > I915_PDES);
1118 pt->used_ptes += gen8_pte_count(start, length);
1123 gen8_ppgtt_clear_pd(vm, pd, from, start - from);
1127 static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm,
1128 struct i915_page_directory_pointer *pdp,
1129 u64 start, u64 length)
1131 struct i915_page_directory *pd;
1136 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1137 if (pd == vm->scratch_pd) {
1142 gen8_initialize_pd(vm, pd);
1143 gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
1145 GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm));
1147 mark_tlbs_dirty(i915_vm_to_ppgtt(vm));
1150 ret = gen8_ppgtt_alloc_pd(vm, pd, start, length);
1158 if (!pd->used_pdes) {
1159 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
1160 GEM_BUG_ON(!pdp->used_pdpes);
1165 gen8_ppgtt_clear_pdp(vm, pdp, from, start - from);
1169 static int gen8_ppgtt_alloc_3lvl(struct i915_address_space *vm,
1170 u64 start, u64 length)
1172 return gen8_ppgtt_alloc_pdp(vm,
1173 &i915_vm_to_ppgtt(vm)->pdp, start, length);
1176 static int gen8_ppgtt_alloc_4lvl(struct i915_address_space *vm,
1177 u64 start, u64 length)
1179 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1180 struct i915_pml4 *pml4 = &ppgtt->pml4;
1181 struct i915_page_directory_pointer *pdp;
1186 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1187 if (pml4->pdps[pml4e] == vm->scratch_pdp) {
1188 pdp = alloc_pdp(vm);
1192 gen8_initialize_pdp(vm, pdp);
1193 gen8_ppgtt_set_pml4e(pml4, pdp, pml4e);
1196 ret = gen8_ppgtt_alloc_pdp(vm, pdp, start, length);
1204 if (!pdp->used_pdpes) {
1205 gen8_ppgtt_set_pml4e(pml4, vm->scratch_pdp, pml4e);
1209 gen8_ppgtt_clear_4lvl(vm, from, start - from);
1213 static void gen8_dump_pdp(struct i915_hw_ppgtt *ppgtt,
1214 struct i915_page_directory_pointer *pdp,
1215 u64 start, u64 length,
1216 gen8_pte_t scratch_pte,
1219 struct i915_address_space *vm = &ppgtt->base;
1220 struct i915_page_directory *pd;
1223 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1224 struct i915_page_table *pt;
1225 u64 pd_len = length;
1226 u64 pd_start = start;
1229 if (pdp->page_directory[pdpe] == ppgtt->base.scratch_pd)
1232 seq_printf(m, "\tPDPE #%d\n", pdpe);
1233 gen8_for_each_pde(pt, pd, pd_start, pd_len, pde) {
1235 gen8_pte_t *pt_vaddr;
1237 if (pd->page_table[pde] == ppgtt->base.scratch_pt)
1240 pt_vaddr = kmap_atomic_px(pt);
1241 for (pte = 0; pte < GEN8_PTES; pte += 4) {
1242 u64 va = (pdpe << GEN8_PDPE_SHIFT |
1243 pde << GEN8_PDE_SHIFT |
1244 pte << GEN8_PTE_SHIFT);
1248 for (i = 0; i < 4; i++)
1249 if (pt_vaddr[pte + i] != scratch_pte)
1254 seq_printf(m, "\t\t0x%llx [%03d,%03d,%04d]: =", va, pdpe, pde, pte);
1255 for (i = 0; i < 4; i++) {
1256 if (pt_vaddr[pte + i] != scratch_pte)
1257 seq_printf(m, " %llx", pt_vaddr[pte + i]);
1259 seq_puts(m, " SCRATCH ");
1263 kunmap_atomic(pt_vaddr);
1268 static void gen8_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1270 struct i915_address_space *vm = &ppgtt->base;
1271 const gen8_pte_t scratch_pte =
1272 gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
1273 u64 start = 0, length = ppgtt->base.total;
1277 struct i915_pml4 *pml4 = &ppgtt->pml4;
1278 struct i915_page_directory_pointer *pdp;
1280 gen8_for_each_pml4e(pdp, pml4, start, length, pml4e) {
1281 if (pml4->pdps[pml4e] == ppgtt->base.scratch_pdp)
1284 seq_printf(m, " PML4E #%llu\n", pml4e);
1285 gen8_dump_pdp(ppgtt, pdp, start, length, scratch_pte, m);
1288 gen8_dump_pdp(ppgtt, &ppgtt->pdp, start, length, scratch_pte, m);
1292 static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt *ppgtt)
1294 struct i915_address_space *vm = &ppgtt->base;
1295 struct i915_page_directory_pointer *pdp = &ppgtt->pdp;
1296 struct i915_page_directory *pd;
1297 u64 start = 0, length = ppgtt->base.total;
1301 gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
1306 gen8_initialize_pd(vm, pd);
1307 gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
1311 pdp->used_pdpes++; /* never remove */
1316 gen8_for_each_pdpe(pd, pdp, from, start, pdpe) {
1317 gen8_ppgtt_set_pdpe(vm, pdp, vm->scratch_pd, pdpe);
1320 pdp->used_pdpes = 0;
1325 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1326 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1327 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1331 static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1333 struct i915_address_space *vm = &ppgtt->base;
1334 struct drm_i915_private *dev_priv = vm->i915;
1337 ppgtt->base.total = USES_FULL_48BIT_PPGTT(dev_priv) ?
1341 ret = gen8_init_scratch(&ppgtt->base);
1343 ppgtt->base.total = 0;
1348 * From bdw, there is support for read-only pages in the PPGTT.
1350 * XXX GVT is not honouring the lack of RW in the PTE bits.
1352 ppgtt->base.has_read_only = !intel_vgpu_active(dev_priv);
1354 /* There are only few exceptions for gen >=6. chv and bxt.
1355 * And we are not sure about the latter so play safe for now.
1357 if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
1358 ppgtt->base.pt_kmap_wc = true;
1361 ret = setup_px(&ppgtt->base, &ppgtt->pml4);
1365 gen8_initialize_pml4(&ppgtt->base, &ppgtt->pml4);
1367 ppgtt->switch_mm = gen8_mm_switch_4lvl;
1368 ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_4lvl;
1369 ppgtt->base.insert_entries = gen8_ppgtt_insert_4lvl;
1370 ppgtt->base.clear_range = gen8_ppgtt_clear_4lvl;
1372 ret = __pdp_init(&ppgtt->base, &ppgtt->pdp);
1376 if (intel_vgpu_active(dev_priv)) {
1377 ret = gen8_preallocate_top_level_pdp(ppgtt);
1379 __pdp_fini(&ppgtt->pdp);
1384 ppgtt->switch_mm = gen8_mm_switch_3lvl;
1385 ppgtt->base.allocate_va_range = gen8_ppgtt_alloc_3lvl;
1386 ppgtt->base.insert_entries = gen8_ppgtt_insert_3lvl;
1387 ppgtt->base.clear_range = gen8_ppgtt_clear_3lvl;
1390 if (intel_vgpu_active(dev_priv))
1391 gen8_ppgtt_notify_vgt(ppgtt, true);
1393 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
1394 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1395 ppgtt->base.bind_vma = ppgtt_bind_vma;
1396 ppgtt->debug_dump = gen8_dump_ppgtt;
1401 gen8_free_scratch(&ppgtt->base);
1405 static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m)
1407 struct i915_address_space *vm = &ppgtt->base;
1408 struct i915_page_table *unused;
1409 gen6_pte_t scratch_pte;
1410 u32 pd_entry, pte, pde;
1411 u32 start = 0, length = ppgtt->base.total;
1413 scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
1416 gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde) {
1418 gen6_pte_t *pt_vaddr;
1419 const dma_addr_t pt_addr = px_dma(ppgtt->pd.page_table[pde]);
1420 pd_entry = readl(ppgtt->pd_addr + pde);
1421 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID);
1423 if (pd_entry != expected)
1424 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1428 seq_printf(m, "\tPDE: %x\n", pd_entry);
1430 pt_vaddr = kmap_atomic_px(ppgtt->pd.page_table[pde]);
1432 for (pte = 0; pte < GEN6_PTES; pte+=4) {
1434 (pde * PAGE_SIZE * GEN6_PTES) +
1438 for (i = 0; i < 4; i++)
1439 if (pt_vaddr[pte + i] != scratch_pte)
1444 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte);
1445 for (i = 0; i < 4; i++) {
1446 if (pt_vaddr[pte + i] != scratch_pte)
1447 seq_printf(m, " %08x", pt_vaddr[pte + i]);
1449 seq_puts(m, " SCRATCH ");
1453 kunmap_atomic(pt_vaddr);
1457 /* Write pde (index) from the page directory @pd to the page table @pt */
1458 static inline void gen6_write_pde(const struct i915_hw_ppgtt *ppgtt,
1459 const unsigned int pde,
1460 const struct i915_page_table *pt)
1462 /* Caller needs to make sure the write completes if necessary */
1463 writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt)) | GEN6_PDE_VALID,
1464 ppgtt->pd_addr + pde);
1467 /* Write all the page tables found in the ppgtt structure to incrementing page
1469 static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt,
1470 u32 start, u32 length)
1472 struct i915_page_table *pt;
1475 gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde)
1476 gen6_write_pde(ppgtt, pde, pt);
1478 mark_tlbs_dirty(ppgtt);
1482 static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
1484 GEM_BUG_ON(ppgtt->pd.base.ggtt_offset & 0x3f);
1485 return ppgtt->pd.base.ggtt_offset << 10;
1488 static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
1489 struct drm_i915_gem_request *req)
1491 struct intel_engine_cs *engine = req->engine;
1494 /* NB: TLBs must be flushed and invalidated before a switch */
1495 cs = intel_ring_begin(req, 6);
1499 *cs++ = MI_LOAD_REGISTER_IMM(2);
1500 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
1501 *cs++ = PP_DIR_DCLV_2G;
1502 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1503 *cs++ = get_pd_offset(ppgtt);
1505 intel_ring_advance(req, cs);
1510 static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt,
1511 struct drm_i915_gem_request *req)
1513 struct intel_engine_cs *engine = req->engine;
1516 /* NB: TLBs must be flushed and invalidated before a switch */
1517 cs = intel_ring_begin(req, 6);
1521 *cs++ = MI_LOAD_REGISTER_IMM(2);
1522 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine));
1523 *cs++ = PP_DIR_DCLV_2G;
1524 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
1525 *cs++ = get_pd_offset(ppgtt);
1527 intel_ring_advance(req, cs);
1532 static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt,
1533 struct drm_i915_gem_request *req)
1535 struct intel_engine_cs *engine = req->engine;
1536 struct drm_i915_private *dev_priv = req->i915;
1538 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
1539 I915_WRITE(RING_PP_DIR_BASE(engine), get_pd_offset(ppgtt));
1543 static void gen8_ppgtt_enable(struct drm_i915_private *dev_priv)
1545 struct intel_engine_cs *engine;
1546 enum intel_engine_id id;
1548 for_each_engine(engine, dev_priv, id) {
1549 u32 four_level = USES_FULL_48BIT_PPGTT(dev_priv) ?
1550 GEN8_GFX_PPGTT_48B : 0;
1551 I915_WRITE(RING_MODE_GEN7(engine),
1552 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE | four_level));
1556 static void gen7_ppgtt_enable(struct drm_i915_private *dev_priv)
1558 struct intel_engine_cs *engine;
1559 u32 ecochk, ecobits;
1560 enum intel_engine_id id;
1562 ecobits = I915_READ(GAC_ECO_BITS);
1563 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B);
1565 ecochk = I915_READ(GAM_ECOCHK);
1566 if (IS_HASWELL(dev_priv)) {
1567 ecochk |= ECOCHK_PPGTT_WB_HSW;
1569 ecochk |= ECOCHK_PPGTT_LLC_IVB;
1570 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB;
1572 I915_WRITE(GAM_ECOCHK, ecochk);
1574 for_each_engine(engine, dev_priv, id) {
1575 /* GFX_MODE is per-ring on gen7+ */
1576 I915_WRITE(RING_MODE_GEN7(engine),
1577 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1581 static void gen6_ppgtt_enable(struct drm_i915_private *dev_priv)
1583 u32 ecochk, gab_ctl, ecobits;
1585 ecobits = I915_READ(GAC_ECO_BITS);
1586 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT |
1587 ECOBITS_PPGTT_CACHE64B);
1589 gab_ctl = I915_READ(GAB_CTL);
1590 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT);
1592 ecochk = I915_READ(GAM_ECOCHK);
1593 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B);
1595 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
1598 /* PPGTT support for Sandybdrige/Gen6 and later */
1599 static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
1600 u64 start, u64 length)
1602 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1603 unsigned int first_entry = start >> PAGE_SHIFT;
1604 unsigned int pde = first_entry / GEN6_PTES;
1605 unsigned int pte = first_entry % GEN6_PTES;
1606 unsigned int num_entries = length >> PAGE_SHIFT;
1607 gen6_pte_t scratch_pte =
1608 vm->pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
1610 while (num_entries) {
1611 struct i915_page_table *pt = ppgtt->pd.page_table[pde++];
1612 unsigned int end = min(pte + num_entries, GEN6_PTES);
1615 num_entries -= end - pte;
1617 /* Note that the hw doesn't support removing PDE on the fly
1618 * (they are cached inside the context with no means to
1619 * invalidate the cache), so we can only reset the PTE
1620 * entries back to scratch.
1623 vaddr = kmap_atomic_px(pt);
1625 vaddr[pte++] = scratch_pte;
1626 } while (pte < end);
1627 kunmap_atomic(vaddr);
1633 static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
1634 struct i915_vma *vma,
1635 enum i915_cache_level cache_level,
1638 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1639 unsigned first_entry = vma->node.start >> PAGE_SHIFT;
1640 unsigned act_pt = first_entry / GEN6_PTES;
1641 unsigned act_pte = first_entry % GEN6_PTES;
1642 const u32 pte_encode = vm->pte_encode(0, cache_level, flags);
1643 struct sgt_dma iter = sgt_dma(vma);
1646 vaddr = kmap_atomic_px(ppgtt->pd.page_table[act_pt]);
1648 vaddr[act_pte] = pte_encode | GEN6_PTE_ADDR_ENCODE(iter.dma);
1650 iter.dma += PAGE_SIZE;
1651 if (iter.dma == iter.max) {
1652 iter.sg = __sg_next(iter.sg);
1656 iter.dma = sg_dma_address(iter.sg);
1657 iter.max = iter.dma + iter.sg->length;
1660 if (++act_pte == GEN6_PTES) {
1661 kunmap_atomic(vaddr);
1662 vaddr = kmap_atomic_px(ppgtt->pd.page_table[++act_pt]);
1666 kunmap_atomic(vaddr);
1669 static int gen6_alloc_va_range(struct i915_address_space *vm,
1670 u64 start, u64 length)
1672 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1673 struct i915_page_table *pt;
1678 gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde) {
1679 if (pt == vm->scratch_pt) {
1684 gen6_initialize_pt(vm, pt);
1685 ppgtt->pd.page_table[pde] = pt;
1686 gen6_write_pde(ppgtt, pde, pt);
1692 mark_tlbs_dirty(ppgtt);
1699 gen6_ppgtt_clear_range(vm, from, start);
1703 static int gen6_init_scratch(struct i915_address_space *vm)
1707 ret = setup_scratch_page(vm, I915_GFP_DMA);
1711 vm->scratch_pt = alloc_pt(vm);
1712 if (IS_ERR(vm->scratch_pt)) {
1713 cleanup_scratch_page(vm);
1714 return PTR_ERR(vm->scratch_pt);
1717 gen6_initialize_pt(vm, vm->scratch_pt);
1722 static void gen6_free_scratch(struct i915_address_space *vm)
1724 free_pt(vm, vm->scratch_pt);
1725 cleanup_scratch_page(vm);
1728 static void gen6_ppgtt_cleanup(struct i915_address_space *vm)
1730 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
1731 struct i915_page_directory *pd = &ppgtt->pd;
1732 struct i915_page_table *pt;
1735 drm_mm_remove_node(&ppgtt->node);
1737 gen6_for_all_pdes(pt, pd, pde)
1738 if (pt != vm->scratch_pt)
1741 gen6_free_scratch(vm);
1744 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt)
1746 struct i915_address_space *vm = &ppgtt->base;
1747 struct drm_i915_private *dev_priv = ppgtt->base.i915;
1748 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1751 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1752 * allocator works in address space sizes, so it's multiplied by page
1753 * size. We allocate at the top of the GTT to avoid fragmentation.
1755 BUG_ON(!drm_mm_initialized(&ggtt->base.mm));
1757 ret = gen6_init_scratch(vm);
1761 ret = i915_gem_gtt_insert(&ggtt->base, &ppgtt->node,
1762 GEN6_PD_SIZE, GEN6_PD_ALIGN,
1763 I915_COLOR_UNEVICTABLE,
1764 0, ggtt->base.total,
1769 if (ppgtt->node.start < ggtt->mappable_end)
1770 DRM_DEBUG("Forced to use aperture for PDEs\n");
1772 ppgtt->pd.base.ggtt_offset =
1773 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t);
1775 ppgtt->pd_addr = (gen6_pte_t __iomem *)ggtt->gsm +
1776 ppgtt->pd.base.ggtt_offset / sizeof(gen6_pte_t);
1781 gen6_free_scratch(vm);
1785 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt)
1787 return gen6_ppgtt_allocate_page_directories(ppgtt);
1790 static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt,
1791 u64 start, u64 length)
1793 struct i915_page_table *unused;
1796 gen6_for_each_pde(unused, &ppgtt->pd, start, length, pde)
1797 ppgtt->pd.page_table[pde] = ppgtt->base.scratch_pt;
1800 static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
1802 struct drm_i915_private *dev_priv = ppgtt->base.i915;
1803 struct i915_ggtt *ggtt = &dev_priv->ggtt;
1806 ppgtt->base.pte_encode = ggtt->base.pte_encode;
1807 if (intel_vgpu_active(dev_priv) || IS_GEN6(dev_priv))
1808 ppgtt->switch_mm = gen6_mm_switch;
1809 else if (IS_HASWELL(dev_priv))
1810 ppgtt->switch_mm = hsw_mm_switch;
1811 else if (IS_GEN7(dev_priv))
1812 ppgtt->switch_mm = gen7_mm_switch;
1816 ret = gen6_ppgtt_alloc(ppgtt);
1820 ppgtt->base.total = I915_PDES * GEN6_PTES * PAGE_SIZE;
1822 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total);
1823 gen6_write_page_range(ppgtt, 0, ppgtt->base.total);
1825 ret = gen6_alloc_va_range(&ppgtt->base, 0, ppgtt->base.total);
1827 gen6_ppgtt_cleanup(&ppgtt->base);
1831 ppgtt->base.clear_range = gen6_ppgtt_clear_range;
1832 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
1833 ppgtt->base.unbind_vma = ppgtt_unbind_vma;
1834 ppgtt->base.bind_vma = ppgtt_bind_vma;
1835 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
1836 ppgtt->debug_dump = gen6_dump_ppgtt;
1838 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
1839 ppgtt->node.size >> 20,
1840 ppgtt->node.start / PAGE_SIZE);
1842 DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n",
1843 ppgtt->pd.base.ggtt_offset << 10);
1848 static int __hw_ppgtt_init(struct i915_hw_ppgtt *ppgtt,
1849 struct drm_i915_private *dev_priv)
1851 ppgtt->base.i915 = dev_priv;
1852 ppgtt->base.dma = &dev_priv->drm.pdev->dev;
1854 if (INTEL_INFO(dev_priv)->gen < 8)
1855 return gen6_ppgtt_init(ppgtt);
1857 return gen8_ppgtt_init(ppgtt);
1860 static void i915_address_space_init(struct i915_address_space *vm,
1861 struct drm_i915_private *dev_priv,
1864 i915_gem_timeline_init(dev_priv, &vm->timeline, name);
1866 drm_mm_init(&vm->mm, 0, vm->total);
1867 vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;
1869 INIT_LIST_HEAD(&vm->active_list);
1870 INIT_LIST_HEAD(&vm->inactive_list);
1871 INIT_LIST_HEAD(&vm->unbound_list);
1873 list_add_tail(&vm->global_link, &dev_priv->vm_list);
1874 pagevec_init(&vm->free_pages, false);
1877 static void i915_address_space_fini(struct i915_address_space *vm)
1879 if (pagevec_count(&vm->free_pages))
1880 vm_free_pages_release(vm);
1882 i915_gem_timeline_fini(&vm->timeline);
1883 drm_mm_takedown(&vm->mm);
1884 list_del(&vm->global_link);
1887 static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
1889 /* This function is for gtt related workarounds. This function is
1890 * called on driver load and after a GPU reset, so you can place
1891 * workarounds here even if they get overwritten by GPU reset.
1893 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
1894 if (IS_BROADWELL(dev_priv))
1895 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
1896 else if (IS_CHERRYVIEW(dev_priv))
1897 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
1898 else if (IS_GEN9_BC(dev_priv))
1899 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
1900 else if (IS_GEN9_LP(dev_priv))
1901 I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
1904 int i915_ppgtt_init_hw(struct drm_i915_private *dev_priv)
1906 gtt_write_workarounds(dev_priv);
1908 /* In the case of execlists, PPGTT is enabled by the context descriptor
1909 * and the PDPs are contained within the context itself. We don't
1910 * need to do anything here. */
1911 if (i915.enable_execlists)
1914 if (!USES_PPGTT(dev_priv))
1917 if (IS_GEN6(dev_priv))
1918 gen6_ppgtt_enable(dev_priv);
1919 else if (IS_GEN7(dev_priv))
1920 gen7_ppgtt_enable(dev_priv);
1921 else if (INTEL_GEN(dev_priv) >= 8)
1922 gen8_ppgtt_enable(dev_priv);
1924 MISSING_CASE(INTEL_GEN(dev_priv));
1929 struct i915_hw_ppgtt *
1930 i915_ppgtt_create(struct drm_i915_private *dev_priv,
1931 struct drm_i915_file_private *fpriv,
1934 struct i915_hw_ppgtt *ppgtt;
1937 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL);
1939 return ERR_PTR(-ENOMEM);
1941 ret = __hw_ppgtt_init(ppgtt, dev_priv);
1944 return ERR_PTR(ret);
1947 kref_init(&ppgtt->ref);
1948 i915_address_space_init(&ppgtt->base, dev_priv, name);
1949 ppgtt->base.file = fpriv;
1951 trace_i915_ppgtt_create(&ppgtt->base);
1956 void i915_ppgtt_close(struct i915_address_space *vm)
1958 struct list_head *phases[] = {
1965 GEM_BUG_ON(vm->closed);
1968 for (phase = phases; *phase; phase++) {
1969 struct i915_vma *vma, *vn;
1971 list_for_each_entry_safe(vma, vn, *phase, vm_link)
1972 if (!i915_vma_is_closed(vma))
1973 i915_vma_close(vma);
1977 void i915_ppgtt_release(struct kref *kref)
1979 struct i915_hw_ppgtt *ppgtt =
1980 container_of(kref, struct i915_hw_ppgtt, ref);
1982 trace_i915_ppgtt_release(&ppgtt->base);
1984 /* vmas should already be unbound and destroyed */
1985 WARN_ON(!list_empty(&ppgtt->base.active_list));
1986 WARN_ON(!list_empty(&ppgtt->base.inactive_list));
1987 WARN_ON(!list_empty(&ppgtt->base.unbound_list));
1989 ppgtt->base.cleanup(&ppgtt->base);
1990 i915_address_space_fini(&ppgtt->base);
1994 /* Certain Gen5 chipsets require require idling the GPU before
1995 * unmapping anything from the GTT when VT-d is enabled.
1997 static bool needs_idle_maps(struct drm_i915_private *dev_priv)
1999 /* Query intel_iommu to see if we need the workaround. Presumably that
2002 return IS_GEN5(dev_priv) && IS_MOBILE(dev_priv) && intel_vtd_active();
2005 void i915_check_and_clear_faults(struct drm_i915_private *dev_priv)
2007 struct intel_engine_cs *engine;
2008 enum intel_engine_id id;
2010 if (INTEL_INFO(dev_priv)->gen < 6)
2013 for_each_engine(engine, dev_priv, id) {
2015 fault_reg = I915_READ(RING_FAULT_REG(engine));
2016 if (fault_reg & RING_FAULT_VALID) {
2017 DRM_DEBUG_DRIVER("Unexpected fault\n"
2019 "\tAddress space: %s\n"
2022 fault_reg & PAGE_MASK,
2023 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
2024 RING_FAULT_SRCID(fault_reg),
2025 RING_FAULT_FAULT_TYPE(fault_reg));
2026 I915_WRITE(RING_FAULT_REG(engine),
2027 fault_reg & ~RING_FAULT_VALID);
2031 /* Engine specific init may not have been done till this point. */
2032 if (dev_priv->engine[RCS])
2033 POSTING_READ(RING_FAULT_REG(dev_priv->engine[RCS]));
2036 void i915_gem_suspend_gtt_mappings(struct drm_i915_private *dev_priv)
2038 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2040 /* Don't bother messing with faults pre GEN6 as we have little
2041 * documentation supporting that it's a good idea.
2043 if (INTEL_GEN(dev_priv) < 6)
2046 i915_check_and_clear_faults(dev_priv);
2048 ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total);
2050 i915_ggtt_invalidate(dev_priv);
2053 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object *obj,
2054 struct sg_table *pages)
2057 if (dma_map_sg(&obj->base.dev->pdev->dev,
2058 pages->sgl, pages->nents,
2059 PCI_DMA_BIDIRECTIONAL))
2062 /* If the DMA remap fails, one cause can be that we have
2063 * too many objects pinned in a small remapping table,
2064 * such as swiotlb. Incrementally purge all other objects and
2065 * try again - if there are no more pages to remove from
2066 * the DMA remapper, i915_gem_shrink will return 0.
2068 GEM_BUG_ON(obj->mm.pages == pages);
2069 } while (i915_gem_shrink(to_i915(obj->base.dev),
2070 obj->base.size >> PAGE_SHIFT, NULL,
2072 I915_SHRINK_UNBOUND |
2073 I915_SHRINK_ACTIVE));
2078 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
2083 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
2086 enum i915_cache_level level,
2089 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2090 gen8_pte_t __iomem *pte =
2091 (gen8_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT);
2093 gen8_set_pte(pte, gen8_pte_encode(addr, level, 0));
2095 ggtt->invalidate(vm->i915);
2098 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
2099 struct i915_vma *vma,
2100 enum i915_cache_level level,
2103 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2104 struct sgt_iter sgt_iter;
2105 gen8_pte_t __iomem *gtt_entries;
2106 const gen8_pte_t pte_encode = gen8_pte_encode(0, level, 0);
2110 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
2111 * not to allow the user to override access to a read only page.
2114 gtt_entries = (gen8_pte_t __iomem *)ggtt->gsm;
2115 gtt_entries += vma->node.start >> PAGE_SHIFT;
2116 for_each_sgt_dma(addr, sgt_iter, vma->pages)
2117 gen8_set_pte(gtt_entries++, pte_encode | addr);
2121 /* This next bit makes the above posting read even more important. We
2122 * want to flush the TLBs only after we're certain all the PTE updates
2125 ggtt->invalidate(vm->i915);
2128 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
2131 enum i915_cache_level level,
2134 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2135 gen6_pte_t __iomem *pte =
2136 (gen6_pte_t __iomem *)ggtt->gsm + (offset >> PAGE_SHIFT);
2138 iowrite32(vm->pte_encode(addr, level, flags), pte);
2140 ggtt->invalidate(vm->i915);
2144 * Binds an object into the global gtt with the specified cache level. The object
2145 * will be accessible to the GPU via commands whose operands reference offsets
2146 * within the global GTT as well as accessible by the GPU through the GMADR
2147 * mapped BAR (dev_priv->mm.gtt->gtt).
2149 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
2150 struct i915_vma *vma,
2151 enum i915_cache_level level,
2154 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2155 gen6_pte_t __iomem *entries = (gen6_pte_t __iomem *)ggtt->gsm;
2156 unsigned int i = vma->node.start >> PAGE_SHIFT;
2157 struct sgt_iter iter;
2159 for_each_sgt_dma(addr, iter, vma->pages)
2160 iowrite32(vm->pte_encode(addr, level, flags), &entries[i++]);
2163 /* This next bit makes the above posting read even more important. We
2164 * want to flush the TLBs only after we're certain all the PTE updates
2167 ggtt->invalidate(vm->i915);
2170 static void nop_clear_range(struct i915_address_space *vm,
2171 u64 start, u64 length)
2175 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
2176 u64 start, u64 length)
2178 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2179 unsigned first_entry = start >> PAGE_SHIFT;
2180 unsigned num_entries = length >> PAGE_SHIFT;
2181 const gen8_pte_t scratch_pte =
2182 gen8_pte_encode(vm->scratch_page.daddr, I915_CACHE_LLC, 0);
2183 gen8_pte_t __iomem *gtt_base =
2184 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
2185 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2188 if (WARN(num_entries > max_entries,
2189 "First entry = %d; Num entries = %d (max=%d)\n",
2190 first_entry, num_entries, max_entries))
2191 num_entries = max_entries;
2193 for (i = 0; i < num_entries; i++)
2194 gen8_set_pte(>t_base[i], scratch_pte);
2197 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
2199 struct drm_i915_private *dev_priv = vm->i915;
2202 * Make sure the internal GAM fifo has been cleared of all GTT
2203 * writes before exiting stop_machine(). This guarantees that
2204 * any aperture accesses waiting to start in another process
2205 * cannot back up behind the GTT writes causing a hang.
2206 * The register can be any arbitrary GAM register.
2208 POSTING_READ(GFX_FLSH_CNTL_GEN6);
2211 struct insert_page {
2212 struct i915_address_space *vm;
2215 enum i915_cache_level level;
2218 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
2220 struct insert_page *arg = _arg;
2222 gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
2223 bxt_vtd_ggtt_wa(arg->vm);
2228 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
2231 enum i915_cache_level level,
2234 struct insert_page arg = { vm, addr, offset, level };
2236 stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
2239 struct insert_entries {
2240 struct i915_address_space *vm;
2241 struct i915_vma *vma;
2242 enum i915_cache_level level;
2246 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
2248 struct insert_entries *arg = _arg;
2250 gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, arg->flags);
2251 bxt_vtd_ggtt_wa(arg->vm);
2256 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
2257 struct i915_vma *vma,
2258 enum i915_cache_level level,
2261 struct insert_entries arg = { vm, vma, level, flags };
2263 stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
2266 struct clear_range {
2267 struct i915_address_space *vm;
2272 static int bxt_vtd_ggtt_clear_range__cb(void *_arg)
2274 struct clear_range *arg = _arg;
2276 gen8_ggtt_clear_range(arg->vm, arg->start, arg->length);
2277 bxt_vtd_ggtt_wa(arg->vm);
2282 static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space *vm,
2286 struct clear_range arg = { vm, start, length };
2288 stop_machine(bxt_vtd_ggtt_clear_range__cb, &arg, NULL);
2291 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
2292 u64 start, u64 length)
2294 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2295 unsigned first_entry = start >> PAGE_SHIFT;
2296 unsigned num_entries = length >> PAGE_SHIFT;
2297 gen6_pte_t scratch_pte, __iomem *gtt_base =
2298 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
2299 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
2302 if (WARN(num_entries > max_entries,
2303 "First entry = %d; Num entries = %d (max=%d)\n",
2304 first_entry, num_entries, max_entries))
2305 num_entries = max_entries;
2307 scratch_pte = vm->pte_encode(vm->scratch_page.daddr,
2310 for (i = 0; i < num_entries; i++)
2311 iowrite32(scratch_pte, >t_base[i]);
2314 static void i915_ggtt_insert_page(struct i915_address_space *vm,
2317 enum i915_cache_level cache_level,
2320 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2321 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2323 intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
2326 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
2327 struct i915_vma *vma,
2328 enum i915_cache_level cache_level,
2331 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
2332 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
2334 intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
2338 static void i915_ggtt_clear_range(struct i915_address_space *vm,
2339 u64 start, u64 length)
2341 intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
2344 static int ggtt_bind_vma(struct i915_vma *vma,
2345 enum i915_cache_level cache_level,
2348 struct drm_i915_private *i915 = vma->vm->i915;
2349 struct drm_i915_gem_object *obj = vma->obj;
2352 if (unlikely(!vma->pages)) {
2353 int ret = i915_get_ggtt_vma_pages(vma);
2358 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
2360 if (i915_gem_object_is_readonly(obj))
2361 pte_flags |= PTE_READ_ONLY;
2363 intel_runtime_pm_get(i915);
2364 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
2365 intel_runtime_pm_put(i915);
2368 * Without aliasing PPGTT there's no difference between
2369 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2370 * upgrade to both bound if we bind either to avoid double-binding.
2372 vma->flags |= I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
2377 static void ggtt_unbind_vma(struct i915_vma *vma)
2379 struct drm_i915_private *i915 = vma->vm->i915;
2381 intel_runtime_pm_get(i915);
2382 vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
2383 intel_runtime_pm_put(i915);
2386 static int aliasing_gtt_bind_vma(struct i915_vma *vma,
2387 enum i915_cache_level cache_level,
2390 struct drm_i915_private *i915 = vma->vm->i915;
2394 if (unlikely(!vma->pages)) {
2395 ret = i915_get_ggtt_vma_pages(vma);
2400 /* Currently applicable only to VLV */
2402 if (i915_gem_object_is_readonly(vma->obj))
2403 pte_flags |= PTE_READ_ONLY;
2405 if (flags & I915_VMA_LOCAL_BIND) {
2406 struct i915_hw_ppgtt *appgtt = i915->mm.aliasing_ppgtt;
2408 if (!(vma->flags & I915_VMA_LOCAL_BIND) &&
2409 appgtt->base.allocate_va_range) {
2410 ret = appgtt->base.allocate_va_range(&appgtt->base,
2417 appgtt->base.insert_entries(&appgtt->base, vma, cache_level,
2421 if (flags & I915_VMA_GLOBAL_BIND) {
2422 intel_runtime_pm_get(i915);
2423 vma->vm->insert_entries(vma->vm, vma, cache_level, pte_flags);
2424 intel_runtime_pm_put(i915);
2430 if (!(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND))) {
2431 if (vma->pages != vma->obj->mm.pages) {
2432 GEM_BUG_ON(!vma->pages);
2433 sg_free_table(vma->pages);
2441 static void aliasing_gtt_unbind_vma(struct i915_vma *vma)
2443 struct drm_i915_private *i915 = vma->vm->i915;
2445 if (vma->flags & I915_VMA_GLOBAL_BIND) {
2446 intel_runtime_pm_get(i915);
2447 vma->vm->clear_range(vma->vm, vma->node.start, vma->size);
2448 intel_runtime_pm_put(i915);
2451 if (vma->flags & I915_VMA_LOCAL_BIND) {
2452 struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->base;
2454 vm->clear_range(vm, vma->node.start, vma->size);
2458 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object *obj,
2459 struct sg_table *pages)
2461 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
2462 struct device *kdev = &dev_priv->drm.pdev->dev;
2463 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2465 if (unlikely(ggtt->do_idle_maps)) {
2466 if (i915_gem_wait_for_idle(dev_priv, 0)) {
2467 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2468 /* Wait a bit, in hopes it avoids the hang */
2473 dma_unmap_sg(kdev, pages->sgl, pages->nents, PCI_DMA_BIDIRECTIONAL);
2476 static void i915_gtt_color_adjust(const struct drm_mm_node *node,
2477 unsigned long color,
2481 if (node->allocated && node->color != color)
2482 *start += I915_GTT_PAGE_SIZE;
2484 /* Also leave a space between the unallocated reserved node after the
2485 * GTT and any objects within the GTT, i.e. we use the color adjustment
2486 * to insert a guard page to prevent prefetches crossing over the
2489 node = list_next_entry(node, node_list);
2490 if (node->color != color)
2491 *end -= I915_GTT_PAGE_SIZE;
2494 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private *i915)
2496 struct i915_ggtt *ggtt = &i915->ggtt;
2497 struct i915_hw_ppgtt *ppgtt;
2500 ppgtt = i915_ppgtt_create(i915, ERR_PTR(-EPERM), "[alias]");
2502 return PTR_ERR(ppgtt);
2504 if (WARN_ON(ppgtt->base.total < ggtt->base.total)) {
2509 if (ppgtt->base.allocate_va_range) {
2510 /* Note we only pre-allocate as far as the end of the global
2511 * GTT. On 48b / 4-level page-tables, the difference is very,
2512 * very significant! We have to preallocate as GVT/vgpu does
2513 * not like the page directory disappearing.
2515 err = ppgtt->base.allocate_va_range(&ppgtt->base,
2516 0, ggtt->base.total);
2521 i915->mm.aliasing_ppgtt = ppgtt;
2523 WARN_ON(ggtt->base.bind_vma != ggtt_bind_vma);
2524 ggtt->base.bind_vma = aliasing_gtt_bind_vma;
2526 WARN_ON(ggtt->base.unbind_vma != ggtt_unbind_vma);
2527 ggtt->base.unbind_vma = aliasing_gtt_unbind_vma;
2532 i915_ppgtt_put(ppgtt);
2536 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private *i915)
2538 struct i915_ggtt *ggtt = &i915->ggtt;
2539 struct i915_hw_ppgtt *ppgtt;
2541 ppgtt = fetch_and_zero(&i915->mm.aliasing_ppgtt);
2545 i915_ppgtt_put(ppgtt);
2547 ggtt->base.bind_vma = ggtt_bind_vma;
2548 ggtt->base.unbind_vma = ggtt_unbind_vma;
2551 int i915_gem_init_ggtt(struct drm_i915_private *dev_priv)
2553 /* Let GEM Manage all of the aperture.
2555 * However, leave one page at the end still bound to the scratch page.
2556 * There are a number of places where the hardware apparently prefetches
2557 * past the end of the object, and we've seen multiple hangs with the
2558 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2559 * aperture. One page should be enough to keep any prefetching inside
2562 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2563 unsigned long hole_start, hole_end;
2564 struct drm_mm_node *entry;
2567 ret = intel_vgt_balloon(dev_priv);
2571 /* Reserve a mappable slot for our lockless error capture */
2572 ret = drm_mm_insert_node_in_range(&ggtt->base.mm, &ggtt->error_capture,
2573 PAGE_SIZE, 0, I915_COLOR_UNEVICTABLE,
2574 0, ggtt->mappable_end,
2579 /* Clear any non-preallocated blocks */
2580 drm_mm_for_each_hole(entry, &ggtt->base.mm, hole_start, hole_end) {
2581 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2582 hole_start, hole_end);
2583 ggtt->base.clear_range(&ggtt->base, hole_start,
2584 hole_end - hole_start);
2587 /* And finally clear the reserved guard page */
2588 ggtt->base.clear_range(&ggtt->base,
2589 ggtt->base.total - PAGE_SIZE, PAGE_SIZE);
2591 if (USES_PPGTT(dev_priv) && !USES_FULL_PPGTT(dev_priv)) {
2592 ret = i915_gem_init_aliasing_ppgtt(dev_priv);
2600 drm_mm_remove_node(&ggtt->error_capture);
2605 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2606 * @dev_priv: i915 device
2608 void i915_ggtt_cleanup_hw(struct drm_i915_private *dev_priv)
2610 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2611 struct i915_vma *vma, *vn;
2613 ggtt->base.closed = true;
2615 mutex_lock(&dev_priv->drm.struct_mutex);
2616 WARN_ON(!list_empty(&ggtt->base.active_list));
2617 list_for_each_entry_safe(vma, vn, &ggtt->base.inactive_list, vm_link)
2618 WARN_ON(i915_vma_unbind(vma));
2619 mutex_unlock(&dev_priv->drm.struct_mutex);
2621 i915_gem_cleanup_stolen(&dev_priv->drm);
2623 mutex_lock(&dev_priv->drm.struct_mutex);
2624 i915_gem_fini_aliasing_ppgtt(dev_priv);
2626 if (drm_mm_node_allocated(&ggtt->error_capture))
2627 drm_mm_remove_node(&ggtt->error_capture);
2629 if (drm_mm_initialized(&ggtt->base.mm)) {
2630 intel_vgt_deballoon(dev_priv);
2631 i915_address_space_fini(&ggtt->base);
2634 ggtt->base.cleanup(&ggtt->base);
2635 mutex_unlock(&dev_priv->drm.struct_mutex);
2637 arch_phys_wc_del(ggtt->mtrr);
2638 io_mapping_fini(&ggtt->mappable);
2641 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
2643 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
2644 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
2645 return snb_gmch_ctl << 20;
2648 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
2650 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
2651 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
2653 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
2655 #ifdef CONFIG_X86_32
2656 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2657 if (bdw_gmch_ctl > 4)
2661 return bdw_gmch_ctl << 20;
2664 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
2666 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
2667 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
2670 return 1 << (20 + gmch_ctrl);
2675 static size_t gen6_get_stolen_size(u16 snb_gmch_ctl)
2677 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT;
2678 snb_gmch_ctl &= SNB_GMCH_GMS_MASK;
2679 return (size_t)snb_gmch_ctl << 25; /* 32 MB units */
2682 static size_t gen8_get_stolen_size(u16 bdw_gmch_ctl)
2684 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2685 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK;
2686 return (size_t)bdw_gmch_ctl << 25; /* 32 MB units */
2689 static size_t chv_get_stolen_size(u16 gmch_ctrl)
2691 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
2692 gmch_ctrl &= SNB_GMCH_GMS_MASK;
2695 * 0x0 to 0x10: 32MB increments starting at 0MB
2696 * 0x11 to 0x16: 4MB increments starting at 8MB
2697 * 0x17 to 0x1d: 4MB increments start at 36MB
2699 if (gmch_ctrl < 0x11)
2700 return (size_t)gmch_ctrl << 25;
2701 else if (gmch_ctrl < 0x17)
2702 return (size_t)(gmch_ctrl - 0x11 + 2) << 22;
2704 return (size_t)(gmch_ctrl - 0x17 + 9) << 22;
2707 static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl)
2709 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT;
2710 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK;
2712 if (gen9_gmch_ctl < 0xf0)
2713 return (size_t)gen9_gmch_ctl << 25; /* 32 MB units */
2715 /* 4MB increments starting at 0xf0 for 4MB */
2716 return (size_t)(gen9_gmch_ctl - 0xf0 + 1) << 22;
2719 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
2721 struct drm_i915_private *dev_priv = ggtt->base.i915;
2722 struct pci_dev *pdev = dev_priv->drm.pdev;
2723 phys_addr_t phys_addr;
2726 /* For Modern GENs the PTEs and register space are split in the BAR */
2727 phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
2730 * On BXT writes larger than 64 bit to the GTT pagetable range will be
2731 * dropped. For WC mappings in general we have 64 byte burst writes
2732 * when the WC buffer is flushed, so we can't use it, but have to
2733 * resort to an uncached mapping. The WC issue is easily caught by the
2734 * readback check when writing GTT PTE entries.
2736 if (IS_GEN9_LP(dev_priv))
2737 ggtt->gsm = ioremap_nocache(phys_addr, size);
2739 ggtt->gsm = ioremap_wc(phys_addr, size);
2741 DRM_ERROR("Failed to map the ggtt page table\n");
2745 ret = setup_scratch_page(&ggtt->base, GFP_DMA32);
2747 DRM_ERROR("Scratch setup failed\n");
2748 /* iounmap will also get called at remove, but meh */
2756 static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
2758 /* XXX: spec is unclear if this is still needed for CNL+ */
2759 if (!USES_PPGTT(dev_priv)) {
2760 I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_UC);
2764 I915_WRITE(GEN10_PAT_INDEX(0), GEN8_PPAT_WB | GEN8_PPAT_LLC);
2765 I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
2766 I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
2767 I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
2768 I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
2769 I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
2770 I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
2771 I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2774 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
2775 * bits. When using advanced contexts each context stores its own PAT, but
2776 * writing this data shouldn't be harmful even in those cases. */
2777 static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
2781 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */
2782 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */
2783 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */
2784 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */
2785 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) |
2786 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) |
2787 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
2788 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
2790 if (!USES_PPGTT(dev_priv))
2791 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
2792 * so RTL will always use the value corresponding to
2794 * So let's disable cache for GGTT to avoid screen corruptions.
2795 * MOCS still can be used though.
2796 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
2797 * before this patch, i.e. the same uncached + snooping access
2798 * like on gen6/7 seems to be in effect.
2799 * - So this just fixes blitter/render access. Again it looks
2800 * like it's not just uncached access, but uncached + snooping.
2801 * So we can still hold onto all our assumptions wrt cpu
2802 * clflushing on LLC machines.
2804 pat = GEN8_PPAT(0, GEN8_PPAT_UC);
2806 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
2807 * write would work. */
2808 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2809 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2812 static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
2817 * Map WB on BDW to snooped on CHV.
2819 * Only the snoop bit has meaning for CHV, the rest is
2822 * The hardware will never snoop for certain types of accesses:
2823 * - CPU GTT (GMADR->GGTT->no snoop->memory)
2824 * - PPGTT page tables
2825 * - some other special cycles
2827 * As with BDW, we also need to consider the following for GT accesses:
2828 * "For GGTT, there is NO pat_sel[2:0] from the entry,
2829 * so RTL will always use the value corresponding to
2831 * Which means we must set the snoop bit in PAT entry 0
2832 * in order to keep the global status page working.
2834 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
2838 GEN8_PPAT(4, CHV_PPAT_SNOOP) |
2839 GEN8_PPAT(5, CHV_PPAT_SNOOP) |
2840 GEN8_PPAT(6, CHV_PPAT_SNOOP) |
2841 GEN8_PPAT(7, CHV_PPAT_SNOOP);
2843 I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
2844 I915_WRITE(GEN8_PRIVATE_PAT_HI, pat >> 32);
2847 static void gen6_gmch_remove(struct i915_address_space *vm)
2849 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
2852 cleanup_scratch_page(vm);
2855 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
2857 struct drm_i915_private *dev_priv = ggtt->base.i915;
2858 struct pci_dev *pdev = dev_priv->drm.pdev;
2863 /* TODO: We're not aware of mappable constraints on gen8 yet */
2864 ggtt->mappable_base = pci_resource_start(pdev, 2);
2865 ggtt->mappable_end = pci_resource_len(pdev, 2);
2867 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
2869 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
2871 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
2873 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2875 if (INTEL_GEN(dev_priv) >= 9) {
2876 ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
2877 size = gen8_get_total_gtt_size(snb_gmch_ctl);
2878 } else if (IS_CHERRYVIEW(dev_priv)) {
2879 ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
2880 size = chv_get_total_gtt_size(snb_gmch_ctl);
2882 ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
2883 size = gen8_get_total_gtt_size(snb_gmch_ctl);
2886 ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
2888 if (INTEL_GEN(dev_priv) >= 10)
2889 cnl_setup_private_ppat(dev_priv);
2890 else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
2891 chv_setup_private_ppat(dev_priv);
2893 bdw_setup_private_ppat(dev_priv);
2895 ggtt->base.cleanup = gen6_gmch_remove;
2896 ggtt->base.bind_vma = ggtt_bind_vma;
2897 ggtt->base.unbind_vma = ggtt_unbind_vma;
2898 ggtt->base.insert_page = gen8_ggtt_insert_page;
2899 ggtt->base.clear_range = nop_clear_range;
2900 if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv))
2901 ggtt->base.clear_range = gen8_ggtt_clear_range;
2903 ggtt->base.insert_entries = gen8_ggtt_insert_entries;
2905 /* Serialize GTT updates with aperture access on BXT if VT-d is on. */
2906 if (intel_ggtt_update_needs_vtd_wa(dev_priv)) {
2907 ggtt->base.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
2908 ggtt->base.insert_page = bxt_vtd_ggtt_insert_page__BKL;
2909 if (ggtt->base.clear_range != nop_clear_range)
2910 ggtt->base.clear_range = bxt_vtd_ggtt_clear_range__BKL;
2913 ggtt->invalidate = gen6_ggtt_invalidate;
2915 return ggtt_probe_common(ggtt, size);
2918 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
2920 struct drm_i915_private *dev_priv = ggtt->base.i915;
2921 struct pci_dev *pdev = dev_priv->drm.pdev;
2926 ggtt->mappable_base = pci_resource_start(pdev, 2);
2927 ggtt->mappable_end = pci_resource_len(pdev, 2);
2929 /* 64/512MB is the current min/max we actually know of, but this is just
2930 * a coarse sanity check.
2932 if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
2933 DRM_ERROR("Unknown GMADR size (%llx)\n", ggtt->mappable_end);
2937 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
2939 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
2941 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
2942 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
2944 ggtt->stolen_size = gen6_get_stolen_size(snb_gmch_ctl);
2946 size = gen6_get_total_gtt_size(snb_gmch_ctl);
2947 ggtt->base.total = (size / sizeof(gen6_pte_t)) << PAGE_SHIFT;
2949 ggtt->base.clear_range = gen6_ggtt_clear_range;
2950 ggtt->base.insert_page = gen6_ggtt_insert_page;
2951 ggtt->base.insert_entries = gen6_ggtt_insert_entries;
2952 ggtt->base.bind_vma = ggtt_bind_vma;
2953 ggtt->base.unbind_vma = ggtt_unbind_vma;
2954 ggtt->base.cleanup = gen6_gmch_remove;
2956 ggtt->invalidate = gen6_ggtt_invalidate;
2958 if (HAS_EDRAM(dev_priv))
2959 ggtt->base.pte_encode = iris_pte_encode;
2960 else if (IS_HASWELL(dev_priv))
2961 ggtt->base.pte_encode = hsw_pte_encode;
2962 else if (IS_VALLEYVIEW(dev_priv))
2963 ggtt->base.pte_encode = byt_pte_encode;
2964 else if (INTEL_GEN(dev_priv) >= 7)
2965 ggtt->base.pte_encode = ivb_pte_encode;
2967 ggtt->base.pte_encode = snb_pte_encode;
2969 return ggtt_probe_common(ggtt, size);
2972 static void i915_gmch_remove(struct i915_address_space *vm)
2974 intel_gmch_remove();
2977 static int i915_gmch_probe(struct i915_ggtt *ggtt)
2979 struct drm_i915_private *dev_priv = ggtt->base.i915;
2982 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->drm.pdev, NULL);
2984 DRM_ERROR("failed to set up gmch\n");
2988 intel_gtt_get(&ggtt->base.total,
2990 &ggtt->mappable_base,
2991 &ggtt->mappable_end);
2993 ggtt->do_idle_maps = needs_idle_maps(dev_priv);
2994 ggtt->base.insert_page = i915_ggtt_insert_page;
2995 ggtt->base.insert_entries = i915_ggtt_insert_entries;
2996 ggtt->base.clear_range = i915_ggtt_clear_range;
2997 ggtt->base.bind_vma = ggtt_bind_vma;
2998 ggtt->base.unbind_vma = ggtt_unbind_vma;
2999 ggtt->base.cleanup = i915_gmch_remove;
3001 ggtt->invalidate = gmch_ggtt_invalidate;
3003 if (unlikely(ggtt->do_idle_maps))
3004 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3010 * i915_ggtt_probe_hw - Probe GGTT hardware location
3011 * @dev_priv: i915 device
3013 int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
3015 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3018 ggtt->base.i915 = dev_priv;
3019 ggtt->base.dma = &dev_priv->drm.pdev->dev;
3021 if (INTEL_GEN(dev_priv) <= 5)
3022 ret = i915_gmch_probe(ggtt);
3023 else if (INTEL_GEN(dev_priv) < 8)
3024 ret = gen6_gmch_probe(ggtt);
3026 ret = gen8_gmch_probe(ggtt);
3030 /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
3031 * This is easier than doing range restriction on the fly, as we
3032 * currently don't have any bits spare to pass in this upper
3035 if (HAS_GUC(dev_priv) && i915.enable_guc_loading) {
3036 ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
3037 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3040 if ((ggtt->base.total - 1) >> 32) {
3041 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3042 " of address space! Found %lldM!\n",
3043 ggtt->base.total >> 20);
3044 ggtt->base.total = 1ULL << 32;
3045 ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
3048 if (ggtt->mappable_end > ggtt->base.total) {
3049 DRM_ERROR("mappable aperture extends past end of GGTT,"
3050 " aperture=%llx, total=%llx\n",
3051 ggtt->mappable_end, ggtt->base.total);
3052 ggtt->mappable_end = ggtt->base.total;
3055 /* GMADR is the PCI mmio aperture into the global GTT. */
3056 DRM_INFO("Memory usable by graphics device = %lluM\n",
3057 ggtt->base.total >> 20);
3058 DRM_DEBUG_DRIVER("GMADR size = %lldM\n", ggtt->mappable_end >> 20);
3059 DRM_DEBUG_DRIVER("GTT stolen size = %uM\n", ggtt->stolen_size >> 20);
3060 if (intel_vtd_active())
3061 DRM_INFO("VT-d active for gfx access\n");
3067 * i915_ggtt_init_hw - Initialize GGTT hardware
3068 * @dev_priv: i915 device
3070 int i915_ggtt_init_hw(struct drm_i915_private *dev_priv)
3072 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3075 INIT_LIST_HEAD(&dev_priv->vm_list);
3077 /* Note that we use page colouring to enforce a guard page at the
3078 * end of the address space. This is required as the CS may prefetch
3079 * beyond the end of the batch buffer, across the page boundary,
3080 * and beyond the end of the GTT if we do not provide a guard.
3082 mutex_lock(&dev_priv->drm.struct_mutex);
3083 i915_address_space_init(&ggtt->base, dev_priv, "[global]");
3085 /* Only VLV supports read-only GGTT mappings */
3086 ggtt->base.has_read_only = IS_VALLEYVIEW(dev_priv);
3088 if (!HAS_LLC(dev_priv) && !USES_PPGTT(dev_priv))
3089 ggtt->base.mm.color_adjust = i915_gtt_color_adjust;
3090 mutex_unlock(&dev_priv->drm.struct_mutex);
3092 if (!io_mapping_init_wc(&dev_priv->ggtt.mappable,
3093 dev_priv->ggtt.mappable_base,
3094 dev_priv->ggtt.mappable_end)) {
3096 goto out_gtt_cleanup;
3099 ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base, ggtt->mappable_end);
3102 * Initialise stolen early so that we may reserve preallocated
3103 * objects for the BIOS to KMS transition.
3105 ret = i915_gem_init_stolen(dev_priv);
3107 goto out_gtt_cleanup;
3112 ggtt->base.cleanup(&ggtt->base);
3116 int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv)
3118 if (INTEL_GEN(dev_priv) < 6 && !intel_enable_gtt())
3123 void i915_ggtt_enable_guc(struct drm_i915_private *i915)
3125 GEM_BUG_ON(i915->ggtt.invalidate != gen6_ggtt_invalidate);
3127 i915->ggtt.invalidate = guc_ggtt_invalidate;
3130 void i915_ggtt_disable_guc(struct drm_i915_private *i915)
3132 /* We should only be called after i915_ggtt_enable_guc() */
3133 GEM_BUG_ON(i915->ggtt.invalidate != guc_ggtt_invalidate);
3135 i915->ggtt.invalidate = gen6_ggtt_invalidate;
3138 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv)
3140 struct i915_ggtt *ggtt = &dev_priv->ggtt;
3141 struct drm_i915_gem_object *obj, *on;
3143 i915_check_and_clear_faults(dev_priv);
3145 /* First fill our portion of the GTT with scratch pages */
3146 ggtt->base.clear_range(&ggtt->base, 0, ggtt->base.total);
3148 ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */
3150 /* clflush objects bound into the GGTT and rebind them. */
3151 list_for_each_entry_safe(obj, on,
3152 &dev_priv->mm.bound_list, global_link) {
3153 bool ggtt_bound = false;
3154 struct i915_vma *vma;
3156 list_for_each_entry(vma, &obj->vma_list, obj_link) {
3157 if (vma->vm != &ggtt->base)
3160 if (!i915_vma_unbind(vma))
3163 WARN_ON(i915_vma_bind(vma, obj->cache_level,
3169 WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
3172 ggtt->base.closed = false;
3174 if (INTEL_GEN(dev_priv) >= 8) {
3175 if (INTEL_GEN(dev_priv) >= 10)
3176 cnl_setup_private_ppat(dev_priv);
3177 else if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
3178 chv_setup_private_ppat(dev_priv);
3180 bdw_setup_private_ppat(dev_priv);
3185 if (USES_PPGTT(dev_priv)) {
3186 struct i915_address_space *vm;
3188 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3189 struct i915_hw_ppgtt *ppgtt;
3191 if (i915_is_ggtt(vm))
3192 ppgtt = dev_priv->mm.aliasing_ppgtt;
3194 ppgtt = i915_vm_to_ppgtt(vm);
3196 gen6_write_page_range(ppgtt, 0, ppgtt->base.total);
3200 i915_ggtt_invalidate(dev_priv);
3203 static struct scatterlist *
3204 rotate_pages(const dma_addr_t *in, unsigned int offset,
3205 unsigned int width, unsigned int height,
3206 unsigned int stride,
3207 struct sg_table *st, struct scatterlist *sg)
3209 unsigned int column, row;
3210 unsigned int src_idx;
3212 for (column = 0; column < width; column++) {
3213 src_idx = stride * (height - 1) + column;
3214 for (row = 0; row < height; row++) {
3216 /* We don't need the pages, but need to initialize
3217 * the entries so the sg list can be happily traversed.
3218 * The only thing we need are DMA addresses.
3220 sg_set_page(sg, NULL, PAGE_SIZE, 0);
3221 sg_dma_address(sg) = in[offset + src_idx];
3222 sg_dma_len(sg) = PAGE_SIZE;
3231 static noinline struct sg_table *
3232 intel_rotate_pages(struct intel_rotation_info *rot_info,
3233 struct drm_i915_gem_object *obj)
3235 const unsigned long n_pages = obj->base.size / PAGE_SIZE;
3236 unsigned int size = intel_rotation_info_size(rot_info);
3237 struct sgt_iter sgt_iter;
3238 dma_addr_t dma_addr;
3240 dma_addr_t *page_addr_list;
3241 struct sg_table *st;
3242 struct scatterlist *sg;
3245 /* Allocate a temporary list of source pages for random access. */
3246 page_addr_list = kvmalloc_array(n_pages,
3249 if (!page_addr_list)
3250 return ERR_PTR(ret);
3252 /* Allocate target SG list. */
3253 st = kmalloc(sizeof(*st), GFP_KERNEL);
3257 ret = sg_alloc_table(st, size, GFP_KERNEL);
3261 /* Populate source page list from the object. */
3263 for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages)
3264 page_addr_list[i++] = dma_addr;
3266 GEM_BUG_ON(i != n_pages);
3270 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
3271 sg = rotate_pages(page_addr_list, rot_info->plane[i].offset,
3272 rot_info->plane[i].width, rot_info->plane[i].height,
3273 rot_info->plane[i].stride, st, sg);
3276 DRM_DEBUG_KMS("Created rotated page mapping for object size %zu (%ux%u tiles, %u pages)\n",
3277 obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
3279 kvfree(page_addr_list);
3286 kvfree(page_addr_list);
3288 DRM_DEBUG_KMS("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
3289 obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
3291 return ERR_PTR(ret);
3294 static noinline struct sg_table *
3295 intel_partial_pages(const struct i915_ggtt_view *view,
3296 struct drm_i915_gem_object *obj)
3298 struct sg_table *st;
3299 struct scatterlist *sg, *iter;
3300 unsigned int count = view->partial.size;
3301 unsigned int offset;
3304 st = kmalloc(sizeof(*st), GFP_KERNEL);
3308 ret = sg_alloc_table(st, count, GFP_KERNEL);
3312 iter = i915_gem_object_get_sg(obj, view->partial.offset, &offset);
3320 len = min(iter->length - (offset << PAGE_SHIFT),
3321 count << PAGE_SHIFT);
3322 sg_set_page(sg, NULL, len, 0);
3323 sg_dma_address(sg) =
3324 sg_dma_address(iter) + (offset << PAGE_SHIFT);
3325 sg_dma_len(sg) = len;
3328 count -= len >> PAGE_SHIFT;
3335 iter = __sg_next(iter);
3342 return ERR_PTR(ret);
3346 i915_get_ggtt_vma_pages(struct i915_vma *vma)
3350 /* The vma->pages are only valid within the lifespan of the borrowed
3351 * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
3352 * must be the vma->pages. A simple rule is that vma->pages must only
3353 * be accessed when the obj->mm.pages are pinned.
3355 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj));
3357 switch (vma->ggtt_view.type) {
3358 case I915_GGTT_VIEW_NORMAL:
3359 vma->pages = vma->obj->mm.pages;
3362 case I915_GGTT_VIEW_ROTATED:
3364 intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
3367 case I915_GGTT_VIEW_PARTIAL:
3368 vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
3372 WARN_ONCE(1, "GGTT view %u not implemented!\n",
3373 vma->ggtt_view.type);
3378 if (unlikely(IS_ERR(vma->pages))) {
3379 ret = PTR_ERR(vma->pages);
3381 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3382 vma->ggtt_view.type, ret);
3388 * i915_gem_gtt_reserve - reserve a node in an address_space (GTT)
3389 * @vm: the &struct i915_address_space
3390 * @node: the &struct drm_mm_node (typically i915_vma.mode)
3391 * @size: how much space to allocate inside the GTT,
3392 * must be #I915_GTT_PAGE_SIZE aligned
3393 * @offset: where to insert inside the GTT,
3394 * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node
3395 * (@offset + @size) must fit within the address space
3396 * @color: color to apply to node, if this node is not from a VMA,
3397 * color must be #I915_COLOR_UNEVICTABLE
3398 * @flags: control search and eviction behaviour
3400 * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside
3401 * the address space (using @size and @color). If the @node does not fit, it
3402 * tries to evict any overlapping nodes from the GTT, including any
3403 * neighbouring nodes if the colors do not match (to ensure guard pages between
3404 * differing domains). See i915_gem_evict_for_node() for the gory details
3405 * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on
3406 * evicting active overlapping objects, and any overlapping node that is pinned
3407 * or marked as unevictable will also result in failure.
3409 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3410 * asked to wait for eviction and interrupted.
3412 int i915_gem_gtt_reserve(struct i915_address_space *vm,
3413 struct drm_mm_node *node,
3414 u64 size, u64 offset, unsigned long color,
3420 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
3421 GEM_BUG_ON(!IS_ALIGNED(offset, I915_GTT_MIN_ALIGNMENT));
3422 GEM_BUG_ON(range_overflows(offset, size, vm->total));
3423 GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base);
3424 GEM_BUG_ON(drm_mm_node_allocated(node));
3427 node->start = offset;
3428 node->color = color;
3430 err = drm_mm_reserve_node(&vm->mm, node);
3434 if (flags & PIN_NOEVICT)
3437 err = i915_gem_evict_for_node(vm, node, flags);
3439 err = drm_mm_reserve_node(&vm->mm, node);
3444 static u64 random_offset(u64 start, u64 end, u64 len, u64 align)
3448 GEM_BUG_ON(range_overflows(start, len, end));
3449 GEM_BUG_ON(round_up(start, align) > round_down(end - len, align));
3451 range = round_down(end - len, align) - round_up(start, align);
3453 if (sizeof(unsigned long) == sizeof(u64)) {
3454 addr = get_random_long();
3456 addr = get_random_int();
3457 if (range > U32_MAX) {
3459 addr |= get_random_int();
3462 div64_u64_rem(addr, range, &addr);
3466 return round_up(start, align);
3470 * i915_gem_gtt_insert - insert a node into an address_space (GTT)
3471 * @vm: the &struct i915_address_space
3472 * @node: the &struct drm_mm_node (typically i915_vma.node)
3473 * @size: how much space to allocate inside the GTT,
3474 * must be #I915_GTT_PAGE_SIZE aligned
3475 * @alignment: required alignment of starting offset, may be 0 but
3476 * if specified, this must be a power-of-two and at least
3477 * #I915_GTT_MIN_ALIGNMENT
3478 * @color: color to apply to node
3479 * @start: start of any range restriction inside GTT (0 for all),
3480 * must be #I915_GTT_PAGE_SIZE aligned
3481 * @end: end of any range restriction inside GTT (U64_MAX for all),
3482 * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX
3483 * @flags: control search and eviction behaviour
3485 * i915_gem_gtt_insert() first searches for an available hole into which
3486 * is can insert the node. The hole address is aligned to @alignment and
3487 * its @size must then fit entirely within the [@start, @end] bounds. The
3488 * nodes on either side of the hole must match @color, or else a guard page
3489 * will be inserted between the two nodes (or the node evicted). If no
3490 * suitable hole is found, first a victim is randomly selected and tested
3491 * for eviction, otherwise then the LRU list of objects within the GTT
3492 * is scanned to find the first set of replacement nodes to create the hole.
3493 * Those old overlapping nodes are evicted from the GTT (and so must be
3494 * rebound before any future use). Any node that is currently pinned cannot
3495 * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently
3496 * active and #PIN_NONBLOCK is specified, that node is also skipped when
3497 * searching for an eviction candidate. See i915_gem_evict_something() for
3498 * the gory details on the eviction algorithm.
3500 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3501 * asked to wait for eviction and interrupted.
3503 int i915_gem_gtt_insert(struct i915_address_space *vm,
3504 struct drm_mm_node *node,
3505 u64 size, u64 alignment, unsigned long color,
3506 u64 start, u64 end, unsigned int flags)
3508 enum drm_mm_insert_mode mode;
3512 lockdep_assert_held(&vm->i915->drm.struct_mutex);
3514 GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
3515 GEM_BUG_ON(alignment && !is_power_of_2(alignment));
3516 GEM_BUG_ON(alignment && !IS_ALIGNED(alignment, I915_GTT_MIN_ALIGNMENT));
3517 GEM_BUG_ON(start >= end);
3518 GEM_BUG_ON(start > 0 && !IS_ALIGNED(start, I915_GTT_PAGE_SIZE));
3519 GEM_BUG_ON(end < U64_MAX && !IS_ALIGNED(end, I915_GTT_PAGE_SIZE));
3520 GEM_BUG_ON(vm == &vm->i915->mm.aliasing_ppgtt->base);
3521 GEM_BUG_ON(drm_mm_node_allocated(node));
3523 if (unlikely(range_overflows(start, size, end)))
3526 if (unlikely(round_up(start, alignment) > round_down(end - size, alignment)))
3529 mode = DRM_MM_INSERT_BEST;
3530 if (flags & PIN_HIGH)
3531 mode = DRM_MM_INSERT_HIGH;
3532 if (flags & PIN_MAPPABLE)
3533 mode = DRM_MM_INSERT_LOW;
3535 /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks,
3536 * so we know that we always have a minimum alignment of 4096.
3537 * The drm_mm range manager is optimised to return results
3538 * with zero alignment, so where possible use the optimal
3541 BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT > I915_GTT_PAGE_SIZE);
3542 if (alignment <= I915_GTT_MIN_ALIGNMENT)
3545 err = drm_mm_insert_node_in_range(&vm->mm, node,
3546 size, alignment, color,
3551 if (flags & PIN_NOEVICT)
3554 /* No free space, pick a slot at random.
3556 * There is a pathological case here using a GTT shared between
3557 * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt):
3559 * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->|
3560 * (64k objects) (448k objects)
3562 * Now imagine that the eviction LRU is ordered top-down (just because
3563 * pathology meets real life), and that we need to evict an object to
3564 * make room inside the aperture. The eviction scan then has to walk
3565 * the 448k list before it finds one within range. And now imagine that
3566 * it has to search for a new hole between every byte inside the memcpy,
3567 * for several simultaneous clients.
3569 * On a full-ppgtt system, if we have run out of available space, there
3570 * will be lots and lots of objects in the eviction list! Again,
3571 * searching that LRU list may be slow if we are also applying any
3572 * range restrictions (e.g. restriction to low 4GiB) and so, for
3573 * simplicity and similarilty between different GTT, try the single
3574 * random replacement first.
3576 offset = random_offset(start, end,
3577 size, alignment ?: I915_GTT_MIN_ALIGNMENT);
3578 err = i915_gem_gtt_reserve(vm, node, size, offset, color, flags);
3582 /* Randomly selected placement is pinned, do a search */
3583 err = i915_gem_evict_something(vm, size, alignment, color,
3588 return drm_mm_insert_node_in_range(&vm->mm, node,
3589 size, alignment, color,
3590 start, end, DRM_MM_INSERT_EVICT);
3593 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
3594 #include "selftests/mock_gtt.c"
3595 #include "selftests/i915_gem_gtt.c"