2 * Copyright © 2011-2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Ben Widawsky <ben@bwidawsk.net>
29 * This file implements HW context support. On gen5+ a HW context consists of an
30 * opaque GPU object which is referenced at times of context saves and restores.
31 * With RC6 enabled, the context is also referenced as the GPU enters and exists
32 * from RC6 (GPU has it's own internal power context, except on gen5). Though
33 * something like a context does exist for the media ring, the code only
34 * supports contexts for the render ring.
36 * In software, there is a distinction between contexts created by the user,
37 * and the default HW context. The default HW context is used by GPU clients
38 * that do not request setup of their own hardware context. The default
39 * context's state is never restored to help prevent programming errors. This
40 * would happen if a client ran and piggy-backed off another clients GPU state.
41 * The default context only exists to give the GPU some offset to load as the
42 * current to invoke a save of the context we actually care about. In fact, the
43 * code could likely be constructed, albeit in a more complicated fashion, to
44 * never use the default context, though that limits the driver's ability to
45 * swap out, and/or destroy other contexts.
47 * All other contexts are created as a request by the GPU client. These contexts
48 * store GPU state, and thus allow GPU clients to not re-emit state (and
49 * potentially query certain state) at any time. The kernel driver makes
50 * certain that the appropriate commands are inserted.
52 * The context life cycle is semi-complicated in that context BOs may live
53 * longer than the context itself because of the way the hardware, and object
54 * tracking works. Below is a very crude representation of the state machine
55 * describing the context life.
56 * refcount pincount active
57 * S0: initial state 0 0 0
58 * S1: context created 1 0 0
59 * S2: context is currently running 2 1 X
60 * S3: GPU referenced, but not current 2 0 1
61 * S4: context is current, but destroyed 1 1 0
62 * S5: like S3, but destroyed 1 0 1
64 * The most common (but not all) transitions:
65 * S0->S1: client creates a context
66 * S1->S2: client submits execbuf with context
67 * S2->S3: other clients submits execbuf with context
68 * S3->S1: context object was retired
69 * S3->S2: clients submits another execbuf
70 * S2->S4: context destroy called with current context
71 * S3->S5->S0: destroy path
72 * S4->S5->S0: destroy path on current context
74 * There are two confusing terms used above:
75 * The "current context" means the context which is currently running on the
76 * GPU. The GPU has loaded its state already and has stored away the gtt
77 * offset of the BO. The GPU is not actively referencing the data at this
78 * offset, but it will on the next context switch. The only way to avoid this
79 * is to do a GPU reset.
81 * An "active context' is one which was previously the "current context" and is
82 * on the active list waiting for the next context switch to occur. Until this
83 * happens, the object must remain at the same gtt offset. It is therefore
84 * possible to destroy a context, but it is still active.
88 #include <linux/log2.h>
90 #include <drm/i915_drm.h>
92 #include "i915_trace.h"
94 #define ALL_L3_SLICES(dev) (1 << NUM_L3_SLICES(dev)) - 1
96 static void lut_close(struct i915_gem_context *ctx)
98 struct i915_lut_handle *lut, *ln;
99 struct radix_tree_iter iter;
102 list_for_each_entry_safe(lut, ln, &ctx->handles_list, ctx_link) {
103 list_del(&lut->obj_link);
104 kmem_cache_free(ctx->i915->luts, lut);
108 radix_tree_for_each_slot(slot, &ctx->handles_vma, &iter, 0) {
109 struct i915_vma *vma = rcu_dereference_raw(*slot);
110 struct drm_i915_gem_object *obj = vma->obj;
112 radix_tree_iter_delete(&ctx->handles_vma, &iter, slot);
114 if (!i915_vma_is_ggtt(vma))
117 __i915_gem_object_release_unless_active(obj);
122 static void i915_gem_context_free(struct i915_gem_context *ctx)
126 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
127 GEM_BUG_ON(!i915_gem_context_is_closed(ctx));
129 i915_ppgtt_put(ctx->ppgtt);
131 for (i = 0; i < I915_NUM_ENGINES; i++) {
132 struct intel_context *ce = &ctx->engine[i];
137 WARN_ON(ce->pin_count);
139 intel_ring_free(ce->ring);
141 __i915_gem_object_release_unless_active(ce->state->obj);
144 kfree(ctx->jump_whitelist);
149 list_del(&ctx->link);
151 ida_simple_remove(&ctx->i915->contexts.hw_ida, ctx->hw_id);
155 static void contexts_free(struct drm_i915_private *i915)
157 struct llist_node *freed = llist_del_all(&i915->contexts.free_list);
158 struct i915_gem_context *ctx, *cn;
160 lockdep_assert_held(&i915->drm.struct_mutex);
162 llist_for_each_entry_safe(ctx, cn, freed, free_link)
163 i915_gem_context_free(ctx);
166 static void contexts_free_first(struct drm_i915_private *i915)
168 struct i915_gem_context *ctx;
169 struct llist_node *freed;
171 lockdep_assert_held(&i915->drm.struct_mutex);
173 freed = llist_del_first(&i915->contexts.free_list);
177 ctx = container_of(freed, typeof(*ctx), free_link);
178 i915_gem_context_free(ctx);
181 static void contexts_free_worker(struct work_struct *work)
183 struct drm_i915_private *i915 =
184 container_of(work, typeof(*i915), contexts.free_work);
186 mutex_lock(&i915->drm.struct_mutex);
188 mutex_unlock(&i915->drm.struct_mutex);
191 void i915_gem_context_release(struct kref *ref)
193 struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
194 struct drm_i915_private *i915 = ctx->i915;
196 trace_i915_context_free(ctx);
197 if (llist_add(&ctx->free_link, &i915->contexts.free_list))
198 queue_work(i915->wq, &i915->contexts.free_work);
201 static void context_close(struct i915_gem_context *ctx)
203 i915_gem_context_set_closed(ctx);
207 i915_ppgtt_close(&ctx->ppgtt->base);
209 ctx->file_priv = ERR_PTR(-EBADF);
210 i915_gem_context_put(ctx);
213 static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
217 ret = ida_simple_get(&dev_priv->contexts.hw_ida,
218 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
220 /* Contexts are only released when no longer active.
221 * Flush any pending retires to hopefully release some
222 * stale contexts and try again.
224 i915_gem_retire_requests(dev_priv);
225 ret = ida_simple_get(&dev_priv->contexts.hw_ida,
226 0, MAX_CONTEXT_HW_ID, GFP_KERNEL);
235 static u32 default_desc_template(const struct drm_i915_private *i915,
236 const struct i915_hw_ppgtt *ppgtt)
241 desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
243 address_mode = INTEL_LEGACY_32B_CONTEXT;
244 if (ppgtt && i915_vm_is_48bit(&ppgtt->base))
245 address_mode = INTEL_LEGACY_64B_CONTEXT;
246 desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
249 desc |= GEN8_CTX_L3LLC_COHERENT;
251 /* TODO: WaDisableLiteRestore when we start using semaphore
252 * signalling between Command Streamers
253 * ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
259 static struct i915_gem_context *
260 __create_hw_context(struct drm_i915_private *dev_priv,
261 struct drm_i915_file_private *file_priv)
263 struct i915_gem_context *ctx;
266 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
268 return ERR_PTR(-ENOMEM);
270 ret = assign_hw_id(dev_priv, &ctx->hw_id);
276 kref_init(&ctx->ref);
277 list_add_tail(&ctx->link, &dev_priv->contexts.list);
278 ctx->i915 = dev_priv;
279 ctx->priority = I915_PRIORITY_NORMAL;
281 INIT_RADIX_TREE(&ctx->handles_vma, GFP_KERNEL);
282 INIT_LIST_HEAD(&ctx->handles_list);
284 /* Default context will never have a file_priv */
285 ret = DEFAULT_CONTEXT_HANDLE;
287 ret = idr_alloc(&file_priv->context_idr, ctx,
288 DEFAULT_CONTEXT_HANDLE, 0, GFP_KERNEL);
292 ctx->user_handle = ret;
294 ctx->file_priv = file_priv;
296 ctx->pid = get_task_pid(current, PIDTYPE_PID);
297 ctx->name = kasprintf(GFP_KERNEL, "%s[%d]/%x",
307 /* NB: Mark all slices as needing a remap so that when the context first
308 * loads it will restore whatever remap state already exists. If there
309 * is no remap info, it will be a NOP. */
310 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
312 i915_gem_context_set_bannable(ctx);
313 ctx->ring_size = 4 * PAGE_SIZE;
315 default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
317 /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
318 * present or not in use we still need a small bias as ring wraparound
319 * at offset 0 sometimes hangs. No idea why.
321 if (HAS_GUC(dev_priv) && i915.enable_guc_loading)
322 ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
324 ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
326 ctx->jump_whitelist = NULL;
327 ctx->jump_whitelist_cmds = 0;
333 idr_remove(&file_priv->context_idr, ctx->user_handle);
339 static void __destroy_hw_context(struct i915_gem_context *ctx,
340 struct drm_i915_file_private *file_priv)
342 idr_remove(&file_priv->context_idr, ctx->user_handle);
347 * The default context needs to exist per ring that uses contexts. It stores the
348 * context state of the GPU for applications that don't utilize HW contexts, as
349 * well as an idle case.
351 static struct i915_gem_context *
352 i915_gem_create_context(struct drm_i915_private *dev_priv,
353 struct drm_i915_file_private *file_priv)
355 struct i915_gem_context *ctx;
357 lockdep_assert_held(&dev_priv->drm.struct_mutex);
359 /* Reap the most stale context */
360 contexts_free_first(dev_priv);
362 ctx = __create_hw_context(dev_priv, file_priv);
366 if (USES_FULL_PPGTT(dev_priv)) {
367 struct i915_hw_ppgtt *ppgtt;
369 ppgtt = i915_ppgtt_create(dev_priv, file_priv, ctx->name);
371 DRM_DEBUG_DRIVER("PPGTT setup failed (%ld)\n",
373 __destroy_hw_context(ctx, file_priv);
374 return ERR_CAST(ppgtt);
378 ctx->desc_template = default_desc_template(dev_priv, ppgtt);
381 trace_i915_context_create(ctx);
387 * i915_gem_context_create_gvt - create a GVT GEM context
390 * This function is used to create a GVT specific GEM context.
393 * pointer to i915_gem_context on success, error pointer if failed
396 struct i915_gem_context *
397 i915_gem_context_create_gvt(struct drm_device *dev)
399 struct i915_gem_context *ctx;
402 if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
403 return ERR_PTR(-ENODEV);
405 ret = i915_mutex_lock_interruptible(dev);
409 ctx = __create_hw_context(to_i915(dev), NULL);
413 ctx->file_priv = ERR_PTR(-EBADF);
414 i915_gem_context_set_closed(ctx); /* not user accessible */
415 i915_gem_context_clear_bannable(ctx);
416 i915_gem_context_set_force_single_submission(ctx);
417 if (!i915.enable_guc_submission)
418 ctx->ring_size = 512 * PAGE_SIZE; /* Max ring buffer size */
420 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
422 mutex_unlock(&dev->struct_mutex);
426 int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
428 struct i915_gem_context *ctx;
430 /* Init should only be called once per module load. Eventually the
431 * restriction on the context_disabled check can be loosened. */
432 if (WARN_ON(dev_priv->kernel_context))
435 INIT_LIST_HEAD(&dev_priv->contexts.list);
436 INIT_WORK(&dev_priv->contexts.free_work, contexts_free_worker);
437 init_llist_head(&dev_priv->contexts.free_list);
439 if (intel_vgpu_active(dev_priv) &&
440 HAS_LOGICAL_RING_CONTEXTS(dev_priv)) {
441 if (!i915.enable_execlists) {
442 DRM_INFO("Only EXECLIST mode is supported in vgpu.\n");
447 /* Using the simple ida interface, the max is limited by sizeof(int) */
448 BUILD_BUG_ON(MAX_CONTEXT_HW_ID > INT_MAX);
449 ida_init(&dev_priv->contexts.hw_ida);
451 ctx = i915_gem_create_context(dev_priv, NULL);
453 DRM_ERROR("Failed to create default global context (error %ld)\n",
458 /* For easy recognisablity, we want the kernel context to be 0 and then
459 * all user contexts will have non-zero hw_id.
461 GEM_BUG_ON(ctx->hw_id);
463 i915_gem_context_clear_bannable(ctx);
464 ctx->priority = I915_PRIORITY_MIN; /* lowest priority; idle task */
465 dev_priv->kernel_context = ctx;
467 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
469 DRM_DEBUG_DRIVER("%s context support initialized\n",
470 dev_priv->engine[RCS]->context_size ? "logical" :
475 void i915_gem_contexts_lost(struct drm_i915_private *dev_priv)
477 struct intel_engine_cs *engine;
478 enum intel_engine_id id;
480 lockdep_assert_held(&dev_priv->drm.struct_mutex);
482 for_each_engine(engine, dev_priv, id) {
483 engine->legacy_active_context = NULL;
485 if (!engine->last_retired_context)
488 engine->context_unpin(engine, engine->last_retired_context);
489 engine->last_retired_context = NULL;
492 /* Force the GPU state to be restored on enabling */
493 if (!i915.enable_execlists) {
494 struct i915_gem_context *ctx;
496 list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
497 if (!i915_gem_context_is_default(ctx))
500 for_each_engine(engine, dev_priv, id)
501 ctx->engine[engine->id].initialised = false;
503 ctx->remap_slice = ALL_L3_SLICES(dev_priv);
506 for_each_engine(engine, dev_priv, id) {
507 struct intel_context *kce =
508 &dev_priv->kernel_context->engine[engine->id];
510 kce->initialised = true;
515 void i915_gem_contexts_fini(struct drm_i915_private *i915)
517 struct i915_gem_context *ctx;
519 lockdep_assert_held(&i915->drm.struct_mutex);
521 /* Keep the context so that we can free it immediately ourselves */
522 ctx = i915_gem_context_get(fetch_and_zero(&i915->kernel_context));
523 GEM_BUG_ON(!i915_gem_context_is_kernel(ctx));
525 i915_gem_context_free(ctx);
527 /* Must free all deferred contexts (via flush_workqueue) first */
528 ida_destroy(&i915->contexts.hw_ida);
531 static int context_idr_cleanup(int id, void *p, void *data)
533 struct i915_gem_context *ctx = p;
539 int i915_gem_context_open(struct drm_i915_private *i915,
540 struct drm_file *file)
542 struct drm_i915_file_private *file_priv = file->driver_priv;
543 struct i915_gem_context *ctx;
545 idr_init(&file_priv->context_idr);
547 mutex_lock(&i915->drm.struct_mutex);
548 ctx = i915_gem_create_context(i915, file_priv);
549 mutex_unlock(&i915->drm.struct_mutex);
551 idr_destroy(&file_priv->context_idr);
555 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
560 void i915_gem_context_close(struct drm_file *file)
562 struct drm_i915_file_private *file_priv = file->driver_priv;
564 lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
566 idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
567 idr_destroy(&file_priv->context_idr);
571 mi_set_context(struct drm_i915_gem_request *req, u32 flags)
573 struct drm_i915_private *dev_priv = req->i915;
574 struct intel_engine_cs *engine = req->engine;
575 enum intel_engine_id id;
576 const int num_rings =
577 /* Use an extended w/a on gen7 if signalling from other rings */
578 (i915.semaphores && INTEL_GEN(dev_priv) == 7) ?
579 INTEL_INFO(dev_priv)->num_rings - 1 :
584 flags |= MI_MM_SPACE_GTT;
585 if (IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8)
586 /* These flags are for resource streamer on HSW+ */
587 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
589 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
592 if (INTEL_GEN(dev_priv) >= 7)
593 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
595 cs = intel_ring_begin(req, len);
599 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
600 if (INTEL_GEN(dev_priv) >= 7) {
601 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
603 struct intel_engine_cs *signaller;
605 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
606 for_each_engine(signaller, dev_priv, id) {
607 if (signaller == engine)
610 *cs++ = i915_mmio_reg_offset(
611 RING_PSMI_CTL(signaller->mmio_base));
612 *cs++ = _MASKED_BIT_ENABLE(
613 GEN6_PSMI_SLEEP_MSG_DISABLE);
619 *cs++ = MI_SET_CONTEXT;
620 *cs++ = i915_ggtt_offset(req->ctx->engine[RCS].state) | flags;
622 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
623 * WaMiSetContext_Hang:snb,ivb,vlv
627 if (INTEL_GEN(dev_priv) >= 7) {
629 struct intel_engine_cs *signaller;
630 i915_reg_t last_reg = {}; /* keep gcc quiet */
632 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
633 for_each_engine(signaller, dev_priv, id) {
634 if (signaller == engine)
637 last_reg = RING_PSMI_CTL(signaller->mmio_base);
638 *cs++ = i915_mmio_reg_offset(last_reg);
639 *cs++ = _MASKED_BIT_DISABLE(
640 GEN6_PSMI_SLEEP_MSG_DISABLE);
643 /* Insert a delay before the next switch! */
644 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
645 *cs++ = i915_mmio_reg_offset(last_reg);
646 *cs++ = i915_ggtt_offset(engine->scratch);
649 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
652 intel_ring_advance(req, cs);
657 static int remap_l3(struct drm_i915_gem_request *req, int slice)
659 u32 *cs, *remap_info = req->i915->l3_parity.remap_info[slice];
665 cs = intel_ring_begin(req, GEN7_L3LOG_SIZE/4 * 2 + 2);
670 * Note: We do not worry about the concurrent register cacheline hang
671 * here because no other code should access these registers other than
672 * at initialization time.
674 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
675 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
676 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
677 *cs++ = remap_info[i];
680 intel_ring_advance(req, cs);
685 static inline bool skip_rcs_switch(struct i915_hw_ppgtt *ppgtt,
686 struct intel_engine_cs *engine,
687 struct i915_gem_context *to)
692 if (!to->engine[RCS].initialised)
695 if (ppgtt && (intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
698 return to == engine->legacy_active_context;
702 needs_pd_load_pre(struct i915_hw_ppgtt *ppgtt, struct intel_engine_cs *engine)
704 struct i915_gem_context *from = engine->legacy_active_context;
709 /* Always load the ppgtt on first use */
713 /* Same context without new entries, skip */
714 if ((!from->ppgtt || from->ppgtt == ppgtt) &&
715 !(intel_engine_flag(engine) & ppgtt->pd_dirty_rings))
718 if (engine->id != RCS)
721 if (INTEL_GEN(engine->i915) < 8)
728 needs_pd_load_post(struct i915_hw_ppgtt *ppgtt,
729 struct i915_gem_context *to,
735 if (!IS_GEN8(to->i915))
738 if (hw_flags & MI_RESTORE_INHIBIT)
744 static int do_rcs_switch(struct drm_i915_gem_request *req)
746 struct i915_gem_context *to = req->ctx;
747 struct intel_engine_cs *engine = req->engine;
748 struct i915_hw_ppgtt *ppgtt = to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
749 struct i915_gem_context *from = engine->legacy_active_context;
753 GEM_BUG_ON(engine->id != RCS);
755 if (skip_rcs_switch(ppgtt, engine, to))
758 if (needs_pd_load_pre(ppgtt, engine)) {
759 /* Older GENs and non render rings still want the load first,
760 * "PP_DCLV followed by PP_DIR_BASE register through Load
761 * Register Immediate commands in Ring Buffer before submitting
763 trace_switch_mm(engine, to);
764 ret = ppgtt->switch_mm(ppgtt, req);
769 if (!to->engine[RCS].initialised || i915_gem_context_is_default(to))
770 /* NB: If we inhibit the restore, the context is not allowed to
771 * die because future work may end up depending on valid address
772 * space. This means we must enforce that a page table load
773 * occur when this occurs. */
774 hw_flags = MI_RESTORE_INHIBIT;
775 else if (ppgtt && intel_engine_flag(engine) & ppgtt->pd_dirty_rings)
776 hw_flags = MI_FORCE_RESTORE;
780 if (to != from || (hw_flags & MI_FORCE_RESTORE)) {
781 ret = mi_set_context(req, hw_flags);
785 engine->legacy_active_context = to;
788 /* GEN8 does *not* require an explicit reload if the PDPs have been
789 * setup, and we do not wish to move them.
791 if (needs_pd_load_post(ppgtt, to, hw_flags)) {
792 trace_switch_mm(engine, to);
793 ret = ppgtt->switch_mm(ppgtt, req);
794 /* The hardware context switch is emitted, but we haven't
795 * actually changed the state - so it's probably safe to bail
796 * here. Still, let the user know something dangerous has
804 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
806 for (i = 0; i < MAX_L3_SLICES; i++) {
807 if (!(to->remap_slice & (1<<i)))
810 ret = remap_l3(req, i);
814 to->remap_slice &= ~(1<<i);
817 if (!to->engine[RCS].initialised) {
818 if (engine->init_context) {
819 ret = engine->init_context(req);
823 to->engine[RCS].initialised = true;
830 * i915_switch_context() - perform a GPU context switch.
831 * @req: request for which we'll execute the context switch
833 * The context life cycle is simple. The context refcount is incremented and
834 * decremented by 1 and create and destroy. If the context is in use by the GPU,
835 * it will have a refcount > 1. This allows us to destroy the context abstract
836 * object while letting the normal object tracking destroy the backing BO.
838 * This function should not be used in execlists mode. Instead the context is
839 * switched by writing to the ELSP and requests keep a reference to their
842 int i915_switch_context(struct drm_i915_gem_request *req)
844 struct intel_engine_cs *engine = req->engine;
846 lockdep_assert_held(&req->i915->drm.struct_mutex);
847 if (i915.enable_execlists)
850 if (!req->ctx->engine[engine->id].state) {
851 struct i915_gem_context *to = req->ctx;
852 struct i915_hw_ppgtt *ppgtt =
853 to->ppgtt ?: req->i915->mm.aliasing_ppgtt;
855 if (needs_pd_load_pre(ppgtt, engine)) {
858 trace_switch_mm(engine, to);
859 ret = ppgtt->switch_mm(ppgtt, req);
863 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
866 engine->legacy_active_context = to;
870 return do_rcs_switch(req);
873 static bool engine_has_kernel_context(struct intel_engine_cs *engine)
875 struct i915_gem_timeline *timeline;
877 list_for_each_entry(timeline, &engine->i915->gt.timelines, link) {
878 struct intel_timeline *tl;
880 if (timeline == &engine->i915->gt.global_timeline)
883 tl = &timeline->engine[engine->id];
884 if (i915_gem_active_peek(&tl->last_request,
885 &engine->i915->drm.struct_mutex))
889 return (!engine->last_retired_context ||
890 i915_gem_context_is_kernel(engine->last_retired_context));
893 int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv)
895 struct intel_engine_cs *engine;
896 struct i915_gem_timeline *timeline;
897 enum intel_engine_id id;
899 lockdep_assert_held(&dev_priv->drm.struct_mutex);
901 i915_gem_retire_requests(dev_priv);
903 for_each_engine(engine, dev_priv, id) {
904 struct drm_i915_gem_request *req;
907 if (engine_has_kernel_context(engine))
910 req = i915_gem_request_alloc(engine, dev_priv->kernel_context);
914 /* Queue this switch after all other activity */
915 list_for_each_entry(timeline, &dev_priv->gt.timelines, link) {
916 struct drm_i915_gem_request *prev;
917 struct intel_timeline *tl;
919 tl = &timeline->engine[engine->id];
920 prev = i915_gem_active_raw(&tl->last_request,
921 &dev_priv->drm.struct_mutex);
923 i915_sw_fence_await_sw_fence_gfp(&req->submit,
928 ret = i915_switch_context(req);
929 i915_add_request(req);
937 static bool client_is_banned(struct drm_i915_file_private *file_priv)
939 return atomic_read(&file_priv->context_bans) > I915_MAX_CLIENT_CONTEXT_BANS;
942 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
943 struct drm_file *file)
945 struct drm_i915_private *dev_priv = to_i915(dev);
946 struct drm_i915_gem_context_create *args = data;
947 struct drm_i915_file_private *file_priv = file->driver_priv;
948 struct i915_gem_context *ctx;
951 if (!dev_priv->engine[RCS]->context_size)
957 if (client_is_banned(file_priv)) {
958 DRM_DEBUG("client %s[%d] banned from creating ctx\n",
960 pid_nr(get_task_pid(current, PIDTYPE_PID)));
965 ret = i915_mutex_lock_interruptible(dev);
969 ctx = i915_gem_create_context(dev_priv, file_priv);
970 mutex_unlock(&dev->struct_mutex);
974 GEM_BUG_ON(i915_gem_context_is_kernel(ctx));
976 args->ctx_id = ctx->user_handle;
977 DRM_DEBUG("HW context %d created\n", args->ctx_id);
982 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
983 struct drm_file *file)
985 struct drm_i915_gem_context_destroy *args = data;
986 struct drm_i915_file_private *file_priv = file->driver_priv;
987 struct i915_gem_context *ctx;
993 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE)
996 ret = i915_mutex_lock_interruptible(dev);
1000 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1002 mutex_unlock(&dev->struct_mutex);
1006 __destroy_hw_context(ctx, file_priv);
1007 mutex_unlock(&dev->struct_mutex);
1009 i915_gem_context_put(ctx);
1013 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
1014 struct drm_file *file)
1016 struct drm_i915_file_private *file_priv = file->driver_priv;
1017 struct drm_i915_gem_context_param *args = data;
1018 struct i915_gem_context *ctx;
1021 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1026 switch (args->param) {
1027 case I915_CONTEXT_PARAM_BAN_PERIOD:
1030 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1031 args->value = ctx->flags & CONTEXT_NO_ZEROMAP;
1033 case I915_CONTEXT_PARAM_GTT_SIZE:
1035 args->value = ctx->ppgtt->base.total;
1036 else if (to_i915(dev)->mm.aliasing_ppgtt)
1037 args->value = to_i915(dev)->mm.aliasing_ppgtt->base.total;
1039 args->value = to_i915(dev)->ggtt.base.total;
1041 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1042 args->value = i915_gem_context_no_error_capture(ctx);
1044 case I915_CONTEXT_PARAM_BANNABLE:
1045 args->value = i915_gem_context_is_bannable(ctx);
1052 i915_gem_context_put(ctx);
1056 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
1057 struct drm_file *file)
1059 struct drm_i915_file_private *file_priv = file->driver_priv;
1060 struct drm_i915_gem_context_param *args = data;
1061 struct i915_gem_context *ctx;
1064 ctx = i915_gem_context_lookup(file_priv, args->ctx_id);
1068 ret = i915_mutex_lock_interruptible(dev);
1072 switch (args->param) {
1073 case I915_CONTEXT_PARAM_BAN_PERIOD:
1076 case I915_CONTEXT_PARAM_NO_ZEROMAP:
1080 ctx->flags &= ~CONTEXT_NO_ZEROMAP;
1081 ctx->flags |= args->value ? CONTEXT_NO_ZEROMAP : 0;
1084 case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE:
1087 else if (args->value)
1088 i915_gem_context_set_no_error_capture(ctx);
1090 i915_gem_context_clear_no_error_capture(ctx);
1092 case I915_CONTEXT_PARAM_BANNABLE:
1095 else if (!capable(CAP_SYS_ADMIN) && !args->value)
1097 else if (args->value)
1098 i915_gem_context_set_bannable(ctx);
1100 i915_gem_context_clear_bannable(ctx);
1106 mutex_unlock(&dev->struct_mutex);
1109 i915_gem_context_put(ctx);
1113 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev,
1114 void *data, struct drm_file *file)
1116 struct drm_i915_private *dev_priv = to_i915(dev);
1117 struct drm_i915_reset_stats *args = data;
1118 struct i915_gem_context *ctx;
1121 if (args->flags || args->pad)
1126 ctx = __i915_gem_context_lookup_rcu(file->driver_priv, args->ctx_id);
1131 * We opt for unserialised reads here. This may result in tearing
1132 * in the extremely unlikely event of a GPU hang on this context
1133 * as we are querying them. If we need that extra layer of protection,
1134 * we should wrap the hangstats with a seqlock.
1137 if (capable(CAP_SYS_ADMIN))
1138 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1140 args->reset_count = 0;
1142 args->batch_active = atomic_read(&ctx->guilty_count);
1143 args->batch_pending = atomic_read(&ctx->active_count);
1151 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1152 #include "selftests/mock_context.c"
1153 #include "selftests/i915_gem_context.c"