drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/sched/mm.h>
  30 #include <linux/sort.h>
  31
  32 #include <drm/drm_debugfs.h>
  33
  34 #include "gem/i915_gem_context.h"
  35 #include "gt/intel_gt_buffer_pool.h"
  36 #include "gt/intel_gt_clock_utils.h"
  37 #include "gt/intel_gt.h"
  38 #include "gt/intel_gt_pm.h"
  39 #include "gt/intel_gt_requests.h"
  40 #include "gt/intel_reset.h"
  41 #include "gt/intel_rc6.h"
  42 #include "gt/intel_rps.h"
  43 #include "gt/intel_sseu_debugfs.h"
  44
  45 #include "i915_debugfs.h"
  46 #include "i915_debugfs_params.h"
  47 #include "i915_irq.h"
  48 #include "i915_trace.h"
  49 #include "intel_pm.h"
  50 #include "intel_sideband.h"
  51
  52 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  53 {
  54         return to_i915(node->minor->dev);
  55 }
  56
  57 static int i915_capabilities(struct seq_file *m, void *data)
  58 {
  59         struct drm_i915_private *i915 = node_to_i915(m->private);
  60         struct drm_printer p = drm_seq_file_printer(m);
  61
  62         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
  63
  64         intel_device_info_print_static(INTEL_INFO(i915), &p);
  65         intel_device_info_print_runtime(RUNTIME_INFO(i915), &p);
  66         intel_gt_info_print(&i915->gt.info, &p);
  67         intel_driver_caps_print(&i915->caps, &p);
  68
  69         kernel_param_lock(THIS_MODULE);
  70         i915_params_dump(&i915->params, &p);
  71         kernel_param_unlock(THIS_MODULE);
  72
  73         return 0;
  74 }
  75
  76 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  77 {
  78         switch (i915_gem_object_get_tiling(obj)) {
  79         default:
  80         case I915_TILING_NONE: return ' ';
  81         case I915_TILING_X: return 'X';
  82         case I915_TILING_Y: return 'Y';
  83         }
  84 }
  85
  86 static char get_global_flag(struct drm_i915_gem_object *obj)
  87 {
  88         return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
  89 }
  90
  91 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
  92 {
  93         return obj->mm.mapping ? 'M' : ' ';
  94 }
  95
  96 static const char *
  97 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
  98 {
  99         size_t x = 0;
 100
 101         switch (page_sizes) {
 102         case 0:
 103                 return "";
 104         case I915_GTT_PAGE_SIZE_4K:
 105                 return "4K";
 106         case I915_GTT_PAGE_SIZE_64K:
 107                 return "64K";
 108         case I915_GTT_PAGE_SIZE_2M:
 109                 return "2M";
 110         default:
 111                 if (!buf)
 112                         return "M";
 113
 114                 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
 115                         x += snprintf(buf + x, len - x, "2M, ");
 116                 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
 117                         x += snprintf(buf + x, len - x, "64K, ");
 118                 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
 119                         x += snprintf(buf + x, len - x, "4K, ");
 120                 buf[x-2] = '\0';
 121
 122                 return buf;
 123         }
 124 }
 125
 126 void
 127 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 128 {
 129         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 130         struct intel_engine_cs *engine;
 131         struct i915_vma *vma;
 132         int pin_count = 0;
 133
 134         seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
 135                    &obj->base,
 136                    get_tiling_flag(obj),
 137                    get_global_flag(obj),
 138                    get_pin_mapped_flag(obj),
 139                    obj->base.size / 1024,
 140                    obj->read_domains,
 141                    obj->write_domain,
 142                    i915_cache_level_str(dev_priv, obj->cache_level),
 143                    obj->mm.dirty ? " dirty" : "",
 144                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 145         if (obj->base.name)
 146                 seq_printf(m, " (name: %d)", obj->base.name);
 147
 148         spin_lock(&obj->vma.lock);
 149         list_for_each_entry(vma, &obj->vma.list, obj_link) {
 150                 if (!drm_mm_node_allocated(&vma->node))
 151                         continue;
 152
 153                 spin_unlock(&obj->vma.lock);
 154
 155                 if (i915_vma_is_pinned(vma))
 156                         pin_count++;
 157
 158                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s",
 159                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 160                            vma->node.start, vma->node.size,
 161                            stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
 162                 if (i915_vma_is_ggtt(vma)) {
 163                         switch (vma->ggtt_view.type) {
 164                         case I915_GGTT_VIEW_NORMAL:
 165                                 seq_puts(m, ", normal");
 166                                 break;
 167
 168                         case I915_GGTT_VIEW_PARTIAL:
 169                                 seq_printf(m, ", partial [%08llx+%x]",
 170                                            vma->ggtt_view.partial.offset << PAGE_SHIFT,
 171                                            vma->ggtt_view.partial.size << PAGE_SHIFT);
 172                                 break;
 173
 174                         case I915_GGTT_VIEW_ROTATED:
 175                                 seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 176                                            vma->ggtt_view.rotated.plane[0].width,
 177                                            vma->ggtt_view.rotated.plane[0].height,
 178                                            vma->ggtt_view.rotated.plane[0].stride,
 179                                            vma->ggtt_view.rotated.plane[0].offset,
 180                                            vma->ggtt_view.rotated.plane[1].width,
 181                                            vma->ggtt_view.rotated.plane[1].height,
 182                                            vma->ggtt_view.rotated.plane[1].stride,
 183                                            vma->ggtt_view.rotated.plane[1].offset);
 184                                 break;
 185
 186                         case I915_GGTT_VIEW_REMAPPED:
 187                                 seq_printf(m, ", remapped [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
 188                                            vma->ggtt_view.remapped.plane[0].width,
 189                                            vma->ggtt_view.remapped.plane[0].height,
 190                                            vma->ggtt_view.remapped.plane[0].stride,
 191                                            vma->ggtt_view.remapped.plane[0].offset,
 192                                            vma->ggtt_view.remapped.plane[1].width,
 193                                            vma->ggtt_view.remapped.plane[1].height,
 194                                            vma->ggtt_view.remapped.plane[1].stride,
 195                                            vma->ggtt_view.remapped.plane[1].offset);
 196                                 break;
 197
 198                         default:
 199                                 MISSING_CASE(vma->ggtt_view.type);
 200                                 break;
 201                         }
 202                 }
 203                 if (vma->fence)
 204                         seq_printf(m, " , fence: %d", vma->fence->id);
 205                 seq_puts(m, ")");
 206
 207                 spin_lock(&obj->vma.lock);
 208         }
 209         spin_unlock(&obj->vma.lock);
 210
 211         seq_printf(m, " (pinned x %d)", pin_count);
 212         if (obj->stolen)
 213                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 214         if (i915_gem_object_is_framebuffer(obj))
 215                 seq_printf(m, " (fb)");
 216
 217         engine = i915_gem_object_last_write_engine(obj);
 218         if (engine)
 219                 seq_printf(m, " (%s)", engine->name);
 220 }
 221
 222 struct file_stats {
 223         struct i915_address_space *vm;
 224         unsigned long count;
 225         u64 total;
 226         u64 active, inactive;
 227         u64 closed;
 228 };
 229
 230 static int per_file_stats(int id, void *ptr, void *data)
 231 {
 232         struct drm_i915_gem_object *obj = ptr;
 233         struct file_stats *stats = data;
 234         struct i915_vma *vma;
 235
 236         if (IS_ERR_OR_NULL(obj) || !kref_get_unless_zero(&obj->base.refcount))
 237                 return 0;
 238
 239         stats->count++;
 240         stats->total += obj->base.size;
 241
 242         spin_lock(&obj->vma.lock);
 243         if (!stats->vm) {
 244                 for_each_ggtt_vma(vma, obj) {
 245                         if (!drm_mm_node_allocated(&vma->node))
 246                                 continue;
 247
 248                         if (i915_vma_is_active(vma))
 249                                 stats->active += vma->node.size;
 250                         else
 251                                 stats->inactive += vma->node.size;
 252
 253                         if (i915_vma_is_closed(vma))
 254                                 stats->closed += vma->node.size;
 255                 }
 256         } else {
 257                 struct rb_node *p = obj->vma.tree.rb_node;
 258
 259                 while (p) {
 260                         long cmp;
 261
 262                         vma = rb_entry(p, typeof(*vma), obj_node);
 263                         cmp = i915_vma_compare(vma, stats->vm, NULL);
 264                         if (cmp == 0) {
 265                                 if (drm_mm_node_allocated(&vma->node)) {
 266                                         if (i915_vma_is_active(vma))
 267                                                 stats->active += vma->node.size;
 268                                         else
 269                                                 stats->inactive += vma->node.size;
 270
 271                                         if (i915_vma_is_closed(vma))
 272                                                 stats->closed += vma->node.size;
 273                                 }
 274                                 break;
 275                         }
 276                         if (cmp < 0)
 277                                 p = p->rb_right;
 278                         else
 279                                 p = p->rb_left;
 280                 }
 281         }
 282         spin_unlock(&obj->vma.lock);
 283
 284         i915_gem_object_put(obj);
 285         return 0;
 286 }
 287
 288 #define print_file_stats(m, name, stats) do { \
 289         if (stats.count) \
 290                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu closed)\n", \
 291                            name, \
 292                            stats.count, \
 293                            stats.total, \
 294                            stats.active, \
 295                            stats.inactive, \
 296                            stats.closed); \
 297 } while (0)
 298
 299 static void print_context_stats(struct seq_file *m,
 300                                 struct drm_i915_private *i915)
 301 {
 302         struct file_stats kstats = {};
 303         struct i915_gem_context *ctx, *cn;
 304
 305         spin_lock(&i915->gem.contexts.lock);
 306         list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
 307                 struct i915_gem_engines_iter it;
 308                 struct intel_context *ce;
 309
 310                 if (!kref_get_unless_zero(&ctx->ref))
 311                         continue;
 312
 313                 spin_unlock(&i915->gem.contexts.lock);
 314
 315                 for_each_gem_engine(ce,
 316                                     i915_gem_context_lock_engines(ctx), it) {
 317                         if (intel_context_pin_if_active(ce)) {
 318                                 rcu_read_lock();
 319                                 if (ce->state)
 320                                         per_file_stats(0,
 321                                                        ce->state->obj, &kstats);
 322                                 per_file_stats(0, ce->ring->vma->obj, &kstats);
 323                                 rcu_read_unlock();
 324                                 intel_context_unpin(ce);
 325                         }
 326                 }
 327                 i915_gem_context_unlock_engines(ctx);
 328
 329                 mutex_lock(&ctx->mutex);
 330                 if (!IS_ERR_OR_NULL(ctx->file_priv)) {
 331                         struct file_stats stats = {
 332                                 .vm = rcu_access_pointer(ctx->vm),
 333                         };
 334                         struct drm_file *file = ctx->file_priv->file;
 335                         struct task_struct *task;
 336                         char name[80];
 337
 338                         rcu_read_lock();
 339                         idr_for_each(&file->object_idr, per_file_stats, &stats);
 340                         rcu_read_unlock();
 341
 342                         rcu_read_lock();
 343                         task = pid_task(ctx->pid ?: file->pid, PIDTYPE_PID);
 344                         snprintf(name, sizeof(name), "%s",
 345                                  task ? task->comm : "<unknown>");
 346                         rcu_read_unlock();
 347
 348                         print_file_stats(m, name, stats);
 349                 }
 350                 mutex_unlock(&ctx->mutex);
 351
 352                 spin_lock(&i915->gem.contexts.lock);
 353                 list_safe_reset_next(ctx, cn, link);
 354                 i915_gem_context_put(ctx);
 355         }
 356         spin_unlock(&i915->gem.contexts.lock);
 357
 358         print_file_stats(m, "[k]contexts", kstats);
 359 }
 360
 361 static int i915_gem_object_info(struct seq_file *m, void *data)
 362 {
 363         struct drm_i915_private *i915 = node_to_i915(m->private);
 364         struct intel_memory_region *mr;
 365         enum intel_region_id id;
 366
 367         seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
 368                    i915->mm.shrink_count,
 369                    atomic_read(&i915->mm.free_count),
 370                    i915->mm.shrink_memory);
 371         for_each_memory_region(mr, i915, id)
 372                 seq_printf(m, "%s: total:%pa, available:%pa bytes\n",
 373                            mr->name, &mr->total, &mr->avail);
 374         seq_putc(m, '\n');
 375
 376         print_context_stats(m, i915);
 377
 378         return 0;
 379 }
 380
 381 static void gen8_display_interrupt_info(struct seq_file *m)
 382 {
 383         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 384         enum pipe pipe;
 385
 386         for_each_pipe(dev_priv, pipe) {
 387                 enum intel_display_power_domain power_domain;
 388                 intel_wakeref_t wakeref;
 389
 390                 power_domain = POWER_DOMAIN_PIPE(pipe);
 391                 wakeref = intel_display_power_get_if_enabled(dev_priv,
 392                                                              power_domain);
 393                 if (!wakeref) {
 394                         seq_printf(m, "Pipe %c power disabled\n",
 395                                    pipe_name(pipe));
 396                         continue;
 397                 }
 398                 seq_printf(m, "Pipe %c IMR:\t%08x\n",
 399                            pipe_name(pipe),
 400                            I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 401                 seq_printf(m, "Pipe %c IIR:\t%08x\n",
 402                            pipe_name(pipe),
 403                            I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 404                 seq_printf(m, "Pipe %c IER:\t%08x\n",
 405                            pipe_name(pipe),
 406                            I915_READ(GEN8_DE_PIPE_IER(pipe)));
 407
 408                 intel_display_power_put(dev_priv, power_domain, wakeref);
 409         }
 410
 411         seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 412                    I915_READ(GEN8_DE_PORT_IMR));
 413         seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 414                    I915_READ(GEN8_DE_PORT_IIR));
 415         seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 416                    I915_READ(GEN8_DE_PORT_IER));
 417
 418         seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 419                    I915_READ(GEN8_DE_MISC_IMR));
 420         seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 421                    I915_READ(GEN8_DE_MISC_IIR));
 422         seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 423                    I915_READ(GEN8_DE_MISC_IER));
 424
 425         seq_printf(m, "PCU interrupt mask:\t%08x\n",
 426                    I915_READ(GEN8_PCU_IMR));
 427         seq_printf(m, "PCU interrupt identity:\t%08x\n",
 428                    I915_READ(GEN8_PCU_IIR));
 429         seq_printf(m, "PCU interrupt enable:\t%08x\n",
 430                    I915_READ(GEN8_PCU_IER));
 431 }
 432
 433 static int i915_interrupt_info(struct seq_file *m, void *data)
 434 {
 435         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 436         struct intel_engine_cs *engine;
 437         intel_wakeref_t wakeref;
 438         int i, pipe;
 439
 440         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 441
 442         if (IS_CHERRYVIEW(dev_priv)) {
 443                 intel_wakeref_t pref;
 444
 445                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 446                            I915_READ(GEN8_MASTER_IRQ));
 447
 448                 seq_printf(m, "Display IER:\t%08x\n",
 449                            I915_READ(VLV_IER));
 450                 seq_printf(m, "Display IIR:\t%08x\n",
 451                            I915_READ(VLV_IIR));
 452                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 453                            I915_READ(VLV_IIR_RW));
 454                 seq_printf(m, "Display IMR:\t%08x\n",
 455                            I915_READ(VLV_IMR));
 456                 for_each_pipe(dev_priv, pipe) {
 457                         enum intel_display_power_domain power_domain;
 458
 459                         power_domain = POWER_DOMAIN_PIPE(pipe);
 460                         pref = intel_display_power_get_if_enabled(dev_priv,
 461                                                                   power_domain);
 462                         if (!pref) {
 463                                 seq_printf(m, "Pipe %c power disabled\n",
 464                                            pipe_name(pipe));
 465                                 continue;
 466                         }
 467
 468                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 469                                    pipe_name(pipe),
 470                                    I915_READ(PIPESTAT(pipe)));
 471
 472                         intel_display_power_put(dev_priv, power_domain, pref);
 473                 }
 474
 475                 pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 476                 seq_printf(m, "Port hotplug:\t%08x\n",
 477                            I915_READ(PORT_HOTPLUG_EN));
 478                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 479                            I915_READ(VLV_DPFLIPSTAT));
 480                 seq_printf(m, "DPINVGTT:\t%08x\n",
 481                            I915_READ(DPINVGTT));
 482                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
 483
 484                 for (i = 0; i < 4; i++) {
 485                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 486                                    i, I915_READ(GEN8_GT_IMR(i)));
 487                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 488                                    i, I915_READ(GEN8_GT_IIR(i)));
 489                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 490                                    i, I915_READ(GEN8_GT_IER(i)));
 491                 }
 492
 493                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 494                            I915_READ(GEN8_PCU_IMR));
 495                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 496                            I915_READ(GEN8_PCU_IIR));
 497                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 498                            I915_READ(GEN8_PCU_IER));
 499         } else if (INTEL_GEN(dev_priv) >= 11) {
 500                 if (HAS_MASTER_UNIT_IRQ(dev_priv))
 501                         seq_printf(m, "Master Unit Interrupt Control:  %08x\n",
 502                                    I915_READ(DG1_MSTR_UNIT_INTR));
 503
 504                 seq_printf(m, "Master Interrupt Control:  %08x\n",
 505                            I915_READ(GEN11_GFX_MSTR_IRQ));
 506
 507                 seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
 508                            I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
 509                 seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
 510                            I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
 511                 seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
 512                            I915_READ(GEN11_GUC_SG_INTR_ENABLE));
 513                 seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
 514                            I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
 515                 seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
 516                            I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
 517                 seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
 518                            I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
 519
 520                 seq_printf(m, "Display Interrupt Control:\t%08x\n",
 521                            I915_READ(GEN11_DISPLAY_INT_CTL));
 522
 523                 gen8_display_interrupt_info(m);
 524         } else if (INTEL_GEN(dev_priv) >= 8) {
 525                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 526                            I915_READ(GEN8_MASTER_IRQ));
 527
 528                 for (i = 0; i < 4; i++) {
 529                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 530                                    i, I915_READ(GEN8_GT_IMR(i)));
 531                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 532                                    i, I915_READ(GEN8_GT_IIR(i)));
 533                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 534                                    i, I915_READ(GEN8_GT_IER(i)));
 535                 }
 536
 537                 gen8_display_interrupt_info(m);
 538         } else if (IS_VALLEYVIEW(dev_priv)) {
 539                 intel_wakeref_t pref;
 540
 541                 seq_printf(m, "Display IER:\t%08x\n",
 542                            I915_READ(VLV_IER));
 543                 seq_printf(m, "Display IIR:\t%08x\n",
 544                            I915_READ(VLV_IIR));
 545                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 546                            I915_READ(VLV_IIR_RW));
 547                 seq_printf(m, "Display IMR:\t%08x\n",
 548                            I915_READ(VLV_IMR));
 549                 for_each_pipe(dev_priv, pipe) {
 550                         enum intel_display_power_domain power_domain;
 551
 552                         power_domain = POWER_DOMAIN_PIPE(pipe);
 553                         pref = intel_display_power_get_if_enabled(dev_priv,
 554                                                                   power_domain);
 555                         if (!pref) {
 556                                 seq_printf(m, "Pipe %c power disabled\n",
 557                                            pipe_name(pipe));
 558                                 continue;
 559                         }
 560
 561                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 562                                    pipe_name(pipe),
 563                                    I915_READ(PIPESTAT(pipe)));
 564                         intel_display_power_put(dev_priv, power_domain, pref);
 565                 }
 566
 567                 seq_printf(m, "Master IER:\t%08x\n",
 568                            I915_READ(VLV_MASTER_IER));
 569
 570                 seq_printf(m, "Render IER:\t%08x\n",
 571                            I915_READ(GTIER));
 572                 seq_printf(m, "Render IIR:\t%08x\n",
 573                            I915_READ(GTIIR));
 574                 seq_printf(m, "Render IMR:\t%08x\n",
 575                            I915_READ(GTIMR));
 576
 577                 seq_printf(m, "PM IER:\t\t%08x\n",
 578                            I915_READ(GEN6_PMIER));
 579                 seq_printf(m, "PM IIR:\t\t%08x\n",
 580                            I915_READ(GEN6_PMIIR));
 581                 seq_printf(m, "PM IMR:\t\t%08x\n",
 582                            I915_READ(GEN6_PMIMR));
 583
 584                 pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 585                 seq_printf(m, "Port hotplug:\t%08x\n",
 586                            I915_READ(PORT_HOTPLUG_EN));
 587                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 588                            I915_READ(VLV_DPFLIPSTAT));
 589                 seq_printf(m, "DPINVGTT:\t%08x\n",
 590                            I915_READ(DPINVGTT));
 591                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
 592
 593         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 594                 seq_printf(m, "Interrupt enable:    %08x\n",
 595                            I915_READ(GEN2_IER));
 596                 seq_printf(m, "Interrupt identity:  %08x\n",
 597                            I915_READ(GEN2_IIR));
 598                 seq_printf(m, "Interrupt mask:      %08x\n",
 599                            I915_READ(GEN2_IMR));
 600                 for_each_pipe(dev_priv, pipe)
 601                         seq_printf(m, "Pipe %c stat:         %08x\n",
 602                                    pipe_name(pipe),
 603                                    I915_READ(PIPESTAT(pipe)));
 604         } else {
 605                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 606                            I915_READ(DEIER));
 607                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 608                            I915_READ(DEIIR));
 609                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 610                            I915_READ(DEIMR));
 611                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 612                            I915_READ(SDEIER));
 613                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 614                            I915_READ(SDEIIR));
 615                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 616                            I915_READ(SDEIMR));
 617                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 618                            I915_READ(GTIER));
 619                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 620                            I915_READ(GTIIR));
 621                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 622                            I915_READ(GTIMR));
 623         }
 624
 625         if (INTEL_GEN(dev_priv) >= 11) {
 626                 seq_printf(m, "RCS Intr Mask:\t %08x\n",
 627                            I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
 628                 seq_printf(m, "BCS Intr Mask:\t %08x\n",
 629                            I915_READ(GEN11_BCS_RSVD_INTR_MASK));
 630                 seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
 631                            I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
 632                 seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
 633                            I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
 634                 seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
 635                            I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
 636                 seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
 637                            I915_READ(GEN11_GUC_SG_INTR_MASK));
 638                 seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
 639                            I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
 640                 seq_printf(m, "Crypto Intr Mask:\t %08x\n",
 641                            I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
 642                 seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
 643                            I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
 644
 645         } else if (INTEL_GEN(dev_priv) >= 6) {
 646                 for_each_uabi_engine(engine, dev_priv) {
 647                         seq_printf(m,
 648                                    "Graphics Interrupt mask (%s):       %08x\n",
 649                                    engine->name, ENGINE_READ(engine, RING_IMR));
 650                 }
 651         }
 652
 653         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
 654
 655         return 0;
 656 }
 657
 658 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 659 {
 660         struct drm_i915_private *i915 = node_to_i915(m->private);
 661         unsigned int i;
 662
 663         seq_printf(m, "Total fences = %d\n", i915->ggtt.num_fences);
 664
 665         rcu_read_lock();
 666         for (i = 0; i < i915->ggtt.num_fences; i++) {
 667                 struct i915_fence_reg *reg = &i915->ggtt.fence_regs[i];
 668                 struct i915_vma *vma = reg->vma;
 669
 670                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 671                            i, atomic_read(&reg->pin_count));
 672                 if (!vma)
 673                         seq_puts(m, "unused");
 674                 else
 675                         i915_debugfs_describe_obj(m, vma->obj);
 676                 seq_putc(m, '\n');
 677         }
 678         rcu_read_unlock();
 679
 680         return 0;
 681 }
 682
 683 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 684 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
 685                               size_t count, loff_t *pos)
 686 {
 687         struct i915_gpu_coredump *error;
 688         ssize_t ret;
 689         void *buf;
 690
 691         error = file->private_data;
 692         if (!error)
 693                 return 0;
 694
 695         /* Bounce buffer required because of kernfs __user API convenience. */
 696         buf = kmalloc(count, GFP_KERNEL);
 697         if (!buf)
 698                 return -ENOMEM;
 699
 700         ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);
 701         if (ret <= 0)
 702                 goto out;
 703
 704         if (!copy_to_user(ubuf, buf, ret))
 705                 *pos += ret;
 706         else
 707                 ret = -EFAULT;
 708
 709 out:
 710         kfree(buf);
 711         return ret;
 712 }
 713
 714 static int gpu_state_release(struct inode *inode, struct file *file)
 715 {
 716         i915_gpu_coredump_put(file->private_data);
 717         return 0;
 718 }
 719
 720 static int i915_gpu_info_open(struct inode *inode, struct file *file)
 721 {
 722         struct drm_i915_private *i915 = inode->i_private;
 723         struct i915_gpu_coredump *gpu;
 724         intel_wakeref_t wakeref;
 725
 726         gpu = NULL;
 727         with_intel_runtime_pm(&i915->runtime_pm, wakeref)
 728                 gpu = i915_gpu_coredump(i915);
 729         if (IS_ERR(gpu))
 730                 return PTR_ERR(gpu);
 731
 732         file->private_data = gpu;
 733         return 0;
 734 }
 735
 736 static const struct file_operations i915_gpu_info_fops = {
 737         .owner = THIS_MODULE,
 738         .open = i915_gpu_info_open,
 739         .read = gpu_state_read,
 740         .llseek = default_llseek,
 741         .release = gpu_state_release,
 742 };
 743
 744 static ssize_t
 745 i915_error_state_write(struct file *filp,
 746                        const char __user *ubuf,
 747                        size_t cnt,
 748                        loff_t *ppos)
 749 {
 750         struct i915_gpu_coredump *error = filp->private_data;
 751
 752         if (!error)
 753                 return 0;
 754
 755         drm_dbg(&error->i915->drm, "Resetting error state\n");
 756         i915_reset_error_state(error->i915);
 757
 758         return cnt;
 759 }
 760
 761 static int i915_error_state_open(struct inode *inode, struct file *file)
 762 {
 763         struct i915_gpu_coredump *error;
 764
 765         error = i915_first_error_state(inode->i_private);
 766         if (IS_ERR(error))
 767                 return PTR_ERR(error);
 768
 769         file->private_data  = error;
 770         return 0;
 771 }
 772
 773 static const struct file_operations i915_error_state_fops = {
 774         .owner = THIS_MODULE,
 775         .open = i915_error_state_open,
 776         .read = gpu_state_read,
 777         .write = i915_error_state_write,
 778         .llseek = default_llseek,
 779         .release = gpu_state_release,
 780 };
 781 #endif
 782
 783 static int i915_frequency_info(struct seq_file *m, void *unused)
 784 {
 785         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 786         struct intel_uncore *uncore = &dev_priv->uncore;
 787         struct intel_rps *rps = &dev_priv->gt.rps;
 788         intel_wakeref_t wakeref;
 789         int ret = 0;
 790
 791         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 792
 793         if (IS_GEN(dev_priv, 5)) {
 794                 u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
 795                 u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
 796
 797                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 798                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 799                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 800                            MEMSTAT_VID_SHIFT);
 801                 seq_printf(m, "Current P-state: %d\n",
 802                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 803         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 804                 u32 rpmodectl, freq_sts;
 805
 806                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
 807                 seq_printf(m, "Video Turbo Mode: %s\n",
 808                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
 809                 seq_printf(m, "HW control enabled: %s\n",
 810                            yesno(rpmodectl & GEN6_RP_ENABLE));
 811                 seq_printf(m, "SW control enabled: %s\n",
 812                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
 813                                   GEN6_RP_MEDIA_SW_MODE));
 814
 815                 vlv_punit_get(dev_priv);
 816                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
 817                 vlv_punit_put(dev_priv);
 818
 819                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
 820                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
 821
 822                 seq_printf(m, "actual GPU freq: %d MHz\n",
 823                            intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
 824
 825                 seq_printf(m, "current GPU freq: %d MHz\n",
 826                            intel_gpu_freq(rps, rps->cur_freq));
 827
 828                 seq_printf(m, "max GPU freq: %d MHz\n",
 829                            intel_gpu_freq(rps, rps->max_freq));
 830
 831                 seq_printf(m, "min GPU freq: %d MHz\n",
 832                            intel_gpu_freq(rps, rps->min_freq));
 833
 834                 seq_printf(m, "idle GPU freq: %d MHz\n",
 835                            intel_gpu_freq(rps, rps->idle_freq));
 836
 837                 seq_printf(m,
 838                            "efficient (RPe) frequency: %d MHz\n",
 839                            intel_gpu_freq(rps, rps->efficient_freq));
 840         } else if (INTEL_GEN(dev_priv) >= 6) {
 841                 u32 rp_state_limits;
 842                 u32 gt_perf_status;
 843                 u32 rp_state_cap;
 844                 u32 rpmodectl, rpinclimit, rpdeclimit;
 845                 u32 rpstat, cagf, reqf;
 846                 u32 rpupei, rpcurup, rpprevup;
 847                 u32 rpdownei, rpcurdown, rpprevdown;
 848                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
 849                 int max_freq;
 850
 851                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 852                 if (IS_GEN9_LP(dev_priv)) {
 853                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
 854                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
 855                 } else {
 856                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 857                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 858                 }
 859
 860                 /* RPSTAT1 is in the GT power well */
 861                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
 862
 863                 reqf = I915_READ(GEN6_RPNSWREQ);
 864                 if (INTEL_GEN(dev_priv) >= 9)
 865                         reqf >>= 23;
 866                 else {
 867                         reqf &= ~GEN6_TURBO_DISABLE;
 868                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 869                                 reqf >>= 24;
 870                         else
 871                                 reqf >>= 25;
 872                 }
 873                 reqf = intel_gpu_freq(rps, reqf);
 874
 875                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
 876                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
 877                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
 878
 879                 rpstat = I915_READ(GEN6_RPSTAT1);
 880                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
 881                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
 882                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
 883                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
 884                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
 885                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
 886                 cagf = intel_rps_read_actual_frequency(rps);
 887
 888                 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
 889
 890                 if (INTEL_GEN(dev_priv) >= 11) {
 891                         pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
 892                         pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
 893                         /*
 894                          * The equivalent to the PM ISR & IIR cannot be read
 895                          * without affecting the current state of the system
 896                          */
 897                         pm_isr = 0;
 898                         pm_iir = 0;
 899                 } else if (INTEL_GEN(dev_priv) >= 8) {
 900                         pm_ier = I915_READ(GEN8_GT_IER(2));
 901                         pm_imr = I915_READ(GEN8_GT_IMR(2));
 902                         pm_isr = I915_READ(GEN8_GT_ISR(2));
 903                         pm_iir = I915_READ(GEN8_GT_IIR(2));
 904                 } else {
 905                         pm_ier = I915_READ(GEN6_PMIER);
 906                         pm_imr = I915_READ(GEN6_PMIMR);
 907                         pm_isr = I915_READ(GEN6_PMISR);
 908                         pm_iir = I915_READ(GEN6_PMIIR);
 909                 }
 910                 pm_mask = I915_READ(GEN6_PMINTRMSK);
 911
 912                 seq_printf(m, "Video Turbo Mode: %s\n",
 913                            yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
 914                 seq_printf(m, "HW control enabled: %s\n",
 915                            yesno(rpmodectl & GEN6_RP_ENABLE));
 916                 seq_printf(m, "SW control enabled: %s\n",
 917                            yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
 918                                   GEN6_RP_MEDIA_SW_MODE));
 919
 920                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
 921                            pm_ier, pm_imr, pm_mask);
 922                 if (INTEL_GEN(dev_priv) <= 10)
 923                         seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
 924                                    pm_isr, pm_iir);
 925                 seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
 926                            rps->pm_intrmsk_mbz);
 927                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 928                 seq_printf(m, "Render p-state ratio: %d\n",
 929                            (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
 930                 seq_printf(m, "Render p-state VID: %d\n",
 931                            gt_perf_status & 0xff);
 932                 seq_printf(m, "Render p-state limit: %d\n",
 933                            rp_state_limits & 0xff);
 934                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 935                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
 936                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
 937                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
 938                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
 939                 seq_printf(m, "CAGF: %dMHz\n", cagf);
 940                 seq_printf(m, "RP CUR UP EI: %d (%dns)\n",
 941                            rpupei,
 942                            intel_gt_pm_interval_to_ns(&dev_priv->gt, rpupei));
 943                 seq_printf(m, "RP CUR UP: %d (%dun)\n",
 944                            rpcurup,
 945                            intel_gt_pm_interval_to_ns(&dev_priv->gt, rpcurup));
 946                 seq_printf(m, "RP PREV UP: %d (%dns)\n",
 947                            rpprevup,
 948                            intel_gt_pm_interval_to_ns(&dev_priv->gt, rpprevup));
 949                 seq_printf(m, "Up threshold: %d%%\n",
 950                            rps->power.up_threshold);
 951
 952                 seq_printf(m, "RP CUR DOWN EI: %d (%dns)\n",
 953                            rpdownei,
 954                            intel_gt_pm_interval_to_ns(&dev_priv->gt,
 955                                                       rpdownei));
 956                 seq_printf(m, "RP CUR DOWN: %d (%dns)\n",
 957                            rpcurdown,
 958                            intel_gt_pm_interval_to_ns(&dev_priv->gt,
 959                                                       rpcurdown));
 960                 seq_printf(m, "RP PREV DOWN: %d (%dns)\n",
 961                            rpprevdown,
 962                            intel_gt_pm_interval_to_ns(&dev_priv->gt,
 963                                                       rpprevdown));
 964                 seq_printf(m, "Down threshold: %d%%\n",
 965                            rps->power.down_threshold);
 966
 967                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
 968                             rp_state_cap >> 16) & 0xff;
 969                 max_freq *= (IS_GEN9_BC(dev_priv) ||
 970                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 971                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 972                            intel_gpu_freq(rps, max_freq));
 973
 974                 max_freq = (rp_state_cap & 0xff00) >> 8;
 975                 max_freq *= (IS_GEN9_BC(dev_priv) ||
 976                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 977                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 978                            intel_gpu_freq(rps, max_freq));
 979
 980                 max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
 981                             rp_state_cap >> 0) & 0xff;
 982                 max_freq *= (IS_GEN9_BC(dev_priv) ||
 983                              INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
 984                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 985                            intel_gpu_freq(rps, max_freq));
 986                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
 987                            intel_gpu_freq(rps, rps->max_freq));
 988
 989                 seq_printf(m, "Current freq: %d MHz\n",
 990                            intel_gpu_freq(rps, rps->cur_freq));
 991                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
 992                 seq_printf(m, "Idle freq: %d MHz\n",
 993                            intel_gpu_freq(rps, rps->idle_freq));
 994                 seq_printf(m, "Min freq: %d MHz\n",
 995                            intel_gpu_freq(rps, rps->min_freq));
 996                 seq_printf(m, "Boost freq: %d MHz\n",
 997                            intel_gpu_freq(rps, rps->boost_freq));
 998                 seq_printf(m, "Max freq: %d MHz\n",
 999                            intel_gpu_freq(rps, rps->max_freq));
1000                 seq_printf(m,
1001                            "efficient (RPe) frequency: %d MHz\n",
1002                            intel_gpu_freq(rps, rps->efficient_freq));
1003         } else {
1004                 seq_puts(m, "no P-state info available\n");
1005         }
1006
1007         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
1008         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1009         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1010
1011         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1012         return ret;
1013 }
1014
1015 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1016 {
1017         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1018         struct intel_rps *rps = &dev_priv->gt.rps;
1019         unsigned int max_gpu_freq, min_gpu_freq;
1020         intel_wakeref_t wakeref;
1021         int gpu_freq, ia_freq;
1022
1023         if (!HAS_LLC(dev_priv))
1024                 return -ENODEV;
1025
1026         min_gpu_freq = rps->min_freq;
1027         max_gpu_freq = rps->max_freq;
1028         if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
1029                 /* Convert GT frequency to 50 HZ units */
1030                 min_gpu_freq /= GEN9_FREQ_SCALER;
1031                 max_gpu_freq /= GEN9_FREQ_SCALER;
1032         }
1033
1034         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1035
1036         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1037         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1038                 ia_freq = gpu_freq;
1039                 sandybridge_pcode_read(dev_priv,
1040                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1041                                        &ia_freq, NULL);
1042                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1043                            intel_gpu_freq(rps,
1044                                           (gpu_freq *
1045                                            (IS_GEN9_BC(dev_priv) ||
1046                                             INTEL_GEN(dev_priv) >= 10 ?
1047                                             GEN9_FREQ_SCALER : 1))),
1048                            ((ia_freq >> 0) & 0xff) * 100,
1049                            ((ia_freq >> 8) & 0xff) * 100);
1050         }
1051         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1052
1053         return 0;
1054 }
1055
1056 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1057 {
1058         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, emit: %u)",
1059                    ring->space, ring->head, ring->tail, ring->emit);
1060 }
1061
1062 static int i915_context_status(struct seq_file *m, void *unused)
1063 {
1064         struct drm_i915_private *i915 = node_to_i915(m->private);
1065         struct i915_gem_context *ctx, *cn;
1066
1067         spin_lock(&i915->gem.contexts.lock);
1068         list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
1069                 struct i915_gem_engines_iter it;
1070                 struct intel_context *ce;
1071
1072                 if (!kref_get_unless_zero(&ctx->ref))
1073                         continue;
1074
1075                 spin_unlock(&i915->gem.contexts.lock);
1076
1077                 seq_puts(m, "HW context ");
1078                 if (ctx->pid) {
1079                         struct task_struct *task;
1080
1081                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1082                         if (task) {
1083                                 seq_printf(m, "(%s [%d]) ",
1084                                            task->comm, task->pid);
1085                                 put_task_struct(task);
1086                         }
1087                 } else if (IS_ERR(ctx->file_priv)) {
1088                         seq_puts(m, "(deleted) ");
1089                 } else {
1090                         seq_puts(m, "(kernel) ");
1091                 }
1092
1093                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1094                 seq_putc(m, '\n');
1095
1096                 for_each_gem_engine(ce,
1097                                     i915_gem_context_lock_engines(ctx), it) {
1098                         if (intel_context_pin_if_active(ce)) {
1099                                 seq_printf(m, "%s: ", ce->engine->name);
1100                                 if (ce->state)
1101                                         i915_debugfs_describe_obj(m, ce->state->obj);
1102                                 describe_ctx_ring(m, ce->ring);
1103                                 seq_putc(m, '\n');
1104                                 intel_context_unpin(ce);
1105                         }
1106                 }
1107                 i915_gem_context_unlock_engines(ctx);
1108
1109                 seq_putc(m, '\n');
1110
1111                 spin_lock(&i915->gem.contexts.lock);
1112                 list_safe_reset_next(ctx, cn, link);
1113                 i915_gem_context_put(ctx);
1114         }
1115         spin_unlock(&i915->gem.contexts.lock);
1116
1117         return 0;
1118 }
1119
1120 static const char *swizzle_string(unsigned swizzle)
1121 {
1122         switch (swizzle) {
1123         case I915_BIT_6_SWIZZLE_NONE:
1124                 return "none";
1125         case I915_BIT_6_SWIZZLE_9:
1126                 return "bit9";
1127         case I915_BIT_6_SWIZZLE_9_10:
1128                 return "bit9/bit10";
1129         case I915_BIT_6_SWIZZLE_9_11:
1130                 return "bit9/bit11";
1131         case I915_BIT_6_SWIZZLE_9_10_11:
1132                 return "bit9/bit10/bit11";
1133         case I915_BIT_6_SWIZZLE_9_17:
1134                 return "bit9/bit17";
1135         case I915_BIT_6_SWIZZLE_9_10_17:
1136                 return "bit9/bit10/bit17";
1137         case I915_BIT_6_SWIZZLE_UNKNOWN:
1138                 return "unknown";
1139         }
1140
1141         return "bug";
1142 }
1143
1144 static int i915_swizzle_info(struct seq_file *m, void *data)
1145 {
1146         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1147         struct intel_uncore *uncore = &dev_priv->uncore;
1148         intel_wakeref_t wakeref;
1149
1150         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1151                    swizzle_string(dev_priv->ggtt.bit_6_swizzle_x));
1152         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1153                    swizzle_string(dev_priv->ggtt.bit_6_swizzle_y));
1154
1155         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
1156                 seq_puts(m, "L-shaped memory detected\n");
1157
1158         /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
1159         if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
1160                 return 0;
1161
1162         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1163
1164         if (IS_GEN_RANGE(dev_priv, 3, 4)) {
1165                 seq_printf(m, "DDC = 0x%08x\n",
1166                            intel_uncore_read(uncore, DCC));
1167                 seq_printf(m, "DDC2 = 0x%08x\n",
1168                            intel_uncore_read(uncore, DCC2));
1169                 seq_printf(m, "C0DRB3 = 0x%04x\n",
1170                            intel_uncore_read16(uncore, C0DRB3));
1171                 seq_printf(m, "C1DRB3 = 0x%04x\n",
1172                            intel_uncore_read16(uncore, C1DRB3));
1173         } else if (INTEL_GEN(dev_priv) >= 6) {
1174                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1175                            intel_uncore_read(uncore, MAD_DIMM_C0));
1176                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1177                            intel_uncore_read(uncore, MAD_DIMM_C1));
1178                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1179                            intel_uncore_read(uncore, MAD_DIMM_C2));
1180                 seq_printf(m, "TILECTL = 0x%08x\n",
1181                            intel_uncore_read(uncore, TILECTL));
1182                 if (INTEL_GEN(dev_priv) >= 8)
1183                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1184                                    intel_uncore_read(uncore, GAMTARBMODE));
1185                 else
1186                         seq_printf(m, "ARB_MODE = 0x%08x\n",
1187                                    intel_uncore_read(uncore, ARB_MODE));
1188                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1189                            intel_uncore_read(uncore, DISP_ARB_CTL));
1190         }
1191
1192         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1193
1194         return 0;
1195 }
1196
1197 static const char *rps_power_to_str(unsigned int power)
1198 {
1199         static const char * const strings[] = {
1200                 [LOW_POWER] = "low power",
1201                 [BETWEEN] = "mixed",
1202                 [HIGH_POWER] = "high power",
1203         };
1204
1205         if (power >= ARRAY_SIZE(strings) || !strings[power])
1206                 return "unknown";
1207
1208         return strings[power];
1209 }
1210
1211 static int i915_rps_boost_info(struct seq_file *m, void *data)
1212 {
1213         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1214         struct intel_rps *rps = &dev_priv->gt.rps;
1215
1216         seq_printf(m, "RPS enabled? %s\n", yesno(intel_rps_is_enabled(rps)));
1217         seq_printf(m, "RPS active? %s\n", yesno(intel_rps_is_active(rps)));
1218         seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
1219         seq_printf(m, "Boosts outstanding? %d\n",
1220                    atomic_read(&rps->num_waiters));
1221         seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
1222         seq_printf(m, "Frequency requested %d, actual %d\n",
1223                    intel_gpu_freq(rps, rps->cur_freq),
1224                    intel_rps_read_actual_frequency(rps));
1225         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
1226                    intel_gpu_freq(rps, rps->min_freq),
1227                    intel_gpu_freq(rps, rps->min_freq_softlimit),
1228                    intel_gpu_freq(rps, rps->max_freq_softlimit),
1229                    intel_gpu_freq(rps, rps->max_freq));
1230         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
1231                    intel_gpu_freq(rps, rps->idle_freq),
1232                    intel_gpu_freq(rps, rps->efficient_freq),
1233                    intel_gpu_freq(rps, rps->boost_freq));
1234
1235         seq_printf(m, "Wait boosts: %d\n", atomic_read(&rps->boosts));
1236
1237         if (INTEL_GEN(dev_priv) >= 6 && intel_rps_is_active(rps)) {
1238                 u32 rpup, rpupei;
1239                 u32 rpdown, rpdownei;
1240
1241                 intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
1242                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
1243                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
1244                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
1245                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
1246                 intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
1247
1248                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
1249                            rps_power_to_str(rps->power.mode));
1250                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
1251                            rpup && rpupei ? 100 * rpup / rpupei : 0,
1252                            rps->power.up_threshold);
1253                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
1254                            rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
1255                            rps->power.down_threshold);
1256         } else {
1257                 seq_puts(m, "\nRPS Autotuning inactive\n");
1258         }
1259
1260         return 0;
1261 }
1262
1263 static int i915_llc(struct seq_file *m, void *data)
1264 {
1265         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1266         const bool edram = INTEL_GEN(dev_priv) > 8;
1267
1268         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
1269         seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
1270                    dev_priv->edram_size_mb);
1271
1272         return 0;
1273 }
1274
1275 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
1276 {
1277         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1278         struct pci_dev *pdev = dev_priv->drm.pdev;
1279
1280         if (!HAS_RUNTIME_PM(dev_priv))
1281                 seq_puts(m, "Runtime power management not supported\n");
1282
1283         seq_printf(m, "Runtime power status: %s\n",
1284                    enableddisabled(!dev_priv->power_domains.wakeref));
1285
1286         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
1287         seq_printf(m, "IRQs disabled: %s\n",
1288                    yesno(!intel_irqs_enabled(dev_priv)));
1289 #ifdef CONFIG_PM
1290         seq_printf(m, "Usage count: %d\n",
1291                    atomic_read(&dev_priv->drm.dev->power.usage_count));
1292 #else
1293         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
1294 #endif
1295         seq_printf(m, "PCI device power state: %s [%d]\n",
1296                    pci_power_name(pdev->current_state),
1297                    pdev->current_state);
1298
1299         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
1300                 struct drm_printer p = drm_seq_file_printer(m);
1301
1302                 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
1303         }
1304
1305         return 0;
1306 }
1307
1308 static int i915_engine_info(struct seq_file *m, void *unused)
1309 {
1310         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1311         struct intel_engine_cs *engine;
1312         intel_wakeref_t wakeref;
1313         struct drm_printer p;
1314
1315         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
1316
1317         seq_printf(m, "GT awake? %s [%d]\n",
1318                    yesno(dev_priv->gt.awake),
1319                    atomic_read(&dev_priv->gt.wakeref.count));
1320         seq_printf(m, "CS timestamp frequency: %u Hz\n",
1321                    RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_hz);
1322
1323         p = drm_seq_file_printer(m);
1324         for_each_uabi_engine(engine, dev_priv)
1325                 intel_engine_dump(engine, &p, "%s\n", engine->name);
1326
1327         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
1328
1329         return 0;
1330 }
1331
1332 static int i915_shrinker_info(struct seq_file *m, void *unused)
1333 {
1334         struct drm_i915_private *i915 = node_to_i915(m->private);
1335
1336         seq_printf(m, "seeks = %d\n", i915->mm.shrinker.seeks);
1337         seq_printf(m, "batch = %lu\n", i915->mm.shrinker.batch);
1338
1339         return 0;
1340 }
1341
1342 static int i915_wa_registers(struct seq_file *m, void *unused)
1343 {
1344         struct drm_i915_private *i915 = node_to_i915(m->private);
1345         struct intel_engine_cs *engine;
1346
1347         for_each_uabi_engine(engine, i915) {
1348                 const struct i915_wa_list *wal = &engine->ctx_wa_list;
1349                 const struct i915_wa *wa;
1350                 unsigned int count;
1351
1352                 count = wal->count;
1353                 if (!count)
1354                         continue;
1355
1356                 seq_printf(m, "%s: Workarounds applied: %u\n",
1357                            engine->name, count);
1358
1359                 for (wa = wal->list; count--; wa++)
1360                         seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
1361                                    i915_mmio_reg_offset(wa->reg),
1362                                    wa->set, wa->clr);
1363
1364                 seq_printf(m, "\n");
1365         }
1366
1367         return 0;
1368 }
1369
1370 static int
1371 i915_wedged_get(void *data, u64 *val)
1372 {
1373         struct drm_i915_private *i915 = data;
1374         int ret = intel_gt_terminally_wedged(&i915->gt);
1375
1376         switch (ret) {
1377         case -EIO:
1378                 *val = 1;
1379                 return 0;
1380         case 0:
1381                 *val = 0;
1382                 return 0;
1383         default:
1384                 return ret;
1385         }
1386 }
1387
1388 static int
1389 i915_wedged_set(void *data, u64 val)
1390 {
1391         struct drm_i915_private *i915 = data;
1392
1393         /* Flush any previous reset before applying for a new one */
1394         wait_event(i915->gt.reset.queue,
1395                    !test_bit(I915_RESET_BACKOFF, &i915->gt.reset.flags));
1396
1397         intel_gt_handle_error(&i915->gt, val, I915_ERROR_CAPTURE,
1398                               "Manually set wedged engine mask = %llx", val);
1399         return 0;
1400 }
1401
1402 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
1403                         i915_wedged_get, i915_wedged_set,
1404                         "%llu\n");
1405
1406 static int
1407 i915_perf_noa_delay_set(void *data, u64 val)
1408 {
1409         struct drm_i915_private *i915 = data;
1410
1411         /*
1412          * This would lead to infinite waits as we're doing timestamp
1413          * difference on the CS with only 32bits.
1414          */
1415         if (i915_cs_timestamp_ns_to_ticks(i915, val) > U32_MAX)
1416                 return -EINVAL;
1417
1418         atomic64_set(&i915->perf.noa_programming_delay, val);
1419         return 0;
1420 }
1421
1422 static int
1423 i915_perf_noa_delay_get(void *data, u64 *val)
1424 {
1425         struct drm_i915_private *i915 = data;
1426
1427         *val = atomic64_read(&i915->perf.noa_programming_delay);
1428         return 0;
1429 }
1430
1431 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
1432                         i915_perf_noa_delay_get,
1433                         i915_perf_noa_delay_set,
1434                         "%llu\n");
1435
1436 #define DROP_UNBOUND    BIT(0)
1437 #define DROP_BOUND      BIT(1)
1438 #define DROP_RETIRE     BIT(2)
1439 #define DROP_ACTIVE     BIT(3)
1440 #define DROP_FREED      BIT(4)
1441 #define DROP_SHRINK_ALL BIT(5)
1442 #define DROP_IDLE       BIT(6)
1443 #define DROP_RESET_ACTIVE       BIT(7)
1444 #define DROP_RESET_SEQNO        BIT(8)
1445 #define DROP_RCU        BIT(9)
1446 #define DROP_ALL (DROP_UNBOUND  | \
1447                   DROP_BOUND    | \
1448                   DROP_RETIRE   | \
1449                   DROP_ACTIVE   | \
1450                   DROP_FREED    | \
1451                   DROP_SHRINK_ALL |\
1452                   DROP_IDLE     | \
1453                   DROP_RESET_ACTIVE | \
1454                   DROP_RESET_SEQNO | \
1455                   DROP_RCU)
1456 static int
1457 i915_drop_caches_get(void *data, u64 *val)
1458 {
1459         *val = DROP_ALL;
1460
1461         return 0;
1462 }
1463 static int
1464 gt_drop_caches(struct intel_gt *gt, u64 val)
1465 {
1466         int ret;
1467
1468         if (val & DROP_RESET_ACTIVE &&
1469             wait_for(intel_engines_are_idle(gt), I915_IDLE_ENGINES_TIMEOUT))
1470                 intel_gt_set_wedged(gt);
1471
1472         if (val & DROP_RETIRE)
1473                 intel_gt_retire_requests(gt);
1474
1475         if (val & (DROP_IDLE | DROP_ACTIVE)) {
1476                 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
1477                 if (ret)
1478                         return ret;
1479         }
1480
1481         if (val & DROP_IDLE) {
1482                 ret = intel_gt_pm_wait_for_idle(gt);
1483                 if (ret)
1484                         return ret;
1485         }
1486
1487         if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
1488                 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
1489
1490         if (val & DROP_FREED)
1491                 intel_gt_flush_buffer_pool(gt);
1492
1493         return 0;
1494 }
1495
1496 static int
1497 i915_drop_caches_set(void *data, u64 val)
1498 {
1499         struct drm_i915_private *i915 = data;
1500         int ret;
1501
1502         DRM_DEBUG("Dropping caches: 0x%08llx [0x%08llx]\n",
1503                   val, val & DROP_ALL);
1504
1505         ret = gt_drop_caches(&i915->gt, val);
1506         if (ret)
1507                 return ret;
1508
1509         fs_reclaim_acquire(GFP_KERNEL);
1510         if (val & DROP_BOUND)
1511                 i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
1512
1513         if (val & DROP_UNBOUND)
1514                 i915_gem_shrink(i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
1515
1516         if (val & DROP_SHRINK_ALL)
1517                 i915_gem_shrink_all(i915);
1518         fs_reclaim_release(GFP_KERNEL);
1519
1520         if (val & DROP_RCU)
1521                 rcu_barrier();
1522
1523         if (val & DROP_FREED)
1524                 i915_gem_drain_freed_objects(i915);
1525
1526         return 0;
1527 }
1528
1529 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
1530                         i915_drop_caches_get, i915_drop_caches_set,
1531                         "0x%08llx\n");
1532
1533 static int
1534 i915_cache_sharing_get(void *data, u64 *val)
1535 {
1536         struct drm_i915_private *dev_priv = data;
1537         intel_wakeref_t wakeref;
1538         u32 snpcr = 0;
1539
1540         if (!(IS_GEN_RANGE(dev_priv, 6, 7)))
1541                 return -ENODEV;
1542
1543         with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
1544                 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1545
1546         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
1547
1548         return 0;
1549 }
1550
1551 static int
1552 i915_cache_sharing_set(void *data, u64 val)
1553 {
1554         struct drm_i915_private *dev_priv = data;
1555         intel_wakeref_t wakeref;
1556
1557         if (!(IS_GEN_RANGE(dev_priv, 6, 7)))
1558                 return -ENODEV;
1559
1560         if (val > 3)
1561                 return -EINVAL;
1562
1563         drm_dbg(&dev_priv->drm,
1564                 "Manually setting uncore sharing to %llu\n", val);
1565         with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
1566                 u32 snpcr;
1567
1568                 /* Update the cache sharing policy here as well */
1569                 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1570                 snpcr &= ~GEN6_MBC_SNPCR_MASK;
1571                 snpcr |= val << GEN6_MBC_SNPCR_SHIFT;
1572                 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1573         }
1574
1575         return 0;
1576 }
1577
1578 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
1579                         i915_cache_sharing_get, i915_cache_sharing_set,
1580                         "%llu\n");
1581
1582 static int i915_sseu_status(struct seq_file *m, void *unused)
1583 {
1584         struct drm_i915_private *i915 = node_to_i915(m->private);
1585         struct intel_gt *gt = &i915->gt;
1586
1587         return intel_sseu_status(m, gt);
1588 }
1589
1590 static int i915_forcewake_open(struct inode *inode, struct file *file)
1591 {
1592         struct drm_i915_private *i915 = inode->i_private;
1593         struct intel_gt *gt = &i915->gt;
1594
1595         atomic_inc(&gt->user_wakeref);
1596         intel_gt_pm_get(gt);
1597         if (INTEL_GEN(i915) >= 6)
1598                 intel_uncore_forcewake_user_get(gt->uncore);
1599
1600         return 0;
1601 }
1602
1603 static int i915_forcewake_release(struct inode *inode, struct file *file)
1604 {
1605         struct drm_i915_private *i915 = inode->i_private;
1606         struct intel_gt *gt = &i915->gt;
1607
1608         if (INTEL_GEN(i915) >= 6)
1609                 intel_uncore_forcewake_user_put(&i915->uncore);
1610         intel_gt_pm_put(gt);
1611         atomic_dec(&gt->user_wakeref);
1612
1613         return 0;
1614 }
1615
1616 static const struct file_operations i915_forcewake_fops = {
1617         .owner = THIS_MODULE,
1618         .open = i915_forcewake_open,
1619         .release = i915_forcewake_release,
1620 };
1621
1622 static const struct drm_info_list i915_debugfs_list[] = {
1623         {"i915_capabilities", i915_capabilities, 0},
1624         {"i915_gem_objects", i915_gem_object_info, 0},
1625         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1626         {"i915_gem_interrupt", i915_interrupt_info, 0},
1627         {"i915_frequency_info", i915_frequency_info, 0},
1628         {"i915_ring_freq_table", i915_ring_freq_table, 0},
1629         {"i915_context_status", i915_context_status, 0},
1630         {"i915_swizzle_info", i915_swizzle_info, 0},
1631         {"i915_llc", i915_llc, 0},
1632         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
1633         {"i915_engine_info", i915_engine_info, 0},
1634         {"i915_shrinker_info", i915_shrinker_info, 0},
1635         {"i915_wa_registers", i915_wa_registers, 0},
1636         {"i915_sseu_status", i915_sseu_status, 0},
1637         {"i915_rps_boost_info", i915_rps_boost_info, 0},
1638 };
1639 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
1640
1641 static const struct i915_debugfs_files {
1642         const char *name;
1643         const struct file_operations *fops;
1644 } i915_debugfs_files[] = {
1645         {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
1646         {"i915_wedged", &i915_wedged_fops},
1647         {"i915_cache_sharing", &i915_cache_sharing_fops},
1648         {"i915_gem_drop_caches", &i915_drop_caches_fops},
1649 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
1650         {"i915_error_state", &i915_error_state_fops},
1651         {"i915_gpu_info", &i915_gpu_info_fops},
1652 #endif
1653 };
1654
1655 void i915_debugfs_register(struct drm_i915_private *dev_priv)
1656 {
1657         struct drm_minor *minor = dev_priv->drm.primary;
1658         int i;
1659
1660         i915_debugfs_params(dev_priv);
1661
1662         debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
1663                             to_i915(minor->dev), &i915_forcewake_fops);
1664         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
1665                 debugfs_create_file(i915_debugfs_files[i].name,
1666                                     S_IRUGO | S_IWUSR,
1667                                     minor->debugfs_root,
1668                                     to_i915(minor->dev),
1669                                     i915_debugfs_files[i].fops);
1670         }
1671
1672         drm_debugfs_create_files(i915_debugfs_list,
1673                                  I915_DEBUGFS_ENTRIES,
1674                                  minor->debugfs_root, minor);
1675 }