drivers/gpu/drm/i915/gvt/display.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Ke Yu
  25  *    Zhiyuan Lv <zhiyuan.lv@intel.com>
  26  *
  27  * Contributors:
  28  *    Terrence Xu <terrence.xu@intel.com>
  29  *    Changbin Du <changbin.du@intel.com>
  30  *    Bing Niu <bing.niu@intel.com>
  31  *    Zhi Wang <zhi.a.wang@intel.com>
  32  *
  33  */
  34
  35 #include "i915_drv.h"
  36 #include "gvt.h"
  37
  38 static int get_edp_pipe(struct intel_vgpu *vgpu)
  39 {
  40         u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
  41         int pipe = -1;
  42
  43         switch (data & TRANS_DDI_EDP_INPUT_MASK) {
  44         case TRANS_DDI_EDP_INPUT_A_ON:
  45         case TRANS_DDI_EDP_INPUT_A_ONOFF:
  46                 pipe = PIPE_A;
  47                 break;
  48         case TRANS_DDI_EDP_INPUT_B_ONOFF:
  49                 pipe = PIPE_B;
  50                 break;
  51         case TRANS_DDI_EDP_INPUT_C_ONOFF:
  52                 pipe = PIPE_C;
  53                 break;
  54         }
  55         return pipe;
  56 }
  57
  58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
  59 {
  60         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
  61
  62         if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
  63                 return 0;
  64
  65         if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
  66                 return 0;
  67         return 1;
  68 }
  69
  70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
  71 {
  72         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
  73
  74         if (drm_WARN_ON(&dev_priv->drm,
  75                         pipe < PIPE_A || pipe >= I915_MAX_PIPES))
  76                 return -EINVAL;
  77
  78         if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
  79                 return 1;
  80
  81         if (edp_pipe_is_enabled(vgpu) &&
  82                         get_edp_pipe(vgpu) == pipe)
  83                 return 1;
  84         return 0;
  85 }
  86
  87 static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {
  88         {
  89 /* EDID with 1024x768 as its resolution */
  90                 /*Header*/
  91                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
  92                 /* Vendor & Product Identification */
  93                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
  94                 /* Version & Revision */
  95                 0x01, 0x04,
  96                 /* Basic Display Parameters & Features */
  97                 0xa5, 0x34, 0x20, 0x78, 0x23,
  98                 /* Color Characteristics */
  99                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
 100                 /* Established Timings: maximum resolution is 1024x768 */
 101                 0x21, 0x08, 0x00,
 102                 /* Standard Timings. All invalid */
 103                 0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
 104                 0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
 105                 /* 18 Byte Data Blocks 1: invalid */
 106                 0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
 107                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
 108                 /* 18 Byte Data Blocks 2: invalid */
 109                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
 110                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 111                 /* 18 Byte Data Blocks 3: invalid */
 112                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
 113                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
 114                 /* 18 Byte Data Blocks 4: invalid */
 115                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
 116                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
 117                 /* Extension Block Count */
 118                 0x00,
 119                 /* Checksum */
 120                 0xef,
 121         },
 122         {
 123 /* EDID with 1920x1200 as its resolution */
 124                 /*Header*/
 125                 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
 126                 /* Vendor & Product Identification */
 127                 0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
 128                 /* Version & Revision */
 129                 0x01, 0x04,
 130                 /* Basic Display Parameters & Features */
 131                 0xa5, 0x34, 0x20, 0x78, 0x23,
 132                 /* Color Characteristics */
 133                 0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
 134                 /* Established Timings: maximum resolution is 1024x768 */
 135                 0x21, 0x08, 0x00,
 136                 /*
 137                  * Standard Timings.
 138                  * below new resolutions can be supported:
 139                  * 1920x1080, 1280x720, 1280x960, 1280x1024,
 140                  * 1440x900, 1600x1200, 1680x1050
 141                  */
 142                 0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
 143                 0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
 144                 /* 18 Byte Data Blocks 1: max resolution is 1920x1200 */
 145                 0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
 146                 0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
 147                 /* 18 Byte Data Blocks 2: invalid */
 148                 0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
 149                 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
 150                 /* 18 Byte Data Blocks 3: invalid */
 151                 0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
 152                 0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
 153                 /* 18 Byte Data Blocks 4: invalid */
 154                 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
 155                 0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
 156                 /* Extension Block Count */
 157                 0x00,
 158                 /* Checksum */
 159                 0x45,
 160         },
 161 };
 162
 163 #define DPCD_HEADER_SIZE        0xb
 164
 165 /* let the virtual display supports DP1.2 */
 166 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
 167         0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
 168 };
 169
 170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
 171 {
 172         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 173         int pipe;
 174
 175         if (IS_BROXTON(dev_priv)) {
 176                 enum transcoder trans;
 177                 enum port port;
 178
 179                 /* Clear PIPE, DDI, PHY, HPD before setting new */
 180                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
 181                         BXT_DE_PORT_HP_DDIB |
 182                         BXT_DE_PORT_HP_DDIC);
 183
 184                 for_each_pipe(dev_priv, pipe) {
 185                         vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
 186                                 ~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
 187                         vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
 188                         vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
 189                         vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
 190                         vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
 191                 }
 192
 193                 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
 194                         vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
 195                                 ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 196                                   TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
 197                 }
 198                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 199                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 200                           TRANS_DDI_PORT_MASK);
 201
 202                 for (port = PORT_A; port <= PORT_C; port++) {
 203                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
 204                                 ~BXT_PHY_LANE_ENABLED;
 205                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
 206                                 (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 207                                  BXT_PHY_LANE_POWERDOWN_ACK);
 208
 209                         vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
 210                                 ~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
 211                                   PORT_PLL_REF_SEL | PORT_PLL_LOCK |
 212                                   PORT_PLL_ENABLE);
 213
 214                         vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
 215                                 ~(DDI_INIT_DISPLAY_DETECTED |
 216                                   DDI_BUF_CTL_ENABLE);
 217                         vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
 218                 }
 219                 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
 220                         ~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
 221                 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
 222                         ~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
 223                 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
 224                         ~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
 225                 /* No hpd_invert set in vgpu vbt, need to clear invert mask */
 226                 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
 227                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
 228
 229                 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
 230                 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
 231                         ~PHY_POWER_GOOD;
 232                 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
 233                         ~PHY_POWER_GOOD;
 234                 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
 235                 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
 236
 237                 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
 238                 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
 239
 240                 /*
 241                  * Only 1 PIPE enabled in current vGPU display and PIPE_A is
 242                  *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
 243                  *   TRANSCODER_A can be enabled. PORT_x depends on the input of
 244                  *   setup_virtual_dp_monitor.
 245                  */
 246                 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
 247                 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
 248
 249                 /*
 250                  * Golden M/N are calculated based on:
 251                  *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
 252                  *   DP link clk 1620 MHz and non-constant_n.
 253                  * TODO: calculate DP link symbol clk and stream clk m/n.
 254                  */
 255                 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
 256                 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
 257                 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
 258                 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
 259                 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
 260
 261                 /* Enable per-DDI/PORT vreg */
 262                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 263                         vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
 264                         vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
 265                                 PHY_POWER_GOOD;
 266                         vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
 267                                 BIT(30);
 268                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
 269                                 BXT_PHY_LANE_ENABLED;
 270                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
 271                                 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
 272                                   BXT_PHY_LANE_POWERDOWN_ACK);
 273                         vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
 274                                 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
 275                                  PORT_PLL_REF_SEL | PORT_PLL_LOCK |
 276                                  PORT_PLL_ENABLE);
 277                         vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
 278                                 (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
 279                         vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
 280                                 ~DDI_BUF_IS_IDLE;
 281                         vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
 282                                 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 283                                  TRANS_DDI_FUNC_ENABLE);
 284                         vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
 285                                 PORTA_HOTPLUG_ENABLE;
 286                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 287                                 BXT_DE_PORT_HP_DDIA;
 288                 }
 289
 290                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 291                         vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
 292                         vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
 293                         vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
 294                                 PHY_POWER_GOOD;
 295                         vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
 296                                 BIT(30);
 297                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
 298                                 BXT_PHY_LANE_ENABLED;
 299                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
 300                                 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
 301                                   BXT_PHY_LANE_POWERDOWN_ACK);
 302                         vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
 303                                 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
 304                                  PORT_PLL_REF_SEL | PORT_PLL_LOCK |
 305                                  PORT_PLL_ENABLE);
 306                         vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
 307                                 DDI_BUF_CTL_ENABLE;
 308                         vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
 309                                 ~DDI_BUF_IS_IDLE;
 310                         vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 311                                 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 312                                  (PORT_B << TRANS_DDI_PORT_SHIFT) |
 313                                  TRANS_DDI_FUNC_ENABLE);
 314                         vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
 315                                 PORTB_HOTPLUG_ENABLE;
 316                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 317                                 BXT_DE_PORT_HP_DDIB;
 318                 }
 319
 320                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 321                         vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
 322                         vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
 323                         vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
 324                                 PHY_POWER_GOOD;
 325                         vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
 326                                 BIT(30);
 327                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
 328                                 BXT_PHY_LANE_ENABLED;
 329                         vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
 330                                 ~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
 331                                   BXT_PHY_LANE_POWERDOWN_ACK);
 332                         vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
 333                                 (PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
 334                                  PORT_PLL_REF_SEL | PORT_PLL_LOCK |
 335                                  PORT_PLL_ENABLE);
 336                         vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
 337                                 DDI_BUF_CTL_ENABLE;
 338                         vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
 339                                 ~DDI_BUF_IS_IDLE;
 340                         vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 341                                 (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 342                                  (PORT_B << TRANS_DDI_PORT_SHIFT) |
 343                                  TRANS_DDI_FUNC_ENABLE);
 344                         vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
 345                                 PORTC_HOTPLUG_ENABLE;
 346                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 347                                 BXT_DE_PORT_HP_DDIC;
 348                 }
 349
 350                 return;
 351         }
 352
 353         vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
 354                         SDE_PORTC_HOTPLUG_CPT |
 355                         SDE_PORTD_HOTPLUG_CPT);
 356
 357         if (IS_SKYLAKE(dev_priv) ||
 358             IS_KABYLAKE(dev_priv) ||
 359             IS_COFFEELAKE(dev_priv) ||
 360             IS_COMETLAKE(dev_priv)) {
 361                 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
 362                                 SDE_PORTE_HOTPLUG_SPT);
 363                 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
 364                                 SKL_FUSE_DOWNLOAD_STATUS |
 365                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG0) |
 366                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG1) |
 367                                 SKL_FUSE_PG_DIST_STATUS(SKL_PG2);
 368                 /*
 369                  * Only 1 PIPE enabled in current vGPU display and PIPE_A is
 370                  *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
 371                  *   TRANSCODER_A can be enabled. PORT_x depends on the input of
 372                  *   setup_virtual_dp_monitor, we can bind DPLL0 to any PORT_x
 373                  *   so we fixed to DPLL0 here.
 374                  * Setup DPLL0: DP link clk 1620 MHz, non SSC, DP Mode
 375                  */
 376                 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
 377                         DPLL_CTRL1_OVERRIDE(DPLL_ID_SKL_DPLL0);
 378                 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
 379                         DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, DPLL_ID_SKL_DPLL0);
 380                 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
 381                         LCPLL_PLL_ENABLE | LCPLL_PLL_LOCK;
 382                 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
 383                 /*
 384                  * Golden M/N are calculated based on:
 385                  *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
 386                  *   DP link clk 1620 MHz and non-constant_n.
 387                  * TODO: calculate DP link symbol clk and stream clk m/n.
 388                  */
 389                 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
 390                 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
 391                 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
 392                 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
 393                 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
 394         }
 395
 396         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 397                 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
 398                         ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B);
 399                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 400                         DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_B);
 401                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 402                         DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B);
 403                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
 404                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 405                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 406                         TRANS_DDI_PORT_MASK);
 407                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 408                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 409                         (PORT_B << TRANS_DDI_PORT_SHIFT) |
 410                         TRANS_DDI_FUNC_ENABLE);
 411                 if (IS_BROADWELL(dev_priv)) {
 412                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
 413                                 ~PORT_CLK_SEL_MASK;
 414                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
 415                                 PORT_CLK_SEL_LCPLL_810;
 416                 }
 417                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
 418                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
 419                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
 420         }
 421
 422         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 423                 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
 424                         ~DPLL_CTRL2_DDI_CLK_OFF(PORT_C);
 425                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 426                         DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_C);
 427                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 428                         DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C);
 429                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
 430                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 431                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 432                         TRANS_DDI_PORT_MASK);
 433                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 434                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 435                         (PORT_C << TRANS_DDI_PORT_SHIFT) |
 436                         TRANS_DDI_FUNC_ENABLE);
 437                 if (IS_BROADWELL(dev_priv)) {
 438                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
 439                                 ~PORT_CLK_SEL_MASK;
 440                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
 441                                 PORT_CLK_SEL_LCPLL_810;
 442                 }
 443                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
 444                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
 445                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
 446         }
 447
 448         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
 449                 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
 450                         ~DPLL_CTRL2_DDI_CLK_OFF(PORT_D);
 451                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 452                         DPLL_CTRL2_DDI_CLK_SEL(DPLL_ID_SKL_DPLL0, PORT_D);
 453                 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
 454                         DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D);
 455                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
 456                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
 457                         ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
 458                         TRANS_DDI_PORT_MASK);
 459                 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
 460                         (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
 461                         (PORT_D << TRANS_DDI_PORT_SHIFT) |
 462                         TRANS_DDI_FUNC_ENABLE);
 463                 if (IS_BROADWELL(dev_priv)) {
 464                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
 465                                 ~PORT_CLK_SEL_MASK;
 466                         vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
 467                                 PORT_CLK_SEL_LCPLL_810;
 468                 }
 469                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
 470                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
 471                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
 472         }
 473
 474         if ((IS_SKYLAKE(dev_priv) ||
 475              IS_KABYLAKE(dev_priv) ||
 476              IS_COFFEELAKE(dev_priv) ||
 477              IS_COMETLAKE(dev_priv)) &&
 478                         intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
 479                 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
 480         }
 481
 482         if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 483                 if (IS_BROADWELL(dev_priv))
 484                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 485                                 GEN8_PORT_DP_A_HOTPLUG;
 486                 else
 487                         vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
 488
 489                 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
 490         }
 491
 492         /* Clear host CRT status, so guest couldn't detect this host CRT. */
 493         if (IS_BROADWELL(dev_priv))
 494                 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
 495
 496         /* Disable Primary/Sprite/Cursor plane */
 497         for_each_pipe(dev_priv, pipe) {
 498                 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
 499                 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
 500                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
 501                 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
 502         }
 503
 504         vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
 505 }
 506
 507 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
 508 {
 509         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
 510
 511         kfree(port->edid);
 512         port->edid = NULL;
 513
 514         kfree(port->dpcd);
 515         port->dpcd = NULL;
 516 }
 517
 518 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
 519                                     int type, unsigned int resolution)
 520 {
 521         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
 522         struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
 523
 524         if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
 525                 return -EINVAL;
 526
 527         port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
 528         if (!port->edid)
 529                 return -ENOMEM;
 530
 531         port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL);
 532         if (!port->dpcd) {
 533                 kfree(port->edid);
 534                 return -ENOMEM;
 535         }
 536
 537         memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],
 538                         EDID_SIZE);
 539         port->edid->data_valid = true;
 540
 541         memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE);
 542         port->dpcd->data_valid = true;
 543         port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
 544         port->type = type;
 545         port->id = resolution;
 546
 547         emulate_monitor_status_change(vgpu);
 548
 549         return 0;
 550 }
 551
 552 /**
 553  * intel_gvt_check_vblank_emulation - check if vblank emulation timer should
 554  * be turned on/off when a virtual pipe is enabled/disabled.
 555  * @gvt: a GVT device
 556  *
 557  * This function is used to turn on/off vblank timer according to currently
 558  * enabled/disabled virtual pipes.
 559  *
 560  */
 561 void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt)
 562 {
 563         struct intel_gvt_irq *irq = &gvt->irq;
 564         struct intel_vgpu *vgpu;
 565         int pipe, id;
 566         int found = false;
 567
 568         mutex_lock(&gvt->lock);
 569         for_each_active_vgpu(gvt, vgpu, id) {
 570                 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {
 571                         if (pipe_is_enabled(vgpu, pipe)) {
 572                                 found = true;
 573                                 break;
 574                         }
 575                 }
 576                 if (found)
 577                         break;
 578         }
 579
 580         /* all the pipes are disabled */
 581         if (!found)
 582                 hrtimer_cancel(&irq->vblank_timer.timer);
 583         else
 584                 hrtimer_start(&irq->vblank_timer.timer,
 585                         ktime_add_ns(ktime_get(), irq->vblank_timer.period),
 586                         HRTIMER_MODE_ABS);
 587         mutex_unlock(&gvt->lock);
 588 }
 589
 590 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
 591 {
 592         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 593         struct intel_vgpu_irq *irq = &vgpu->irq;
 594         int vblank_event[] = {
 595                 [PIPE_A] = PIPE_A_VBLANK,
 596                 [PIPE_B] = PIPE_B_VBLANK,
 597                 [PIPE_C] = PIPE_C_VBLANK,
 598         };
 599         int event;
 600
 601         if (pipe < PIPE_A || pipe > PIPE_C)
 602                 return;
 603
 604         for_each_set_bit(event, irq->flip_done_event[pipe],
 605                         INTEL_GVT_EVENT_MAX) {
 606                 clear_bit(event, irq->flip_done_event[pipe]);
 607                 if (!pipe_is_enabled(vgpu, pipe))
 608                         continue;
 609
 610                 intel_vgpu_trigger_virtual_event(vgpu, event);
 611         }
 612
 613         if (pipe_is_enabled(vgpu, pipe)) {
 614                 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
 615                 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
 616         }
 617 }
 618
 619 static void emulate_vblank(struct intel_vgpu *vgpu)
 620 {
 621         int pipe;
 622
 623         mutex_lock(&vgpu->vgpu_lock);
 624         for_each_pipe(vgpu->gvt->gt->i915, pipe)
 625                 emulate_vblank_on_pipe(vgpu, pipe);
 626         mutex_unlock(&vgpu->vgpu_lock);
 627 }
 628
 629 /**
 630  * intel_gvt_emulate_vblank - trigger vblank events for vGPUs on GVT device
 631  * @gvt: a GVT device
 632  *
 633  * This function is used to trigger vblank interrupts for vGPUs on GVT device
 634  *
 635  */
 636 void intel_gvt_emulate_vblank(struct intel_gvt *gvt)
 637 {
 638         struct intel_vgpu *vgpu;
 639         int id;
 640
 641         mutex_lock(&gvt->lock);
 642         for_each_active_vgpu(gvt, vgpu, id)
 643                 emulate_vblank(vgpu);
 644         mutex_unlock(&gvt->lock);
 645 }
 646
 647 /**
 648  * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
 649  * @vgpu: a vGPU
 650  * @connected: link state
 651  *
 652  * This function is used to trigger hotplug interrupt for vGPU
 653  *
 654  */
 655 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
 656 {
 657         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
 658
 659         /* TODO: add more platforms support */
 660         if (IS_SKYLAKE(i915) ||
 661             IS_KABYLAKE(i915) ||
 662             IS_COFFEELAKE(i915) ||
 663             IS_COMETLAKE(i915)) {
 664                 if (connected) {
 665                         vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
 666                                 SFUSE_STRAP_DDID_DETECTED;
 667                         vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
 668                 } else {
 669                         vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
 670                                 ~SFUSE_STRAP_DDID_DETECTED;
 671                         vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
 672                 }
 673                 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
 674                 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
 675                                 PORTD_HOTPLUG_STATUS_MASK;
 676                 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
 677         } else if (IS_BROXTON(i915)) {
 678                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
 679                         if (connected) {
 680                                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 681                                         BXT_DE_PORT_HP_DDIA;
 682                         } else {
 683                                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
 684                                         ~BXT_DE_PORT_HP_DDIA;
 685                         }
 686                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
 687                                 BXT_DE_PORT_HP_DDIA;
 688                         vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
 689                                 ~PORTA_HOTPLUG_STATUS_MASK;
 690                         vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
 691                                 PORTA_HOTPLUG_LONG_DETECT;
 692                         intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
 693                 }
 694                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
 695                         if (connected) {
 696                                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 697                                         BXT_DE_PORT_HP_DDIB;
 698                                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
 699                                         SFUSE_STRAP_DDIB_DETECTED;
 700                         } else {
 701                                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
 702                                         ~BXT_DE_PORT_HP_DDIB;
 703                                 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
 704                                         ~SFUSE_STRAP_DDIB_DETECTED;
 705                         }
 706                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
 707                                 BXT_DE_PORT_HP_DDIB;
 708                         vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
 709                                 ~PORTB_HOTPLUG_STATUS_MASK;
 710                         vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
 711                                 PORTB_HOTPLUG_LONG_DETECT;
 712                         intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
 713                 }
 714                 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
 715                         if (connected) {
 716                                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
 717                                         BXT_DE_PORT_HP_DDIC;
 718                                 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
 719                                         SFUSE_STRAP_DDIC_DETECTED;
 720                         } else {
 721                                 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
 722                                         ~BXT_DE_PORT_HP_DDIC;
 723                                 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
 724                                         ~SFUSE_STRAP_DDIC_DETECTED;
 725                         }
 726                         vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
 727                                 BXT_DE_PORT_HP_DDIC;
 728                         vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
 729                                 ~PORTC_HOTPLUG_STATUS_MASK;
 730                         vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
 731                                 PORTC_HOTPLUG_LONG_DETECT;
 732                         intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
 733                 }
 734         }
 735 }
 736
 737 /**
 738  * intel_vgpu_clean_display - clean vGPU virtual display emulation
 739  * @vgpu: a vGPU
 740  *
 741  * This function is used to clean vGPU virtual display emulation stuffs
 742  *
 743  */
 744 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
 745 {
 746         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 747
 748         if (IS_SKYLAKE(dev_priv) ||
 749             IS_KABYLAKE(dev_priv) ||
 750             IS_COFFEELAKE(dev_priv) ||
 751             IS_COMETLAKE(dev_priv))
 752                 clean_virtual_dp_monitor(vgpu, PORT_D);
 753         else
 754                 clean_virtual_dp_monitor(vgpu, PORT_B);
 755 }
 756
 757 /**
 758  * intel_vgpu_init_display- initialize vGPU virtual display emulation
 759  * @vgpu: a vGPU
 760  * @resolution: resolution index for intel_vgpu_edid
 761  *
 762  * This function is used to initialize vGPU virtual display emulation stuffs
 763  *
 764  * Returns:
 765  * Zero on success, negative error code if failed.
 766  *
 767  */
 768 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
 769 {
 770         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 771
 772         intel_vgpu_init_i2c_edid(vgpu);
 773
 774         if (IS_SKYLAKE(dev_priv) ||
 775             IS_KABYLAKE(dev_priv) ||
 776             IS_COFFEELAKE(dev_priv) ||
 777             IS_COMETLAKE(dev_priv))
 778                 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
 779                                                 resolution);
 780         else
 781                 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
 782                                                 resolution);
 783 }
 784
 785 /**
 786  * intel_vgpu_reset_display- reset vGPU virtual display emulation
 787  * @vgpu: a vGPU
 788  *
 789  * This function is used to reset vGPU virtual display emulation stuffs
 790  *
 791  */
 792 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
 793 {
 794         emulate_monitor_status_change(vgpu);
 795 }