2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Kevin Tian <kevin.tian@intel.com>
28 * Pei Zhang <pei.zhang@intel.com>
29 * Min He <min.he@intel.com>
30 * Niu Bing <bing.niu@intel.com>
31 * Yulei Zhang <yulei.zhang@intel.com>
32 * Zhenyu Wang <zhenyuw@linux.intel.com>
33 * Zhi Wang <zhi.a.wang@intel.com>
38 #include "gt/intel_ggtt_fencing.h"
41 static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
43 struct intel_gvt *gvt = vgpu->gvt;
44 struct intel_gt *gt = gvt->gt;
47 struct drm_mm_node *node;
51 node = &vgpu->gm.high_gm_node;
52 size = vgpu_hidden_sz(vgpu);
53 start = ALIGN(gvt_hidden_gmadr_base(gvt), I915_GTT_PAGE_SIZE);
54 end = ALIGN(gvt_hidden_gmadr_end(gvt), I915_GTT_PAGE_SIZE);
57 node = &vgpu->gm.low_gm_node;
58 size = vgpu_aperture_sz(vgpu);
59 start = ALIGN(gvt_aperture_gmadr_base(gvt), I915_GTT_PAGE_SIZE);
60 end = ALIGN(gvt_aperture_gmadr_end(gvt), I915_GTT_PAGE_SIZE);
64 mutex_lock(>->ggtt->vm.mutex);
65 mmio_hw_access_pre(gt);
66 ret = i915_gem_gtt_insert(>->ggtt->vm, node,
67 size, I915_GTT_PAGE_SIZE,
68 I915_COLOR_UNEVICTABLE,
70 mmio_hw_access_post(gt);
71 mutex_unlock(>->ggtt->vm.mutex);
73 gvt_err("fail to alloc %s gm space from host\n",
74 high_gm ? "high" : "low");
79 static int alloc_vgpu_gm(struct intel_vgpu *vgpu)
81 struct intel_gvt *gvt = vgpu->gvt;
82 struct intel_gt *gt = gvt->gt;
85 ret = alloc_gm(vgpu, false);
89 ret = alloc_gm(vgpu, true);
91 goto out_free_aperture;
93 gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,
94 vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu));
96 gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,
97 vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu));
101 mutex_lock(>->ggtt->vm.mutex);
102 drm_mm_remove_node(&vgpu->gm.low_gm_node);
103 mutex_unlock(>->ggtt->vm.mutex);
107 static void free_vgpu_gm(struct intel_vgpu *vgpu)
109 struct intel_gvt *gvt = vgpu->gvt;
110 struct intel_gt *gt = gvt->gt;
112 mutex_lock(>->ggtt->vm.mutex);
113 drm_mm_remove_node(&vgpu->gm.low_gm_node);
114 drm_mm_remove_node(&vgpu->gm.high_gm_node);
115 mutex_unlock(>->ggtt->vm.mutex);
119 * intel_vgpu_write_fence - write fence registers owned by a vGPU
120 * @vgpu: vGPU instance
121 * @fence: vGPU fence register number
122 * @value: Fence register value to be written
124 * This function is used to write fence registers owned by a vGPU. The vGPU
125 * fence register number will be translated into HW fence register number.
128 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
129 u32 fence, u64 value)
131 struct intel_gvt *gvt = vgpu->gvt;
132 struct drm_i915_private *i915 = gvt->gt->i915;
133 struct intel_uncore *uncore = gvt->gt->uncore;
134 struct i915_fence_reg *reg;
135 i915_reg_t fence_reg_lo, fence_reg_hi;
137 assert_rpm_wakelock_held(uncore->rpm);
139 if (drm_WARN_ON(&i915->drm, fence >= vgpu_fence_sz(vgpu)))
142 reg = vgpu->fence.regs[fence];
143 if (drm_WARN_ON(&i915->drm, !reg))
146 fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
147 fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
149 intel_uncore_write(uncore, fence_reg_lo, 0);
150 intel_uncore_posting_read(uncore, fence_reg_lo);
152 intel_uncore_write(uncore, fence_reg_hi, upper_32_bits(value));
153 intel_uncore_write(uncore, fence_reg_lo, lower_32_bits(value));
154 intel_uncore_posting_read(uncore, fence_reg_lo);
157 static void _clear_vgpu_fence(struct intel_vgpu *vgpu)
161 for (i = 0; i < vgpu_fence_sz(vgpu); i++)
162 intel_vgpu_write_fence(vgpu, i, 0);
165 static void free_vgpu_fence(struct intel_vgpu *vgpu)
167 struct intel_gvt *gvt = vgpu->gvt;
168 struct intel_uncore *uncore = gvt->gt->uncore;
169 struct i915_fence_reg *reg;
170 intel_wakeref_t wakeref;
173 if (drm_WARN_ON(&gvt->gt->i915->drm, !vgpu_fence_sz(vgpu)))
176 wakeref = intel_runtime_pm_get(uncore->rpm);
178 mutex_lock(&gvt->gt->ggtt->vm.mutex);
179 _clear_vgpu_fence(vgpu);
180 for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
181 reg = vgpu->fence.regs[i];
182 i915_unreserve_fence(reg);
183 vgpu->fence.regs[i] = NULL;
185 mutex_unlock(&gvt->gt->ggtt->vm.mutex);
187 intel_runtime_pm_put(uncore->rpm, wakeref);
190 static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
192 struct intel_gvt *gvt = vgpu->gvt;
193 struct intel_uncore *uncore = gvt->gt->uncore;
194 struct i915_fence_reg *reg;
195 intel_wakeref_t wakeref;
198 wakeref = intel_runtime_pm_get(uncore->rpm);
200 /* Request fences from host */
201 mutex_lock(&gvt->gt->ggtt->vm.mutex);
203 for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
204 reg = i915_reserve_fence(gvt->gt->ggtt);
208 vgpu->fence.regs[i] = reg;
211 _clear_vgpu_fence(vgpu);
213 mutex_unlock(&gvt->gt->ggtt->vm.mutex);
214 intel_runtime_pm_put(uncore->rpm, wakeref);
218 gvt_vgpu_err("Failed to alloc fences\n");
219 /* Return fences to host, if fail */
220 for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
221 reg = vgpu->fence.regs[i];
224 i915_unreserve_fence(reg);
225 vgpu->fence.regs[i] = NULL;
227 mutex_unlock(&gvt->gt->ggtt->vm.mutex);
228 intel_runtime_pm_put_unchecked(uncore->rpm);
232 static void free_resource(struct intel_vgpu *vgpu)
234 struct intel_gvt *gvt = vgpu->gvt;
236 gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu);
237 gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu);
238 gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu);
241 static int alloc_resource(struct intel_vgpu *vgpu,
242 struct intel_vgpu_creation_params *param)
244 struct intel_gvt *gvt = vgpu->gvt;
245 unsigned long request, avail, max, taken;
248 if (!param->low_gm_sz || !param->high_gm_sz || !param->fence_sz) {
249 gvt_vgpu_err("Invalid vGPU creation params\n");
253 item = "low GM space";
254 max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
255 taken = gvt->gm.vgpu_allocated_low_gm_size;
257 request = MB_TO_BYTES(param->low_gm_sz);
260 goto no_enough_resource;
262 vgpu_aperture_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE);
264 item = "high GM space";
265 max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
266 taken = gvt->gm.vgpu_allocated_high_gm_size;
268 request = MB_TO_BYTES(param->high_gm_sz);
271 goto no_enough_resource;
273 vgpu_hidden_sz(vgpu) = ALIGN(request, I915_GTT_PAGE_SIZE);
276 max = gvt_fence_sz(gvt) - HOST_FENCE;
277 taken = gvt->fence.vgpu_allocated_fence_num;
279 request = param->fence_sz;
282 goto no_enough_resource;
284 vgpu_fence_sz(vgpu) = request;
286 gvt->gm.vgpu_allocated_low_gm_size += MB_TO_BYTES(param->low_gm_sz);
287 gvt->gm.vgpu_allocated_high_gm_size += MB_TO_BYTES(param->high_gm_sz);
288 gvt->fence.vgpu_allocated_fence_num += param->fence_sz;
292 gvt_err("fail to allocate resource %s\n", item);
293 gvt_err("request %luMB avail %luMB max %luMB taken %luMB\n",
294 BYTES_TO_MB(request), BYTES_TO_MB(avail),
295 BYTES_TO_MB(max), BYTES_TO_MB(taken));
300 * inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU
303 * This function is used to free the HW resource owned by a vGPU.
306 void intel_vgpu_free_resource(struct intel_vgpu *vgpu)
309 free_vgpu_fence(vgpu);
314 * intel_vgpu_reset_resource - reset resource state owned by a vGPU
317 * This function is used to reset resource state owned by a vGPU.
320 void intel_vgpu_reset_resource(struct intel_vgpu *vgpu)
322 struct intel_gvt *gvt = vgpu->gvt;
323 intel_wakeref_t wakeref;
325 with_intel_runtime_pm(gvt->gt->uncore->rpm, wakeref)
326 _clear_vgpu_fence(vgpu);
330 * intel_alloc_vgpu_resource - allocate HW resource for a vGPU
332 * @param: vGPU creation params
334 * This function is used to allocate HW resource for a vGPU. User specifies
335 * the resource configuration through the creation params.
338 * zero on success, negative error code if failed.
341 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
342 struct intel_vgpu_creation_params *param)
346 ret = alloc_resource(vgpu, param);
350 ret = alloc_vgpu_gm(vgpu);
352 goto out_free_resource;
354 ret = alloc_vgpu_fence(vgpu);
356 goto out_free_vgpu_gm;