2 * Copyright © 2008-2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
30 #include "gen2_engine_cs.h"
31 #include "gen6_engine_cs.h"
32 #include "gen6_ppgtt.h"
33 #include "gen7_renderclear.h"
35 #include "i915_mitigations.h"
36 #include "intel_breadcrumbs.h"
37 #include "intel_context.h"
39 #include "intel_reset.h"
40 #include "intel_ring.h"
41 #include "shmem_utils.h"
43 /* Rough estimate of the typical request size, performing a flush,
44 * set-context and then emitting the batch.
46 #define LEGACY_REQUEST_SIZE 200
48 static void set_hwstam(struct intel_engine_cs *engine, u32 mask)
51 * Keep the render interrupt unmasked as this papers over
52 * lost interrupts following a reset.
54 if (engine->class == RENDER_CLASS) {
55 if (INTEL_GEN(engine->i915) >= 6)
58 mask &= ~I915_USER_INTERRUPT;
61 intel_engine_set_hwsp_writemask(engine, mask);
64 static void set_hws_pga(struct intel_engine_cs *engine, phys_addr_t phys)
68 addr = lower_32_bits(phys);
69 if (INTEL_GEN(engine->i915) >= 4)
70 addr |= (phys >> 28) & 0xf0;
72 intel_uncore_write(engine->uncore, HWS_PGA, addr);
75 static struct page *status_page(struct intel_engine_cs *engine)
77 struct drm_i915_gem_object *obj = engine->status_page.vma->obj;
79 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
80 return sg_page(obj->mm.pages->sgl);
83 static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
85 set_hws_pga(engine, PFN_PHYS(page_to_pfn(status_page(engine))));
86 set_hwstam(engine, ~0u);
89 static void set_hwsp(struct intel_engine_cs *engine, u32 offset)
94 * The ring status page addresses are no longer next to the rest of
95 * the ring registers as of gen7.
97 if (IS_GEN(engine->i915, 7)) {
100 * No more rings exist on Gen7. Default case is only to shut up
101 * gcc switch check warning.
104 GEM_BUG_ON(engine->id);
107 hwsp = RENDER_HWS_PGA_GEN7;
110 hwsp = BLT_HWS_PGA_GEN7;
113 hwsp = BSD_HWS_PGA_GEN7;
116 hwsp = VEBOX_HWS_PGA_GEN7;
119 } else if (IS_GEN(engine->i915, 6)) {
120 hwsp = RING_HWS_PGA_GEN6(engine->mmio_base);
122 hwsp = RING_HWS_PGA(engine->mmio_base);
125 intel_uncore_write(engine->uncore, hwsp, offset);
126 intel_uncore_posting_read(engine->uncore, hwsp);
129 static void flush_cs_tlb(struct intel_engine_cs *engine)
131 struct drm_i915_private *dev_priv = engine->i915;
133 if (!IS_GEN_RANGE(dev_priv, 6, 7))
136 /* ring should be idle before issuing a sync flush*/
137 drm_WARN_ON(&dev_priv->drm,
138 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
140 ENGINE_WRITE(engine, RING_INSTPM,
141 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
143 if (intel_wait_for_register(engine->uncore,
144 RING_INSTPM(engine->mmio_base),
145 INSTPM_SYNC_FLUSH, 0,
147 drm_err(&dev_priv->drm,
148 "%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
152 static void ring_setup_status_page(struct intel_engine_cs *engine)
154 set_hwsp(engine, i915_ggtt_offset(engine->status_page.vma));
155 set_hwstam(engine, ~0u);
157 flush_cs_tlb(engine);
160 static bool stop_ring(struct intel_engine_cs *engine)
162 struct drm_i915_private *dev_priv = engine->i915;
164 if (INTEL_GEN(dev_priv) > 2) {
166 RING_MI_MODE, _MASKED_BIT_ENABLE(STOP_RING));
167 if (intel_wait_for_register(engine->uncore,
168 RING_MI_MODE(engine->mmio_base),
172 drm_err(&dev_priv->drm,
173 "%s : timed out trying to stop ring\n",
177 * Sometimes we observe that the idle flag is not
178 * set even though the ring is empty. So double
179 * check before giving up.
181 if (ENGINE_READ(engine, RING_HEAD) !=
182 ENGINE_READ(engine, RING_TAIL))
187 ENGINE_WRITE(engine, RING_HEAD, ENGINE_READ(engine, RING_TAIL));
189 ENGINE_WRITE(engine, RING_HEAD, 0);
190 ENGINE_WRITE(engine, RING_TAIL, 0);
192 /* The ring must be empty before it is disabled */
193 ENGINE_WRITE(engine, RING_CTL, 0);
195 return (ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) == 0;
198 static struct i915_address_space *vm_alias(struct i915_address_space *vm)
200 if (i915_is_ggtt(vm))
201 vm = &i915_vm_to_ggtt(vm)->alias->vm;
206 static u32 pp_dir(struct i915_address_space *vm)
208 return to_gen6_ppgtt(i915_vm_to_ppgtt(vm))->pp_dir;
211 static void set_pp_dir(struct intel_engine_cs *engine)
213 struct i915_address_space *vm = vm_alias(engine->gt->vm);
216 ENGINE_WRITE(engine, RING_PP_DIR_DCLV, PP_DIR_DCLV_2G);
217 ENGINE_WRITE(engine, RING_PP_DIR_BASE, pp_dir(vm));
221 static int xcs_resume(struct intel_engine_cs *engine)
223 struct drm_i915_private *dev_priv = engine->i915;
224 struct intel_ring *ring = engine->legacy.ring;
227 ENGINE_TRACE(engine, "ring:{HEAD:%04x, TAIL:%04x}\n",
228 ring->head, ring->tail);
230 intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
232 /* WaClearRingBufHeadRegAtInit:ctg,elk */
233 if (!stop_ring(engine)) {
234 /* G45 ring initialization often fails to reset head to zero */
235 drm_dbg(&dev_priv->drm, "%s head not reset to zero "
236 "ctl %08x head %08x tail %08x start %08x\n",
238 ENGINE_READ(engine, RING_CTL),
239 ENGINE_READ(engine, RING_HEAD),
240 ENGINE_READ(engine, RING_TAIL),
241 ENGINE_READ(engine, RING_START));
243 if (!stop_ring(engine)) {
244 drm_err(&dev_priv->drm,
245 "failed to set %s head to zero "
246 "ctl %08x head %08x tail %08x start %08x\n",
248 ENGINE_READ(engine, RING_CTL),
249 ENGINE_READ(engine, RING_HEAD),
250 ENGINE_READ(engine, RING_TAIL),
251 ENGINE_READ(engine, RING_START));
257 if (HWS_NEEDS_PHYSICAL(dev_priv))
258 ring_setup_phys_status_page(engine);
260 ring_setup_status_page(engine);
262 intel_breadcrumbs_reset(engine->breadcrumbs);
264 /* Enforce ordering by reading HEAD register back */
265 ENGINE_POSTING_READ(engine, RING_HEAD);
268 * Initialize the ring. This must happen _after_ we've cleared the ring
269 * registers with the above sequence (the readback of the HEAD registers
270 * also enforces ordering), otherwise the hw might lose the new ring
273 ENGINE_WRITE(engine, RING_START, i915_ggtt_offset(ring->vma));
275 /* Check that the ring offsets point within the ring! */
276 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->head));
277 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
278 intel_ring_update_space(ring);
282 /* First wake the ring up to an empty/idle ring */
283 ENGINE_WRITE(engine, RING_HEAD, ring->head);
284 ENGINE_WRITE(engine, RING_TAIL, ring->head);
285 ENGINE_POSTING_READ(engine, RING_TAIL);
287 ENGINE_WRITE(engine, RING_CTL, RING_CTL_SIZE(ring->size) | RING_VALID);
289 /* If the head is still not zero, the ring is dead */
290 if (intel_wait_for_register(engine->uncore,
291 RING_CTL(engine->mmio_base),
292 RING_VALID, RING_VALID,
294 drm_err(&dev_priv->drm, "%s initialization failed "
295 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
297 ENGINE_READ(engine, RING_CTL),
298 ENGINE_READ(engine, RING_CTL) & RING_VALID,
299 ENGINE_READ(engine, RING_HEAD), ring->head,
300 ENGINE_READ(engine, RING_TAIL), ring->tail,
301 ENGINE_READ(engine, RING_START),
302 i915_ggtt_offset(ring->vma));
307 if (INTEL_GEN(dev_priv) > 2)
309 RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
311 /* Now awake, let it get started */
312 if (ring->tail != ring->head) {
313 ENGINE_WRITE(engine, RING_TAIL, ring->tail);
314 ENGINE_POSTING_READ(engine, RING_TAIL);
317 /* Papering over lost _interrupts_ immediately following the restart */
318 intel_engine_signal_breadcrumbs(engine);
320 intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
325 static void reset_prepare(struct intel_engine_cs *engine)
327 struct intel_uncore *uncore = engine->uncore;
328 const u32 base = engine->mmio_base;
331 * We stop engines, otherwise we might get failed reset and a
332 * dead gpu (on elk). Also as modern gpu as kbl can suffer
333 * from system hang if batchbuffer is progressing when
334 * the reset is issued, regardless of READY_TO_RESET ack.
335 * Thus assume it is best to stop engines on all gens
336 * where we have a gpu reset.
338 * WaKBLVECSSemaphoreWaitPoll:kbl (on ALL_ENGINES)
340 * WaMediaResetMainRingCleanup:ctg,elk (presumably)
342 * FIXME: Wa for more modern gens needs to be validated
344 ENGINE_TRACE(engine, "\n");
346 if (intel_engine_stop_cs(engine))
347 ENGINE_TRACE(engine, "timed out on STOP_RING\n");
349 intel_uncore_write_fw(uncore,
351 intel_uncore_read_fw(uncore, RING_TAIL(base)));
352 intel_uncore_posting_read_fw(uncore, RING_HEAD(base)); /* paranoia */
354 intel_uncore_write_fw(uncore, RING_HEAD(base), 0);
355 intel_uncore_write_fw(uncore, RING_TAIL(base), 0);
356 intel_uncore_posting_read_fw(uncore, RING_TAIL(base));
358 /* The ring must be empty before it is disabled */
359 intel_uncore_write_fw(uncore, RING_CTL(base), 0);
361 /* Check acts as a post */
362 if (intel_uncore_read_fw(uncore, RING_HEAD(base)))
363 ENGINE_TRACE(engine, "ring head [%x] not parked\n",
364 intel_uncore_read_fw(uncore, RING_HEAD(base)));
367 static void reset_rewind(struct intel_engine_cs *engine, bool stalled)
369 struct i915_request *pos, *rq;
374 spin_lock_irqsave(&engine->active.lock, flags);
375 list_for_each_entry(pos, &engine->active.requests, sched.link) {
376 if (!i915_request_completed(pos)) {
383 * The guilty request will get skipped on a hung engine.
385 * Users of client default contexts do not rely on logical
386 * state preserved between batches so it is safe to execute
387 * queued requests following the hang. Non default contexts
388 * rely on preserved state, so skipping a batch loses the
389 * evolution of the state and it needs to be considered corrupted.
390 * Executing more queued batches on top of corrupted state is
391 * risky. But we take the risk by trying to advance through
392 * the queued requests in order to make the client behaviour
393 * more predictable around resets, by not throwing away random
394 * amount of batches it has prepared for execution. Sophisticated
395 * clients can use gem_reset_stats_ioctl and dma fence status
396 * (exported via sync_file info ioctl on explicit fences) to observe
397 * when it loses the context state and should rebuild accordingly.
399 * The context ban, and ultimately the client ban, mechanism are safety
400 * valves if client submission ends up resulting in nothing more than
406 * Try to restore the logical GPU state to match the
407 * continuation of the request queue. If we skip the
408 * context/PD restore, then the next request may try to execute
409 * assuming that its context is valid and loaded on the GPU and
410 * so may try to access invalid memory, prompting repeated GPU
413 * If the request was guilty, we still restore the logical
414 * state in case the next request requires it (e.g. the
415 * aliasing ppgtt), but skip over the hung batch.
417 * If the request was innocent, we try to replay the request
418 * with the restored context.
420 __i915_request_reset(rq, stalled);
422 GEM_BUG_ON(rq->ring != engine->legacy.ring);
425 head = engine->legacy.ring->tail;
427 engine->legacy.ring->head = intel_ring_wrap(engine->legacy.ring, head);
429 spin_unlock_irqrestore(&engine->active.lock, flags);
432 static void reset_finish(struct intel_engine_cs *engine)
436 static void reset_cancel(struct intel_engine_cs *engine)
438 struct i915_request *request;
441 spin_lock_irqsave(&engine->active.lock, flags);
443 /* Mark all submitted requests as skipped. */
444 list_for_each_entry(request, &engine->active.requests, sched.link) {
445 i915_request_set_error_once(request, -EIO);
446 i915_request_mark_complete(request);
449 /* Remaining _unready_ requests will be nop'ed when submitted */
451 spin_unlock_irqrestore(&engine->active.lock, flags);
454 static void i9xx_submit_request(struct i915_request *request)
456 i915_request_submit(request);
457 wmb(); /* paranoid flush writes out of the WCB before mmio */
459 ENGINE_WRITE(request->engine, RING_TAIL,
460 intel_ring_set_tail(request->ring, request->tail));
463 static void __ring_context_fini(struct intel_context *ce)
465 i915_vma_put(ce->state);
468 static void ring_context_destroy(struct kref *ref)
470 struct intel_context *ce = container_of(ref, typeof(*ce), ref);
472 GEM_BUG_ON(intel_context_is_pinned(ce));
475 __ring_context_fini(ce);
477 intel_context_fini(ce);
478 intel_context_free(ce);
481 static int ring_context_pre_pin(struct intel_context *ce,
482 struct i915_gem_ww_ctx *ww,
485 struct i915_address_space *vm;
488 vm = vm_alias(ce->vm);
490 err = gen6_ppgtt_pin(i915_vm_to_ppgtt((vm)), ww);
495 static void __context_unpin_ppgtt(struct intel_context *ce)
497 struct i915_address_space *vm;
499 vm = vm_alias(ce->vm);
501 gen6_ppgtt_unpin(i915_vm_to_ppgtt(vm));
504 static void ring_context_unpin(struct intel_context *ce)
508 static void ring_context_post_unpin(struct intel_context *ce)
510 __context_unpin_ppgtt(ce);
513 static struct i915_vma *
514 alloc_context_vma(struct intel_engine_cs *engine)
516 struct drm_i915_private *i915 = engine->i915;
517 struct drm_i915_gem_object *obj;
518 struct i915_vma *vma;
521 obj = i915_gem_object_create_shmem(i915, engine->context_size);
523 return ERR_CAST(obj);
526 * Try to make the context utilize L3 as well as LLC.
528 * On VLV we don't have L3 controls in the PTEs so we
529 * shouldn't touch the cache level, especially as that
530 * would make the object snooped which might have a
531 * negative performance impact.
533 * Snooping is required on non-llc platforms in execlist
534 * mode, but since all GGTT accesses use PAT entry 0 we
535 * get snooping anyway regardless of cache_level.
537 * This is only applicable for Ivy Bridge devices since
538 * later platforms don't have L3 control bits in the PTE.
540 if (IS_IVYBRIDGE(i915))
541 i915_gem_object_set_cache_coherency(obj, I915_CACHE_L3_LLC);
543 if (engine->default_state) {
546 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
548 err = PTR_ERR(vaddr);
552 shmem_read(engine->default_state, 0,
553 vaddr, engine->context_size);
555 i915_gem_object_flush_map(obj);
556 __i915_gem_object_release_map(obj);
559 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
568 i915_gem_object_put(obj);
572 static int ring_context_alloc(struct intel_context *ce)
574 struct intel_engine_cs *engine = ce->engine;
576 /* One ringbuffer to rule them all */
577 GEM_BUG_ON(!engine->legacy.ring);
578 ce->ring = engine->legacy.ring;
579 ce->timeline = intel_timeline_get(engine->legacy.timeline);
581 GEM_BUG_ON(ce->state);
582 if (engine->context_size) {
583 struct i915_vma *vma;
585 vma = alloc_context_vma(engine);
590 if (engine->default_state)
591 __set_bit(CONTEXT_VALID_BIT, &ce->flags);
597 static int ring_context_pin(struct intel_context *ce, void *unused)
602 static void ring_context_reset(struct intel_context *ce)
604 intel_ring_reset(ce->ring, ce->ring->emit);
607 static const struct intel_context_ops ring_context_ops = {
608 .alloc = ring_context_alloc,
610 .pre_pin = ring_context_pre_pin,
611 .pin = ring_context_pin,
612 .unpin = ring_context_unpin,
613 .post_unpin = ring_context_post_unpin,
615 .enter = intel_context_enter_engine,
616 .exit = intel_context_exit_engine,
618 .reset = ring_context_reset,
619 .destroy = ring_context_destroy,
622 static int load_pd_dir(struct i915_request *rq,
623 struct i915_address_space *vm,
626 const struct intel_engine_cs * const engine = rq->engine;
629 cs = intel_ring_begin(rq, 12);
633 *cs++ = MI_LOAD_REGISTER_IMM(1);
634 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base));
637 *cs++ = MI_LOAD_REGISTER_IMM(1);
638 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
641 /* Stall until the page table load is complete? */
642 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
643 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
644 *cs++ = intel_gt_scratch_offset(engine->gt,
645 INTEL_GT_SCRATCH_FIELD_DEFAULT);
647 *cs++ = MI_LOAD_REGISTER_IMM(1);
648 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base));
649 *cs++ = _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE);
651 intel_ring_advance(rq, cs);
653 return rq->engine->emit_flush(rq, EMIT_FLUSH);
656 static inline int mi_set_context(struct i915_request *rq,
657 struct intel_context *ce,
660 struct intel_engine_cs *engine = rq->engine;
661 struct drm_i915_private *i915 = engine->i915;
662 enum intel_engine_id id;
663 const int num_engines =
664 IS_HASWELL(i915) ? engine->gt->info.num_engines - 1 : 0;
665 bool force_restore = false;
671 len += 2 + (num_engines ? 4 * num_engines + 6 : 0);
672 else if (IS_GEN(i915, 5))
674 if (flags & MI_FORCE_RESTORE) {
675 GEM_BUG_ON(flags & MI_RESTORE_INHIBIT);
676 flags &= ~MI_FORCE_RESTORE;
677 force_restore = true;
681 cs = intel_ring_begin(rq, len);
685 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
686 if (IS_GEN(i915, 7)) {
687 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
689 struct intel_engine_cs *signaller;
691 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
692 for_each_engine(signaller, engine->gt, id) {
693 if (signaller == engine)
696 *cs++ = i915_mmio_reg_offset(
697 RING_PSMI_CTL(signaller->mmio_base));
698 *cs++ = _MASKED_BIT_ENABLE(
699 GEN6_PSMI_SLEEP_MSG_DISABLE);
702 } else if (IS_GEN(i915, 5)) {
704 * This w/a is only listed for pre-production ilk a/b steppings,
705 * but is also mentioned for programming the powerctx. To be
706 * safe, just apply the workaround; we do not use SyncFlush so
707 * this should never take effect and so be a no-op!
709 *cs++ = MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN;
714 * The HW doesn't handle being told to restore the current
715 * context very well. Quite often it likes goes to go off and
716 * sulk, especially when it is meant to be reloading PP_DIR.
717 * A very simple fix to force the reload is to simply switch
718 * away from the current context and back again.
720 * Note that the kernel_context will contain random state
721 * following the INHIBIT_RESTORE. We accept this since we
722 * never use the kernel_context state; it is merely a
723 * placeholder we use to flush other contexts.
725 *cs++ = MI_SET_CONTEXT;
726 *cs++ = i915_ggtt_offset(engine->kernel_context->state) |
732 *cs++ = MI_SET_CONTEXT;
733 *cs++ = i915_ggtt_offset(ce->state) | flags;
735 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
736 * WaMiSetContext_Hang:snb,ivb,vlv
740 if (IS_GEN(i915, 7)) {
742 struct intel_engine_cs *signaller;
743 i915_reg_t last_reg = {}; /* keep gcc quiet */
745 *cs++ = MI_LOAD_REGISTER_IMM(num_engines);
746 for_each_engine(signaller, engine->gt, id) {
747 if (signaller == engine)
750 last_reg = RING_PSMI_CTL(signaller->mmio_base);
751 *cs++ = i915_mmio_reg_offset(last_reg);
752 *cs++ = _MASKED_BIT_DISABLE(
753 GEN6_PSMI_SLEEP_MSG_DISABLE);
756 /* Insert a delay before the next switch! */
757 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
758 *cs++ = i915_mmio_reg_offset(last_reg);
759 *cs++ = intel_gt_scratch_offset(engine->gt,
760 INTEL_GT_SCRATCH_FIELD_DEFAULT);
763 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
764 } else if (IS_GEN(i915, 5)) {
765 *cs++ = MI_SUSPEND_FLUSH;
768 intel_ring_advance(rq, cs);
773 static int remap_l3_slice(struct i915_request *rq, int slice)
775 u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];
781 cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
786 * Note: We do not worry about the concurrent register cacheline hang
787 * here because no other code should access these registers other than
788 * at initialization time.
790 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
791 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
792 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
793 *cs++ = remap_info[i];
796 intel_ring_advance(rq, cs);
801 static int remap_l3(struct i915_request *rq)
803 struct i915_gem_context *ctx = i915_request_gem_context(rq);
806 if (!ctx || !ctx->remap_slice)
809 for (i = 0; i < MAX_L3_SLICES; i++) {
810 if (!(ctx->remap_slice & BIT(i)))
813 err = remap_l3_slice(rq, i);
818 ctx->remap_slice = 0;
822 static int switch_mm(struct i915_request *rq, struct i915_address_space *vm)
829 ret = rq->engine->emit_flush(rq, EMIT_FLUSH);
834 * Not only do we need a full barrier (post-sync write) after
835 * invalidating the TLBs, but we need to wait a little bit
836 * longer. Whether this is merely delaying us, or the
837 * subsequent flush is a key part of serialising with the
838 * post-sync op, this extra pass appears vital before a
841 ret = load_pd_dir(rq, vm, PP_DIR_DCLV_2G);
845 return rq->engine->emit_flush(rq, EMIT_INVALIDATE);
848 static int clear_residuals(struct i915_request *rq)
850 struct intel_engine_cs *engine = rq->engine;
853 ret = switch_mm(rq, vm_alias(engine->kernel_context->vm));
857 if (engine->kernel_context->state) {
858 ret = mi_set_context(rq,
859 engine->kernel_context,
860 MI_MM_SPACE_GTT | MI_RESTORE_INHIBIT);
865 ret = engine->emit_bb_start(rq,
866 engine->wa_ctx.vma->node.start, 0,
871 ret = engine->emit_flush(rq, EMIT_FLUSH);
875 /* Always invalidate before the next switch_mm() */
876 return engine->emit_flush(rq, EMIT_INVALIDATE);
879 static int switch_context(struct i915_request *rq)
881 struct intel_engine_cs *engine = rq->engine;
882 struct intel_context *ce = rq->context;
883 void **residuals = NULL;
886 GEM_BUG_ON(HAS_EXECLISTS(engine->i915));
888 if (engine->wa_ctx.vma && ce != engine->kernel_context) {
889 if (engine->wa_ctx.vma->private != ce &&
890 i915_mitigate_clear_residuals()) {
891 ret = clear_residuals(rq);
895 residuals = &engine->wa_ctx.vma->private;
899 ret = switch_mm(rq, vm_alias(ce->vm));
906 GEM_BUG_ON(engine->id != RCS0);
908 /* For resource streamer on HSW+ and power context elsewhere */
909 BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN);
910 BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN);
912 flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT;
913 if (test_bit(CONTEXT_VALID_BIT, &ce->flags))
914 flags |= MI_RESTORE_EXT_STATE_EN;
916 flags |= MI_RESTORE_INHIBIT;
918 ret = mi_set_context(rq, ce, flags);
928 * Now past the point of no return, this request _will_ be emitted.
930 * Or at least this preamble will be emitted, the request may be
931 * interrupted prior to submitting the user payload. If so, we
932 * still submit the "empty" request in order to preserve global
933 * state tracking such as this, our tracking of the current
937 intel_context_put(*residuals);
938 *residuals = intel_context_get(ce);
944 static int ring_request_alloc(struct i915_request *request)
948 GEM_BUG_ON(!intel_context_is_pinned(request->context));
949 GEM_BUG_ON(i915_request_timeline(request)->has_initial_breadcrumb);
952 * Flush enough space to reduce the likelihood of waiting after
953 * we start building the request - in which case we will just
954 * have to repeat work.
956 request->reserved_space += LEGACY_REQUEST_SIZE;
958 /* Unconditionally invalidate GPU caches and TLBs. */
959 ret = request->engine->emit_flush(request, EMIT_INVALIDATE);
963 ret = switch_context(request);
967 request->reserved_space -= LEGACY_REQUEST_SIZE;
971 static void gen6_bsd_submit_request(struct i915_request *request)
973 struct intel_uncore *uncore = request->engine->uncore;
975 intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
977 /* Every tail move must follow the sequence below */
979 /* Disable notification that the ring is IDLE. The GT
980 * will then assume that it is busy and bring it out of rc6.
982 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
983 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
985 /* Clear the context id. Here be magic! */
986 intel_uncore_write64_fw(uncore, GEN6_BSD_RNCID, 0x0);
988 /* Wait for the ring not to be idle, i.e. for it to wake up. */
989 if (__intel_wait_for_register_fw(uncore,
990 GEN6_BSD_SLEEP_PSMI_CONTROL,
991 GEN6_BSD_SLEEP_INDICATOR,
994 drm_err(&uncore->i915->drm,
995 "timed out waiting for the BSD ring to wake up\n");
997 /* Now that the ring is fully powered up, update the tail */
998 i9xx_submit_request(request);
1000 /* Let the ring send IDLE messages to the GT again,
1001 * and so let it sleep to conserve power when idle.
1003 intel_uncore_write_fw(uncore, GEN6_BSD_SLEEP_PSMI_CONTROL,
1004 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1006 intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
1009 static void i9xx_set_default_submission(struct intel_engine_cs *engine)
1011 engine->submit_request = i9xx_submit_request;
1013 engine->park = NULL;
1014 engine->unpark = NULL;
1017 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
1019 i9xx_set_default_submission(engine);
1020 engine->submit_request = gen6_bsd_submit_request;
1023 static void ring_release(struct intel_engine_cs *engine)
1025 struct drm_i915_private *dev_priv = engine->i915;
1027 drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) > 2 &&
1028 (ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
1030 intel_engine_cleanup_common(engine);
1032 if (engine->wa_ctx.vma) {
1033 intel_context_put(engine->wa_ctx.vma->private);
1034 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1037 intel_ring_unpin(engine->legacy.ring);
1038 intel_ring_put(engine->legacy.ring);
1040 intel_timeline_unpin(engine->legacy.timeline);
1041 intel_timeline_put(engine->legacy.timeline);
1044 static void setup_irq(struct intel_engine_cs *engine)
1046 struct drm_i915_private *i915 = engine->i915;
1048 if (INTEL_GEN(i915) >= 6) {
1049 engine->irq_enable = gen6_irq_enable;
1050 engine->irq_disable = gen6_irq_disable;
1051 } else if (INTEL_GEN(i915) >= 5) {
1052 engine->irq_enable = gen5_irq_enable;
1053 engine->irq_disable = gen5_irq_disable;
1054 } else if (INTEL_GEN(i915) >= 3) {
1055 engine->irq_enable = gen3_irq_enable;
1056 engine->irq_disable = gen3_irq_disable;
1058 engine->irq_enable = gen2_irq_enable;
1059 engine->irq_disable = gen2_irq_disable;
1063 static void setup_common(struct intel_engine_cs *engine)
1065 struct drm_i915_private *i915 = engine->i915;
1067 /* gen8+ are only supported with execlists */
1068 GEM_BUG_ON(INTEL_GEN(i915) >= 8);
1072 engine->resume = xcs_resume;
1073 engine->reset.prepare = reset_prepare;
1074 engine->reset.rewind = reset_rewind;
1075 engine->reset.cancel = reset_cancel;
1076 engine->reset.finish = reset_finish;
1078 engine->cops = &ring_context_ops;
1079 engine->request_alloc = ring_request_alloc;
1082 * Using a global execution timeline; the previous final breadcrumb is
1083 * equivalent to our next initial bread so we can elide
1084 * engine->emit_init_breadcrumb().
1086 engine->emit_fini_breadcrumb = gen3_emit_breadcrumb;
1087 if (IS_GEN(i915, 5))
1088 engine->emit_fini_breadcrumb = gen5_emit_breadcrumb;
1090 engine->set_default_submission = i9xx_set_default_submission;
1092 if (INTEL_GEN(i915) >= 6)
1093 engine->emit_bb_start = gen6_emit_bb_start;
1094 else if (INTEL_GEN(i915) >= 4)
1095 engine->emit_bb_start = gen4_emit_bb_start;
1096 else if (IS_I830(i915) || IS_I845G(i915))
1097 engine->emit_bb_start = i830_emit_bb_start;
1099 engine->emit_bb_start = gen3_emit_bb_start;
1102 static void setup_rcs(struct intel_engine_cs *engine)
1104 struct drm_i915_private *i915 = engine->i915;
1106 if (HAS_L3_DPF(i915))
1107 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
1109 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1111 if (INTEL_GEN(i915) >= 7) {
1112 engine->emit_flush = gen7_emit_flush_rcs;
1113 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_rcs;
1114 } else if (IS_GEN(i915, 6)) {
1115 engine->emit_flush = gen6_emit_flush_rcs;
1116 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_rcs;
1117 } else if (IS_GEN(i915, 5)) {
1118 engine->emit_flush = gen4_emit_flush_rcs;
1120 if (INTEL_GEN(i915) < 4)
1121 engine->emit_flush = gen2_emit_flush;
1123 engine->emit_flush = gen4_emit_flush_rcs;
1124 engine->irq_enable_mask = I915_USER_INTERRUPT;
1127 if (IS_HASWELL(i915))
1128 engine->emit_bb_start = hsw_emit_bb_start;
1131 static void setup_vcs(struct intel_engine_cs *engine)
1133 struct drm_i915_private *i915 = engine->i915;
1135 if (INTEL_GEN(i915) >= 6) {
1136 /* gen6 bsd needs a special wa for tail updates */
1137 if (IS_GEN(i915, 6))
1138 engine->set_default_submission = gen6_bsd_set_default_submission;
1139 engine->emit_flush = gen6_emit_flush_vcs;
1140 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1142 if (IS_GEN(i915, 6))
1143 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
1145 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
1147 engine->emit_flush = gen4_emit_flush_vcs;
1148 if (IS_GEN(i915, 5))
1149 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1151 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1155 static void setup_bcs(struct intel_engine_cs *engine)
1157 struct drm_i915_private *i915 = engine->i915;
1159 engine->emit_flush = gen6_emit_flush_xcs;
1160 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1162 if (IS_GEN(i915, 6))
1163 engine->emit_fini_breadcrumb = gen6_emit_breadcrumb_xcs;
1165 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
1168 static void setup_vecs(struct intel_engine_cs *engine)
1170 struct drm_i915_private *i915 = engine->i915;
1172 GEM_BUG_ON(INTEL_GEN(i915) < 7);
1174 engine->emit_flush = gen6_emit_flush_xcs;
1175 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
1176 engine->irq_enable = hsw_irq_enable_vecs;
1177 engine->irq_disable = hsw_irq_disable_vecs;
1179 engine->emit_fini_breadcrumb = gen7_emit_breadcrumb_xcs;
1182 static int gen7_ctx_switch_bb_setup(struct intel_engine_cs * const engine,
1183 struct i915_vma * const vma)
1185 return gen7_setup_clear_gpr_bb(engine, vma);
1188 static int gen7_ctx_switch_bb_init(struct intel_engine_cs *engine)
1190 struct drm_i915_gem_object *obj;
1191 struct i915_vma *vma;
1195 size = gen7_ctx_switch_bb_setup(engine, NULL /* probe size */);
1199 size = ALIGN(size, PAGE_SIZE);
1200 obj = i915_gem_object_create_internal(engine->i915, size);
1202 return PTR_ERR(obj);
1204 vma = i915_vma_instance(obj, engine->gt->vm, NULL);
1210 vma->private = intel_context_create(engine); /* dummy residuals */
1211 if (IS_ERR(vma->private)) {
1212 err = PTR_ERR(vma->private);
1216 err = i915_vma_pin(vma, 0, 0, PIN_USER | PIN_HIGH);
1220 err = i915_vma_sync(vma);
1224 err = gen7_ctx_switch_bb_setup(engine, vma);
1228 engine->wa_ctx.vma = vma;
1232 i915_vma_unpin(vma);
1234 intel_context_put(vma->private);
1236 i915_gem_object_put(obj);
1240 int intel_ring_submission_setup(struct intel_engine_cs *engine)
1242 struct intel_timeline *timeline;
1243 struct intel_ring *ring;
1246 setup_common(engine);
1248 switch (engine->class) {
1252 case VIDEO_DECODE_CLASS:
1255 case COPY_ENGINE_CLASS:
1258 case VIDEO_ENHANCEMENT_CLASS:
1262 MISSING_CASE(engine->class);
1266 timeline = intel_timeline_create_from_engine(engine,
1267 I915_GEM_HWS_SEQNO_ADDR);
1268 if (IS_ERR(timeline)) {
1269 err = PTR_ERR(timeline);
1272 GEM_BUG_ON(timeline->has_initial_breadcrumb);
1274 err = intel_timeline_pin(timeline, NULL);
1278 ring = intel_engine_create_ring(engine, SZ_16K);
1280 err = PTR_ERR(ring);
1281 goto err_timeline_unpin;
1284 err = intel_ring_pin(ring, NULL);
1288 GEM_BUG_ON(engine->legacy.ring);
1289 engine->legacy.ring = ring;
1290 engine->legacy.timeline = timeline;
1292 GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma);
1294 if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) {
1295 err = gen7_ctx_switch_bb_init(engine);
1297 goto err_ring_unpin;
1300 /* Finally, take ownership and responsibility for cleanup! */
1301 engine->release = ring_release;
1306 intel_ring_unpin(ring);
1308 intel_ring_put(ring);
1310 intel_timeline_unpin(timeline);
1312 intel_timeline_put(timeline);
1314 intel_engine_cleanup_common(engine);
1318 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1319 #include "selftest_ring_submission.c"