drivers/gpu/drm/i915/gt/intel_reset.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2008-2018 Intel Corporation
   5  */
   6
   7 #include <linux/sched/mm.h>
   8 #include <linux/stop_machine.h>
   9
  10 #include "display/intel_display_types.h"
  11 #include "display/intel_overlay.h"
  12
  13 #include "gem/i915_gem_context.h"
  14
  15 #include "i915_drv.h"
  16 #include "i915_gpu_error.h"
  17 #include "i915_irq.h"
  18 #include "intel_breadcrumbs.h"
  19 #include "intel_engine_pm.h"
  20 #include "intel_gt.h"
  21 #include "intel_gt_pm.h"
  22 #include "intel_reset.h"
  23
  24 #include "uc/intel_guc.h"
  25 #include "uc/intel_guc_submission.h"
  26
  27 #define RESET_MAX_RETRIES 3
  28
  29 /* XXX How to handle concurrent GGTT updates using tiling registers? */
  30 #define RESET_UNDER_STOP_MACHINE 0
  31
  32 static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
  33 {
  34         intel_uncore_rmw_fw(uncore, reg, 0, set);
  35 }
  36
  37 static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
  38 {
  39         intel_uncore_rmw_fw(uncore, reg, clr, 0);
  40 }
  41
  42 static void engine_skip_context(struct i915_request *rq)
  43 {
  44         struct intel_engine_cs *engine = rq->engine;
  45         struct intel_context *hung_ctx = rq->context;
  46
  47         if (!i915_request_is_active(rq))
  48                 return;
  49
  50         lockdep_assert_held(&engine->active.lock);
  51         list_for_each_entry_continue(rq, &engine->active.requests, sched.link)
  52                 if (rq->context == hung_ctx) {
  53                         i915_request_set_error_once(rq, -EIO);
  54                         __i915_request_skip(rq);
  55                 }
  56 }
  57
  58 static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
  59 {
  60         struct drm_i915_file_private *file_priv = ctx->file_priv;
  61         unsigned long prev_hang;
  62         unsigned int score;
  63
  64         if (IS_ERR_OR_NULL(file_priv))
  65                 return;
  66
  67         score = 0;
  68         if (banned)
  69                 score = I915_CLIENT_SCORE_CONTEXT_BAN;
  70
  71         prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
  72         if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
  73                 score += I915_CLIENT_SCORE_HANG_FAST;
  74
  75         if (score) {
  76                 atomic_add(score, &file_priv->ban_score);
  77
  78                 drm_dbg(&ctx->i915->drm,
  79                         "client %s: gained %u ban score, now %u\n",
  80                         ctx->name, score,
  81                         atomic_read(&file_priv->ban_score));
  82         }
  83 }
  84
  85 static bool mark_guilty(struct i915_request *rq)
  86 {
  87         struct i915_gem_context *ctx;
  88         unsigned long prev_hang;
  89         bool banned;
  90         int i;
  91
  92         if (intel_context_is_closed(rq->context)) {
  93                 intel_context_set_banned(rq->context);
  94                 return true;
  95         }
  96
  97         rcu_read_lock();
  98         ctx = rcu_dereference(rq->context->gem_context);
  99         if (ctx && !kref_get_unless_zero(&ctx->ref))
 100                 ctx = NULL;
 101         rcu_read_unlock();
 102         if (!ctx)
 103                 return intel_context_is_banned(rq->context);
 104
 105         atomic_inc(&ctx->guilty_count);
 106
 107         /* Cool contexts are too cool to be banned! (Used for reset testing.) */
 108         if (!i915_gem_context_is_bannable(ctx)) {
 109                 banned = false;
 110                 goto out;
 111         }
 112
 113         drm_notice(&ctx->i915->drm,
 114                    "%s context reset due to GPU hang\n",
 115                    ctx->name);
 116
 117         /* Record the timestamp for the last N hangs */
 118         prev_hang = ctx->hang_timestamp[0];
 119         for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
 120                 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
 121         ctx->hang_timestamp[i] = jiffies;
 122
 123         /* If we have hung N+1 times in rapid succession, we ban the context! */
 124         banned = !i915_gem_context_is_recoverable(ctx);
 125         if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
 126                 banned = true;
 127         if (banned) {
 128                 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
 129                         ctx->name, atomic_read(&ctx->guilty_count));
 130                 intel_context_set_banned(rq->context);
 131         }
 132
 133         client_mark_guilty(ctx, banned);
 134
 135 out:
 136         i915_gem_context_put(ctx);
 137         return banned;
 138 }
 139
 140 static void mark_innocent(struct i915_request *rq)
 141 {
 142         struct i915_gem_context *ctx;
 143
 144         rcu_read_lock();
 145         ctx = rcu_dereference(rq->context->gem_context);
 146         if (ctx)
 147                 atomic_inc(&ctx->active_count);
 148         rcu_read_unlock();
 149 }
 150
 151 void __i915_request_reset(struct i915_request *rq, bool guilty)
 152 {
 153         RQ_TRACE(rq, "guilty? %s\n", yesno(guilty));
 154
 155         GEM_BUG_ON(i915_request_completed(rq));
 156
 157         rcu_read_lock(); /* protect the GEM context */
 158         if (guilty) {
 159                 i915_request_set_error_once(rq, -EIO);
 160                 __i915_request_skip(rq);
 161                 if (mark_guilty(rq))
 162                         engine_skip_context(rq);
 163         } else {
 164                 i915_request_set_error_once(rq, -EAGAIN);
 165                 mark_innocent(rq);
 166         }
 167         rcu_read_unlock();
 168 }
 169
 170 static bool i915_in_reset(struct pci_dev *pdev)
 171 {
 172         u8 gdrst;
 173
 174         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 175         return gdrst & GRDOM_RESET_STATUS;
 176 }
 177
 178 static int i915_do_reset(struct intel_gt *gt,
 179                          intel_engine_mask_t engine_mask,
 180                          unsigned int retry)
 181 {
 182         struct pci_dev *pdev = gt->i915->drm.pdev;
 183         int err;
 184
 185         /* Assert reset for at least 20 usec, and wait for acknowledgement. */
 186         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 187         udelay(50);
 188         err = wait_for_atomic(i915_in_reset(pdev), 50);
 189
 190         /* Clear the reset request. */
 191         pci_write_config_byte(pdev, I915_GDRST, 0);
 192         udelay(50);
 193         if (!err)
 194                 err = wait_for_atomic(!i915_in_reset(pdev), 50);
 195
 196         return err;
 197 }
 198
 199 static bool g4x_reset_complete(struct pci_dev *pdev)
 200 {
 201         u8 gdrst;
 202
 203         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 204         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 205 }
 206
 207 static int g33_do_reset(struct intel_gt *gt,
 208                         intel_engine_mask_t engine_mask,
 209                         unsigned int retry)
 210 {
 211         struct pci_dev *pdev = gt->i915->drm.pdev;
 212
 213         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 214         return wait_for_atomic(g4x_reset_complete(pdev), 50);
 215 }
 216
 217 static int g4x_do_reset(struct intel_gt *gt,
 218                         intel_engine_mask_t engine_mask,
 219                         unsigned int retry)
 220 {
 221         struct pci_dev *pdev = gt->i915->drm.pdev;
 222         struct intel_uncore *uncore = gt->uncore;
 223         int ret;
 224
 225         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
 226         rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
 227         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 228
 229         pci_write_config_byte(pdev, I915_GDRST,
 230                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 231         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 232         if (ret) {
 233                 drm_dbg(&gt->i915->drm, "Wait for media reset failed\n");
 234                 goto out;
 235         }
 236
 237         pci_write_config_byte(pdev, I915_GDRST,
 238                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
 239         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 240         if (ret) {
 241                 drm_dbg(&gt->i915->drm, "Wait for render reset failed\n");
 242                 goto out;
 243         }
 244
 245 out:
 246         pci_write_config_byte(pdev, I915_GDRST, 0);
 247
 248         rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
 249         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 250
 251         return ret;
 252 }
 253
 254 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
 255                         unsigned int retry)
 256 {
 257         struct intel_uncore *uncore = gt->uncore;
 258         int ret;
 259
 260         intel_uncore_write_fw(uncore, ILK_GDSR,
 261                               ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
 262         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 263                                            ILK_GRDOM_RESET_ENABLE, 0,
 264                                            5000, 0,
 265                                            NULL);
 266         if (ret) {
 267                 drm_dbg(&gt->i915->drm, "Wait for render reset failed\n");
 268                 goto out;
 269         }
 270
 271         intel_uncore_write_fw(uncore, ILK_GDSR,
 272                               ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
 273         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 274                                            ILK_GRDOM_RESET_ENABLE, 0,
 275                                            5000, 0,
 276                                            NULL);
 277         if (ret) {
 278                 drm_dbg(&gt->i915->drm, "Wait for media reset failed\n");
 279                 goto out;
 280         }
 281
 282 out:
 283         intel_uncore_write_fw(uncore, ILK_GDSR, 0);
 284         intel_uncore_posting_read_fw(uncore, ILK_GDSR);
 285         return ret;
 286 }
 287
 288 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
 289 static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
 290 {
 291         struct intel_uncore *uncore = gt->uncore;
 292         int loops = 2;
 293         int err;
 294
 295         /*
 296          * GEN6_GDRST is not in the gt power well, no need to check
 297          * for fifo space for the write or forcewake the chip for
 298          * the read
 299          */
 300         do {
 301                 intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
 302
 303                 /*
 304                  * Wait for the device to ack the reset requests.
 305                  *
 306                  * On some platforms, e.g. Jasperlake, we see that the
 307                  * engine register state is not cleared until shortly after
 308                  * GDRST reports completion, causing a failure as we try
 309                  * to immediately resume while the internal state is still
 310                  * in flux. If we immediately repeat the reset, the second
 311                  * reset appears to serialise with the first, and since
 312                  * it is a no-op, the registers should retain their reset
 313                  * value. However, there is still a concern that upon
 314                  * leaving the second reset, the internal engine state
 315                  * is still in flux and not ready for resuming.
 316                  */
 317                 err = __intel_wait_for_register_fw(uncore, GEN6_GDRST,
 318                                                    hw_domain_mask, 0,
 319                                                    2000, 0,
 320                                                    NULL);
 321         } while (err == 0 && --loops);
 322         if (err)
 323                 drm_dbg(&gt->i915->drm,
 324                         "Wait for 0x%08x engines reset failed\n",
 325                         hw_domain_mask);
 326
 327         /*
 328          * As we have observed that the engine state is still volatile
 329          * after GDRST is acked, impose a small delay to let everything settle.
 330          */
 331         udelay(50);
 332
 333         return err;
 334 }
 335
 336 static int gen6_reset_engines(struct intel_gt *gt,
 337                               intel_engine_mask_t engine_mask,
 338                               unsigned int retry)
 339 {
 340         static const u32 hw_engine_mask[] = {
 341                 [RCS0]  = GEN6_GRDOM_RENDER,
 342                 [BCS0]  = GEN6_GRDOM_BLT,
 343                 [VCS0]  = GEN6_GRDOM_MEDIA,
 344                 [VCS1]  = GEN8_GRDOM_MEDIA2,
 345                 [VECS0] = GEN6_GRDOM_VECS,
 346         };
 347         struct intel_engine_cs *engine;
 348         u32 hw_mask;
 349
 350         if (engine_mask == ALL_ENGINES) {
 351                 hw_mask = GEN6_GRDOM_FULL;
 352         } else {
 353                 intel_engine_mask_t tmp;
 354
 355                 hw_mask = 0;
 356                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 357                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 358                         hw_mask |= hw_engine_mask[engine->id];
 359                 }
 360         }
 361
 362         return gen6_hw_domain_reset(gt, hw_mask);
 363 }
 364
 365 static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
 366 {
 367         struct intel_uncore *uncore = engine->uncore;
 368         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 369         i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
 370         u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
 371         i915_reg_t sfc_usage;
 372         u32 sfc_usage_bit;
 373         u32 sfc_reset_bit;
 374         int ret;
 375
 376         switch (engine->class) {
 377         case VIDEO_DECODE_CLASS:
 378                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 379                         return 0;
 380
 381                 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
 382                 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 383
 384                 sfc_forced_lock_ack = GEN11_VCS_SFC_LOCK_STATUS(engine);
 385                 sfc_forced_lock_ack_bit  = GEN11_VCS_SFC_LOCK_ACK_BIT;
 386
 387                 sfc_usage = GEN11_VCS_SFC_LOCK_STATUS(engine);
 388                 sfc_usage_bit = GEN11_VCS_SFC_USAGE_BIT;
 389                 sfc_reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
 390                 break;
 391
 392         case VIDEO_ENHANCEMENT_CLASS:
 393                 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
 394                 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 395
 396                 sfc_forced_lock_ack = GEN11_VECS_SFC_LOCK_ACK(engine);
 397                 sfc_forced_lock_ack_bit  = GEN11_VECS_SFC_LOCK_ACK_BIT;
 398
 399                 sfc_usage = GEN11_VECS_SFC_USAGE(engine);
 400                 sfc_usage_bit = GEN11_VECS_SFC_USAGE_BIT;
 401                 sfc_reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
 402                 break;
 403
 404         default:
 405                 return 0;
 406         }
 407
 408         /*
 409          * If the engine is using a SFC, tell the engine that a software reset
 410          * is going to happen. The engine will then try to force lock the SFC.
 411          * If SFC ends up being locked to the engine we want to reset, we have
 412          * to reset it as well (we will unlock it once the reset sequence is
 413          * completed).
 414          */
 415         if (!(intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit))
 416                 return 0;
 417
 418         rmw_set_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
 419
 420         ret = __intel_wait_for_register_fw(uncore,
 421                                            sfc_forced_lock_ack,
 422                                            sfc_forced_lock_ack_bit,
 423                                            sfc_forced_lock_ack_bit,
 424                                            1000, 0, NULL);
 425
 426         /* Was the SFC released while we were trying to lock it? */
 427         if (!(intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit))
 428                 return 0;
 429
 430         if (ret) {
 431                 drm_dbg(&engine->i915->drm,
 432                         "Wait for SFC forced lock ack failed\n");
 433                 return ret;
 434         }
 435
 436         *hw_mask |= sfc_reset_bit;
 437         return 0;
 438 }
 439
 440 static void gen11_unlock_sfc(struct intel_engine_cs *engine)
 441 {
 442         struct intel_uncore *uncore = engine->uncore;
 443         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 444         i915_reg_t sfc_forced_lock;
 445         u32 sfc_forced_lock_bit;
 446
 447         switch (engine->class) {
 448         case VIDEO_DECODE_CLASS:
 449                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 450                         return;
 451
 452                 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
 453                 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 454                 break;
 455
 456         case VIDEO_ENHANCEMENT_CLASS:
 457                 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
 458                 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 459                 break;
 460
 461         default:
 462                 return;
 463         }
 464
 465         rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
 466 }
 467
 468 static int gen11_reset_engines(struct intel_gt *gt,
 469                                intel_engine_mask_t engine_mask,
 470                                unsigned int retry)
 471 {
 472         static const u32 hw_engine_mask[] = {
 473                 [RCS0]  = GEN11_GRDOM_RENDER,
 474                 [BCS0]  = GEN11_GRDOM_BLT,
 475                 [VCS0]  = GEN11_GRDOM_MEDIA,
 476                 [VCS1]  = GEN11_GRDOM_MEDIA2,
 477                 [VCS2]  = GEN11_GRDOM_MEDIA3,
 478                 [VCS3]  = GEN11_GRDOM_MEDIA4,
 479                 [VECS0] = GEN11_GRDOM_VECS,
 480                 [VECS1] = GEN11_GRDOM_VECS2,
 481         };
 482         struct intel_engine_cs *engine;
 483         intel_engine_mask_t tmp;
 484         u32 hw_mask;
 485         int ret;
 486
 487         if (engine_mask == ALL_ENGINES) {
 488                 hw_mask = GEN11_GRDOM_FULL;
 489         } else {
 490                 hw_mask = 0;
 491                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 492                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 493                         hw_mask |= hw_engine_mask[engine->id];
 494                         ret = gen11_lock_sfc(engine, &hw_mask);
 495                         if (ret)
 496                                 goto sfc_unlock;
 497                 }
 498         }
 499
 500         ret = gen6_hw_domain_reset(gt, hw_mask);
 501
 502 sfc_unlock:
 503         /*
 504          * We unlock the SFC based on the lock status and not the result of
 505          * gen11_lock_sfc to make sure that we clean properly if something
 506          * wrong happened during the lock (e.g. lock acquired after timeout
 507          * expiration).
 508          */
 509         if (engine_mask != ALL_ENGINES)
 510                 for_each_engine_masked(engine, gt, engine_mask, tmp)
 511                         gen11_unlock_sfc(engine);
 512
 513         return ret;
 514 }
 515
 516 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 517 {
 518         struct intel_uncore *uncore = engine->uncore;
 519         const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
 520         u32 request, mask, ack;
 521         int ret;
 522
 523         ack = intel_uncore_read_fw(uncore, reg);
 524         if (ack & RESET_CTL_CAT_ERROR) {
 525                 /*
 526                  * For catastrophic errors, ready-for-reset sequence
 527                  * needs to be bypassed: HAS#396813
 528                  */
 529                 request = RESET_CTL_CAT_ERROR;
 530                 mask = RESET_CTL_CAT_ERROR;
 531
 532                 /* Catastrophic errors need to be cleared by HW */
 533                 ack = 0;
 534         } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
 535                 request = RESET_CTL_REQUEST_RESET;
 536                 mask = RESET_CTL_READY_TO_RESET;
 537                 ack = RESET_CTL_READY_TO_RESET;
 538         } else {
 539                 return 0;
 540         }
 541
 542         intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
 543         ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
 544                                            700, 0, NULL);
 545         if (ret)
 546                 drm_err(&engine->i915->drm,
 547                         "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
 548                         engine->name, request,
 549                         intel_uncore_read_fw(uncore, reg));
 550
 551         return ret;
 552 }
 553
 554 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
 555 {
 556         intel_uncore_write_fw(engine->uncore,
 557                               RING_RESET_CTL(engine->mmio_base),
 558                               _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
 559 }
 560
 561 static int gen8_reset_engines(struct intel_gt *gt,
 562                               intel_engine_mask_t engine_mask,
 563                               unsigned int retry)
 564 {
 565         struct intel_engine_cs *engine;
 566         const bool reset_non_ready = retry >= 1;
 567         intel_engine_mask_t tmp;
 568         int ret;
 569
 570         for_each_engine_masked(engine, gt, engine_mask, tmp) {
 571                 ret = gen8_engine_reset_prepare(engine);
 572                 if (ret && !reset_non_ready)
 573                         goto skip_reset;
 574
 575                 /*
 576                  * If this is not the first failed attempt to prepare,
 577                  * we decide to proceed anyway.
 578                  *
 579                  * By doing so we risk context corruption and with
 580                  * some gens (kbl), possible system hang if reset
 581                  * happens during active bb execution.
 582                  *
 583                  * We rather take context corruption instead of
 584                  * failed reset with a wedged driver/gpu. And
 585                  * active bb execution case should be covered by
 586                  * stop_engines() we have before the reset.
 587                  */
 588         }
 589
 590         if (INTEL_GEN(gt->i915) >= 11)
 591                 ret = gen11_reset_engines(gt, engine_mask, retry);
 592         else
 593                 ret = gen6_reset_engines(gt, engine_mask, retry);
 594
 595 skip_reset:
 596         for_each_engine_masked(engine, gt, engine_mask, tmp)
 597                 gen8_engine_reset_cancel(engine);
 598
 599         return ret;
 600 }
 601
 602 static int mock_reset(struct intel_gt *gt,
 603                       intel_engine_mask_t mask,
 604                       unsigned int retry)
 605 {
 606         return 0;
 607 }
 608
 609 typedef int (*reset_func)(struct intel_gt *,
 610                           intel_engine_mask_t engine_mask,
 611                           unsigned int retry);
 612
 613 static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
 614 {
 615         struct drm_i915_private *i915 = gt->i915;
 616
 617         if (is_mock_gt(gt))
 618                 return mock_reset;
 619         else if (INTEL_GEN(i915) >= 8)
 620                 return gen8_reset_engines;
 621         else if (INTEL_GEN(i915) >= 6)
 622                 return gen6_reset_engines;
 623         else if (INTEL_GEN(i915) >= 5)
 624                 return ilk_do_reset;
 625         else if (IS_G4X(i915))
 626                 return g4x_do_reset;
 627         else if (IS_G33(i915) || IS_PINEVIEW(i915))
 628                 return g33_do_reset;
 629         else if (INTEL_GEN(i915) >= 3)
 630                 return i915_do_reset;
 631         else
 632                 return NULL;
 633 }
 634
 635 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 636 {
 637         const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
 638         reset_func reset;
 639         int ret = -ETIMEDOUT;
 640         int retry;
 641
 642         reset = intel_get_gpu_reset(gt);
 643         if (!reset)
 644                 return -ENODEV;
 645
 646         /*
 647          * If the power well sleeps during the reset, the reset
 648          * request may be dropped and never completes (causing -EIO).
 649          */
 650         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 651         for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
 652                 GT_TRACE(gt, "engine_mask=%x\n", engine_mask);
 653                 preempt_disable();
 654                 ret = reset(gt, engine_mask, retry);
 655                 preempt_enable();
 656         }
 657         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 658
 659         return ret;
 660 }
 661
 662 bool intel_has_gpu_reset(const struct intel_gt *gt)
 663 {
 664         if (!gt->i915->params.reset)
 665                 return NULL;
 666
 667         return intel_get_gpu_reset(gt);
 668 }
 669
 670 bool intel_has_reset_engine(const struct intel_gt *gt)
 671 {
 672         if (gt->i915->params.reset < 2)
 673                 return false;
 674
 675         return INTEL_INFO(gt->i915)->has_reset_engine;
 676 }
 677
 678 int intel_reset_guc(struct intel_gt *gt)
 679 {
 680         u32 guc_domain =
 681                 INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
 682         int ret;
 683
 684         GEM_BUG_ON(!HAS_GT_UC(gt->i915));
 685
 686         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 687         ret = gen6_hw_domain_reset(gt, guc_domain);
 688         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 689
 690         return ret;
 691 }
 692
 693 /*
 694  * Ensure irq handler finishes, and not run again.
 695  * Also return the active request so that we only search for it once.
 696  */
 697 static void reset_prepare_engine(struct intel_engine_cs *engine)
 698 {
 699         /*
 700          * During the reset sequence, we must prevent the engine from
 701          * entering RC6. As the context state is undefined until we restart
 702          * the engine, if it does enter RC6 during the reset, the state
 703          * written to the powercontext is undefined and so we may lose
 704          * GPU state upon resume, i.e. fail to restart after a reset.
 705          */
 706         intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
 707         if (engine->reset.prepare)
 708                 engine->reset.prepare(engine);
 709 }
 710
 711 static void revoke_mmaps(struct intel_gt *gt)
 712 {
 713         int i;
 714
 715         for (i = 0; i < gt->ggtt->num_fences; i++) {
 716                 struct drm_vma_offset_node *node;
 717                 struct i915_vma *vma;
 718                 u64 vma_offset;
 719
 720                 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
 721                 if (!vma)
 722                         continue;
 723
 724                 if (!i915_vma_has_userfault(vma))
 725                         continue;
 726
 727                 GEM_BUG_ON(vma->fence != &gt->ggtt->fence_regs[i]);
 728
 729                 if (!vma->mmo)
 730                         continue;
 731
 732                 node = &vma->mmo->vma_node;
 733                 vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
 734
 735                 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
 736                                     drm_vma_node_offset_addr(node) + vma_offset,
 737                                     vma->size,
 738                                     1);
 739         }
 740 }
 741
 742 static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
 743 {
 744         struct intel_engine_cs *engine;
 745         intel_engine_mask_t awake = 0;
 746         enum intel_engine_id id;
 747
 748         for_each_engine(engine, gt, id) {
 749                 if (intel_engine_pm_get_if_awake(engine))
 750                         awake |= engine->mask;
 751                 reset_prepare_engine(engine);
 752         }
 753
 754         intel_uc_reset_prepare(&gt->uc);
 755
 756         return awake;
 757 }
 758
 759 static void gt_revoke(struct intel_gt *gt)
 760 {
 761         revoke_mmaps(gt);
 762 }
 763
 764 static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 765 {
 766         struct intel_engine_cs *engine;
 767         enum intel_engine_id id;
 768         int err;
 769
 770         /*
 771          * Everything depends on having the GTT running, so we need to start
 772          * there.
 773          */
 774         err = i915_ggtt_enable_hw(gt->i915);
 775         if (err)
 776                 return err;
 777
 778         for_each_engine(engine, gt, id)
 779                 __intel_engine_reset(engine, stalled_mask & engine->mask);
 780
 781         intel_ggtt_restore_fences(gt->ggtt);
 782
 783         return err;
 784 }
 785
 786 static void reset_finish_engine(struct intel_engine_cs *engine)
 787 {
 788         if (engine->reset.finish)
 789                 engine->reset.finish(engine);
 790         intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
 791
 792         intel_engine_signal_breadcrumbs(engine);
 793 }
 794
 795 static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
 796 {
 797         struct intel_engine_cs *engine;
 798         enum intel_engine_id id;
 799
 800         for_each_engine(engine, gt, id) {
 801                 reset_finish_engine(engine);
 802                 if (awake & engine->mask)
 803                         intel_engine_pm_put(engine);
 804         }
 805 }
 806
 807 static void nop_submit_request(struct i915_request *request)
 808 {
 809         struct intel_engine_cs *engine = request->engine;
 810         unsigned long flags;
 811
 812         RQ_TRACE(request, "-EIO\n");
 813         i915_request_set_error_once(request, -EIO);
 814
 815         spin_lock_irqsave(&engine->active.lock, flags);
 816         __i915_request_submit(request);
 817         i915_request_mark_complete(request);
 818         spin_unlock_irqrestore(&engine->active.lock, flags);
 819
 820         intel_engine_signal_breadcrumbs(engine);
 821 }
 822
 823 static void __intel_gt_set_wedged(struct intel_gt *gt)
 824 {
 825         struct intel_engine_cs *engine;
 826         intel_engine_mask_t awake;
 827         enum intel_engine_id id;
 828
 829         if (test_bit(I915_WEDGED, &gt->reset.flags))
 830                 return;
 831
 832         GT_TRACE(gt, "start\n");
 833
 834         /*
 835          * First, stop submission to hw, but do not yet complete requests by
 836          * rolling the global seqno forward (since this would complete requests
 837          * for which we haven't set the fence error to EIO yet).
 838          */
 839         awake = reset_prepare(gt);
 840
 841         /* Even if the GPU reset fails, it should still stop the engines */
 842         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 843                 __intel_gt_reset(gt, ALL_ENGINES);
 844
 845         for_each_engine(engine, gt, id)
 846                 engine->submit_request = nop_submit_request;
 847
 848         /*
 849          * Make sure no request can slip through without getting completed by
 850          * either this call here to intel_engine_write_global_seqno, or the one
 851          * in nop_submit_request.
 852          */
 853         synchronize_rcu_expedited();
 854         set_bit(I915_WEDGED, &gt->reset.flags);
 855
 856         /* Mark all executing requests as skipped */
 857         for_each_engine(engine, gt, id)
 858                 if (engine->reset.cancel)
 859                         engine->reset.cancel(engine);
 860
 861         reset_finish(gt, awake);
 862
 863         GT_TRACE(gt, "end\n");
 864 }
 865
 866 void intel_gt_set_wedged(struct intel_gt *gt)
 867 {
 868         intel_wakeref_t wakeref;
 869
 870         if (test_bit(I915_WEDGED, &gt->reset.flags))
 871                 return;
 872
 873         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
 874         mutex_lock(&gt->reset.mutex);
 875
 876         if (GEM_SHOW_DEBUG()) {
 877                 struct drm_printer p = drm_debug_printer(__func__);
 878                 struct intel_engine_cs *engine;
 879                 enum intel_engine_id id;
 880
 881                 drm_printf(&p, "called from %pS\n", (void *)_RET_IP_);
 882                 for_each_engine(engine, gt, id) {
 883                         if (intel_engine_is_idle(engine))
 884                                 continue;
 885
 886                         intel_engine_dump(engine, &p, "%s\n", engine->name);
 887                 }
 888         }
 889
 890         __intel_gt_set_wedged(gt);
 891
 892         mutex_unlock(&gt->reset.mutex);
 893         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
 894 }
 895
 896 static bool __intel_gt_unset_wedged(struct intel_gt *gt)
 897 {
 898         struct intel_gt_timelines *timelines = &gt->timelines;
 899         struct intel_timeline *tl;
 900         bool ok;
 901
 902         if (!test_bit(I915_WEDGED, &gt->reset.flags))
 903                 return true;
 904
 905         /* Never fully initialised, recovery impossible */
 906         if (intel_gt_has_unrecoverable_error(gt))
 907                 return false;
 908
 909         GT_TRACE(gt, "start\n");
 910
 911         /*
 912          * Before unwedging, make sure that all pending operations
 913          * are flushed and errored out - we may have requests waiting upon
 914          * third party fences. We marked all inflight requests as EIO, and
 915          * every execbuf since returned EIO, for consistency we want all
 916          * the currently pending requests to also be marked as EIO, which
 917          * is done inside our nop_submit_request - and so we must wait.
 918          *
 919          * No more can be submitted until we reset the wedged bit.
 920          */
 921         spin_lock(&timelines->lock);
 922         list_for_each_entry(tl, &timelines->active_list, link) {
 923                 struct dma_fence *fence;
 924
 925                 fence = i915_active_fence_get(&tl->last_request);
 926                 if (!fence)
 927                         continue;
 928
 929                 spin_unlock(&timelines->lock);
 930
 931                 /*
 932                  * All internal dependencies (i915_requests) will have
 933                  * been flushed by the set-wedge, but we may be stuck waiting
 934                  * for external fences. These should all be capped to 10s
 935                  * (I915_FENCE_TIMEOUT) so this wait should not be unbounded
 936                  * in the worst case.
 937                  */
 938                 dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
 939                 dma_fence_put(fence);
 940
 941                 /* Restart iteration after droping lock */
 942                 spin_lock(&timelines->lock);
 943                 tl = list_entry(&timelines->active_list, typeof(*tl), link);
 944         }
 945         spin_unlock(&timelines->lock);
 946
 947         /* We must reset pending GPU events before restoring our submission */
 948         ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
 949         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 950                 ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
 951         if (!ok) {
 952                 /*
 953                  * Warn CI about the unrecoverable wedged condition.
 954                  * Time for a reboot.
 955                  */
 956                 add_taint_for_CI(gt->i915, TAINT_WARN);
 957                 return false;
 958         }
 959
 960         /*
 961          * Undo nop_submit_request. We prevent all new i915 requests from
 962          * being queued (by disallowing execbuf whilst wedged) so having
 963          * waited for all active requests above, we know the system is idle
 964          * and do not have to worry about a thread being inside
 965          * engine->submit_request() as we swap over. So unlike installing
 966          * the nop_submit_request on reset, we can do this from normal
 967          * context and do not require stop_machine().
 968          */
 969         intel_engines_reset_default_submission(gt);
 970
 971         GT_TRACE(gt, "end\n");
 972
 973         smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
 974         clear_bit(I915_WEDGED, &gt->reset.flags);
 975
 976         return true;
 977 }
 978
 979 bool intel_gt_unset_wedged(struct intel_gt *gt)
 980 {
 981         bool result;
 982
 983         mutex_lock(&gt->reset.mutex);
 984         result = __intel_gt_unset_wedged(gt);
 985         mutex_unlock(&gt->reset.mutex);
 986
 987         return result;
 988 }
 989
 990 static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 991 {
 992         int err, i;
 993
 994         gt_revoke(gt);
 995
 996         err = __intel_gt_reset(gt, ALL_ENGINES);
 997         for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
 998                 msleep(10 * (i + 1));
 999                 err = __intel_gt_reset(gt, ALL_ENGINES);
1000         }
1001         if (err)
1002                 return err;
1003
1004         return gt_reset(gt, stalled_mask);
1005 }
1006
1007 static int resume(struct intel_gt *gt)
1008 {
1009         struct intel_engine_cs *engine;
1010         enum intel_engine_id id;
1011         int ret;
1012
1013         for_each_engine(engine, gt, id) {
1014                 ret = intel_engine_resume(engine);
1015                 if (ret)
1016                         return ret;
1017         }
1018
1019         return 0;
1020 }
1021
1022 /**
1023  * intel_gt_reset - reset chip after a hang
1024  * @gt: #intel_gt to reset
1025  * @stalled_mask: mask of the stalled engines with the guilty requests
1026  * @reason: user error message for why we are resetting
1027  *
1028  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1029  * on failure.
1030  *
1031  * Procedure is fairly simple:
1032  *   - reset the chip using the reset reg
1033  *   - re-init context state
1034  *   - re-init hardware status page
1035  *   - re-init ring buffer
1036  *   - re-init interrupt state
1037  *   - re-init display
1038  */
1039 void intel_gt_reset(struct intel_gt *gt,
1040                     intel_engine_mask_t stalled_mask,
1041                     const char *reason)
1042 {
1043         intel_engine_mask_t awake;
1044         int ret;
1045
1046         GT_TRACE(gt, "flags=%lx\n", gt->reset.flags);
1047
1048         might_sleep();
1049         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1050         mutex_lock(&gt->reset.mutex);
1051
1052         /* Clear any previous failed attempts at recovery. Time to try again. */
1053         if (!__intel_gt_unset_wedged(gt))
1054                 goto unlock;
1055
1056         if (reason)
1057                 drm_notice(&gt->i915->drm,
1058                            "Resetting chip for %s\n", reason);
1059         atomic_inc(&gt->i915->gpu_error.reset_count);
1060
1061         awake = reset_prepare(gt);
1062
1063         if (!intel_has_gpu_reset(gt)) {
1064                 if (gt->i915->params.reset)
1065                         drm_err(&gt->i915->drm, "GPU reset not supported\n");
1066                 else
1067                         drm_dbg(&gt->i915->drm, "GPU reset disabled\n");
1068                 goto error;
1069         }
1070
1071         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1072                 intel_runtime_pm_disable_interrupts(gt->i915);
1073
1074         if (do_reset(gt, stalled_mask)) {
1075                 drm_err(&gt->i915->drm, "Failed to reset chip\n");
1076                 goto taint;
1077         }
1078
1079         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1080                 intel_runtime_pm_enable_interrupts(gt->i915);
1081
1082         intel_overlay_reset(gt->i915);
1083
1084         /*
1085          * Next we need to restore the context, but we don't use those
1086          * yet either...
1087          *
1088          * Ring buffer needs to be re-initialized in the KMS case, or if X
1089          * was running at the time of the reset (i.e. we weren't VT
1090          * switched away).
1091          */
1092         ret = intel_gt_init_hw(gt);
1093         if (ret) {
1094                 drm_err(&gt->i915->drm,
1095                         "Failed to initialise HW following reset (%d)\n",
1096                         ret);
1097                 goto taint;
1098         }
1099
1100         ret = resume(gt);
1101         if (ret)
1102                 goto taint;
1103
1104 finish:
1105         reset_finish(gt, awake);
1106 unlock:
1107         mutex_unlock(&gt->reset.mutex);
1108         return;
1109
1110 taint:
1111         /*
1112          * History tells us that if we cannot reset the GPU now, we
1113          * never will. This then impacts everything that is run
1114          * subsequently. On failing the reset, we mark the driver
1115          * as wedged, preventing further execution on the GPU.
1116          * We also want to go one step further and add a taint to the
1117          * kernel so that any subsequent faults can be traced back to
1118          * this failure. This is important for CI, where if the
1119          * GPU/driver fails we would like to reboot and restart testing
1120          * rather than continue on into oblivion. For everyone else,
1121          * the system should still plod along, but they have been warned!
1122          */
1123         add_taint_for_CI(gt->i915, TAINT_WARN);
1124 error:
1125         __intel_gt_set_wedged(gt);
1126         goto finish;
1127 }
1128
1129 static inline int intel_gt_reset_engine(struct intel_engine_cs *engine)
1130 {
1131         return __intel_gt_reset(engine->gt, engine->mask);
1132 }
1133
1134 /**
1135  * intel_engine_reset - reset GPU engine to recover from a hang
1136  * @engine: engine to reset
1137  * @msg: reason for GPU reset; or NULL for no drm_notice()
1138  *
1139  * Reset a specific GPU engine. Useful if a hang is detected.
1140  * Returns zero on successful reset or otherwise an error code.
1141  *
1142  * Procedure is:
1143  *  - identifies the request that caused the hang and it is dropped
1144  *  - reset engine (which will force the engine to idle)
1145  *  - re-init/configure engine
1146  */
1147 int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1148 {
1149         struct intel_gt *gt = engine->gt;
1150         bool uses_guc = intel_engine_in_guc_submission_mode(engine);
1151         int ret;
1152
1153         ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1154         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));
1155
1156         if (!intel_engine_pm_get_if_awake(engine))
1157                 return 0;
1158
1159         reset_prepare_engine(engine);
1160
1161         if (msg)
1162                 drm_notice(&engine->i915->drm,
1163                            "Resetting %s for %s\n", engine->name, msg);
1164         atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1165
1166         if (!uses_guc)
1167                 ret = intel_gt_reset_engine(engine);
1168         else
1169                 ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
1170         if (ret) {
1171                 /* If we fail here, we expect to fallback to a global reset */
1172                 drm_dbg(&gt->i915->drm, "%sFailed to reset %s, ret=%d\n",
1173                         uses_guc ? "GuC " : "", engine->name, ret);
1174                 goto out;
1175         }
1176
1177         /*
1178          * The request that caused the hang is stuck on elsp, we know the
1179          * active request and can drop it, adjust head to skip the offending
1180          * request to resume executing remaining requests in the queue.
1181          */
1182         __intel_engine_reset(engine, true);
1183
1184         /*
1185          * The engine and its registers (and workarounds in case of render)
1186          * have been reset to their default values. Follow the init_ring
1187          * process to program RING_MODE, HWSP and re-enable submission.
1188          */
1189         ret = intel_engine_resume(engine);
1190
1191 out:
1192         intel_engine_cancel_stop_cs(engine);
1193         reset_finish_engine(engine);
1194         intel_engine_pm_put_async(engine);
1195         return ret;
1196 }
1197
1198 static void intel_gt_reset_global(struct intel_gt *gt,
1199                                   u32 engine_mask,
1200                                   const char *reason)
1201 {
1202         struct kobject *kobj = &gt->i915->drm.primary->kdev->kobj;
1203         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1204         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1205         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1206         struct intel_wedge_me w;
1207
1208         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1209
1210         drm_dbg(&gt->i915->drm, "resetting chip, engines=%x\n", engine_mask);
1211         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1212
1213         /* Use a watchdog to ensure that our reset completes */
1214         intel_wedge_on_timeout(&w, gt, 5 * HZ) {
1215                 intel_prepare_reset(gt->i915);
1216
1217                 /* Flush everyone using a resource about to be clobbered */
1218                 synchronize_srcu_expedited(&gt->reset.backoff_srcu);
1219
1220                 intel_gt_reset(gt, engine_mask, reason);
1221
1222                 intel_finish_reset(gt->i915);
1223         }
1224
1225         if (!test_bit(I915_WEDGED, &gt->reset.flags))
1226                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1227 }
1228
1229 /**
1230  * intel_gt_handle_error - handle a gpu error
1231  * @gt: the intel_gt
1232  * @engine_mask: mask representing engines that are hung
1233  * @flags: control flags
1234  * @fmt: Error message format string
1235  *
1236  * Do some basic checking of register state at error time and
1237  * dump it to the syslog.  Also call i915_capture_error_state() to make
1238  * sure we get a record and make it available in debugfs.  Fire a uevent
1239  * so userspace knows something bad happened (should trigger collection
1240  * of a ring dump etc.).
1241  */
1242 void intel_gt_handle_error(struct intel_gt *gt,
1243                            intel_engine_mask_t engine_mask,
1244                            unsigned long flags,
1245                            const char *fmt, ...)
1246 {
1247         struct intel_engine_cs *engine;
1248         intel_wakeref_t wakeref;
1249         intel_engine_mask_t tmp;
1250         char error_msg[80];
1251         char *msg = NULL;
1252
1253         if (fmt) {
1254                 va_list args;
1255
1256                 va_start(args, fmt);
1257                 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1258                 va_end(args);
1259
1260                 msg = error_msg;
1261         }
1262
1263         /*
1264          * In most cases it's guaranteed that we get here with an RPM
1265          * reference held, for example because there is a pending GPU
1266          * request that won't finish until the reset is done. This
1267          * isn't the case at least when we get here by doing a
1268          * simulated reset via debugfs, so get an RPM reference.
1269          */
1270         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1271
1272         engine_mask &= gt->info.engine_mask;
1273
1274         if (flags & I915_ERROR_CAPTURE) {
1275                 i915_capture_error_state(gt->i915);
1276                 intel_gt_clear_error_registers(gt, engine_mask);
1277         }
1278
1279         /*
1280          * Try engine reset when available. We fall back to full reset if
1281          * single reset fails.
1282          */
1283         if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
1284                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
1285                         BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1286                         if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1287                                              &gt->reset.flags))
1288                                 continue;
1289
1290                         if (intel_engine_reset(engine, msg) == 0)
1291                                 engine_mask &= ~engine->mask;
1292
1293                         clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1294                                               &gt->reset.flags);
1295                 }
1296         }
1297
1298         if (!engine_mask)
1299                 goto out;
1300
1301         /* Full reset needs the mutex, stop any other user trying to do so. */
1302         if (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1303                 wait_event(gt->reset.queue,
1304                            !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1305                 goto out; /* piggy-back on the other reset */
1306         }
1307
1308         /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
1309         synchronize_rcu_expedited();
1310
1311         /* Prevent any other reset-engine attempt. */
1312         for_each_engine(engine, gt, tmp) {
1313                 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1314                                         &gt->reset.flags))
1315                         wait_on_bit(&gt->reset.flags,
1316                                     I915_RESET_ENGINE + engine->id,
1317                                     TASK_UNINTERRUPTIBLE);
1318         }
1319
1320         intel_gt_reset_global(gt, engine_mask, msg);
1321
1322         for_each_engine(engine, gt, tmp)
1323                 clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1324                                  &gt->reset.flags);
1325         clear_bit_unlock(I915_RESET_BACKOFF, &gt->reset.flags);
1326         smp_mb__after_atomic();
1327         wake_up_all(&gt->reset.queue);
1328
1329 out:
1330         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1331 }
1332
1333 int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
1334 {
1335         might_lock(&gt->reset.backoff_srcu);
1336         might_sleep();
1337
1338         rcu_read_lock();
1339         while (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1340                 rcu_read_unlock();
1341
1342                 if (wait_event_interruptible(gt->reset.queue,
1343                                              !test_bit(I915_RESET_BACKOFF,
1344                                                        &gt->reset.flags)))
1345                         return -EINTR;
1346
1347                 rcu_read_lock();
1348         }
1349         *srcu = srcu_read_lock(&gt->reset.backoff_srcu);
1350         rcu_read_unlock();
1351
1352         return 0;
1353 }
1354
1355 void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1356 __releases(&gt->reset.backoff_srcu)
1357 {
1358         srcu_read_unlock(&gt->reset.backoff_srcu, tag);
1359 }
1360
1361 int intel_gt_terminally_wedged(struct intel_gt *gt)
1362 {
1363         might_sleep();
1364
1365         if (!intel_gt_is_wedged(gt))
1366                 return 0;
1367
1368         if (intel_gt_has_unrecoverable_error(gt))
1369                 return -EIO;
1370
1371         /* Reset still in progress? Maybe we will recover? */
1372         if (wait_event_interruptible(gt->reset.queue,
1373                                      !test_bit(I915_RESET_BACKOFF,
1374                                                &gt->reset.flags)))
1375                 return -EINTR;
1376
1377         return intel_gt_is_wedged(gt) ? -EIO : 0;
1378 }
1379
1380 void intel_gt_set_wedged_on_init(struct intel_gt *gt)
1381 {
1382         BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
1383                      I915_WEDGED_ON_INIT);
1384         intel_gt_set_wedged(gt);
1385         set_bit(I915_WEDGED_ON_INIT, &gt->reset.flags);
1386
1387         /* Wedged on init is non-recoverable */
1388         add_taint_for_CI(gt->i915, TAINT_WARN);
1389 }
1390
1391 void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
1392 {
1393         intel_gt_set_wedged(gt);
1394         set_bit(I915_WEDGED_ON_FINI, &gt->reset.flags);
1395 }
1396
1397 void intel_gt_init_reset(struct intel_gt *gt)
1398 {
1399         init_waitqueue_head(&gt->reset.queue);
1400         mutex_init(&gt->reset.mutex);
1401         init_srcu_struct(&gt->reset.backoff_srcu);
1402
1403         /* no GPU until we are ready! */
1404         __set_bit(I915_WEDGED, &gt->reset.flags);
1405 }
1406
1407 void intel_gt_fini_reset(struct intel_gt *gt)
1408 {
1409         cleanup_srcu_struct(&gt->reset.backoff_srcu);
1410 }
1411
1412 static void intel_wedge_me(struct work_struct *work)
1413 {
1414         struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1415
1416         drm_err(&w->gt->i915->drm,
1417                 "%s timed out, cancelling all in-flight rendering.\n",
1418                 w->name);
1419         intel_gt_set_wedged(w->gt);
1420 }
1421
1422 void __intel_init_wedge(struct intel_wedge_me *w,
1423                         struct intel_gt *gt,
1424                         long timeout,
1425                         const char *name)
1426 {
1427         w->gt = gt;
1428         w->name = name;
1429
1430         INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1431         schedule_delayed_work(&w->work, timeout);
1432 }
1433
1434 void __intel_fini_wedge(struct intel_wedge_me *w)
1435 {
1436         cancel_delayed_work_sync(&w->work);
1437         destroy_delayed_work_on_stack(&w->work);
1438         w->gt = NULL;
1439 }
1440
1441 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1442 #include "selftest_reset.c"
1443 #include "selftest_hangcheck.c"
1444 #endif