1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
6 #include <linux/stop_machine.h>
8 #include <asm/set_memory.h>
11 #include <drm/i915_drm.h>
15 #include "i915_scatterlist.h"
16 #include "i915_vgpu.h"
18 #include "intel_gtt.h"
21 i915_get_ggtt_vma_pages(struct i915_vma *vma);
23 static void i915_ggtt_color_adjust(const struct drm_mm_node *node,
28 if (i915_node_color_differs(node, color))
29 *start += I915_GTT_PAGE_SIZE;
32 * Also leave a space between the unallocated reserved node after the
33 * GTT and any objects within the GTT, i.e. we use the color adjustment
34 * to insert a guard page to prevent prefetches crossing over the
37 node = list_next_entry(node, node_list);
38 if (node->color != color)
39 *end -= I915_GTT_PAGE_SIZE;
42 static int ggtt_init_hw(struct i915_ggtt *ggtt)
44 struct drm_i915_private *i915 = ggtt->vm.i915;
46 i915_address_space_init(&ggtt->vm, VM_CLASS_GGTT);
48 ggtt->vm.is_ggtt = true;
50 /* Only VLV supports read-only GGTT mappings */
51 ggtt->vm.has_read_only = IS_VALLEYVIEW(i915);
53 if (!HAS_LLC(i915) && !HAS_PPGTT(i915))
54 ggtt->vm.mm.color_adjust = i915_ggtt_color_adjust;
56 if (ggtt->mappable_end) {
57 if (!io_mapping_init_wc(&ggtt->iomap,
59 ggtt->mappable_end)) {
60 ggtt->vm.cleanup(&ggtt->vm);
64 ggtt->mtrr = arch_phys_wc_add(ggtt->gmadr.start,
68 intel_ggtt_init_fences(ggtt);
74 * i915_ggtt_init_hw - Initialize GGTT hardware
77 int i915_ggtt_init_hw(struct drm_i915_private *i915)
82 * Note that we use page colouring to enforce a guard page at the
83 * end of the address space. This is required as the CS may prefetch
84 * beyond the end of the batch buffer, across the page boundary,
85 * and beyond the end of the GTT if we do not provide a guard.
87 ret = ggtt_init_hw(&i915->ggtt);
95 * Certain Gen5 chipsets require require idling the GPU before
96 * unmapping anything from the GTT when VT-d is enabled.
98 static bool needs_idle_maps(struct drm_i915_private *i915)
101 * Query intel_iommu to see if we need the workaround. Presumably that
104 return IS_GEN(i915, 5) && IS_MOBILE(i915) && intel_vtd_active();
107 void i915_ggtt_suspend(struct i915_ggtt *ggtt)
109 struct i915_vma *vma, *vn;
112 mutex_lock(&ggtt->vm.mutex);
114 /* Skip rewriting PTE on VMA unbind. */
115 open = atomic_xchg(&ggtt->vm.open, 0);
117 list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link) {
118 GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
119 i915_vma_wait_for_bind(vma);
121 if (i915_vma_is_pinned(vma))
124 if (!i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND)) {
125 __i915_vma_evict(vma);
126 drm_mm_remove_node(&vma->node);
130 ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
131 ggtt->invalidate(ggtt);
132 atomic_set(&ggtt->vm.open, open);
134 mutex_unlock(&ggtt->vm.mutex);
136 intel_gt_check_and_clear_faults(ggtt->vm.gt);
139 void gen6_ggtt_invalidate(struct i915_ggtt *ggtt)
141 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
143 spin_lock_irq(&uncore->lock);
144 intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
145 intel_uncore_read_fw(uncore, GFX_FLSH_CNTL_GEN6);
146 spin_unlock_irq(&uncore->lock);
149 static void gen8_ggtt_invalidate(struct i915_ggtt *ggtt)
151 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
154 * Note that as an uncached mmio write, this will flush the
155 * WCB of the writes into the GGTT before it triggers the invalidate.
157 intel_uncore_write_fw(uncore, GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN);
160 static void guc_ggtt_invalidate(struct i915_ggtt *ggtt)
162 struct intel_uncore *uncore = ggtt->vm.gt->uncore;
163 struct drm_i915_private *i915 = ggtt->vm.i915;
165 gen8_ggtt_invalidate(ggtt);
167 if (INTEL_GEN(i915) >= 12)
168 intel_uncore_write_fw(uncore, GEN12_GUC_TLB_INV_CR,
169 GEN12_GUC_TLB_INV_CR_INVALIDATE);
171 intel_uncore_write_fw(uncore, GEN8_GTCR, GEN8_GTCR_INVALIDATE);
174 static void gmch_ggtt_invalidate(struct i915_ggtt *ggtt)
176 intel_gtt_chipset_flush();
179 static u64 gen8_ggtt_pte_encode(dma_addr_t addr,
180 enum i915_cache_level level,
183 return addr | _PAGE_PRESENT;
186 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
191 static void gen8_ggtt_insert_page(struct i915_address_space *vm,
194 enum i915_cache_level level,
197 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
198 gen8_pte_t __iomem *pte =
199 (gen8_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
201 gen8_set_pte(pte, gen8_ggtt_pte_encode(addr, level, 0));
203 ggtt->invalidate(ggtt);
206 static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
207 struct i915_vma *vma,
208 enum i915_cache_level level,
211 const gen8_pte_t pte_encode = gen8_ggtt_pte_encode(0, level, 0);
212 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
213 gen8_pte_t __iomem *gte;
214 gen8_pte_t __iomem *end;
215 struct sgt_iter iter;
219 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
220 * not to allow the user to override access to a read only page.
223 gte = (gen8_pte_t __iomem *)ggtt->gsm;
224 gte += vma->node.start / I915_GTT_PAGE_SIZE;
225 end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
227 for_each_sgt_daddr(addr, iter, vma->pages)
228 gen8_set_pte(gte++, pte_encode | addr);
229 GEM_BUG_ON(gte > end);
231 /* Fill the allocated but "unused" space beyond the end of the buffer */
233 gen8_set_pte(gte++, vm->scratch[0]->encode);
236 * We want to flush the TLBs only after we're certain all the PTE
237 * updates have finished.
239 ggtt->invalidate(ggtt);
242 static void gen6_ggtt_insert_page(struct i915_address_space *vm,
245 enum i915_cache_level level,
248 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
249 gen6_pte_t __iomem *pte =
250 (gen6_pte_t __iomem *)ggtt->gsm + offset / I915_GTT_PAGE_SIZE;
252 iowrite32(vm->pte_encode(addr, level, flags), pte);
254 ggtt->invalidate(ggtt);
258 * Binds an object into the global gtt with the specified cache level.
259 * The object will be accessible to the GPU via commands whose operands
260 * reference offsets within the global GTT as well as accessible by the GPU
261 * through the GMADR mapped BAR (i915->mm.gtt->gtt).
263 static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
264 struct i915_vma *vma,
265 enum i915_cache_level level,
268 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
269 gen6_pte_t __iomem *gte;
270 gen6_pte_t __iomem *end;
271 struct sgt_iter iter;
274 gte = (gen6_pte_t __iomem *)ggtt->gsm;
275 gte += vma->node.start / I915_GTT_PAGE_SIZE;
276 end = gte + vma->node.size / I915_GTT_PAGE_SIZE;
278 for_each_sgt_daddr(addr, iter, vma->pages)
279 iowrite32(vm->pte_encode(addr, level, flags), gte++);
280 GEM_BUG_ON(gte > end);
282 /* Fill the allocated but "unused" space beyond the end of the buffer */
284 iowrite32(vm->scratch[0]->encode, gte++);
287 * We want to flush the TLBs only after we're certain all the PTE
288 * updates have finished.
290 ggtt->invalidate(ggtt);
293 static void nop_clear_range(struct i915_address_space *vm,
294 u64 start, u64 length)
298 static void gen8_ggtt_clear_range(struct i915_address_space *vm,
299 u64 start, u64 length)
301 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
302 unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
303 unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
304 const gen8_pte_t scratch_pte = vm->scratch[0]->encode;
305 gen8_pte_t __iomem *gtt_base =
306 (gen8_pte_t __iomem *)ggtt->gsm + first_entry;
307 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
310 if (WARN(num_entries > max_entries,
311 "First entry = %d; Num entries = %d (max=%d)\n",
312 first_entry, num_entries, max_entries))
313 num_entries = max_entries;
315 for (i = 0; i < num_entries; i++)
316 gen8_set_pte(>t_base[i], scratch_pte);
319 static void bxt_vtd_ggtt_wa(struct i915_address_space *vm)
322 * Make sure the internal GAM fifo has been cleared of all GTT
323 * writes before exiting stop_machine(). This guarantees that
324 * any aperture accesses waiting to start in another process
325 * cannot back up behind the GTT writes causing a hang.
326 * The register can be any arbitrary GAM register.
328 intel_uncore_posting_read_fw(vm->gt->uncore, GFX_FLSH_CNTL_GEN6);
332 struct i915_address_space *vm;
335 enum i915_cache_level level;
338 static int bxt_vtd_ggtt_insert_page__cb(void *_arg)
340 struct insert_page *arg = _arg;
342 gen8_ggtt_insert_page(arg->vm, arg->addr, arg->offset, arg->level, 0);
343 bxt_vtd_ggtt_wa(arg->vm);
348 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space *vm,
351 enum i915_cache_level level,
354 struct insert_page arg = { vm, addr, offset, level };
356 stop_machine(bxt_vtd_ggtt_insert_page__cb, &arg, NULL);
359 struct insert_entries {
360 struct i915_address_space *vm;
361 struct i915_vma *vma;
362 enum i915_cache_level level;
366 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg)
368 struct insert_entries *arg = _arg;
370 gen8_ggtt_insert_entries(arg->vm, arg->vma, arg->level, arg->flags);
371 bxt_vtd_ggtt_wa(arg->vm);
376 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space *vm,
377 struct i915_vma *vma,
378 enum i915_cache_level level,
381 struct insert_entries arg = { vm, vma, level, flags };
383 stop_machine(bxt_vtd_ggtt_insert_entries__cb, &arg, NULL);
386 static void gen6_ggtt_clear_range(struct i915_address_space *vm,
387 u64 start, u64 length)
389 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
390 unsigned int first_entry = start / I915_GTT_PAGE_SIZE;
391 unsigned int num_entries = length / I915_GTT_PAGE_SIZE;
392 gen6_pte_t scratch_pte, __iomem *gtt_base =
393 (gen6_pte_t __iomem *)ggtt->gsm + first_entry;
394 const int max_entries = ggtt_total_entries(ggtt) - first_entry;
397 if (WARN(num_entries > max_entries,
398 "First entry = %d; Num entries = %d (max=%d)\n",
399 first_entry, num_entries, max_entries))
400 num_entries = max_entries;
402 scratch_pte = vm->scratch[0]->encode;
403 for (i = 0; i < num_entries; i++)
404 iowrite32(scratch_pte, >t_base[i]);
407 static void i915_ggtt_insert_page(struct i915_address_space *vm,
410 enum i915_cache_level cache_level,
413 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
414 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
416 intel_gtt_insert_page(addr, offset >> PAGE_SHIFT, flags);
419 static void i915_ggtt_insert_entries(struct i915_address_space *vm,
420 struct i915_vma *vma,
421 enum i915_cache_level cache_level,
424 unsigned int flags = (cache_level == I915_CACHE_NONE) ?
425 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
427 intel_gtt_insert_sg_entries(vma->pages, vma->node.start >> PAGE_SHIFT,
431 static void i915_ggtt_clear_range(struct i915_address_space *vm,
432 u64 start, u64 length)
434 intel_gtt_clear_range(start >> PAGE_SHIFT, length >> PAGE_SHIFT);
437 static void ggtt_bind_vma(struct i915_address_space *vm,
438 struct i915_vm_pt_stash *stash,
439 struct i915_vma *vma,
440 enum i915_cache_level cache_level,
443 struct drm_i915_gem_object *obj = vma->obj;
446 if (i915_vma_is_bound(vma, ~flags & I915_VMA_BIND_MASK))
449 /* Applicable to VLV (gen8+ do not support RO in the GGTT) */
451 if (i915_gem_object_is_readonly(obj))
452 pte_flags |= PTE_READ_ONLY;
454 vm->insert_entries(vm, vma, cache_level, pte_flags);
455 vma->page_sizes.gtt = I915_GTT_PAGE_SIZE;
458 static void ggtt_unbind_vma(struct i915_address_space *vm, struct i915_vma *vma)
460 vm->clear_range(vm, vma->node.start, vma->size);
463 static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
468 if (!intel_uc_uses_guc(&ggtt->vm.gt->uc))
471 GEM_BUG_ON(ggtt->vm.total <= GUC_GGTT_TOP);
472 size = ggtt->vm.total - GUC_GGTT_TOP;
474 ret = i915_gem_gtt_reserve(&ggtt->vm, &ggtt->uc_fw, size,
475 GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
478 drm_dbg(&ggtt->vm.i915->drm,
479 "Failed to reserve top of GGTT for GuC\n");
484 static void ggtt_release_guc_top(struct i915_ggtt *ggtt)
486 if (drm_mm_node_allocated(&ggtt->uc_fw))
487 drm_mm_remove_node(&ggtt->uc_fw);
490 static void cleanup_init_ggtt(struct i915_ggtt *ggtt)
492 ggtt_release_guc_top(ggtt);
493 if (drm_mm_node_allocated(&ggtt->error_capture))
494 drm_mm_remove_node(&ggtt->error_capture);
495 mutex_destroy(&ggtt->error_mutex);
498 static int init_ggtt(struct i915_ggtt *ggtt)
501 * Let GEM Manage all of the aperture.
503 * However, leave one page at the end still bound to the scratch page.
504 * There are a number of places where the hardware apparently prefetches
505 * past the end of the object, and we've seen multiple hangs with the
506 * GPU head pointer stuck in a batchbuffer bound at the last page of the
507 * aperture. One page should be enough to keep any prefetching inside
510 unsigned long hole_start, hole_end;
511 struct drm_mm_node *entry;
515 * GuC requires all resources that we're sharing with it to be placed in
516 * non-WOPCM memory. If GuC is not present or not in use we still need a
517 * small bias as ring wraparound at offset 0 sometimes hangs. No idea
520 ggtt->pin_bias = max_t(u32, I915_GTT_PAGE_SIZE,
521 intel_wopcm_guc_size(&ggtt->vm.i915->wopcm));
523 ret = intel_vgt_balloon(ggtt);
527 mutex_init(&ggtt->error_mutex);
528 if (ggtt->mappable_end) {
530 * Reserve a mappable slot for our lockless error capture.
532 * We strongly prefer taking address 0x0 in order to protect
533 * other critical buffers against accidental overwrites,
534 * as writing to address 0 is a very common mistake.
536 * Since 0 may already be in use by the system (e.g. the BIOS
537 * framebuffer), we let the reservation fail quietly and hope
538 * 0 remains reserved always.
540 * If we fail to reserve 0, and then fail to find any space
541 * for an error-capture, remain silent. We can afford not
542 * to reserve an error_capture node as we have fallback
543 * paths, and we trust that 0 will remain reserved. However,
544 * the only likely reason for failure to insert is a driver
545 * bug, which we expect to cause other failures...
547 ggtt->error_capture.size = I915_GTT_PAGE_SIZE;
548 ggtt->error_capture.color = I915_COLOR_UNEVICTABLE;
549 if (drm_mm_reserve_node(&ggtt->vm.mm, &ggtt->error_capture))
550 drm_mm_insert_node_in_range(&ggtt->vm.mm,
551 &ggtt->error_capture,
552 ggtt->error_capture.size, 0,
553 ggtt->error_capture.color,
554 0, ggtt->mappable_end,
557 if (drm_mm_node_allocated(&ggtt->error_capture))
558 drm_dbg(&ggtt->vm.i915->drm,
559 "Reserved GGTT:[%llx, %llx] for use by error capture\n",
560 ggtt->error_capture.start,
561 ggtt->error_capture.start + ggtt->error_capture.size);
564 * The upper portion of the GuC address space has a sizeable hole
565 * (several MB) that is inaccessible by GuC. Reserve this range within
566 * GGTT as it can comfortably hold GuC/HuC firmware images.
568 ret = ggtt_reserve_guc_top(ggtt);
572 /* Clear any non-preallocated blocks */
573 drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
574 drm_dbg(&ggtt->vm.i915->drm,
575 "clearing unused GTT space: [%lx, %lx]\n",
576 hole_start, hole_end);
577 ggtt->vm.clear_range(&ggtt->vm, hole_start,
578 hole_end - hole_start);
581 /* And finally clear the reserved guard page */
582 ggtt->vm.clear_range(&ggtt->vm, ggtt->vm.total - PAGE_SIZE, PAGE_SIZE);
587 cleanup_init_ggtt(ggtt);
591 static void aliasing_gtt_bind_vma(struct i915_address_space *vm,
592 struct i915_vm_pt_stash *stash,
593 struct i915_vma *vma,
594 enum i915_cache_level cache_level,
599 /* Currently applicable only to VLV */
601 if (i915_gem_object_is_readonly(vma->obj))
602 pte_flags |= PTE_READ_ONLY;
604 if (flags & I915_VMA_LOCAL_BIND)
605 ppgtt_bind_vma(&i915_vm_to_ggtt(vm)->alias->vm,
606 stash, vma, cache_level, flags);
608 if (flags & I915_VMA_GLOBAL_BIND)
609 vm->insert_entries(vm, vma, cache_level, pte_flags);
612 static void aliasing_gtt_unbind_vma(struct i915_address_space *vm,
613 struct i915_vma *vma)
615 if (i915_vma_is_bound(vma, I915_VMA_GLOBAL_BIND))
616 vm->clear_range(vm, vma->node.start, vma->size);
618 if (i915_vma_is_bound(vma, I915_VMA_LOCAL_BIND))
619 ppgtt_unbind_vma(&i915_vm_to_ggtt(vm)->alias->vm, vma);
622 static int init_aliasing_ppgtt(struct i915_ggtt *ggtt)
624 struct i915_vm_pt_stash stash = {};
625 struct i915_ppgtt *ppgtt;
628 ppgtt = i915_ppgtt_create(ggtt->vm.gt);
630 return PTR_ERR(ppgtt);
632 if (GEM_WARN_ON(ppgtt->vm.total < ggtt->vm.total)) {
637 err = i915_vm_alloc_pt_stash(&ppgtt->vm, &stash, ggtt->vm.total);
641 err = i915_vm_pin_pt_stash(&ppgtt->vm, &stash);
646 * Note we only pre-allocate as far as the end of the global
647 * GTT. On 48b / 4-level page-tables, the difference is very,
648 * very significant! We have to preallocate as GVT/vgpu does
649 * not like the page directory disappearing.
651 ppgtt->vm.allocate_va_range(&ppgtt->vm, &stash, 0, ggtt->vm.total);
654 ggtt->vm.bind_async_flags |= ppgtt->vm.bind_async_flags;
656 GEM_BUG_ON(ggtt->vm.vma_ops.bind_vma != ggtt_bind_vma);
657 ggtt->vm.vma_ops.bind_vma = aliasing_gtt_bind_vma;
659 GEM_BUG_ON(ggtt->vm.vma_ops.unbind_vma != ggtt_unbind_vma);
660 ggtt->vm.vma_ops.unbind_vma = aliasing_gtt_unbind_vma;
662 i915_vm_free_pt_stash(&ppgtt->vm, &stash);
666 i915_vm_free_pt_stash(&ppgtt->vm, &stash);
668 i915_vm_put(&ppgtt->vm);
672 static void fini_aliasing_ppgtt(struct i915_ggtt *ggtt)
674 struct i915_ppgtt *ppgtt;
676 ppgtt = fetch_and_zero(&ggtt->alias);
680 i915_vm_put(&ppgtt->vm);
682 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
683 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
686 int i915_init_ggtt(struct drm_i915_private *i915)
690 ret = init_ggtt(&i915->ggtt);
694 if (INTEL_PPGTT(i915) == INTEL_PPGTT_ALIASING) {
695 ret = init_aliasing_ppgtt(&i915->ggtt);
697 cleanup_init_ggtt(&i915->ggtt);
703 static void ggtt_cleanup_hw(struct i915_ggtt *ggtt)
705 struct i915_vma *vma, *vn;
707 atomic_set(&ggtt->vm.open, 0);
709 rcu_barrier(); /* flush the RCU'ed__i915_vm_release */
710 flush_workqueue(ggtt->vm.i915->wq);
712 mutex_lock(&ggtt->vm.mutex);
714 list_for_each_entry_safe(vma, vn, &ggtt->vm.bound_list, vm_link)
715 WARN_ON(__i915_vma_unbind(vma));
717 if (drm_mm_node_allocated(&ggtt->error_capture))
718 drm_mm_remove_node(&ggtt->error_capture);
719 mutex_destroy(&ggtt->error_mutex);
721 ggtt_release_guc_top(ggtt);
722 intel_vgt_deballoon(ggtt);
724 ggtt->vm.cleanup(&ggtt->vm);
726 mutex_unlock(&ggtt->vm.mutex);
727 i915_address_space_fini(&ggtt->vm);
729 arch_phys_wc_del(ggtt->mtrr);
731 if (ggtt->iomap.size)
732 io_mapping_fini(&ggtt->iomap);
736 * i915_ggtt_driver_release - Clean up GGTT hardware initialization
739 void i915_ggtt_driver_release(struct drm_i915_private *i915)
741 struct i915_ggtt *ggtt = &i915->ggtt;
743 fini_aliasing_ppgtt(ggtt);
745 intel_ggtt_fini_fences(ggtt);
746 ggtt_cleanup_hw(ggtt);
749 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl)
751 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT;
752 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK;
753 return snb_gmch_ctl << 20;
756 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
758 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT;
759 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
761 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
764 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * I915_GTT_PAGE_SIZE */
765 if (bdw_gmch_ctl > 4)
769 return bdw_gmch_ctl << 20;
772 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl)
774 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT;
775 gmch_ctrl &= SNB_GMCH_GGMS_MASK;
778 return 1 << (20 + gmch_ctrl);
783 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
785 struct drm_i915_private *i915 = ggtt->vm.i915;
786 struct pci_dev *pdev = i915->drm.pdev;
787 phys_addr_t phys_addr;
790 /* For Modern GENs the PTEs and register space are split in the BAR */
791 phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
794 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
795 * will be dropped. For WC mappings in general we have 64 byte burst
796 * writes when the WC buffer is flushed, so we can't use it, but have to
797 * resort to an uncached mapping. The WC issue is easily caught by the
798 * readback check when writing GTT PTE entries.
800 if (IS_GEN9_LP(i915) || INTEL_GEN(i915) >= 10)
801 ggtt->gsm = ioremap(phys_addr, size);
803 ggtt->gsm = ioremap_wc(phys_addr, size);
805 drm_err(&i915->drm, "Failed to map the ggtt page table\n");
809 ret = setup_scratch_page(&ggtt->vm);
811 drm_err(&i915->drm, "Scratch setup failed\n");
812 /* iounmap will also get called at remove, but meh */
817 ggtt->vm.scratch[0]->encode =
818 ggtt->vm.pte_encode(px_dma(ggtt->vm.scratch[0]),
824 int ggtt_set_pages(struct i915_vma *vma)
828 GEM_BUG_ON(vma->pages);
830 ret = i915_get_ggtt_vma_pages(vma);
834 vma->page_sizes = vma->obj->mm.page_sizes;
839 static void gen6_gmch_remove(struct i915_address_space *vm)
841 struct i915_ggtt *ggtt = i915_vm_to_ggtt(vm);
847 static struct resource pci_resource(struct pci_dev *pdev, int bar)
849 return (struct resource)DEFINE_RES_MEM(pci_resource_start(pdev, bar),
850 pci_resource_len(pdev, bar));
853 static int gen8_gmch_probe(struct i915_ggtt *ggtt)
855 struct drm_i915_private *i915 = ggtt->vm.i915;
856 struct pci_dev *pdev = i915->drm.pdev;
860 /* TODO: We're not aware of mappable constraints on gen8 yet */
861 if (!IS_DGFX(i915)) {
862 ggtt->gmadr = pci_resource(pdev, 2);
863 ggtt->mappable_end = resource_size(&ggtt->gmadr);
866 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
867 if (IS_CHERRYVIEW(i915))
868 size = chv_get_total_gtt_size(snb_gmch_ctl);
870 size = gen8_get_total_gtt_size(snb_gmch_ctl);
872 ggtt->vm.alloc_pt_dma = alloc_pt_dma;
874 ggtt->vm.total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
875 ggtt->vm.cleanup = gen6_gmch_remove;
876 ggtt->vm.insert_page = gen8_ggtt_insert_page;
877 ggtt->vm.clear_range = nop_clear_range;
878 if (intel_scanout_needs_vtd_wa(i915))
879 ggtt->vm.clear_range = gen8_ggtt_clear_range;
881 ggtt->vm.insert_entries = gen8_ggtt_insert_entries;
883 /* Serialize GTT updates with aperture access on BXT if VT-d is on. */
884 if (intel_ggtt_update_needs_vtd_wa(i915) ||
885 IS_CHERRYVIEW(i915) /* fails with concurrent use/update */) {
886 ggtt->vm.insert_entries = bxt_vtd_ggtt_insert_entries__BKL;
887 ggtt->vm.insert_page = bxt_vtd_ggtt_insert_page__BKL;
888 ggtt->vm.bind_async_flags =
889 I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
892 ggtt->invalidate = gen8_ggtt_invalidate;
894 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
895 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
896 ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
897 ggtt->vm.vma_ops.clear_pages = clear_pages;
899 ggtt->vm.pte_encode = gen8_ggtt_pte_encode;
901 setup_private_pat(ggtt->vm.gt->uncore);
903 return ggtt_probe_common(ggtt, size);
906 static u64 snb_pte_encode(dma_addr_t addr,
907 enum i915_cache_level level,
910 gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
913 case I915_CACHE_L3_LLC:
915 pte |= GEN6_PTE_CACHE_LLC;
917 case I915_CACHE_NONE:
918 pte |= GEN6_PTE_UNCACHED;
927 static u64 ivb_pte_encode(dma_addr_t addr,
928 enum i915_cache_level level,
931 gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
934 case I915_CACHE_L3_LLC:
935 pte |= GEN7_PTE_CACHE_L3_LLC;
938 pte |= GEN6_PTE_CACHE_LLC;
940 case I915_CACHE_NONE:
941 pte |= GEN6_PTE_UNCACHED;
950 static u64 byt_pte_encode(dma_addr_t addr,
951 enum i915_cache_level level,
954 gen6_pte_t pte = GEN6_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
956 if (!(flags & PTE_READ_ONLY))
957 pte |= BYT_PTE_WRITEABLE;
959 if (level != I915_CACHE_NONE)
960 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES;
965 static u64 hsw_pte_encode(dma_addr_t addr,
966 enum i915_cache_level level,
969 gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
971 if (level != I915_CACHE_NONE)
972 pte |= HSW_WB_LLC_AGE3;
977 static u64 iris_pte_encode(dma_addr_t addr,
978 enum i915_cache_level level,
981 gen6_pte_t pte = HSW_PTE_ADDR_ENCODE(addr) | GEN6_PTE_VALID;
984 case I915_CACHE_NONE:
987 pte |= HSW_WT_ELLC_LLC_AGE3;
990 pte |= HSW_WB_ELLC_LLC_AGE3;
997 static int gen6_gmch_probe(struct i915_ggtt *ggtt)
999 struct drm_i915_private *i915 = ggtt->vm.i915;
1000 struct pci_dev *pdev = i915->drm.pdev;
1004 ggtt->gmadr = pci_resource(pdev, 2);
1005 ggtt->mappable_end = resource_size(&ggtt->gmadr);
1008 * 64/512MB is the current min/max we actually know of, but this is
1009 * just a coarse sanity check.
1011 if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
1012 drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
1013 &ggtt->mappable_end);
1017 pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
1019 size = gen6_get_total_gtt_size(snb_gmch_ctl);
1020 ggtt->vm.total = (size / sizeof(gen6_pte_t)) * I915_GTT_PAGE_SIZE;
1022 ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1024 ggtt->vm.clear_range = nop_clear_range;
1025 if (!HAS_FULL_PPGTT(i915) || intel_scanout_needs_vtd_wa(i915))
1026 ggtt->vm.clear_range = gen6_ggtt_clear_range;
1027 ggtt->vm.insert_page = gen6_ggtt_insert_page;
1028 ggtt->vm.insert_entries = gen6_ggtt_insert_entries;
1029 ggtt->vm.cleanup = gen6_gmch_remove;
1031 ggtt->invalidate = gen6_ggtt_invalidate;
1033 if (HAS_EDRAM(i915))
1034 ggtt->vm.pte_encode = iris_pte_encode;
1035 else if (IS_HASWELL(i915))
1036 ggtt->vm.pte_encode = hsw_pte_encode;
1037 else if (IS_VALLEYVIEW(i915))
1038 ggtt->vm.pte_encode = byt_pte_encode;
1039 else if (INTEL_GEN(i915) >= 7)
1040 ggtt->vm.pte_encode = ivb_pte_encode;
1042 ggtt->vm.pte_encode = snb_pte_encode;
1044 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
1045 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
1046 ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
1047 ggtt->vm.vma_ops.clear_pages = clear_pages;
1049 return ggtt_probe_common(ggtt, size);
1052 static void i915_gmch_remove(struct i915_address_space *vm)
1054 intel_gmch_remove();
1057 static int i915_gmch_probe(struct i915_ggtt *ggtt)
1059 struct drm_i915_private *i915 = ggtt->vm.i915;
1060 phys_addr_t gmadr_base;
1063 ret = intel_gmch_probe(i915->bridge_dev, i915->drm.pdev, NULL);
1065 drm_err(&i915->drm, "failed to set up gmch\n");
1069 intel_gtt_get(&ggtt->vm.total, &gmadr_base, &ggtt->mappable_end);
1072 (struct resource)DEFINE_RES_MEM(gmadr_base, ggtt->mappable_end);
1074 ggtt->vm.alloc_pt_dma = alloc_pt_dma;
1076 ggtt->do_idle_maps = needs_idle_maps(i915);
1077 ggtt->vm.insert_page = i915_ggtt_insert_page;
1078 ggtt->vm.insert_entries = i915_ggtt_insert_entries;
1079 ggtt->vm.clear_range = i915_ggtt_clear_range;
1080 ggtt->vm.cleanup = i915_gmch_remove;
1082 ggtt->invalidate = gmch_ggtt_invalidate;
1084 ggtt->vm.vma_ops.bind_vma = ggtt_bind_vma;
1085 ggtt->vm.vma_ops.unbind_vma = ggtt_unbind_vma;
1086 ggtt->vm.vma_ops.set_pages = ggtt_set_pages;
1087 ggtt->vm.vma_ops.clear_pages = clear_pages;
1089 if (unlikely(ggtt->do_idle_maps))
1090 drm_notice(&i915->drm,
1091 "Applying Ironlake quirks for intel_iommu\n");
1096 static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
1098 struct drm_i915_private *i915 = gt->i915;
1102 ggtt->vm.i915 = i915;
1103 ggtt->vm.dma = &i915->drm.pdev->dev;
1105 if (INTEL_GEN(i915) <= 5)
1106 ret = i915_gmch_probe(ggtt);
1107 else if (INTEL_GEN(i915) < 8)
1108 ret = gen6_gmch_probe(ggtt);
1110 ret = gen8_gmch_probe(ggtt);
1114 if ((ggtt->vm.total - 1) >> 32) {
1116 "We never expected a Global GTT with more than 32bits"
1117 " of address space! Found %lldM!\n",
1118 ggtt->vm.total >> 20);
1119 ggtt->vm.total = 1ULL << 32;
1120 ggtt->mappable_end =
1121 min_t(u64, ggtt->mappable_end, ggtt->vm.total);
1124 if (ggtt->mappable_end > ggtt->vm.total) {
1126 "mappable aperture extends past end of GGTT,"
1127 " aperture=%pa, total=%llx\n",
1128 &ggtt->mappable_end, ggtt->vm.total);
1129 ggtt->mappable_end = ggtt->vm.total;
1132 /* GMADR is the PCI mmio aperture into the global GTT. */
1133 drm_dbg(&i915->drm, "GGTT size = %lluM\n", ggtt->vm.total >> 20);
1134 drm_dbg(&i915->drm, "GMADR size = %lluM\n",
1135 (u64)ggtt->mappable_end >> 20);
1136 drm_dbg(&i915->drm, "DSM size = %lluM\n",
1137 (u64)resource_size(&intel_graphics_stolen_res) >> 20);
1143 * i915_ggtt_probe_hw - Probe GGTT hardware location
1144 * @i915: i915 device
1146 int i915_ggtt_probe_hw(struct drm_i915_private *i915)
1150 ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
1154 if (intel_vtd_active())
1155 drm_info(&i915->drm, "VT-d active for gfx access\n");
1160 int i915_ggtt_enable_hw(struct drm_i915_private *i915)
1162 if (INTEL_GEN(i915) < 6 && !intel_enable_gtt())
1168 void i915_ggtt_enable_guc(struct i915_ggtt *ggtt)
1170 GEM_BUG_ON(ggtt->invalidate != gen8_ggtt_invalidate);
1172 ggtt->invalidate = guc_ggtt_invalidate;
1174 ggtt->invalidate(ggtt);
1177 void i915_ggtt_disable_guc(struct i915_ggtt *ggtt)
1179 /* XXX Temporary pardon for error unload */
1180 if (ggtt->invalidate == gen8_ggtt_invalidate)
1183 /* We should only be called after i915_ggtt_enable_guc() */
1184 GEM_BUG_ON(ggtt->invalidate != guc_ggtt_invalidate);
1186 ggtt->invalidate = gen8_ggtt_invalidate;
1188 ggtt->invalidate(ggtt);
1191 void i915_ggtt_resume(struct i915_ggtt *ggtt)
1193 struct i915_vma *vma;
1197 intel_gt_check_and_clear_faults(ggtt->vm.gt);
1199 /* First fill our portion of the GTT with scratch pages */
1200 ggtt->vm.clear_range(&ggtt->vm, 0, ggtt->vm.total);
1202 /* Skip rewriting PTE on VMA unbind. */
1203 open = atomic_xchg(&ggtt->vm.open, 0);
1205 /* clflush objects bound into the GGTT and rebind them. */
1206 list_for_each_entry(vma, &ggtt->vm.bound_list, vm_link) {
1207 struct drm_i915_gem_object *obj = vma->obj;
1208 unsigned int was_bound =
1209 atomic_read(&vma->flags) & I915_VMA_BIND_MASK;
1211 GEM_BUG_ON(!was_bound);
1212 vma->ops->bind_vma(&ggtt->vm, NULL, vma,
1213 obj ? obj->cache_level : 0,
1215 if (obj) { /* only used during resume => exclusive access */
1216 flush |= fetch_and_zero(&obj->write_domain);
1217 obj->read_domains |= I915_GEM_DOMAIN_GTT;
1221 atomic_set(&ggtt->vm.open, open);
1222 ggtt->invalidate(ggtt);
1225 wbinvd_on_all_cpus();
1227 if (INTEL_GEN(ggtt->vm.i915) >= 8)
1228 setup_private_pat(ggtt->vm.gt->uncore);
1230 intel_ggtt_restore_fences(ggtt);
1233 static struct scatterlist *
1234 rotate_pages(struct drm_i915_gem_object *obj, unsigned int offset,
1235 unsigned int width, unsigned int height,
1236 unsigned int stride,
1237 struct sg_table *st, struct scatterlist *sg)
1239 unsigned int column, row;
1240 unsigned int src_idx;
1242 for (column = 0; column < width; column++) {
1243 src_idx = stride * (height - 1) + column + offset;
1244 for (row = 0; row < height; row++) {
1247 * We don't need the pages, but need to initialize
1248 * the entries so the sg list can be happily traversed.
1249 * The only thing we need are DMA addresses.
1251 sg_set_page(sg, NULL, I915_GTT_PAGE_SIZE, 0);
1252 sg_dma_address(sg) =
1253 i915_gem_object_get_dma_address(obj, src_idx);
1254 sg_dma_len(sg) = I915_GTT_PAGE_SIZE;
1263 static noinline struct sg_table *
1264 intel_rotate_pages(struct intel_rotation_info *rot_info,
1265 struct drm_i915_gem_object *obj)
1267 unsigned int size = intel_rotation_info_size(rot_info);
1268 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1269 struct sg_table *st;
1270 struct scatterlist *sg;
1274 /* Allocate target SG list. */
1275 st = kmalloc(sizeof(*st), GFP_KERNEL);
1279 ret = sg_alloc_table(st, size, GFP_KERNEL);
1286 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) {
1287 sg = rotate_pages(obj, rot_info->plane[i].offset,
1288 rot_info->plane[i].width, rot_info->plane[i].height,
1289 rot_info->plane[i].stride, st, sg);
1298 drm_dbg(&i915->drm, "Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
1299 obj->base.size, rot_info->plane[0].width,
1300 rot_info->plane[0].height, size);
1302 return ERR_PTR(ret);
1305 static struct scatterlist *
1306 remap_pages(struct drm_i915_gem_object *obj, unsigned int offset,
1307 unsigned int width, unsigned int height,
1308 unsigned int stride,
1309 struct sg_table *st, struct scatterlist *sg)
1313 for (row = 0; row < height; row++) {
1314 unsigned int left = width * I915_GTT_PAGE_SIZE;
1318 unsigned int length;
1321 * We don't need the pages, but need to initialize
1322 * the entries so the sg list can be happily traversed.
1323 * The only thing we need are DMA addresses.
1326 addr = i915_gem_object_get_dma_address_len(obj, offset, &length);
1328 length = min(left, length);
1332 sg_set_page(sg, NULL, length, 0);
1333 sg_dma_address(sg) = addr;
1334 sg_dma_len(sg) = length;
1337 offset += length / I915_GTT_PAGE_SIZE;
1341 offset += stride - width;
1347 static noinline struct sg_table *
1348 intel_remap_pages(struct intel_remapped_info *rem_info,
1349 struct drm_i915_gem_object *obj)
1351 unsigned int size = intel_remapped_info_size(rem_info);
1352 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1353 struct sg_table *st;
1354 struct scatterlist *sg;
1358 /* Allocate target SG list. */
1359 st = kmalloc(sizeof(*st), GFP_KERNEL);
1363 ret = sg_alloc_table(st, size, GFP_KERNEL);
1370 for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
1371 sg = remap_pages(obj, rem_info->plane[i].offset,
1372 rem_info->plane[i].width, rem_info->plane[i].height,
1373 rem_info->plane[i].stride, st, sg);
1384 drm_dbg(&i915->drm, "Failed to create remapped mapping for object size %zu! (%ux%u tiles, %u pages)\n",
1385 obj->base.size, rem_info->plane[0].width,
1386 rem_info->plane[0].height, size);
1388 return ERR_PTR(ret);
1391 static noinline struct sg_table *
1392 intel_partial_pages(const struct i915_ggtt_view *view,
1393 struct drm_i915_gem_object *obj)
1395 struct sg_table *st;
1396 struct scatterlist *sg, *iter;
1397 unsigned int count = view->partial.size;
1398 unsigned int offset;
1401 st = kmalloc(sizeof(*st), GFP_KERNEL);
1405 ret = sg_alloc_table(st, count, GFP_KERNEL);
1409 iter = i915_gem_object_get_sg(obj, view->partial.offset, &offset);
1417 len = min(iter->length - (offset << PAGE_SHIFT),
1418 count << PAGE_SHIFT);
1419 sg_set_page(sg, NULL, len, 0);
1420 sg_dma_address(sg) =
1421 sg_dma_address(iter) + (offset << PAGE_SHIFT);
1422 sg_dma_len(sg) = len;
1425 count -= len >> PAGE_SHIFT;
1428 i915_sg_trim(st); /* Drop any unused tail entries. */
1434 iter = __sg_next(iter);
1441 return ERR_PTR(ret);
1445 i915_get_ggtt_vma_pages(struct i915_vma *vma)
1450 * The vma->pages are only valid within the lifespan of the borrowed
1451 * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
1452 * must be the vma->pages. A simple rule is that vma->pages must only
1453 * be accessed when the obj->mm.pages are pinned.
1455 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma->obj));
1457 switch (vma->ggtt_view.type) {
1459 GEM_BUG_ON(vma->ggtt_view.type);
1461 case I915_GGTT_VIEW_NORMAL:
1462 vma->pages = vma->obj->mm.pages;
1465 case I915_GGTT_VIEW_ROTATED:
1467 intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
1470 case I915_GGTT_VIEW_REMAPPED:
1472 intel_remap_pages(&vma->ggtt_view.remapped, vma->obj);
1475 case I915_GGTT_VIEW_PARTIAL:
1476 vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
1481 if (IS_ERR(vma->pages)) {
1482 ret = PTR_ERR(vma->pages);
1484 drm_err(&vma->vm->i915->drm,
1485 "Failed to get pages for VMA view type %u (%d)!\n",
1486 vma->ggtt_view.type, ret);