2 * Copyright © 2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <drm/drm_print.h>
27 #include "gem/i915_gem_context.h"
31 #include "intel_breadcrumbs.h"
32 #include "intel_context.h"
33 #include "intel_engine.h"
34 #include "intel_engine_pm.h"
35 #include "intel_engine_user.h"
37 #include "intel_gt_requests.h"
38 #include "intel_gt_pm.h"
39 #include "intel_lrc.h"
40 #include "intel_reset.h"
41 #include "intel_ring.h"
43 /* Haswell does have the CXT_SIZE register however it does not appear to be
44 * valid. Now, docs explain in dwords what is in the context object. The full
45 * size is 70720 bytes, however, the power context and execlist context will
46 * never be saved (power context is stored elsewhere, and execlists don't work
47 * on HSW) - so the final size, including the extra state required for the
48 * Resource Streamer, is 66944 bytes, which rounds to 17 pages.
50 #define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
52 #define DEFAULT_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
53 #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
54 #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
55 #define GEN10_LR_CONTEXT_RENDER_SIZE (18 * PAGE_SIZE)
56 #define GEN11_LR_CONTEXT_RENDER_SIZE (14 * PAGE_SIZE)
58 #define GEN8_LR_CONTEXT_OTHER_SIZE ( 2 * PAGE_SIZE)
60 #define MAX_MMIO_BASES 3
65 /* mmio bases table *must* be sorted in reverse gen order */
66 struct engine_mmio_base {
69 } mmio_bases[MAX_MMIO_BASES];
72 static const struct engine_info intel_engines[] = {
75 .class = RENDER_CLASS,
78 { .gen = 1, .base = RENDER_RING_BASE }
83 .class = COPY_ENGINE_CLASS,
86 { .gen = 6, .base = BLT_RING_BASE }
91 .class = VIDEO_DECODE_CLASS,
94 { .gen = 11, .base = GEN11_BSD_RING_BASE },
95 { .gen = 6, .base = GEN6_BSD_RING_BASE },
96 { .gen = 4, .base = BSD_RING_BASE }
101 .class = VIDEO_DECODE_CLASS,
104 { .gen = 11, .base = GEN11_BSD2_RING_BASE },
105 { .gen = 8, .base = GEN8_BSD2_RING_BASE }
110 .class = VIDEO_DECODE_CLASS,
113 { .gen = 11, .base = GEN11_BSD3_RING_BASE }
118 .class = VIDEO_DECODE_CLASS,
121 { .gen = 11, .base = GEN11_BSD4_RING_BASE }
126 .class = VIDEO_ENHANCEMENT_CLASS,
129 { .gen = 11, .base = GEN11_VEBOX_RING_BASE },
130 { .gen = 7, .base = VEBOX_RING_BASE }
135 .class = VIDEO_ENHANCEMENT_CLASS,
138 { .gen = 11, .base = GEN11_VEBOX2_RING_BASE }
144 * intel_engine_context_size() - return the size of the context for an engine
146 * @class: engine class
148 * Each engine class may require a different amount of space for a context
151 * Return: size (in bytes) of an engine class specific context image
153 * Note: this size includes the HWSP, which is part of the context image
154 * in LRC mode, but does not include the "shared data page" used with
155 * GuC submission. The caller should account for this if using the GuC.
157 u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
159 struct intel_uncore *uncore = gt->uncore;
162 BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
166 switch (INTEL_GEN(gt->i915)) {
168 MISSING_CASE(INTEL_GEN(gt->i915));
169 return DEFAULT_LR_CONTEXT_RENDER_SIZE;
172 return GEN11_LR_CONTEXT_RENDER_SIZE;
174 return GEN10_LR_CONTEXT_RENDER_SIZE;
176 return GEN9_LR_CONTEXT_RENDER_SIZE;
178 return GEN8_LR_CONTEXT_RENDER_SIZE;
180 if (IS_HASWELL(gt->i915))
181 return HSW_CXT_TOTAL_SIZE;
183 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE);
184 return round_up(GEN7_CXT_TOTAL_SIZE(cxt_size) * 64,
187 cxt_size = intel_uncore_read(uncore, CXT_SIZE);
188 return round_up(GEN6_CXT_TOTAL_SIZE(cxt_size) * 64,
193 * There is a discrepancy here between the size reported
194 * by the register and the size of the context layout
195 * in the docs. Both are described as authorative!
197 * The discrepancy is on the order of a few cachelines,
198 * but the total is under one page (4k), which is our
199 * minimum allocation anyway so it should all come
202 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
203 drm_dbg(>->i915->drm,
204 "gen%d CXT_SIZE = %d bytes [0x%08x]\n",
205 INTEL_GEN(gt->i915), cxt_size * 64,
207 return round_up(cxt_size * 64, PAGE_SIZE);
210 /* For the special day when i810 gets merged. */
218 case VIDEO_DECODE_CLASS:
219 case VIDEO_ENHANCEMENT_CLASS:
220 case COPY_ENGINE_CLASS:
221 if (INTEL_GEN(gt->i915) < 8)
223 return GEN8_LR_CONTEXT_OTHER_SIZE;
227 static u32 __engine_mmio_base(struct drm_i915_private *i915,
228 const struct engine_mmio_base *bases)
232 for (i = 0; i < MAX_MMIO_BASES; i++)
233 if (INTEL_GEN(i915) >= bases[i].gen)
236 GEM_BUG_ON(i == MAX_MMIO_BASES);
237 GEM_BUG_ON(!bases[i].base);
239 return bases[i].base;
242 static void __sprint_engine_name(struct intel_engine_cs *engine)
245 * Before we know what the uABI name for this engine will be,
246 * we still would like to keep track of this engine in the debug logs.
247 * We throw in a ' here as a reminder that this isn't its final name.
249 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u",
250 intel_engine_class_repr(engine->class),
251 engine->instance) >= sizeof(engine->name));
254 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask)
257 * Though they added more rings on g4x/ilk, they did not add
258 * per-engine HWSTAM until gen6.
260 if (INTEL_GEN(engine->i915) < 6 && engine->class != RENDER_CLASS)
263 if (INTEL_GEN(engine->i915) >= 3)
264 ENGINE_WRITE(engine, RING_HWSTAM, mask);
266 ENGINE_WRITE16(engine, RING_HWSTAM, mask);
269 static void intel_engine_sanitize_mmio(struct intel_engine_cs *engine)
271 /* Mask off all writes into the unknown HWSP */
272 intel_engine_set_hwsp_writemask(engine, ~0u);
275 static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id)
277 const struct engine_info *info = &intel_engines[id];
278 struct drm_i915_private *i915 = gt->i915;
279 struct intel_engine_cs *engine;
281 BUILD_BUG_ON(MAX_ENGINE_CLASS >= BIT(GEN11_ENGINE_CLASS_WIDTH));
282 BUILD_BUG_ON(MAX_ENGINE_INSTANCE >= BIT(GEN11_ENGINE_INSTANCE_WIDTH));
284 if (GEM_DEBUG_WARN_ON(id >= ARRAY_SIZE(gt->engine)))
287 if (GEM_DEBUG_WARN_ON(info->class > MAX_ENGINE_CLASS))
290 if (GEM_DEBUG_WARN_ON(info->instance > MAX_ENGINE_INSTANCE))
293 if (GEM_DEBUG_WARN_ON(gt->engine_class[info->class][info->instance]))
296 engine = kzalloc(sizeof(*engine), GFP_KERNEL);
300 BUILD_BUG_ON(BITS_PER_TYPE(engine->mask) < I915_NUM_ENGINES);
303 engine->legacy_idx = INVALID_ENGINE;
304 engine->mask = BIT(id);
307 engine->uncore = gt->uncore;
308 engine->hw_id = engine->guc_id = info->hw_id;
309 engine->mmio_base = __engine_mmio_base(i915, info->mmio_bases);
311 engine->class = info->class;
312 engine->instance = info->instance;
313 __sprint_engine_name(engine);
315 engine->props.heartbeat_interval_ms =
316 CONFIG_DRM_I915_HEARTBEAT_INTERVAL;
317 engine->props.max_busywait_duration_ns =
318 CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT;
319 engine->props.preempt_timeout_ms =
320 CONFIG_DRM_I915_PREEMPT_TIMEOUT;
321 engine->props.stop_timeout_ms =
322 CONFIG_DRM_I915_STOP_TIMEOUT;
323 engine->props.timeslice_duration_ms =
324 CONFIG_DRM_I915_TIMESLICE_DURATION;
326 /* Override to uninterruptible for OpenCL workloads. */
327 if (INTEL_GEN(i915) == 12 && engine->class == RENDER_CLASS)
328 engine->props.preempt_timeout_ms = 0;
330 engine->defaults = engine->props; /* never to change again */
332 engine->context_size = intel_engine_context_size(gt, engine->class);
333 if (WARN_ON(engine->context_size > BIT(20)))
334 engine->context_size = 0;
335 if (engine->context_size)
336 DRIVER_CAPS(i915)->has_logical_contexts = true;
338 /* Nothing to do here, execute in order of dependencies */
339 engine->schedule = NULL;
341 ewma__engine_latency_init(&engine->latency);
342 seqlock_init(&engine->stats.lock);
344 ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier);
346 /* Scrub mmio state on takeover */
347 intel_engine_sanitize_mmio(engine);
349 gt->engine_class[info->class][info->instance] = engine;
350 gt->engine[id] = engine;
355 static void __setup_engine_capabilities(struct intel_engine_cs *engine)
357 struct drm_i915_private *i915 = engine->i915;
359 if (engine->class == VIDEO_DECODE_CLASS) {
361 * HEVC support is present on first engine instance
362 * before Gen11 and on all instances afterwards.
364 if (INTEL_GEN(i915) >= 11 ||
365 (INTEL_GEN(i915) >= 9 && engine->instance == 0))
366 engine->uabi_capabilities |=
367 I915_VIDEO_CLASS_CAPABILITY_HEVC;
370 * SFC block is present only on even logical engine
373 if ((INTEL_GEN(i915) >= 11 &&
374 (engine->gt->info.vdbox_sfc_access &
375 BIT(engine->instance))) ||
376 (INTEL_GEN(i915) >= 9 && engine->instance == 0))
377 engine->uabi_capabilities |=
378 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
379 } else if (engine->class == VIDEO_ENHANCEMENT_CLASS) {
380 if (INTEL_GEN(i915) >= 9)
381 engine->uabi_capabilities |=
382 I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;
386 static void intel_setup_engine_capabilities(struct intel_gt *gt)
388 struct intel_engine_cs *engine;
389 enum intel_engine_id id;
391 for_each_engine(engine, gt, id)
392 __setup_engine_capabilities(engine);
396 * intel_engines_release() - free the resources allocated for Command Streamers
397 * @gt: pointer to struct intel_gt
399 void intel_engines_release(struct intel_gt *gt)
401 struct intel_engine_cs *engine;
402 enum intel_engine_id id;
405 * Before we release the resources held by engine, we must be certain
406 * that the HW is no longer accessing them -- having the GPU scribble
407 * to or read from a page being used for something else causes no end
410 * The GPU should be reset by this point, but assume the worst just
411 * in case we aborted before completely initialising the engines.
413 GEM_BUG_ON(intel_gt_pm_is_awake(gt));
414 if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
415 __intel_gt_reset(gt, ALL_ENGINES);
417 /* Decouple the backend; but keep the layout for late GPU resets */
418 for_each_engine(engine, gt, id) {
419 if (!engine->release)
422 intel_wakeref_wait_for_idle(&engine->wakeref);
423 GEM_BUG_ON(intel_engine_pm_is_awake(engine));
425 engine->release(engine);
426 engine->release = NULL;
428 memset(&engine->reset, 0, sizeof(engine->reset));
432 void intel_engine_free_request_pool(struct intel_engine_cs *engine)
434 if (!engine->request_pool)
437 kmem_cache_free(i915_request_slab_cache(), engine->request_pool);
440 void intel_engines_free(struct intel_gt *gt)
442 struct intel_engine_cs *engine;
443 enum intel_engine_id id;
445 /* Free the requests! dma-resv keeps fences around for an eternity */
448 for_each_engine(engine, gt, id) {
449 intel_engine_free_request_pool(engine);
451 gt->engine[id] = NULL;
456 * Determine which engines are fused off in our particular hardware.
457 * Note that we have a catch-22 situation where we need to be able to access
458 * the blitter forcewake domain to read the engine fuses, but at the same time
459 * we need to know which engines are available on the system to know which
460 * forcewake domains are present. We solve this by intializing the forcewake
461 * domains based on the full engine mask in the platform capabilities before
462 * calling this function and pruning the domains for fused-off engines
465 static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
467 struct drm_i915_private *i915 = gt->i915;
468 struct intel_gt_info *info = >->info;
469 struct intel_uncore *uncore = gt->uncore;
470 unsigned int logical_vdbox = 0;
476 info->engine_mask = INTEL_INFO(i915)->platform_engine_mask;
478 if (INTEL_GEN(i915) < 11)
479 return info->engine_mask;
481 media_fuse = ~intel_uncore_read(uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);
483 vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;
484 vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>
485 GEN11_GT_VEBOX_DISABLE_SHIFT;
487 for (i = 0; i < I915_MAX_VCS; i++) {
488 if (!HAS_ENGINE(gt, _VCS(i))) {
489 vdbox_mask &= ~BIT(i);
493 if (!(BIT(i) & vdbox_mask)) {
494 info->engine_mask &= ~BIT(_VCS(i));
495 drm_dbg(&i915->drm, "vcs%u fused off\n", i);
500 * In Gen11, only even numbered logical VDBOXes are
501 * hooked up to an SFC (Scaler & Format Converter) unit.
502 * In TGL each VDBOX has access to an SFC.
504 if (INTEL_GEN(i915) >= 12 || logical_vdbox++ % 2 == 0)
505 gt->info.vdbox_sfc_access |= BIT(i);
507 drm_dbg(&i915->drm, "vdbox enable: %04x, instances: %04lx\n",
508 vdbox_mask, VDBOX_MASK(gt));
509 GEM_BUG_ON(vdbox_mask != VDBOX_MASK(gt));
511 for (i = 0; i < I915_MAX_VECS; i++) {
512 if (!HAS_ENGINE(gt, _VECS(i))) {
513 vebox_mask &= ~BIT(i);
517 if (!(BIT(i) & vebox_mask)) {
518 info->engine_mask &= ~BIT(_VECS(i));
519 drm_dbg(&i915->drm, "vecs%u fused off\n", i);
522 drm_dbg(&i915->drm, "vebox enable: %04x, instances: %04lx\n",
523 vebox_mask, VEBOX_MASK(gt));
524 GEM_BUG_ON(vebox_mask != VEBOX_MASK(gt));
526 return info->engine_mask;
530 * intel_engines_init_mmio() - allocate and prepare the Engine Command Streamers
531 * @gt: pointer to struct intel_gt
533 * Return: non-zero if the initialization failed.
535 int intel_engines_init_mmio(struct intel_gt *gt)
537 struct drm_i915_private *i915 = gt->i915;
538 const unsigned int engine_mask = init_engine_mask(gt);
539 unsigned int mask = 0;
543 drm_WARN_ON(&i915->drm, engine_mask == 0);
544 drm_WARN_ON(&i915->drm, engine_mask &
545 GENMASK(BITS_PER_TYPE(mask) - 1, I915_NUM_ENGINES));
547 if (i915_inject_probe_failure(i915))
550 for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
551 if (!HAS_ENGINE(gt, i))
554 err = intel_engine_setup(gt, i);
562 * Catch failures to update intel_engines table when the new engines
563 * are added to the driver by a warning and disabling the forgotten
566 if (drm_WARN_ON(&i915->drm, mask != engine_mask))
567 gt->info.engine_mask = mask;
569 gt->info.num_engines = hweight32(mask);
571 intel_gt_check_and_clear_faults(gt);
573 intel_setup_engine_capabilities(gt);
575 intel_uncore_prune_engine_fw_domains(gt->uncore, gt);
580 intel_engines_free(gt);
584 void intel_engine_init_execlists(struct intel_engine_cs *engine)
586 struct intel_engine_execlists * const execlists = &engine->execlists;
588 execlists->port_mask = 1;
589 GEM_BUG_ON(!is_power_of_2(execlists_num_ports(execlists)));
590 GEM_BUG_ON(execlists_num_ports(execlists) > EXECLIST_MAX_PORTS);
592 memset(execlists->pending, 0, sizeof(execlists->pending));
594 memset(execlists->inflight, 0, sizeof(execlists->inflight));
596 execlists->queue_priority_hint = INT_MIN;
597 execlists->queue = RB_ROOT_CACHED;
600 static void cleanup_status_page(struct intel_engine_cs *engine)
602 struct i915_vma *vma;
604 /* Prevent writes into HWSP after returning the page to the system */
605 intel_engine_set_hwsp_writemask(engine, ~0u);
607 vma = fetch_and_zero(&engine->status_page.vma);
611 if (!HWS_NEEDS_PHYSICAL(engine->i915))
614 i915_gem_object_unpin_map(vma->obj);
615 i915_gem_object_put(vma->obj);
618 static int pin_ggtt_status_page(struct intel_engine_cs *engine,
619 struct i915_vma *vma)
623 if (!HAS_LLC(engine->i915) && i915_ggtt_has_aperture(engine->gt->ggtt))
625 * On g33, we cannot place HWS above 256MiB, so
626 * restrict its pinning to the low mappable arena.
627 * Though this restriction is not documented for
628 * gen4, gen5, or byt, they also behave similarly
629 * and hang if the HWS is placed at the top of the
630 * GTT. To generalise, it appears that all !llc
631 * platforms have issues with us placing the HWS
632 * above the mappable region (even though we never
635 flags = PIN_MAPPABLE;
639 return i915_ggtt_pin(vma, NULL, 0, flags);
642 static int init_status_page(struct intel_engine_cs *engine)
644 struct drm_i915_gem_object *obj;
645 struct i915_vma *vma;
650 * Though the HWS register does support 36bit addresses, historically
651 * we have had hangs and corruption reported due to wild writes if
652 * the HWS is placed above 4G. We only allow objects to be allocated
653 * in GFP_DMA32 for i965, and no earlier physical address users had
654 * access to more than 4G.
656 obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
658 drm_err(&engine->i915->drm,
659 "Failed to allocate status page\n");
663 i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
665 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
671 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
673 ret = PTR_ERR(vaddr);
677 engine->status_page.addr = memset(vaddr, 0, PAGE_SIZE);
678 engine->status_page.vma = vma;
680 if (!HWS_NEEDS_PHYSICAL(engine->i915)) {
681 ret = pin_ggtt_status_page(engine, vma);
689 i915_gem_object_unpin_map(obj);
691 i915_gem_object_put(obj);
695 static int engine_setup_common(struct intel_engine_cs *engine)
699 init_llist_head(&engine->barrier_tasks);
701 err = init_status_page(engine);
705 engine->breadcrumbs = intel_breadcrumbs_create(engine);
706 if (!engine->breadcrumbs) {
711 err = intel_engine_init_cmd_parser(engine);
715 intel_engine_init_active(engine, ENGINE_PHYSICAL);
716 intel_engine_init_execlists(engine);
717 intel_engine_init__pm(engine);
718 intel_engine_init_retire(engine);
720 /* Use the whole device by default */
722 intel_sseu_from_device_info(&engine->gt->info.sseu);
724 intel_engine_init_workarounds(engine);
725 intel_engine_init_whitelist(engine);
726 intel_engine_init_ctx_wa(engine);
731 intel_breadcrumbs_free(engine->breadcrumbs);
733 cleanup_status_page(engine);
737 struct measure_breadcrumb {
738 struct i915_request rq;
739 struct intel_ring ring;
743 static int measure_breadcrumb_dw(struct intel_context *ce)
745 struct intel_engine_cs *engine = ce->engine;
746 struct measure_breadcrumb *frame;
749 GEM_BUG_ON(!engine->gt->scratch);
751 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
755 frame->rq.engine = engine;
756 frame->rq.context = ce;
757 rcu_assign_pointer(frame->rq.timeline, ce->timeline);
759 frame->ring.vaddr = frame->cs;
760 frame->ring.size = sizeof(frame->cs);
762 BITS_PER_TYPE(frame->ring.size) - ilog2(frame->ring.size);
763 frame->ring.effective_size = frame->ring.size;
764 intel_ring_update_space(&frame->ring);
765 frame->rq.ring = &frame->ring;
767 mutex_lock(&ce->timeline->mutex);
768 spin_lock_irq(&engine->active.lock);
770 dw = engine->emit_fini_breadcrumb(&frame->rq, frame->cs) - frame->cs;
772 spin_unlock_irq(&engine->active.lock);
773 mutex_unlock(&ce->timeline->mutex);
775 GEM_BUG_ON(dw & 1); /* RING_TAIL must be qword aligned */
782 intel_engine_init_active(struct intel_engine_cs *engine, unsigned int subclass)
784 INIT_LIST_HEAD(&engine->active.requests);
785 INIT_LIST_HEAD(&engine->active.hold);
787 spin_lock_init(&engine->active.lock);
788 lockdep_set_subclass(&engine->active.lock, subclass);
791 * Due to an interesting quirk in lockdep's internal debug tracking,
792 * after setting a subclass we must ensure the lock is used. Otherwise,
793 * nr_unused_locks is incremented once too often.
795 #ifdef CONFIG_DEBUG_LOCK_ALLOC
797 lock_map_acquire(&engine->active.lock.dep_map);
798 lock_map_release(&engine->active.lock.dep_map);
803 static struct intel_context *
804 create_pinned_context(struct intel_engine_cs *engine,
806 struct lock_class_key *key,
809 struct intel_context *ce;
812 ce = intel_context_create(engine);
816 __set_bit(CONTEXT_BARRIER_BIT, &ce->flags);
817 ce->timeline = page_pack_bits(NULL, hwsp);
819 err = intel_context_pin(ce); /* perma-pin so it is always available */
821 intel_context_put(ce);
826 * Give our perma-pinned kernel timelines a separate lockdep class,
827 * so that we can use them from within the normal user timelines
828 * should we need to inject GPU operations during their request
831 lockdep_set_class_and_name(&ce->timeline->mutex, key, name);
836 static struct intel_context *
837 create_kernel_context(struct intel_engine_cs *engine)
839 static struct lock_class_key kernel;
841 return create_pinned_context(engine, I915_GEM_HWS_SEQNO_ADDR,
842 &kernel, "kernel_context");
846 * intel_engines_init_common - initialize cengine state which might require hw access
847 * @engine: Engine to initialize.
849 * Initializes @engine@ structure members shared between legacy and execlists
850 * submission modes which do require hardware access.
852 * Typcally done at later stages of submission mode specific engine setup.
854 * Returns zero on success or an error code on failure.
856 static int engine_init_common(struct intel_engine_cs *engine)
858 struct intel_context *ce;
861 engine->set_default_submission(engine);
864 * We may need to do things with the shrinker which
865 * require us to immediately switch back to the default
866 * context. This can cause a problem as pinning the
867 * default context also requires GTT space which may not
868 * be available. To avoid this we always pin the default
871 ce = create_kernel_context(engine);
875 ret = measure_breadcrumb_dw(ce);
879 engine->emit_fini_breadcrumb_dw = ret;
880 engine->kernel_context = ce;
885 intel_context_put(ce);
889 int intel_engines_init(struct intel_gt *gt)
891 int (*setup)(struct intel_engine_cs *engine);
892 struct intel_engine_cs *engine;
893 enum intel_engine_id id;
896 if (HAS_EXECLISTS(gt->i915))
897 setup = intel_execlists_submission_setup;
899 setup = intel_ring_submission_setup;
901 for_each_engine(engine, gt, id) {
902 err = engine_setup_common(engine);
910 err = engine_init_common(engine);
914 intel_engine_add_user(engine);
921 * intel_engines_cleanup_common - cleans up the engine state created by
922 * the common initiailizers.
923 * @engine: Engine to cleanup.
925 * This cleans up everything created by the common helpers.
927 void intel_engine_cleanup_common(struct intel_engine_cs *engine)
929 GEM_BUG_ON(!list_empty(&engine->active.requests));
930 tasklet_kill(&engine->execlists.tasklet); /* flush the callback */
932 cleanup_status_page(engine);
933 intel_breadcrumbs_free(engine->breadcrumbs);
935 intel_engine_fini_retire(engine);
936 intel_engine_cleanup_cmd_parser(engine);
938 if (engine->default_state)
939 fput(engine->default_state);
941 if (engine->kernel_context) {
942 intel_context_unpin(engine->kernel_context);
943 intel_context_put(engine->kernel_context);
945 GEM_BUG_ON(!llist_empty(&engine->barrier_tasks));
947 intel_wa_list_free(&engine->ctx_wa_list);
948 intel_wa_list_free(&engine->wa_list);
949 intel_wa_list_free(&engine->whitelist);
953 * intel_engine_resume - re-initializes the HW state of the engine
954 * @engine: Engine to resume.
956 * Returns zero on success or an error code on failure.
958 int intel_engine_resume(struct intel_engine_cs *engine)
960 intel_engine_apply_workarounds(engine);
961 intel_engine_apply_whitelist(engine);
963 return engine->resume(engine);
966 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
968 struct drm_i915_private *i915 = engine->i915;
972 if (INTEL_GEN(i915) >= 8)
973 acthd = ENGINE_READ64(engine, RING_ACTHD, RING_ACTHD_UDW);
974 else if (INTEL_GEN(i915) >= 4)
975 acthd = ENGINE_READ(engine, RING_ACTHD);
977 acthd = ENGINE_READ(engine, ACTHD);
982 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
986 if (INTEL_GEN(engine->i915) >= 8)
987 bbaddr = ENGINE_READ64(engine, RING_BBADDR, RING_BBADDR_UDW);
989 bbaddr = ENGINE_READ(engine, RING_BBADDR);
994 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
996 if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
1000 * If we are doing a normal GPU reset, we can take our time and allow
1001 * the engine to quiesce. We've stopped submission to the engine, and
1002 * if we wait long enough an innocent context should complete and
1003 * leave the engine idle. So they should not be caught unaware by
1004 * the forthcoming GPU reset (which usually follows the stop_cs)!
1006 return READ_ONCE(engine->props.stop_timeout_ms);
1009 int intel_engine_stop_cs(struct intel_engine_cs *engine)
1011 struct intel_uncore *uncore = engine->uncore;
1012 const u32 base = engine->mmio_base;
1013 const i915_reg_t mode = RING_MI_MODE(base);
1016 if (INTEL_GEN(engine->i915) < 3)
1019 ENGINE_TRACE(engine, "\n");
1021 intel_uncore_write_fw(uncore, mode, _MASKED_BIT_ENABLE(STOP_RING));
1024 if (__intel_wait_for_register_fw(uncore,
1025 mode, MODE_IDLE, MODE_IDLE,
1026 1000, stop_timeout(engine),
1028 ENGINE_TRACE(engine, "timed out on STOP_RING -> IDLE\n");
1032 /* A final mmio read to let GPU writes be hopefully flushed to memory */
1033 intel_uncore_posting_read_fw(uncore, mode);
1038 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine)
1040 ENGINE_TRACE(engine, "\n");
1042 ENGINE_WRITE_FW(engine, RING_MI_MODE, _MASKED_BIT_DISABLE(STOP_RING));
1045 const char *i915_cache_level_str(struct drm_i915_private *i915, int type)
1048 case I915_CACHE_NONE: return " uncached";
1049 case I915_CACHE_LLC: return HAS_LLC(i915) ? " LLC" : " snooped";
1050 case I915_CACHE_L3_LLC: return " L3+LLC";
1051 case I915_CACHE_WT: return " WT";
1057 read_subslice_reg(const struct intel_engine_cs *engine,
1058 int slice, int subslice, i915_reg_t reg)
1060 struct drm_i915_private *i915 = engine->i915;
1061 struct intel_uncore *uncore = engine->uncore;
1062 u32 mcr_mask, mcr_ss, mcr, old_mcr, val;
1063 enum forcewake_domains fw_domains;
1065 if (INTEL_GEN(i915) >= 11) {
1066 mcr_mask = GEN11_MCR_SLICE_MASK | GEN11_MCR_SUBSLICE_MASK;
1067 mcr_ss = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice);
1069 mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
1070 mcr_ss = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice);
1073 fw_domains = intel_uncore_forcewake_for_reg(uncore, reg,
1075 fw_domains |= intel_uncore_forcewake_for_reg(uncore,
1077 FW_REG_READ | FW_REG_WRITE);
1079 spin_lock_irq(&uncore->lock);
1080 intel_uncore_forcewake_get__locked(uncore, fw_domains);
1082 old_mcr = mcr = intel_uncore_read_fw(uncore, GEN8_MCR_SELECTOR);
1086 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1088 val = intel_uncore_read_fw(uncore, reg);
1091 mcr |= old_mcr & mcr_mask;
1093 intel_uncore_write_fw(uncore, GEN8_MCR_SELECTOR, mcr);
1095 intel_uncore_forcewake_put__locked(uncore, fw_domains);
1096 spin_unlock_irq(&uncore->lock);
1101 /* NB: please notice the memset */
1102 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
1103 struct intel_instdone *instdone)
1105 struct drm_i915_private *i915 = engine->i915;
1106 const struct sseu_dev_info *sseu = &engine->gt->info.sseu;
1107 struct intel_uncore *uncore = engine->uncore;
1108 u32 mmio_base = engine->mmio_base;
1112 memset(instdone, 0, sizeof(*instdone));
1114 switch (INTEL_GEN(i915)) {
1116 instdone->instdone =
1117 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1119 if (engine->id != RCS0)
1122 instdone->slice_common =
1123 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1124 if (INTEL_GEN(i915) >= 12) {
1125 instdone->slice_common_extra[0] =
1126 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA);
1127 instdone->slice_common_extra[1] =
1128 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA2);
1130 for_each_instdone_slice_subslice(i915, sseu, slice, subslice) {
1131 instdone->sampler[slice][subslice] =
1132 read_subslice_reg(engine, slice, subslice,
1133 GEN7_SAMPLER_INSTDONE);
1134 instdone->row[slice][subslice] =
1135 read_subslice_reg(engine, slice, subslice,
1140 instdone->instdone =
1141 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1143 if (engine->id != RCS0)
1146 instdone->slice_common =
1147 intel_uncore_read(uncore, GEN7_SC_INSTDONE);
1148 instdone->sampler[0][0] =
1149 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE);
1150 instdone->row[0][0] =
1151 intel_uncore_read(uncore, GEN7_ROW_INSTDONE);
1157 instdone->instdone =
1158 intel_uncore_read(uncore, RING_INSTDONE(mmio_base));
1159 if (engine->id == RCS0)
1160 /* HACK: Using the wrong struct member */
1161 instdone->slice_common =
1162 intel_uncore_read(uncore, GEN4_INSTDONE1);
1166 instdone->instdone = intel_uncore_read(uncore, GEN2_INSTDONE);
1171 static bool ring_is_idle(struct intel_engine_cs *engine)
1175 if (I915_SELFTEST_ONLY(!engine->mmio_base))
1178 if (!intel_engine_pm_get_if_awake(engine))
1181 /* First check that no commands are left in the ring */
1182 if ((ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR) !=
1183 (ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR))
1186 /* No bit for gen2, so assume the CS parser is idle */
1187 if (INTEL_GEN(engine->i915) > 2 &&
1188 !(ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE))
1191 intel_engine_pm_put(engine);
1196 void intel_engine_flush_submission(struct intel_engine_cs *engine)
1198 struct tasklet_struct *t = &engine->execlists.tasklet;
1203 /* Synchronise and wait for the tasklet on another CPU */
1206 /* Having cancelled the tasklet, ensure that is run */
1208 if (tasklet_trylock(t)) {
1209 /* Must wait for any GPU reset in progress. */
1210 if (__tasklet_is_enabled(t))
1218 * intel_engine_is_idle() - Report if the engine has finished process all work
1219 * @engine: the intel_engine_cs
1221 * Return true if there are no requests pending, nothing left to be submitted
1222 * to hardware, and that the engine is idle.
1224 bool intel_engine_is_idle(struct intel_engine_cs *engine)
1226 /* More white lies, if wedged, hw state is inconsistent */
1227 if (intel_gt_is_wedged(engine->gt))
1230 if (!intel_engine_pm_is_awake(engine))
1233 /* Waiting to drain ELSP? */
1234 if (execlists_active(&engine->execlists)) {
1235 synchronize_hardirq(engine->i915->drm.pdev->irq);
1237 intel_engine_flush_submission(engine);
1239 if (execlists_active(&engine->execlists))
1243 /* ELSP is empty, but there are ready requests? E.g. after reset */
1244 if (!RB_EMPTY_ROOT(&engine->execlists.queue.rb_root))
1248 return ring_is_idle(engine);
1251 bool intel_engines_are_idle(struct intel_gt *gt)
1253 struct intel_engine_cs *engine;
1254 enum intel_engine_id id;
1257 * If the driver is wedged, HW state may be very inconsistent and
1258 * report that it is still busy, even though we have stopped using it.
1260 if (intel_gt_is_wedged(gt))
1263 /* Already parked (and passed an idleness test); must still be idle */
1264 if (!READ_ONCE(gt->awake))
1267 for_each_engine(engine, gt, id) {
1268 if (!intel_engine_is_idle(engine))
1275 void intel_engines_reset_default_submission(struct intel_gt *gt)
1277 struct intel_engine_cs *engine;
1278 enum intel_engine_id id;
1280 for_each_engine(engine, gt, id)
1281 engine->set_default_submission(engine);
1284 bool intel_engine_can_store_dword(struct intel_engine_cs *engine)
1286 switch (INTEL_GEN(engine->i915)) {
1288 return false; /* uses physical not virtual addresses */
1290 /* maybe only uses physical not virtual addresses */
1291 return !(IS_I915G(engine->i915) || IS_I915GM(engine->i915));
1293 return !IS_I965G(engine->i915); /* who knows! */
1295 return engine->class != VIDEO_DECODE_CLASS; /* b0rked */
1301 static int print_sched_attr(const struct i915_sched_attr *attr,
1302 char *buf, int x, int len)
1304 if (attr->priority == I915_PRIORITY_INVALID)
1307 x += snprintf(buf + x, len - x,
1308 " prio=%d", attr->priority);
1313 static void print_request(struct drm_printer *m,
1314 struct i915_request *rq,
1317 const char *name = rq->fence.ops->get_timeline_name(&rq->fence);
1321 x = print_sched_attr(&rq->sched.attr, buf, x, sizeof(buf));
1323 drm_printf(m, "%s %llx:%llx%s%s %s @ %dms: %s\n",
1325 rq->fence.context, rq->fence.seqno,
1326 i915_request_completed(rq) ? "!" :
1327 i915_request_started(rq) ? "*" :
1329 test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
1330 &rq->fence.flags) ? "+" :
1331 test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
1332 &rq->fence.flags) ? "-" :
1335 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
1339 static struct intel_timeline *get_timeline(struct i915_request *rq)
1341 struct intel_timeline *tl;
1344 * Even though we are holding the engine->active.lock here, there
1345 * is no control over the submission queue per-se and we are
1346 * inspecting the active state at a random point in time, with an
1347 * unknown queue. Play safe and make sure the timeline remains valid.
1348 * (Only being used for pretty printing, one extra kref shouldn't
1349 * cause a camel stampede!)
1352 tl = rcu_dereference(rq->timeline);
1353 if (!kref_get_unless_zero(&tl->kref))
1360 static int print_ring(char *buf, int sz, struct i915_request *rq)
1364 if (!i915_request_signaled(rq)) {
1365 struct intel_timeline *tl = get_timeline(rq);
1367 len = scnprintf(buf, sz,
1368 "ring:{start:%08x, hwsp:%08x, seqno:%08x, runtime:%llums}, ",
1369 i915_ggtt_offset(rq->ring->vma),
1370 tl ? tl->hwsp_offset : 0,
1372 DIV_ROUND_CLOSEST_ULL(intel_context_get_total_runtime_ns(rq->context),
1376 intel_timeline_put(tl);
1382 static void hexdump(struct drm_printer *m, const void *buf, size_t len)
1384 const size_t rowsize = 8 * sizeof(u32);
1385 const void *prev = NULL;
1389 for (pos = 0; pos < len; pos += rowsize) {
1392 if (prev && !memcmp(prev, buf + pos, rowsize)) {
1394 drm_printf(m, "*\n");
1400 WARN_ON_ONCE(hex_dump_to_buffer(buf + pos, len - pos,
1401 rowsize, sizeof(u32),
1403 false) >= sizeof(line));
1404 drm_printf(m, "[%04zx] %s\n", pos, line);
1411 static const char *repr_timer(const struct timer_list *t)
1413 if (!READ_ONCE(t->expires))
1416 if (timer_pending(t))
1422 static void intel_engine_print_registers(struct intel_engine_cs *engine,
1423 struct drm_printer *m)
1425 struct drm_i915_private *dev_priv = engine->i915;
1426 struct intel_engine_execlists * const execlists = &engine->execlists;
1429 if (engine->id == RENDER_CLASS && IS_GEN_RANGE(dev_priv, 4, 7))
1430 drm_printf(m, "\tCCID: 0x%08x\n", ENGINE_READ(engine, CCID));
1431 if (HAS_EXECLISTS(dev_priv)) {
1432 drm_printf(m, "\tEL_STAT_HI: 0x%08x\n",
1433 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI));
1434 drm_printf(m, "\tEL_STAT_LO: 0x%08x\n",
1435 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO));
1437 drm_printf(m, "\tRING_START: 0x%08x\n",
1438 ENGINE_READ(engine, RING_START));
1439 drm_printf(m, "\tRING_HEAD: 0x%08x\n",
1440 ENGINE_READ(engine, RING_HEAD) & HEAD_ADDR);
1441 drm_printf(m, "\tRING_TAIL: 0x%08x\n",
1442 ENGINE_READ(engine, RING_TAIL) & TAIL_ADDR);
1443 drm_printf(m, "\tRING_CTL: 0x%08x%s\n",
1444 ENGINE_READ(engine, RING_CTL),
1445 ENGINE_READ(engine, RING_CTL) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? " [waiting]" : "");
1446 if (INTEL_GEN(engine->i915) > 2) {
1447 drm_printf(m, "\tRING_MODE: 0x%08x%s\n",
1448 ENGINE_READ(engine, RING_MI_MODE),
1449 ENGINE_READ(engine, RING_MI_MODE) & (MODE_IDLE) ? " [idle]" : "");
1452 if (INTEL_GEN(dev_priv) >= 6) {
1453 drm_printf(m, "\tRING_IMR: 0x%08x\n",
1454 ENGINE_READ(engine, RING_IMR));
1455 drm_printf(m, "\tRING_ESR: 0x%08x\n",
1456 ENGINE_READ(engine, RING_ESR));
1457 drm_printf(m, "\tRING_EMR: 0x%08x\n",
1458 ENGINE_READ(engine, RING_EMR));
1459 drm_printf(m, "\tRING_EIR: 0x%08x\n",
1460 ENGINE_READ(engine, RING_EIR));
1463 addr = intel_engine_get_active_head(engine);
1464 drm_printf(m, "\tACTHD: 0x%08x_%08x\n",
1465 upper_32_bits(addr), lower_32_bits(addr));
1466 addr = intel_engine_get_last_batch_head(engine);
1467 drm_printf(m, "\tBBADDR: 0x%08x_%08x\n",
1468 upper_32_bits(addr), lower_32_bits(addr));
1469 if (INTEL_GEN(dev_priv) >= 8)
1470 addr = ENGINE_READ64(engine, RING_DMA_FADD, RING_DMA_FADD_UDW);
1471 else if (INTEL_GEN(dev_priv) >= 4)
1472 addr = ENGINE_READ(engine, RING_DMA_FADD);
1474 addr = ENGINE_READ(engine, DMA_FADD_I8XX);
1475 drm_printf(m, "\tDMA_FADDR: 0x%08x_%08x\n",
1476 upper_32_bits(addr), lower_32_bits(addr));
1477 if (INTEL_GEN(dev_priv) >= 4) {
1478 drm_printf(m, "\tIPEIR: 0x%08x\n",
1479 ENGINE_READ(engine, RING_IPEIR));
1480 drm_printf(m, "\tIPEHR: 0x%08x\n",
1481 ENGINE_READ(engine, RING_IPEHR));
1483 drm_printf(m, "\tIPEIR: 0x%08x\n", ENGINE_READ(engine, IPEIR));
1484 drm_printf(m, "\tIPEHR: 0x%08x\n", ENGINE_READ(engine, IPEHR));
1487 if (HAS_EXECLISTS(dev_priv)) {
1488 struct i915_request * const *port, *rq;
1490 &engine->status_page.addr[I915_HWS_CSB_BUF0_INDEX];
1491 const u8 num_entries = execlists->csb_size;
1495 drm_printf(m, "\tExeclist tasklet queued? %s (%s), preempt? %s, timeslice? %s\n",
1496 yesno(test_bit(TASKLET_STATE_SCHED,
1497 &engine->execlists.tasklet.state)),
1498 enableddisabled(!atomic_read(&engine->execlists.tasklet.count)),
1499 repr_timer(&engine->execlists.preempt),
1500 repr_timer(&engine->execlists.timer));
1502 read = execlists->csb_head;
1503 write = READ_ONCE(*execlists->csb_write);
1505 drm_printf(m, "\tExeclist status: 0x%08x %08x; CSB read:%d, write:%d, entries:%d\n",
1506 ENGINE_READ(engine, RING_EXECLIST_STATUS_LO),
1507 ENGINE_READ(engine, RING_EXECLIST_STATUS_HI),
1508 read, write, num_entries);
1510 if (read >= num_entries)
1512 if (write >= num_entries)
1515 write += num_entries;
1516 while (read < write) {
1517 idx = ++read % num_entries;
1518 drm_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
1519 idx, hws[idx * 2], hws[idx * 2 + 1]);
1522 execlists_active_lock_bh(execlists);
1524 for (port = execlists->active; (rq = *port); port++) {
1528 len = scnprintf(hdr, sizeof(hdr),
1529 "\t\tActive[%d]: ccid:%08x%s%s, ",
1530 (int)(port - execlists->active),
1531 rq->context->lrc.ccid,
1532 intel_context_is_closed(rq->context) ? "!" : "",
1533 intel_context_is_banned(rq->context) ? "*" : "");
1534 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1535 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1536 print_request(m, rq, hdr);
1538 for (port = execlists->pending; (rq = *port); port++) {
1542 len = scnprintf(hdr, sizeof(hdr),
1543 "\t\tPending[%d]: ccid:%08x%s%s, ",
1544 (int)(port - execlists->pending),
1545 rq->context->lrc.ccid,
1546 intel_context_is_closed(rq->context) ? "!" : "",
1547 intel_context_is_banned(rq->context) ? "*" : "");
1548 len += print_ring(hdr + len, sizeof(hdr) - len, rq);
1549 scnprintf(hdr + len, sizeof(hdr) - len, "rq: ");
1550 print_request(m, rq, hdr);
1553 execlists_active_unlock_bh(execlists);
1554 } else if (INTEL_GEN(dev_priv) > 6) {
1555 drm_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
1556 ENGINE_READ(engine, RING_PP_DIR_BASE));
1557 drm_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
1558 ENGINE_READ(engine, RING_PP_DIR_BASE_READ));
1559 drm_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
1560 ENGINE_READ(engine, RING_PP_DIR_DCLV));
1564 static void print_request_ring(struct drm_printer *m, struct i915_request *rq)
1570 "[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]:\n",
1571 rq->head, rq->postfix, rq->tail,
1572 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
1573 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
1575 size = rq->tail - rq->head;
1576 if (rq->tail < rq->head)
1577 size += rq->ring->size;
1579 ring = kmalloc(size, GFP_ATOMIC);
1581 const void *vaddr = rq->ring->vaddr;
1582 unsigned int head = rq->head;
1583 unsigned int len = 0;
1585 if (rq->tail < head) {
1586 len = rq->ring->size - head;
1587 memcpy(ring, vaddr + head, len);
1590 memcpy(ring + len, vaddr + head, size - len);
1592 hexdump(m, ring, size);
1597 static unsigned long list_count(struct list_head *list)
1599 struct list_head *pos;
1600 unsigned long count = 0;
1602 list_for_each(pos, list)
1608 void intel_engine_dump(struct intel_engine_cs *engine,
1609 struct drm_printer *m,
1610 const char *header, ...)
1612 struct i915_gpu_error * const error = &engine->i915->gpu_error;
1613 struct i915_request *rq;
1614 intel_wakeref_t wakeref;
1615 unsigned long flags;
1621 va_start(ap, header);
1622 drm_vprintf(m, header, &ap);
1626 if (intel_gt_is_wedged(engine->gt))
1627 drm_printf(m, "*** WEDGED ***\n");
1629 drm_printf(m, "\tAwake? %d\n", atomic_read(&engine->wakeref.count));
1630 drm_printf(m, "\tBarriers?: %s\n",
1631 yesno(!llist_empty(&engine->barrier_tasks)));
1632 drm_printf(m, "\tLatency: %luus\n",
1633 ewma__engine_latency_read(&engine->latency));
1634 if (intel_engine_supports_stats(engine))
1635 drm_printf(m, "\tRuntime: %llums\n",
1636 ktime_to_ms(intel_engine_get_busy_time(engine,
1638 drm_printf(m, "\tForcewake: %x domains, %d active\n",
1639 engine->fw_domain, atomic_read(&engine->fw_active));
1642 rq = READ_ONCE(engine->heartbeat.systole);
1644 drm_printf(m, "\tHeartbeat: %d ms ago\n",
1645 jiffies_to_msecs(jiffies - rq->emitted_jiffies));
1647 drm_printf(m, "\tReset count: %d (global %d)\n",
1648 i915_reset_engine_count(error, engine),
1649 i915_reset_count(error));
1651 drm_printf(m, "\tRequests:\n");
1653 spin_lock_irqsave(&engine->active.lock, flags);
1654 rq = intel_engine_find_active_request(engine);
1656 struct intel_timeline *tl = get_timeline(rq);
1658 print_request(m, rq, "\t\tactive ");
1660 drm_printf(m, "\t\tring->start: 0x%08x\n",
1661 i915_ggtt_offset(rq->ring->vma));
1662 drm_printf(m, "\t\tring->head: 0x%08x\n",
1664 drm_printf(m, "\t\tring->tail: 0x%08x\n",
1666 drm_printf(m, "\t\tring->emit: 0x%08x\n",
1668 drm_printf(m, "\t\tring->space: 0x%08x\n",
1672 drm_printf(m, "\t\tring->hwsp: 0x%08x\n",
1674 intel_timeline_put(tl);
1677 print_request_ring(m, rq);
1679 if (rq->context->lrc_reg_state) {
1680 drm_printf(m, "Logical Ring Context:\n");
1681 hexdump(m, rq->context->lrc_reg_state, PAGE_SIZE);
1684 drm_printf(m, "\tOn hold?: %lu\n", list_count(&engine->active.hold));
1685 spin_unlock_irqrestore(&engine->active.lock, flags);
1687 drm_printf(m, "\tMMIO base: 0x%08x\n", engine->mmio_base);
1688 wakeref = intel_runtime_pm_get_if_in_use(engine->uncore->rpm);
1690 intel_engine_print_registers(engine, m);
1691 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
1693 drm_printf(m, "\tDevice is asleep; skipping register dump\n");
1696 intel_execlists_show_requests(engine, m, print_request, 8);
1698 drm_printf(m, "HWSP:\n");
1699 hexdump(m, engine->status_page.addr, PAGE_SIZE);
1701 drm_printf(m, "Idle? %s\n", yesno(intel_engine_is_idle(engine)));
1703 intel_engine_print_breadcrumbs(engine, m);
1706 static ktime_t __intel_engine_get_busy_time(struct intel_engine_cs *engine,
1709 ktime_t total = engine->stats.total;
1712 * If the engine is executing something at the moment
1713 * add it to the total.
1716 if (atomic_read(&engine->stats.active))
1717 total = ktime_add(total, ktime_sub(*now, engine->stats.start));
1723 * intel_engine_get_busy_time() - Return current accumulated engine busyness
1724 * @engine: engine to report on
1725 * @now: monotonic timestamp of sampling
1727 * Returns accumulated time @engine was busy since engine stats were enabled.
1729 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine, ktime_t *now)
1735 seq = read_seqbegin(&engine->stats.lock);
1736 total = __intel_engine_get_busy_time(engine, now);
1737 } while (read_seqretry(&engine->stats.lock, seq));
1742 static bool match_ring(struct i915_request *rq)
1744 u32 ring = ENGINE_READ(rq->engine, RING_START);
1746 return ring == i915_ggtt_offset(rq->ring->vma);
1749 struct i915_request *
1750 intel_engine_find_active_request(struct intel_engine_cs *engine)
1752 struct i915_request *request, *active = NULL;
1755 * We are called by the error capture, reset and to dump engine
1756 * state at random points in time. In particular, note that neither is
1757 * crucially ordered with an interrupt. After a hang, the GPU is dead
1758 * and we assume that no more writes can happen (we waited long enough
1759 * for all writes that were in transaction to be flushed) - adding an
1760 * extra delay for a recent interrupt is pointless. Hence, we do
1761 * not need an engine->irq_seqno_barrier() before the seqno reads.
1762 * At all other times, we must assume the GPU is still running, but
1763 * we only care about the snapshot of this moment.
1765 lockdep_assert_held(&engine->active.lock);
1768 request = execlists_active(&engine->execlists);
1770 struct intel_timeline *tl = request->context->timeline;
1772 list_for_each_entry_from_reverse(request, &tl->requests, link) {
1773 if (i915_request_completed(request))
1783 list_for_each_entry(request, &engine->active.requests, sched.link) {
1784 if (i915_request_completed(request))
1787 if (!i915_request_started(request))
1790 /* More than one preemptible request may match! */
1791 if (!match_ring(request))
1801 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1802 #include "mock_engine.c"
1803 #include "selftest_engine.c"
1804 #include "selftest_engine_cs.c"