drivers/gpu/drm/i2c/tda998x_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Texas Instruments
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  */
   6
   7 #include <linux/component.h>
   8 #include <linux/gpio/consumer.h>
   9 #include <linux/hdmi.h>
  10 #include <linux/module.h>
  11 #include <linux/platform_data/tda9950.h>
  12 #include <linux/irq.h>
  13 #include <sound/asoundef.h>
  14 #include <sound/hdmi-codec.h>
  15
  16 #include <drm/drm_atomic_helper.h>
  17 #include <drm/drm_bridge.h>
  18 #include <drm/drm_edid.h>
  19 #include <drm/drm_of.h>
  20 #include <drm/drm_print.h>
  21 #include <drm/drm_probe_helper.h>
  22 #include <drm/drm_simple_kms_helper.h>
  23 #include <drm/i2c/tda998x.h>
  24
  25 #include <media/cec-notifier.h>
  26
  27 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
  28
  29 enum {
  30         AUDIO_ROUTE_I2S,
  31         AUDIO_ROUTE_SPDIF,
  32         AUDIO_ROUTE_NUM
  33 };
  34
  35 struct tda998x_audio_route {
  36         u8 ena_aclk;
  37         u8 mux_ap;
  38         u8 aip_clksel;
  39 };
  40
  41 struct tda998x_audio_settings {
  42         const struct tda998x_audio_route *route;
  43         struct hdmi_audio_infoframe cea;
  44         unsigned int sample_rate;
  45         u8 status[5];
  46         u8 ena_ap;
  47         u8 i2s_format;
  48         u8 cts_n;
  49 };
  50
  51 struct tda998x_priv {
  52         struct i2c_client *cec;
  53         struct i2c_client *hdmi;
  54         struct mutex mutex;
  55         u16 rev;
  56         u8 cec_addr;
  57         u8 current_page;
  58         bool is_on;
  59         bool supports_infoframes;
  60         bool sink_has_audio;
  61         enum hdmi_quantization_range rgb_quant_range;
  62         u8 vip_cntrl_0;
  63         u8 vip_cntrl_1;
  64         u8 vip_cntrl_2;
  65         unsigned long tmds_clock;
  66         struct tda998x_audio_settings audio;
  67
  68         struct platform_device *audio_pdev;
  69         struct mutex audio_mutex;
  70
  71         struct mutex edid_mutex;
  72         wait_queue_head_t wq_edid;
  73         volatile int wq_edid_wait;
  74
  75         struct work_struct detect_work;
  76         struct timer_list edid_delay_timer;
  77         wait_queue_head_t edid_delay_waitq;
  78         bool edid_delay_active;
  79
  80         struct drm_encoder encoder;
  81         struct drm_bridge bridge;
  82         struct drm_connector connector;
  83
  84         u8 audio_port_enable[AUDIO_ROUTE_NUM];
  85         struct tda9950_glue cec_glue;
  86         struct gpio_desc *calib;
  87         struct cec_notifier *cec_notify;
  88 };
  89
  90 #define conn_to_tda998x_priv(x) \
  91         container_of(x, struct tda998x_priv, connector)
  92 #define enc_to_tda998x_priv(x) \
  93         container_of(x, struct tda998x_priv, encoder)
  94 #define bridge_to_tda998x_priv(x) \
  95         container_of(x, struct tda998x_priv, bridge)
  96
  97 /* The TDA9988 series of devices use a paged register scheme.. to simplify
  98  * things we encode the page # in upper bits of the register #.  To read/
  99  * write a given register, we need to make sure CURPAGE register is set
 100  * appropriately.  Which implies reads/writes are not atomic.  Fun!
 101  */
 102
 103 #define REG(page, addr) (((page) << 8) | (addr))
 104 #define REG2ADDR(reg)   ((reg) & 0xff)
 105 #define REG2PAGE(reg)   (((reg) >> 8) & 0xff)
 106
 107 #define REG_CURPAGE               0xff                /* write */
 108
 109
 110 /* Page 00h: General Control */
 111 #define REG_VERSION_LSB           REG(0x00, 0x00)     /* read */
 112 #define REG_MAIN_CNTRL0           REG(0x00, 0x01)     /* read/write */
 113 # define MAIN_CNTRL0_SR           (1 << 0)
 114 # define MAIN_CNTRL0_DECS         (1 << 1)
 115 # define MAIN_CNTRL0_DEHS         (1 << 2)
 116 # define MAIN_CNTRL0_CECS         (1 << 3)
 117 # define MAIN_CNTRL0_CEHS         (1 << 4)
 118 # define MAIN_CNTRL0_SCALER       (1 << 7)
 119 #define REG_VERSION_MSB           REG(0x00, 0x02)     /* read */
 120 #define REG_SOFTRESET             REG(0x00, 0x0a)     /* write */
 121 # define SOFTRESET_AUDIO          (1 << 0)
 122 # define SOFTRESET_I2C_MASTER     (1 << 1)
 123 #define REG_DDC_DISABLE           REG(0x00, 0x0b)     /* read/write */
 124 #define REG_CCLK_ON               REG(0x00, 0x0c)     /* read/write */
 125 #define REG_I2C_MASTER            REG(0x00, 0x0d)     /* read/write */
 126 # define I2C_MASTER_DIS_MM        (1 << 0)
 127 # define I2C_MASTER_DIS_FILT      (1 << 1)
 128 # define I2C_MASTER_APP_STRT_LAT  (1 << 2)
 129 #define REG_FEAT_POWERDOWN        REG(0x00, 0x0e)     /* read/write */
 130 # define FEAT_POWERDOWN_PREFILT   BIT(0)
 131 # define FEAT_POWERDOWN_CSC       BIT(1)
 132 # define FEAT_POWERDOWN_SPDIF     (1 << 3)
 133 #define REG_INT_FLAGS_0           REG(0x00, 0x0f)     /* read/write */
 134 #define REG_INT_FLAGS_1           REG(0x00, 0x10)     /* read/write */
 135 #define REG_INT_FLAGS_2           REG(0x00, 0x11)     /* read/write */
 136 # define INT_FLAGS_2_EDID_BLK_RD  (1 << 1)
 137 #define REG_ENA_ACLK              REG(0x00, 0x16)     /* read/write */
 138 #define REG_ENA_VP_0              REG(0x00, 0x18)     /* read/write */
 139 #define REG_ENA_VP_1              REG(0x00, 0x19)     /* read/write */
 140 #define REG_ENA_VP_2              REG(0x00, 0x1a)     /* read/write */
 141 #define REG_ENA_AP                REG(0x00, 0x1e)     /* read/write */
 142 #define REG_VIP_CNTRL_0           REG(0x00, 0x20)     /* write */
 143 # define VIP_CNTRL_0_MIRR_A       (1 << 7)
 144 # define VIP_CNTRL_0_SWAP_A(x)    (((x) & 7) << 4)
 145 # define VIP_CNTRL_0_MIRR_B       (1 << 3)
 146 # define VIP_CNTRL_0_SWAP_B(x)    (((x) & 7) << 0)
 147 #define REG_VIP_CNTRL_1           REG(0x00, 0x21)     /* write */
 148 # define VIP_CNTRL_1_MIRR_C       (1 << 7)
 149 # define VIP_CNTRL_1_SWAP_C(x)    (((x) & 7) << 4)
 150 # define VIP_CNTRL_1_MIRR_D       (1 << 3)
 151 # define VIP_CNTRL_1_SWAP_D(x)    (((x) & 7) << 0)
 152 #define REG_VIP_CNTRL_2           REG(0x00, 0x22)     /* write */
 153 # define VIP_CNTRL_2_MIRR_E       (1 << 7)
 154 # define VIP_CNTRL_2_SWAP_E(x)    (((x) & 7) << 4)
 155 # define VIP_CNTRL_2_MIRR_F       (1 << 3)
 156 # define VIP_CNTRL_2_SWAP_F(x)    (((x) & 7) << 0)
 157 #define REG_VIP_CNTRL_3           REG(0x00, 0x23)     /* write */
 158 # define VIP_CNTRL_3_X_TGL        (1 << 0)
 159 # define VIP_CNTRL_3_H_TGL        (1 << 1)
 160 # define VIP_CNTRL_3_V_TGL        (1 << 2)
 161 # define VIP_CNTRL_3_EMB          (1 << 3)
 162 # define VIP_CNTRL_3_SYNC_DE      (1 << 4)
 163 # define VIP_CNTRL_3_SYNC_HS      (1 << 5)
 164 # define VIP_CNTRL_3_DE_INT       (1 << 6)
 165 # define VIP_CNTRL_3_EDGE         (1 << 7)
 166 #define REG_VIP_CNTRL_4           REG(0x00, 0x24)     /* write */
 167 # define VIP_CNTRL_4_BLC(x)       (((x) & 3) << 0)
 168 # define VIP_CNTRL_4_BLANKIT(x)   (((x) & 3) << 2)
 169 # define VIP_CNTRL_4_CCIR656      (1 << 4)
 170 # define VIP_CNTRL_4_656_ALT      (1 << 5)
 171 # define VIP_CNTRL_4_TST_656      (1 << 6)
 172 # define VIP_CNTRL_4_TST_PAT      (1 << 7)
 173 #define REG_VIP_CNTRL_5           REG(0x00, 0x25)     /* write */
 174 # define VIP_CNTRL_5_CKCASE       (1 << 0)
 175 # define VIP_CNTRL_5_SP_CNT(x)    (((x) & 3) << 1)
 176 #define REG_MUX_AP                REG(0x00, 0x26)     /* read/write */
 177 # define MUX_AP_SELECT_I2S        0x64
 178 # define MUX_AP_SELECT_SPDIF      0x40
 179 #define REG_MUX_VP_VIP_OUT        REG(0x00, 0x27)     /* read/write */
 180 #define REG_MAT_CONTRL            REG(0x00, 0x80)     /* write */
 181 # define MAT_CONTRL_MAT_SC(x)     (((x) & 3) << 0)
 182 # define MAT_CONTRL_MAT_BP        (1 << 2)
 183 #define REG_VIDFORMAT             REG(0x00, 0xa0)     /* write */
 184 #define REG_REFPIX_MSB            REG(0x00, 0xa1)     /* write */
 185 #define REG_REFPIX_LSB            REG(0x00, 0xa2)     /* write */
 186 #define REG_REFLINE_MSB           REG(0x00, 0xa3)     /* write */
 187 #define REG_REFLINE_LSB           REG(0x00, 0xa4)     /* write */
 188 #define REG_NPIX_MSB              REG(0x00, 0xa5)     /* write */
 189 #define REG_NPIX_LSB              REG(0x00, 0xa6)     /* write */
 190 #define REG_NLINE_MSB             REG(0x00, 0xa7)     /* write */
 191 #define REG_NLINE_LSB             REG(0x00, 0xa8)     /* write */
 192 #define REG_VS_LINE_STRT_1_MSB    REG(0x00, 0xa9)     /* write */
 193 #define REG_VS_LINE_STRT_1_LSB    REG(0x00, 0xaa)     /* write */
 194 #define REG_VS_PIX_STRT_1_MSB     REG(0x00, 0xab)     /* write */
 195 #define REG_VS_PIX_STRT_1_LSB     REG(0x00, 0xac)     /* write */
 196 #define REG_VS_LINE_END_1_MSB     REG(0x00, 0xad)     /* write */
 197 #define REG_VS_LINE_END_1_LSB     REG(0x00, 0xae)     /* write */
 198 #define REG_VS_PIX_END_1_MSB      REG(0x00, 0xaf)     /* write */
 199 #define REG_VS_PIX_END_1_LSB      REG(0x00, 0xb0)     /* write */
 200 #define REG_VS_LINE_STRT_2_MSB    REG(0x00, 0xb1)     /* write */
 201 #define REG_VS_LINE_STRT_2_LSB    REG(0x00, 0xb2)     /* write */
 202 #define REG_VS_PIX_STRT_2_MSB     REG(0x00, 0xb3)     /* write */
 203 #define REG_VS_PIX_STRT_2_LSB     REG(0x00, 0xb4)     /* write */
 204 #define REG_VS_LINE_END_2_MSB     REG(0x00, 0xb5)     /* write */
 205 #define REG_VS_LINE_END_2_LSB     REG(0x00, 0xb6)     /* write */
 206 #define REG_VS_PIX_END_2_MSB      REG(0x00, 0xb7)     /* write */
 207 #define REG_VS_PIX_END_2_LSB      REG(0x00, 0xb8)     /* write */
 208 #define REG_HS_PIX_START_MSB      REG(0x00, 0xb9)     /* write */
 209 #define REG_HS_PIX_START_LSB      REG(0x00, 0xba)     /* write */
 210 #define REG_HS_PIX_STOP_MSB       REG(0x00, 0xbb)     /* write */
 211 #define REG_HS_PIX_STOP_LSB       REG(0x00, 0xbc)     /* write */
 212 #define REG_VWIN_START_1_MSB      REG(0x00, 0xbd)     /* write */
 213 #define REG_VWIN_START_1_LSB      REG(0x00, 0xbe)     /* write */
 214 #define REG_VWIN_END_1_MSB        REG(0x00, 0xbf)     /* write */
 215 #define REG_VWIN_END_1_LSB        REG(0x00, 0xc0)     /* write */
 216 #define REG_VWIN_START_2_MSB      REG(0x00, 0xc1)     /* write */
 217 #define REG_VWIN_START_2_LSB      REG(0x00, 0xc2)     /* write */
 218 #define REG_VWIN_END_2_MSB        REG(0x00, 0xc3)     /* write */
 219 #define REG_VWIN_END_2_LSB        REG(0x00, 0xc4)     /* write */
 220 #define REG_DE_START_MSB          REG(0x00, 0xc5)     /* write */
 221 #define REG_DE_START_LSB          REG(0x00, 0xc6)     /* write */
 222 #define REG_DE_STOP_MSB           REG(0x00, 0xc7)     /* write */
 223 #define REG_DE_STOP_LSB           REG(0x00, 0xc8)     /* write */
 224 #define REG_TBG_CNTRL_0           REG(0x00, 0xca)     /* write */
 225 # define TBG_CNTRL_0_TOP_TGL      (1 << 0)
 226 # define TBG_CNTRL_0_TOP_SEL      (1 << 1)
 227 # define TBG_CNTRL_0_DE_EXT       (1 << 2)
 228 # define TBG_CNTRL_0_TOP_EXT      (1 << 3)
 229 # define TBG_CNTRL_0_FRAME_DIS    (1 << 5)
 230 # define TBG_CNTRL_0_SYNC_MTHD    (1 << 6)
 231 # define TBG_CNTRL_0_SYNC_ONCE    (1 << 7)
 232 #define REG_TBG_CNTRL_1           REG(0x00, 0xcb)     /* write */
 233 # define TBG_CNTRL_1_H_TGL        (1 << 0)
 234 # define TBG_CNTRL_1_V_TGL        (1 << 1)
 235 # define TBG_CNTRL_1_TGL_EN       (1 << 2)
 236 # define TBG_CNTRL_1_X_EXT        (1 << 3)
 237 # define TBG_CNTRL_1_H_EXT        (1 << 4)
 238 # define TBG_CNTRL_1_V_EXT        (1 << 5)
 239 # define TBG_CNTRL_1_DWIN_DIS     (1 << 6)
 240 #define REG_ENABLE_SPACE          REG(0x00, 0xd6)     /* write */
 241 #define REG_HVF_CNTRL_0           REG(0x00, 0xe4)     /* write */
 242 # define HVF_CNTRL_0_SM           (1 << 7)
 243 # define HVF_CNTRL_0_RWB          (1 << 6)
 244 # define HVF_CNTRL_0_PREFIL(x)    (((x) & 3) << 2)
 245 # define HVF_CNTRL_0_INTPOL(x)    (((x) & 3) << 0)
 246 #define REG_HVF_CNTRL_1           REG(0x00, 0xe5)     /* write */
 247 # define HVF_CNTRL_1_FOR          (1 << 0)
 248 # define HVF_CNTRL_1_YUVBLK       (1 << 1)
 249 # define HVF_CNTRL_1_VQR(x)       (((x) & 3) << 2)
 250 # define HVF_CNTRL_1_PAD(x)       (((x) & 3) << 4)
 251 # define HVF_CNTRL_1_SEMI_PLANAR  (1 << 6)
 252 #define REG_RPT_CNTRL             REG(0x00, 0xf0)     /* write */
 253 # define RPT_CNTRL_REPEAT(x)      ((x) & 15)
 254 #define REG_I2S_FORMAT            REG(0x00, 0xfc)     /* read/write */
 255 # define I2S_FORMAT_PHILIPS       (0 << 0)
 256 # define I2S_FORMAT_LEFT_J        (2 << 0)
 257 # define I2S_FORMAT_RIGHT_J       (3 << 0)
 258 #define REG_AIP_CLKSEL            REG(0x00, 0xfd)     /* write */
 259 # define AIP_CLKSEL_AIP_SPDIF     (0 << 3)
 260 # define AIP_CLKSEL_AIP_I2S       (1 << 3)
 261 # define AIP_CLKSEL_FS_ACLK       (0 << 0)
 262 # define AIP_CLKSEL_FS_MCLK       (1 << 0)
 263 # define AIP_CLKSEL_FS_FS64SPDIF  (2 << 0)
 264
 265 /* Page 02h: PLL settings */
 266 #define REG_PLL_SERIAL_1          REG(0x02, 0x00)     /* read/write */
 267 # define PLL_SERIAL_1_SRL_FDN     (1 << 0)
 268 # define PLL_SERIAL_1_SRL_IZ(x)   (((x) & 3) << 1)
 269 # define PLL_SERIAL_1_SRL_MAN_IZ  (1 << 6)
 270 #define REG_PLL_SERIAL_2          REG(0x02, 0x01)     /* read/write */
 271 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
 272 # define PLL_SERIAL_2_SRL_PR(x)   (((x) & 0xf) << 4)
 273 #define REG_PLL_SERIAL_3          REG(0x02, 0x02)     /* read/write */
 274 # define PLL_SERIAL_3_SRL_CCIR    (1 << 0)
 275 # define PLL_SERIAL_3_SRL_DE      (1 << 2)
 276 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
 277 #define REG_SERIALIZER            REG(0x02, 0x03)     /* read/write */
 278 #define REG_BUFFER_OUT            REG(0x02, 0x04)     /* read/write */
 279 #define REG_PLL_SCG1              REG(0x02, 0x05)     /* read/write */
 280 #define REG_PLL_SCG2              REG(0x02, 0x06)     /* read/write */
 281 #define REG_PLL_SCGN1             REG(0x02, 0x07)     /* read/write */
 282 #define REG_PLL_SCGN2             REG(0x02, 0x08)     /* read/write */
 283 #define REG_PLL_SCGR1             REG(0x02, 0x09)     /* read/write */
 284 #define REG_PLL_SCGR2             REG(0x02, 0x0a)     /* read/write */
 285 #define REG_AUDIO_DIV             REG(0x02, 0x0e)     /* read/write */
 286 # define AUDIO_DIV_SERCLK_1       0
 287 # define AUDIO_DIV_SERCLK_2       1
 288 # define AUDIO_DIV_SERCLK_4       2
 289 # define AUDIO_DIV_SERCLK_8       3
 290 # define AUDIO_DIV_SERCLK_16      4
 291 # define AUDIO_DIV_SERCLK_32      5
 292 #define REG_SEL_CLK               REG(0x02, 0x11)     /* read/write */
 293 # define SEL_CLK_SEL_CLK1         (1 << 0)
 294 # define SEL_CLK_SEL_VRF_CLK(x)   (((x) & 3) << 1)
 295 # define SEL_CLK_ENA_SC_CLK       (1 << 3)
 296 #define REG_ANA_GENERAL           REG(0x02, 0x12)     /* read/write */
 297
 298
 299 /* Page 09h: EDID Control */
 300 #define REG_EDID_DATA_0           REG(0x09, 0x00)     /* read */
 301 /* next 127 successive registers are the EDID block */
 302 #define REG_EDID_CTRL             REG(0x09, 0xfa)     /* read/write */
 303 #define REG_DDC_ADDR              REG(0x09, 0xfb)     /* read/write */
 304 #define REG_DDC_OFFS              REG(0x09, 0xfc)     /* read/write */
 305 #define REG_DDC_SEGM_ADDR         REG(0x09, 0xfd)     /* read/write */
 306 #define REG_DDC_SEGM              REG(0x09, 0xfe)     /* read/write */
 307
 308
 309 /* Page 10h: information frames and packets */
 310 #define REG_IF1_HB0               REG(0x10, 0x20)     /* read/write */
 311 #define REG_IF2_HB0               REG(0x10, 0x40)     /* read/write */
 312 #define REG_IF3_HB0               REG(0x10, 0x60)     /* read/write */
 313 #define REG_IF4_HB0               REG(0x10, 0x80)     /* read/write */
 314 #define REG_IF5_HB0               REG(0x10, 0xa0)     /* read/write */
 315
 316
 317 /* Page 11h: audio settings and content info packets */
 318 #define REG_AIP_CNTRL_0           REG(0x11, 0x00)     /* read/write */
 319 # define AIP_CNTRL_0_RST_FIFO     (1 << 0)
 320 # define AIP_CNTRL_0_SWAP         (1 << 1)
 321 # define AIP_CNTRL_0_LAYOUT       (1 << 2)
 322 # define AIP_CNTRL_0_ACR_MAN      (1 << 5)
 323 # define AIP_CNTRL_0_RST_CTS      (1 << 6)
 324 #define REG_CA_I2S                REG(0x11, 0x01)     /* read/write */
 325 # define CA_I2S_CA_I2S(x)         (((x) & 31) << 0)
 326 # define CA_I2S_HBR_CHSTAT        (1 << 6)
 327 #define REG_LATENCY_RD            REG(0x11, 0x04)     /* read/write */
 328 #define REG_ACR_CTS_0             REG(0x11, 0x05)     /* read/write */
 329 #define REG_ACR_CTS_1             REG(0x11, 0x06)     /* read/write */
 330 #define REG_ACR_CTS_2             REG(0x11, 0x07)     /* read/write */
 331 #define REG_ACR_N_0               REG(0x11, 0x08)     /* read/write */
 332 #define REG_ACR_N_1               REG(0x11, 0x09)     /* read/write */
 333 #define REG_ACR_N_2               REG(0x11, 0x0a)     /* read/write */
 334 #define REG_CTS_N                 REG(0x11, 0x0c)     /* read/write */
 335 # define CTS_N_K(x)               (((x) & 7) << 0)
 336 # define CTS_N_M(x)               (((x) & 3) << 4)
 337 #define REG_ENC_CNTRL             REG(0x11, 0x0d)     /* read/write */
 338 # define ENC_CNTRL_RST_ENC        (1 << 0)
 339 # define ENC_CNTRL_RST_SEL        (1 << 1)
 340 # define ENC_CNTRL_CTL_CODE(x)    (((x) & 3) << 2)
 341 #define REG_DIP_FLAGS             REG(0x11, 0x0e)     /* read/write */
 342 # define DIP_FLAGS_ACR            (1 << 0)
 343 # define DIP_FLAGS_GC             (1 << 1)
 344 #define REG_DIP_IF_FLAGS          REG(0x11, 0x0f)     /* read/write */
 345 # define DIP_IF_FLAGS_IF1         (1 << 1)
 346 # define DIP_IF_FLAGS_IF2         (1 << 2)
 347 # define DIP_IF_FLAGS_IF3         (1 << 3)
 348 # define DIP_IF_FLAGS_IF4         (1 << 4)
 349 # define DIP_IF_FLAGS_IF5         (1 << 5)
 350 #define REG_CH_STAT_B(x)          REG(0x11, 0x14 + (x)) /* read/write */
 351
 352
 353 /* Page 12h: HDCP and OTP */
 354 #define REG_TX3                   REG(0x12, 0x9a)     /* read/write */
 355 #define REG_TX4                   REG(0x12, 0x9b)     /* read/write */
 356 # define TX4_PD_RAM               (1 << 1)
 357 #define REG_TX33                  REG(0x12, 0xb8)     /* read/write */
 358 # define TX33_HDMI                (1 << 1)
 359
 360
 361 /* Page 13h: Gamut related metadata packets */
 362
 363
 364
 365 /* CEC registers: (not paged)
 366  */
 367 #define REG_CEC_INTSTATUS         0xee                /* read */
 368 # define CEC_INTSTATUS_CEC        (1 << 0)
 369 # define CEC_INTSTATUS_HDMI       (1 << 1)
 370 #define REG_CEC_CAL_XOSC_CTRL1    0xf2
 371 # define CEC_CAL_XOSC_CTRL1_ENA_CAL     BIT(0)
 372 #define REG_CEC_DES_FREQ2         0xf5
 373 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7)
 374 #define REG_CEC_CLK               0xf6
 375 # define CEC_CLK_FRO              0x11
 376 #define REG_CEC_FRO_IM_CLK_CTRL   0xfb                /* read/write */
 377 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
 378 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP   (1 << 6)
 379 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
 380 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV   (1 << 0)
 381 #define REG_CEC_RXSHPDINTENA      0xfc                /* read/write */
 382 #define REG_CEC_RXSHPDINT         0xfd                /* read */
 383 # define CEC_RXSHPDINT_RXSENS     BIT(0)
 384 # define CEC_RXSHPDINT_HPD        BIT(1)
 385 #define REG_CEC_RXSHPDLEV         0xfe                /* read */
 386 # define CEC_RXSHPDLEV_RXSENS     (1 << 0)
 387 # define CEC_RXSHPDLEV_HPD        (1 << 1)
 388
 389 #define REG_CEC_ENAMODS           0xff                /* read/write */
 390 # define CEC_ENAMODS_EN_CEC_CLK   (1 << 7)
 391 # define CEC_ENAMODS_DIS_FRO      (1 << 6)
 392 # define CEC_ENAMODS_DIS_CCLK     (1 << 5)
 393 # define CEC_ENAMODS_EN_RXSENS    (1 << 2)
 394 # define CEC_ENAMODS_EN_HDMI      (1 << 1)
 395 # define CEC_ENAMODS_EN_CEC       (1 << 0)
 396
 397
 398 /* Device versions: */
 399 #define TDA9989N2                 0x0101
 400 #define TDA19989                  0x0201
 401 #define TDA19989N2                0x0202
 402 #define TDA19988                  0x0301
 403
 404 static void
 405 cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
 406 {
 407         u8 buf[] = {addr, val};
 408         struct i2c_msg msg = {
 409                 .addr = priv->cec_addr,
 410                 .len = 2,
 411                 .buf = buf,
 412         };
 413         int ret;
 414
 415         ret = i2c_transfer(priv->hdmi->adapter, &msg, 1);
 416         if (ret < 0)
 417                 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n",
 418                         ret, addr);
 419 }
 420
 421 static u8
 422 cec_read(struct tda998x_priv *priv, u8 addr)
 423 {
 424         u8 val;
 425         struct i2c_msg msg[2] = {
 426                 {
 427                         .addr = priv->cec_addr,
 428                         .len = 1,
 429                         .buf = &addr,
 430                 }, {
 431                         .addr = priv->cec_addr,
 432                         .flags = I2C_M_RD,
 433                         .len = 1,
 434                         .buf = &val,
 435                 },
 436         };
 437         int ret;
 438
 439         ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg));
 440         if (ret < 0) {
 441                 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n",
 442                         ret, addr);
 443                 val = 0;
 444         }
 445
 446         return val;
 447 }
 448
 449 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable)
 450 {
 451         int val = cec_read(priv, REG_CEC_ENAMODS);
 452
 453         if (val < 0)
 454                 return;
 455
 456         if (enable)
 457                 val |= mods;
 458         else
 459                 val &= ~mods;
 460
 461         cec_write(priv, REG_CEC_ENAMODS, val);
 462 }
 463
 464 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable)
 465 {
 466         if (enable) {
 467                 u8 val;
 468
 469                 cec_write(priv, 0xf3, 0xc0);
 470                 cec_write(priv, 0xf4, 0xd4);
 471
 472                 /* Enable automatic calibration mode */
 473                 val = cec_read(priv, REG_CEC_DES_FREQ2);
 474                 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL;
 475                 cec_write(priv, REG_CEC_DES_FREQ2, val);
 476
 477                 /* Enable free running oscillator */
 478                 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO);
 479                 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false);
 480
 481                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1,
 482                           CEC_CAL_XOSC_CTRL1_ENA_CAL);
 483         } else {
 484                 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0);
 485         }
 486 }
 487
 488 /*
 489  * Calibration for the internal oscillator: we need to set calibration mode,
 490  * and then pulse the IRQ line low for a 10ms ± 1% period.
 491  */
 492 static void tda998x_cec_calibration(struct tda998x_priv *priv)
 493 {
 494         struct gpio_desc *calib = priv->calib;
 495
 496         mutex_lock(&priv->edid_mutex);
 497         if (priv->hdmi->irq > 0)
 498                 disable_irq(priv->hdmi->irq);
 499         gpiod_direction_output(calib, 1);
 500         tda998x_cec_set_calibration(priv, true);
 501
 502         local_irq_disable();
 503         gpiod_set_value(calib, 0);
 504         mdelay(10);
 505         gpiod_set_value(calib, 1);
 506         local_irq_enable();
 507
 508         tda998x_cec_set_calibration(priv, false);
 509         gpiod_direction_input(calib);
 510         if (priv->hdmi->irq > 0)
 511                 enable_irq(priv->hdmi->irq);
 512         mutex_unlock(&priv->edid_mutex);
 513 }
 514
 515 static int tda998x_cec_hook_init(void *data)
 516 {
 517         struct tda998x_priv *priv = data;
 518         struct gpio_desc *calib;
 519
 520         calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS);
 521         if (IS_ERR(calib)) {
 522                 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n",
 523                          PTR_ERR(calib));
 524                 return PTR_ERR(calib);
 525         }
 526
 527         priv->calib = calib;
 528
 529         return 0;
 530 }
 531
 532 static void tda998x_cec_hook_exit(void *data)
 533 {
 534         struct tda998x_priv *priv = data;
 535
 536         gpiod_put(priv->calib);
 537         priv->calib = NULL;
 538 }
 539
 540 static int tda998x_cec_hook_open(void *data)
 541 {
 542         struct tda998x_priv *priv = data;
 543
 544         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true);
 545         tda998x_cec_calibration(priv);
 546
 547         return 0;
 548 }
 549
 550 static void tda998x_cec_hook_release(void *data)
 551 {
 552         struct tda998x_priv *priv = data;
 553
 554         cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false);
 555 }
 556
 557 static int
 558 set_page(struct tda998x_priv *priv, u16 reg)
 559 {
 560         if (REG2PAGE(reg) != priv->current_page) {
 561                 struct i2c_client *client = priv->hdmi;
 562                 u8 buf[] = {
 563                                 REG_CURPAGE, REG2PAGE(reg)
 564                 };
 565                 int ret = i2c_master_send(client, buf, sizeof(buf));
 566                 if (ret < 0) {
 567                         dev_err(&client->dev, "%s %04x err %d\n", __func__,
 568                                         reg, ret);
 569                         return ret;
 570                 }
 571
 572                 priv->current_page = REG2PAGE(reg);
 573         }
 574         return 0;
 575 }
 576
 577 static int
 578 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
 579 {
 580         struct i2c_client *client = priv->hdmi;
 581         u8 addr = REG2ADDR(reg);
 582         int ret;
 583
 584         mutex_lock(&priv->mutex);
 585         ret = set_page(priv, reg);
 586         if (ret < 0)
 587                 goto out;
 588
 589         ret = i2c_master_send(client, &addr, sizeof(addr));
 590         if (ret < 0)
 591                 goto fail;
 592
 593         ret = i2c_master_recv(client, buf, cnt);
 594         if (ret < 0)
 595                 goto fail;
 596
 597         goto out;
 598
 599 fail:
 600         dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
 601 out:
 602         mutex_unlock(&priv->mutex);
 603         return ret;
 604 }
 605
 606 #define MAX_WRITE_RANGE_BUF 32
 607
 608 static void
 609 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
 610 {
 611         struct i2c_client *client = priv->hdmi;
 612         /* This is the maximum size of the buffer passed in */
 613         u8 buf[MAX_WRITE_RANGE_BUF + 1];
 614         int ret;
 615
 616         if (cnt > MAX_WRITE_RANGE_BUF) {
 617                 dev_err(&client->dev, "Fixed write buffer too small (%d)\n",
 618                                 MAX_WRITE_RANGE_BUF);
 619                 return;
 620         }
 621
 622         buf[0] = REG2ADDR(reg);
 623         memcpy(&buf[1], p, cnt);
 624
 625         mutex_lock(&priv->mutex);
 626         ret = set_page(priv, reg);
 627         if (ret < 0)
 628                 goto out;
 629
 630         ret = i2c_master_send(client, buf, cnt + 1);
 631         if (ret < 0)
 632                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 633 out:
 634         mutex_unlock(&priv->mutex);
 635 }
 636
 637 static int
 638 reg_read(struct tda998x_priv *priv, u16 reg)
 639 {
 640         u8 val = 0;
 641         int ret;
 642
 643         ret = reg_read_range(priv, reg, &val, sizeof(val));
 644         if (ret < 0)
 645                 return ret;
 646         return val;
 647 }
 648
 649 static void
 650 reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
 651 {
 652         struct i2c_client *client = priv->hdmi;
 653         u8 buf[] = {REG2ADDR(reg), val};
 654         int ret;
 655
 656         mutex_lock(&priv->mutex);
 657         ret = set_page(priv, reg);
 658         if (ret < 0)
 659                 goto out;
 660
 661         ret = i2c_master_send(client, buf, sizeof(buf));
 662         if (ret < 0)
 663                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 664 out:
 665         mutex_unlock(&priv->mutex);
 666 }
 667
 668 static void
 669 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
 670 {
 671         struct i2c_client *client = priv->hdmi;
 672         u8 buf[] = {REG2ADDR(reg), val >> 8, val};
 673         int ret;
 674
 675         mutex_lock(&priv->mutex);
 676         ret = set_page(priv, reg);
 677         if (ret < 0)
 678                 goto out;
 679
 680         ret = i2c_master_send(client, buf, sizeof(buf));
 681         if (ret < 0)
 682                 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
 683 out:
 684         mutex_unlock(&priv->mutex);
 685 }
 686
 687 static void
 688 reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
 689 {
 690         int old_val;
 691
 692         old_val = reg_read(priv, reg);
 693         if (old_val >= 0)
 694                 reg_write(priv, reg, old_val | val);
 695 }
 696
 697 static void
 698 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
 699 {
 700         int old_val;
 701
 702         old_val = reg_read(priv, reg);
 703         if (old_val >= 0)
 704                 reg_write(priv, reg, old_val & ~val);
 705 }
 706
 707 static void
 708 tda998x_reset(struct tda998x_priv *priv)
 709 {
 710         /* reset audio and i2c master: */
 711         reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
 712         msleep(50);
 713         reg_write(priv, REG_SOFTRESET, 0);
 714         msleep(50);
 715
 716         /* reset transmitter: */
 717         reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 718         reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
 719
 720         /* PLL registers common configuration */
 721         reg_write(priv, REG_PLL_SERIAL_1, 0x00);
 722         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
 723         reg_write(priv, REG_PLL_SERIAL_3, 0x00);
 724         reg_write(priv, REG_SERIALIZER,   0x00);
 725         reg_write(priv, REG_BUFFER_OUT,   0x00);
 726         reg_write(priv, REG_PLL_SCG1,     0x00);
 727         reg_write(priv, REG_AUDIO_DIV,    AUDIO_DIV_SERCLK_8);
 728         reg_write(priv, REG_SEL_CLK,      SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
 729         reg_write(priv, REG_PLL_SCGN1,    0xfa);
 730         reg_write(priv, REG_PLL_SCGN2,    0x00);
 731         reg_write(priv, REG_PLL_SCGR1,    0x5b);
 732         reg_write(priv, REG_PLL_SCGR2,    0x00);
 733         reg_write(priv, REG_PLL_SCG2,     0x10);
 734
 735         /* Write the default value MUX register */
 736         reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
 737 }
 738
 739 /*
 740  * The TDA998x has a problem when trying to read the EDID close to a
 741  * HPD assertion: it needs a delay of 100ms to avoid timing out while
 742  * trying to read EDID data.
 743  *
 744  * However, tda998x_connector_get_modes() may be called at any moment
 745  * after tda998x_connector_detect() indicates that we are connected, so
 746  * we need to delay probing modes in tda998x_connector_get_modes() after
 747  * we have seen a HPD inactive->active transition.  This code implements
 748  * that delay.
 749  */
 750 static void tda998x_edid_delay_done(struct timer_list *t)
 751 {
 752         struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer);
 753
 754         priv->edid_delay_active = false;
 755         wake_up(&priv->edid_delay_waitq);
 756         schedule_work(&priv->detect_work);
 757 }
 758
 759 static void tda998x_edid_delay_start(struct tda998x_priv *priv)
 760 {
 761         priv->edid_delay_active = true;
 762         mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
 763 }
 764
 765 static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
 766 {
 767         return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
 768 }
 769
 770 /*
 771  * We need to run the KMS hotplug event helper outside of our threaded
 772  * interrupt routine as this can call back into our get_modes method,
 773  * which will want to make use of interrupts.
 774  */
 775 static void tda998x_detect_work(struct work_struct *work)
 776 {
 777         struct tda998x_priv *priv =
 778                 container_of(work, struct tda998x_priv, detect_work);
 779         struct drm_device *dev = priv->connector.dev;
 780
 781         if (dev)
 782                 drm_kms_helper_hotplug_event(dev);
 783 }
 784
 785 /*
 786  * only 2 interrupts may occur: screen plug/unplug and EDID read
 787  */
 788 static irqreturn_t tda998x_irq_thread(int irq, void *data)
 789 {
 790         struct tda998x_priv *priv = data;
 791         u8 sta, cec, lvl, flag0, flag1, flag2;
 792         bool handled = false;
 793
 794         sta = cec_read(priv, REG_CEC_INTSTATUS);
 795         if (sta & CEC_INTSTATUS_HDMI) {
 796                 cec = cec_read(priv, REG_CEC_RXSHPDINT);
 797                 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
 798                 flag0 = reg_read(priv, REG_INT_FLAGS_0);
 799                 flag1 = reg_read(priv, REG_INT_FLAGS_1);
 800                 flag2 = reg_read(priv, REG_INT_FLAGS_2);
 801                 DRM_DEBUG_DRIVER(
 802                         "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
 803                         sta, cec, lvl, flag0, flag1, flag2);
 804
 805                 if (cec & CEC_RXSHPDINT_HPD) {
 806                         if (lvl & CEC_RXSHPDLEV_HPD) {
 807                                 tda998x_edid_delay_start(priv);
 808                         } else {
 809                                 schedule_work(&priv->detect_work);
 810                                 cec_notifier_phys_addr_invalidate(
 811                                                 priv->cec_notify);
 812                         }
 813
 814                         handled = true;
 815                 }
 816
 817                 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
 818                         priv->wq_edid_wait = 0;
 819                         wake_up(&priv->wq_edid);
 820                         handled = true;
 821                 }
 822         }
 823
 824         return IRQ_RETVAL(handled);
 825 }
 826
 827 static void
 828 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
 829                  union hdmi_infoframe *frame)
 830 {
 831         u8 buf[MAX_WRITE_RANGE_BUF];
 832         ssize_t len;
 833
 834         len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
 835         if (len < 0) {
 836                 dev_err(&priv->hdmi->dev,
 837                         "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
 838                         frame->any.type, len);
 839                 return;
 840         }
 841
 842         reg_clear(priv, REG_DIP_IF_FLAGS, bit);
 843         reg_write_range(priv, addr, buf, len);
 844         reg_set(priv, REG_DIP_IF_FLAGS, bit);
 845 }
 846
 847 static void tda998x_write_aif(struct tda998x_priv *priv,
 848                               const struct hdmi_audio_infoframe *cea)
 849 {
 850         union hdmi_infoframe frame;
 851
 852         frame.audio = *cea;
 853
 854         tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
 855 }
 856
 857 static void
 858 tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode)
 859 {
 860         union hdmi_infoframe frame;
 861
 862         drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 863                                                  &priv->connector, mode);
 864         frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
 865         drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode,
 866                                            priv->rgb_quant_range);
 867
 868         tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
 869 }
 870
 871 static void tda998x_write_vsi(struct tda998x_priv *priv,
 872                               const struct drm_display_mode *mode)
 873 {
 874         union hdmi_infoframe frame;
 875
 876         if (drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
 877                                                         &priv->connector,
 878                                                         mode))
 879                 reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1);
 880         else
 881                 tda998x_write_if(priv, DIP_IF_FLAGS_IF1, REG_IF1_HB0, &frame);
 882 }
 883
 884 /* Audio support */
 885
 886 static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = {
 887         [AUDIO_ROUTE_I2S] = {
 888                 .ena_aclk = 1,
 889                 .mux_ap = MUX_AP_SELECT_I2S,
 890                 .aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK,
 891         },
 892         [AUDIO_ROUTE_SPDIF] = {
 893                 .ena_aclk = 0,
 894                 .mux_ap = MUX_AP_SELECT_SPDIF,
 895                 .aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF,
 896         },
 897 };
 898
 899 /* Configure the TDA998x audio data and clock routing. */
 900 static int tda998x_derive_routing(struct tda998x_priv *priv,
 901                                   struct tda998x_audio_settings *s,
 902                                   unsigned int route)
 903 {
 904         s->route = &tda998x_audio_route[route];
 905         s->ena_ap = priv->audio_port_enable[route];
 906         if (s->ena_ap == 0) {
 907                 dev_err(&priv->hdmi->dev, "no audio configuration found\n");
 908                 return -EINVAL;
 909         }
 910
 911         return 0;
 912 }
 913
 914 /*
 915  * The audio clock divisor register controls a divider producing Audio_Clk_Out
 916  * from SERclk by dividing it by 2^n where 0 <= n <= 5.  We don't know what
 917  * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock.
 918  *
 919  * It seems that Audio_Clk_Out must be the smallest value that is greater
 920  * than 128*fs, otherwise audio does not function. There is some suggestion
 921  * that 126*fs is a better value.
 922  */
 923 static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs)
 924 {
 925         unsigned long min_audio_clk = fs * 128;
 926         unsigned long ser_clk = priv->tmds_clock * 1000;
 927         u8 adiv;
 928
 929         for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--)
 930                 if (ser_clk > min_audio_clk << adiv)
 931                         break;
 932
 933         dev_dbg(&priv->hdmi->dev,
 934                 "ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n",
 935                 ser_clk, fs, min_audio_clk, adiv);
 936
 937         return adiv;
 938 }
 939
 940 /*
 941  * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to
 942  * generate the CTS value.  It appears that the "measured time stamp" is
 943  * the number of TDMS clock cycles within a number of audio input clock
 944  * cycles defined by the k and N parameters defined below, in a similar
 945  * way to that which is set out in the CTS generation in the HDMI spec.
 946  *
 947  *  tmdsclk ----> mts -> /m ---> CTS
 948  *                 ^
 949  *  sclk -> /k -> /N
 950  *
 951  * CTS = mts / m, where m is 2^M.
 952  * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4
 953  * /N is a divider based on the HDMI specified N value.
 954  *
 955  * This produces the following equation:
 956  *  CTS = tmds_clock * k * N / (sclk * m)
 957  *
 958  * When combined with the sink-side equation, and realising that sclk is
 959  * bclk_ratio * fs, we end up with:
 960  *  k = m * bclk_ratio / 128.
 961  *
 962  * Note: S/PDIF always uses a bclk_ratio of 64.
 963  */
 964 static int tda998x_derive_cts_n(struct tda998x_priv *priv,
 965                                 struct tda998x_audio_settings *settings,
 966                                 unsigned int ratio)
 967 {
 968         switch (ratio) {
 969         case 16:
 970                 settings->cts_n = CTS_N_M(3) | CTS_N_K(0);
 971                 break;
 972         case 32:
 973                 settings->cts_n = CTS_N_M(3) | CTS_N_K(1);
 974                 break;
 975         case 48:
 976                 settings->cts_n = CTS_N_M(3) | CTS_N_K(2);
 977                 break;
 978         case 64:
 979                 settings->cts_n = CTS_N_M(3) | CTS_N_K(3);
 980                 break;
 981         case 128:
 982                 settings->cts_n = CTS_N_M(0) | CTS_N_K(0);
 983                 break;
 984         default:
 985                 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n",
 986                         ratio);
 987                 return -EINVAL;
 988         }
 989         return 0;
 990 }
 991
 992 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
 993 {
 994         if (on) {
 995                 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 996                 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
 997                 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
 998         } else {
 999                 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1000         }
1001 }
1002
1003 static void tda998x_configure_audio(struct tda998x_priv *priv)
1004 {
1005         const struct tda998x_audio_settings *settings = &priv->audio;
1006         u8 buf[6], adiv;
1007         u32 n;
1008
1009         /* If audio is not configured, there is nothing to do. */
1010         if (settings->ena_ap == 0)
1011                 return;
1012
1013         adiv = tda998x_get_adiv(priv, settings->sample_rate);
1014
1015         /* Enable audio ports */
1016         reg_write(priv, REG_ENA_AP, settings->ena_ap);
1017         reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk);
1018         reg_write(priv, REG_MUX_AP, settings->route->mux_ap);
1019         reg_write(priv, REG_I2S_FORMAT, settings->i2s_format);
1020         reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel);
1021         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
1022                                         AIP_CNTRL_0_ACR_MAN);   /* auto CTS */
1023         reg_write(priv, REG_CTS_N, settings->cts_n);
1024         reg_write(priv, REG_AUDIO_DIV, adiv);
1025
1026         /*
1027          * This is the approximate value of N, which happens to be
1028          * the recommended values for non-coherent clocks.
1029          */
1030         n = 128 * settings->sample_rate / 1000;
1031
1032         /* Write the CTS and N values */
1033         buf[0] = 0x44;
1034         buf[1] = 0x42;
1035         buf[2] = 0x01;
1036         buf[3] = n;
1037         buf[4] = n >> 8;
1038         buf[5] = n >> 16;
1039         reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
1040
1041         /* Reset CTS generator */
1042         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1043         reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
1044
1045         /* Write the channel status
1046          * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because
1047          * there is a separate register for each I2S wire.
1048          */
1049         buf[0] = settings->status[0];
1050         buf[1] = settings->status[1];
1051         buf[2] = settings->status[3];
1052         buf[3] = settings->status[4];
1053         reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
1054
1055         tda998x_audio_mute(priv, true);
1056         msleep(20);
1057         tda998x_audio_mute(priv, false);
1058
1059         tda998x_write_aif(priv, &settings->cea);
1060 }
1061
1062 static int tda998x_audio_hw_params(struct device *dev, void *data,
1063                                    struct hdmi_codec_daifmt *daifmt,
1064                                    struct hdmi_codec_params *params)
1065 {
1066         struct tda998x_priv *priv = dev_get_drvdata(dev);
1067         unsigned int bclk_ratio;
1068         bool spdif = daifmt->fmt == HDMI_SPDIF;
1069         int ret;
1070         struct tda998x_audio_settings audio = {
1071                 .sample_rate = params->sample_rate,
1072                 .cea = params->cea,
1073         };
1074
1075         memcpy(audio.status, params->iec.status,
1076                min(sizeof(audio.status), sizeof(params->iec.status)));
1077
1078         switch (daifmt->fmt) {
1079         case HDMI_I2S:
1080                 audio.i2s_format = I2S_FORMAT_PHILIPS;
1081                 break;
1082         case HDMI_LEFT_J:
1083                 audio.i2s_format = I2S_FORMAT_LEFT_J;
1084                 break;
1085         case HDMI_RIGHT_J:
1086                 audio.i2s_format = I2S_FORMAT_RIGHT_J;
1087                 break;
1088         case HDMI_SPDIF:
1089                 audio.i2s_format = 0;
1090                 break;
1091         default:
1092                 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt);
1093                 return -EINVAL;
1094         }
1095
1096         if (!spdif &&
1097             (daifmt->bit_clk_inv || daifmt->frame_clk_inv ||
1098              daifmt->bit_clk_master || daifmt->frame_clk_master)) {
1099                 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1100                         daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1101                         daifmt->bit_clk_master,
1102                         daifmt->frame_clk_master);
1103                 return -EINVAL;
1104         }
1105
1106         ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif);
1107         if (ret < 0)
1108                 return ret;
1109
1110         bclk_ratio = spdif ? 64 : params->sample_width * 2;
1111         ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio);
1112         if (ret < 0)
1113                 return ret;
1114
1115         mutex_lock(&priv->audio_mutex);
1116         priv->audio = audio;
1117         if (priv->supports_infoframes && priv->sink_has_audio)
1118                 tda998x_configure_audio(priv);
1119         mutex_unlock(&priv->audio_mutex);
1120
1121         return 0;
1122 }
1123
1124 static void tda998x_audio_shutdown(struct device *dev, void *data)
1125 {
1126         struct tda998x_priv *priv = dev_get_drvdata(dev);
1127
1128         mutex_lock(&priv->audio_mutex);
1129
1130         reg_write(priv, REG_ENA_AP, 0);
1131         priv->audio.ena_ap = 0;
1132
1133         mutex_unlock(&priv->audio_mutex);
1134 }
1135
1136 static int tda998x_audio_mute_stream(struct device *dev, void *data,
1137                                      bool enable, int direction)
1138 {
1139         struct tda998x_priv *priv = dev_get_drvdata(dev);
1140
1141         mutex_lock(&priv->audio_mutex);
1142
1143         tda998x_audio_mute(priv, enable);
1144
1145         mutex_unlock(&priv->audio_mutex);
1146         return 0;
1147 }
1148
1149 static int tda998x_audio_get_eld(struct device *dev, void *data,
1150                                  uint8_t *buf, size_t len)
1151 {
1152         struct tda998x_priv *priv = dev_get_drvdata(dev);
1153
1154         mutex_lock(&priv->audio_mutex);
1155         memcpy(buf, priv->connector.eld,
1156                min(sizeof(priv->connector.eld), len));
1157         mutex_unlock(&priv->audio_mutex);
1158
1159         return 0;
1160 }
1161
1162 static const struct hdmi_codec_ops audio_codec_ops = {
1163         .hw_params = tda998x_audio_hw_params,
1164         .audio_shutdown = tda998x_audio_shutdown,
1165         .mute_stream = tda998x_audio_mute_stream,
1166         .get_eld = tda998x_audio_get_eld,
1167         .no_capture_mute = 1,
1168 };
1169
1170 static int tda998x_audio_codec_init(struct tda998x_priv *priv,
1171                                     struct device *dev)
1172 {
1173         struct hdmi_codec_pdata codec_data = {
1174                 .ops = &audio_codec_ops,
1175                 .max_i2s_channels = 2,
1176         };
1177
1178         if (priv->audio_port_enable[AUDIO_ROUTE_I2S])
1179                 codec_data.i2s = 1;
1180         if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1181                 codec_data.spdif = 1;
1182
1183         priv->audio_pdev = platform_device_register_data(
1184                 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1185                 &codec_data, sizeof(codec_data));
1186
1187         return PTR_ERR_OR_ZERO(priv->audio_pdev);
1188 }
1189
1190 /* DRM connector functions */
1191
1192 static enum drm_connector_status
1193 tda998x_connector_detect(struct drm_connector *connector, bool force)
1194 {
1195         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1196         u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
1197
1198         return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1199                         connector_status_disconnected;
1200 }
1201
1202 static void tda998x_connector_destroy(struct drm_connector *connector)
1203 {
1204         drm_connector_cleanup(connector);
1205 }
1206
1207 static const struct drm_connector_funcs tda998x_connector_funcs = {
1208         .reset = drm_atomic_helper_connector_reset,
1209         .fill_modes = drm_helper_probe_single_connector_modes,
1210         .detect = tda998x_connector_detect,
1211         .destroy = tda998x_connector_destroy,
1212         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1213         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1214 };
1215
1216 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
1217 {
1218         struct tda998x_priv *priv = data;
1219         u8 offset, segptr;
1220         int ret, i;
1221
1222         offset = (blk & 1) ? 128 : 0;
1223         segptr = blk / 2;
1224
1225         mutex_lock(&priv->edid_mutex);
1226
1227         reg_write(priv, REG_DDC_ADDR, 0xa0);
1228         reg_write(priv, REG_DDC_OFFS, offset);
1229         reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1230         reg_write(priv, REG_DDC_SEGM, segptr);
1231
1232         /* enable reading EDID: */
1233         priv->wq_edid_wait = 1;
1234         reg_write(priv, REG_EDID_CTRL, 0x1);
1235
1236         /* flag must be cleared by sw: */
1237         reg_write(priv, REG_EDID_CTRL, 0x0);
1238
1239         /* wait for block read to complete: */
1240         if (priv->hdmi->irq) {
1241                 i = wait_event_timeout(priv->wq_edid,
1242                                         !priv->wq_edid_wait,
1243                                         msecs_to_jiffies(100));
1244                 if (i < 0) {
1245                         dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
1246                         ret = i;
1247                         goto failed;
1248                 }
1249         } else {
1250                 for (i = 100; i > 0; i--) {
1251                         msleep(1);
1252                         ret = reg_read(priv, REG_INT_FLAGS_2);
1253                         if (ret < 0)
1254                                 goto failed;
1255                         if (ret & INT_FLAGS_2_EDID_BLK_RD)
1256                                 break;
1257                 }
1258         }
1259
1260         if (i == 0) {
1261                 dev_err(&priv->hdmi->dev, "read edid timeout\n");
1262                 ret = -ETIMEDOUT;
1263                 goto failed;
1264         }
1265
1266         ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1267         if (ret != length) {
1268                 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1269                         blk, ret);
1270                 goto failed;
1271         }
1272
1273         ret = 0;
1274
1275  failed:
1276         mutex_unlock(&priv->edid_mutex);
1277         return ret;
1278 }
1279
1280 static int tda998x_connector_get_modes(struct drm_connector *connector)
1281 {
1282         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1283         struct edid *edid;
1284         int n;
1285
1286         /*
1287          * If we get killed while waiting for the HPD timeout, return
1288          * no modes found: we are not in a restartable path, so we
1289          * can't handle signals gracefully.
1290          */
1291         if (tda998x_edid_delay_wait(priv))
1292                 return 0;
1293
1294         if (priv->rev == TDA19988)
1295                 reg_clear(priv, REG_TX4, TX4_PD_RAM);
1296
1297         edid = drm_do_get_edid(connector, read_edid_block, priv);
1298
1299         if (priv->rev == TDA19988)
1300                 reg_set(priv, REG_TX4, TX4_PD_RAM);
1301
1302         if (!edid) {
1303                 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1304                 return 0;
1305         }
1306
1307         drm_connector_update_edid_property(connector, edid);
1308         cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid);
1309
1310         mutex_lock(&priv->audio_mutex);
1311         n = drm_add_edid_modes(connector, edid);
1312         priv->sink_has_audio = drm_detect_monitor_audio(edid);
1313         mutex_unlock(&priv->audio_mutex);
1314
1315         kfree(edid);
1316
1317         return n;
1318 }
1319
1320 static struct drm_encoder *
1321 tda998x_connector_best_encoder(struct drm_connector *connector)
1322 {
1323         struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
1324
1325         return priv->bridge.encoder;
1326 }
1327
1328 static
1329 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1330         .get_modes = tda998x_connector_get_modes,
1331         .best_encoder = tda998x_connector_best_encoder,
1332 };
1333
1334 static int tda998x_connector_init(struct tda998x_priv *priv,
1335                                   struct drm_device *drm)
1336 {
1337         struct drm_connector *connector = &priv->connector;
1338         int ret;
1339
1340         connector->interlace_allowed = 1;
1341
1342         if (priv->hdmi->irq)
1343                 connector->polled = DRM_CONNECTOR_POLL_HPD;
1344         else
1345                 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1346                         DRM_CONNECTOR_POLL_DISCONNECT;
1347
1348         drm_connector_helper_add(connector, &tda998x_connector_helper_funcs);
1349         ret = drm_connector_init(drm, connector, &tda998x_connector_funcs,
1350                                  DRM_MODE_CONNECTOR_HDMIA);
1351         if (ret)
1352                 return ret;
1353
1354         drm_connector_attach_encoder(&priv->connector,
1355                                      priv->bridge.encoder);
1356
1357         return 0;
1358 }
1359
1360 /* DRM bridge functions */
1361
1362 static int tda998x_bridge_attach(struct drm_bridge *bridge,
1363                                  enum drm_bridge_attach_flags flags)
1364 {
1365         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1366
1367         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
1368                 DRM_ERROR("Fix bridge driver to make connector optional!");
1369                 return -EINVAL;
1370         }
1371
1372         return tda998x_connector_init(priv, bridge->dev);
1373 }
1374
1375 static void tda998x_bridge_detach(struct drm_bridge *bridge)
1376 {
1377         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1378
1379         drm_connector_cleanup(&priv->connector);
1380 }
1381
1382 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge,
1383                                      const struct drm_display_info *info,
1384                                      const struct drm_display_mode *mode)
1385 {
1386         /* TDA19988 dotclock can go up to 165MHz */
1387         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1388
1389         if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
1390                 return MODE_CLOCK_HIGH;
1391         if (mode->htotal >= BIT(13))
1392                 return MODE_BAD_HVALUE;
1393         if (mode->vtotal >= BIT(11))
1394                 return MODE_BAD_VVALUE;
1395         return MODE_OK;
1396 }
1397
1398 static void tda998x_bridge_enable(struct drm_bridge *bridge)
1399 {
1400         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1401
1402         if (!priv->is_on) {
1403                 /* enable video ports, audio will be enabled later */
1404                 reg_write(priv, REG_ENA_VP_0, 0xff);
1405                 reg_write(priv, REG_ENA_VP_1, 0xff);
1406                 reg_write(priv, REG_ENA_VP_2, 0xff);
1407                 /* set muxing after enabling ports: */
1408                 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
1409                 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
1410                 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
1411
1412                 priv->is_on = true;
1413         }
1414 }
1415
1416 static void tda998x_bridge_disable(struct drm_bridge *bridge)
1417 {
1418         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1419
1420         if (priv->is_on) {
1421                 /* disable video ports */
1422                 reg_write(priv, REG_ENA_VP_0, 0x00);
1423                 reg_write(priv, REG_ENA_VP_1, 0x00);
1424                 reg_write(priv, REG_ENA_VP_2, 0x00);
1425
1426                 priv->is_on = false;
1427         }
1428 }
1429
1430 static void tda998x_bridge_mode_set(struct drm_bridge *bridge,
1431                                     const struct drm_display_mode *mode,
1432                                     const struct drm_display_mode *adjusted_mode)
1433 {
1434         struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge);
1435         unsigned long tmds_clock;
1436         u16 ref_pix, ref_line, n_pix, n_line;
1437         u16 hs_pix_s, hs_pix_e;
1438         u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
1439         u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
1440         u16 vwin1_line_s, vwin1_line_e;
1441         u16 vwin2_line_s, vwin2_line_e;
1442         u16 de_pix_s, de_pix_e;
1443         u8 reg, div, rep, sel_clk;
1444
1445         /*
1446          * Since we are "computer" like, our source invariably produces
1447          * full-range RGB.  If the monitor supports full-range, then use
1448          * it, otherwise reduce to limited-range.
1449          */
1450         priv->rgb_quant_range =
1451                 priv->connector.display_info.rgb_quant_range_selectable ?
1452                 HDMI_QUANTIZATION_RANGE_FULL :
1453                 drm_default_rgb_quant_range(adjusted_mode);
1454
1455         /*
1456          * Internally TDA998x is using ITU-R BT.656 style sync but
1457          * we get VESA style sync. TDA998x is using a reference pixel
1458          * relative to ITU to sync to the input frame and for output
1459          * sync generation. Currently, we are using reference detection
1460          * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
1461          * which is position of rising VS with coincident rising HS.
1462          *
1463          * Now there is some issues to take care of:
1464          * - HDMI data islands require sync-before-active
1465          * - TDA998x register values must be > 0 to be enabled
1466          * - REFLINE needs an additional offset of +1
1467          * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
1468          *
1469          * So we add +1 to all horizontal and vertical register values,
1470          * plus an additional +3 for REFPIX as we are using RGB input only.
1471          */
1472         n_pix        = mode->htotal;
1473         n_line       = mode->vtotal;
1474
1475         hs_pix_e     = mode->hsync_end - mode->hdisplay;
1476         hs_pix_s     = mode->hsync_start - mode->hdisplay;
1477         de_pix_e     = mode->htotal;
1478         de_pix_s     = mode->htotal - mode->hdisplay;
1479         ref_pix      = 3 + hs_pix_s;
1480
1481         /*
1482          * Attached LCD controllers may generate broken sync. Allow
1483          * those to adjust the position of the rising VS edge by adding
1484          * HSKEW to ref_pix.
1485          */
1486         if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
1487                 ref_pix += adjusted_mode->hskew;
1488
1489         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
1490                 ref_line     = 1 + mode->vsync_start - mode->vdisplay;
1491                 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
1492                 vwin1_line_e = vwin1_line_s + mode->vdisplay;
1493                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1494                 vs1_line_s   = mode->vsync_start - mode->vdisplay;
1495                 vs1_line_e   = vs1_line_s +
1496                                mode->vsync_end - mode->vsync_start;
1497                 vwin2_line_s = vwin2_line_e = 0;
1498                 vs2_pix_s    = vs2_pix_e  = 0;
1499                 vs2_line_s   = vs2_line_e = 0;
1500         } else {
1501                 ref_line     = 1 + (mode->vsync_start - mode->vdisplay)/2;
1502                 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
1503                 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
1504                 vs1_pix_s    = vs1_pix_e = hs_pix_s;
1505                 vs1_line_s   = (mode->vsync_start - mode->vdisplay)/2;
1506                 vs1_line_e   = vs1_line_s +
1507                                (mode->vsync_end - mode->vsync_start)/2;
1508                 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
1509                 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
1510                 vs2_pix_s    = vs2_pix_e = hs_pix_s + mode->htotal/2;
1511                 vs2_line_s   = vs1_line_s + mode->vtotal/2 ;
1512                 vs2_line_e   = vs2_line_s +
1513                                (mode->vsync_end - mode->vsync_start)/2;
1514         }
1515
1516         /*
1517          * Select pixel repeat depending on the double-clock flag
1518          * (which means we have to repeat each pixel once.)
1519          */
1520         rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0;
1521         sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 |
1522                   SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0);
1523
1524         /* the TMDS clock is scaled up by the pixel repeat */
1525         tmds_clock = mode->clock * (1 + rep);
1526
1527         /*
1528          * The divisor is power-of-2. The TDA9983B datasheet gives
1529          * this as ranges of Msample/s, which is 10x the TMDS clock:
1530          *   0 - 800 to 1500 Msample/s
1531          *   1 - 400 to 800 Msample/s
1532          *   2 - 200 to 400 Msample/s
1533          *   3 - as 2 above
1534          */
1535         for (div = 0; div < 3; div++)
1536                 if (80000 >> div <= tmds_clock)
1537                         break;
1538
1539         mutex_lock(&priv->audio_mutex);
1540
1541         priv->tmds_clock = tmds_clock;
1542
1543         /* mute the audio FIFO: */
1544         reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
1545
1546         /* set HDMI HDCP mode off: */
1547         reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
1548         reg_clear(priv, REG_TX33, TX33_HDMI);
1549         reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
1550
1551         /* no pre-filter or interpolator: */
1552         reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
1553                         HVF_CNTRL_0_INTPOL(0));
1554         reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT);
1555         reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
1556         reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
1557                         VIP_CNTRL_4_BLC(0));
1558
1559         reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
1560         reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
1561                                           PLL_SERIAL_3_SRL_DE);
1562         reg_write(priv, REG_SERIALIZER, 0);
1563         reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
1564
1565         reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep));
1566         reg_write(priv, REG_SEL_CLK, sel_clk);
1567         reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
1568                         PLL_SERIAL_2_SRL_PR(rep));
1569
1570         /* set color matrix according to output rgb quant range */
1571         if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) {
1572                 static u8 tda998x_full_to_limited_range[] = {
1573                         MAT_CONTRL_MAT_SC(2),
1574                         0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1575                         0x03, 0x6f, 0x00, 0x00, 0x00, 0x00,
1576                         0x00, 0x00, 0x03, 0x6f, 0x00, 0x00,
1577                         0x00, 0x00, 0x00, 0x00, 0x03, 0x6f,
1578                         0x00, 0x40, 0x00, 0x40, 0x00, 0x40
1579                 };
1580                 reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1581                 reg_write_range(priv, REG_MAT_CONTRL,
1582                                 tda998x_full_to_limited_range,
1583                                 sizeof(tda998x_full_to_limited_range));
1584         } else {
1585                 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
1586                                         MAT_CONTRL_MAT_SC(1));
1587                 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC);
1588         }
1589
1590         /* set BIAS tmds value: */
1591         reg_write(priv, REG_ANA_GENERAL, 0x09);
1592
1593         /*
1594          * Sync on rising HSYNC/VSYNC
1595          */
1596         reg = VIP_CNTRL_3_SYNC_HS;
1597
1598         /*
1599          * TDA19988 requires high-active sync at input stage,
1600          * so invert low-active sync provided by master encoder here
1601          */
1602         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1603                 reg |= VIP_CNTRL_3_H_TGL;
1604         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1605                 reg |= VIP_CNTRL_3_V_TGL;
1606         reg_write(priv, REG_VIP_CNTRL_3, reg);
1607
1608         reg_write(priv, REG_VIDFORMAT, 0x00);
1609         reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1610         reg_write16(priv, REG_REFLINE_MSB, ref_line);
1611         reg_write16(priv, REG_NPIX_MSB, n_pix);
1612         reg_write16(priv, REG_NLINE_MSB, n_line);
1613         reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1614         reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1615         reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1616         reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1617         reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1618         reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1619         reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1620         reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1621         reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1622         reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1623         reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1624         reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1625         reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1626         reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1627         reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1628         reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
1629
1630         if (priv->rev == TDA19988) {
1631                 /* let incoming pixels fill the active space (if any) */
1632                 reg_write(priv, REG_ENABLE_SPACE, 0x00);
1633         }
1634
1635         /*
1636          * Always generate sync polarity relative to input sync and
1637          * revert input stage toggled sync at output stage
1638          */
1639         reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1640         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1641                 reg |= TBG_CNTRL_1_H_TGL;
1642         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1643                 reg |= TBG_CNTRL_1_V_TGL;
1644         reg_write(priv, REG_TBG_CNTRL_1, reg);
1645
1646         /* must be last register set: */
1647         reg_write(priv, REG_TBG_CNTRL_0, 0);
1648
1649         /* CEA-861B section 6 says that:
1650          * CEA version 1 (CEA-861) has no support for infoframes.
1651          * CEA version 2 (CEA-861A) supports version 1 AVI infoframes,
1652          * and optional basic audio.
1653          * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes,
1654          * and optional digital audio, with audio infoframes.
1655          *
1656          * Since we only support generation of version 2 AVI infoframes,
1657          * ignore CEA version 2 and below (iow, behave as if we're a
1658          * CEA-861 source.)
1659          */
1660         priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3;
1661
1662         if (priv->supports_infoframes) {
1663                 /* We need to turn HDMI HDCP stuff on to get audio through */
1664                 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1665                 reg_write(priv, REG_TBG_CNTRL_1, reg);
1666                 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1667                 reg_set(priv, REG_TX33, TX33_HDMI);
1668
1669                 tda998x_write_avi(priv, adjusted_mode);
1670                 tda998x_write_vsi(priv, adjusted_mode);
1671
1672                 if (priv->sink_has_audio)
1673                         tda998x_configure_audio(priv);
1674         }
1675
1676         mutex_unlock(&priv->audio_mutex);
1677 }
1678
1679 static const struct drm_bridge_funcs tda998x_bridge_funcs = {
1680         .attach = tda998x_bridge_attach,
1681         .detach = tda998x_bridge_detach,
1682         .mode_valid = tda998x_bridge_mode_valid,
1683         .disable = tda998x_bridge_disable,
1684         .mode_set = tda998x_bridge_mode_set,
1685         .enable = tda998x_bridge_enable,
1686 };
1687
1688 /* I2C driver functions */
1689
1690 static int tda998x_get_audio_ports(struct tda998x_priv *priv,
1691                                    struct device_node *np)
1692 {
1693         const u32 *port_data;
1694         u32 size;
1695         int i;
1696
1697         port_data = of_get_property(np, "audio-ports", &size);
1698         if (!port_data)
1699                 return 0;
1700
1701         size /= sizeof(u32);
1702         if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) {
1703                 dev_err(&priv->hdmi->dev,
1704                         "Bad number of elements in audio-ports dt-property\n");
1705                 return -EINVAL;
1706         }
1707
1708         size /= 2;
1709
1710         for (i = 0; i < size; i++) {
1711                 unsigned int route;
1712                 u8 afmt = be32_to_cpup(&port_data[2*i]);
1713                 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]);
1714
1715                 switch (afmt) {
1716                 case AFMT_I2S:
1717                         route = AUDIO_ROUTE_I2S;
1718                         break;
1719                 case AFMT_SPDIF:
1720                         route = AUDIO_ROUTE_SPDIF;
1721                         break;
1722                 default:
1723                         dev_err(&priv->hdmi->dev,
1724                                 "Bad audio format %u\n", afmt);
1725                         return -EINVAL;
1726                 }
1727
1728                 if (!ena_ap) {
1729                         dev_err(&priv->hdmi->dev, "invalid zero port config\n");
1730                         continue;
1731                 }
1732
1733                 if (priv->audio_port_enable[route]) {
1734                         dev_err(&priv->hdmi->dev,
1735                                 "%s format already configured\n",
1736                                 route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S");
1737                         return -EINVAL;
1738                 }
1739
1740                 priv->audio_port_enable[route] = ena_ap;
1741         }
1742         return 0;
1743 }
1744
1745 static int tda998x_set_config(struct tda998x_priv *priv,
1746                               const struct tda998x_encoder_params *p)
1747 {
1748         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
1749                             (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
1750                             VIP_CNTRL_0_SWAP_B(p->swap_b) |
1751                             (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
1752         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
1753                             (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
1754                             VIP_CNTRL_1_SWAP_D(p->swap_d) |
1755                             (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
1756         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
1757                             (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
1758                             VIP_CNTRL_2_SWAP_F(p->swap_f) |
1759                             (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
1760
1761         if (p->audio_params.format != AFMT_UNUSED) {
1762                 unsigned int ratio, route;
1763                 bool spdif = p->audio_params.format == AFMT_SPDIF;
1764
1765                 route = AUDIO_ROUTE_I2S + spdif;
1766
1767                 priv->audio.route = &tda998x_audio_route[route];
1768                 priv->audio.cea = p->audio_params.cea;
1769                 priv->audio.sample_rate = p->audio_params.sample_rate;
1770                 memcpy(priv->audio.status, p->audio_params.status,
1771                        min(sizeof(priv->audio.status),
1772                            sizeof(p->audio_params.status)));
1773                 priv->audio.ena_ap = p->audio_params.config;
1774                 priv->audio.i2s_format = I2S_FORMAT_PHILIPS;
1775
1776                 ratio = spdif ? 64 : p->audio_params.sample_width * 2;
1777                 return tda998x_derive_cts_n(priv, &priv->audio, ratio);
1778         }
1779
1780         return 0;
1781 }
1782
1783 static void tda998x_destroy(struct device *dev)
1784 {
1785         struct tda998x_priv *priv = dev_get_drvdata(dev);
1786
1787         drm_bridge_remove(&priv->bridge);
1788
1789         /* disable all IRQs and free the IRQ handler */
1790         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1791         reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1792
1793         if (priv->audio_pdev)
1794                 platform_device_unregister(priv->audio_pdev);
1795
1796         if (priv->hdmi->irq)
1797                 free_irq(priv->hdmi->irq, priv);
1798
1799         del_timer_sync(&priv->edid_delay_timer);
1800         cancel_work_sync(&priv->detect_work);
1801
1802         i2c_unregister_device(priv->cec);
1803
1804         cec_notifier_conn_unregister(priv->cec_notify);
1805 }
1806
1807 static int tda998x_create(struct device *dev)
1808 {
1809         struct i2c_client *client = to_i2c_client(dev);
1810         struct device_node *np = client->dev.of_node;
1811         struct i2c_board_info cec_info;
1812         struct tda998x_priv *priv;
1813         u32 video;
1814         int rev_lo, rev_hi, ret;
1815
1816         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1817         if (!priv)
1818                 return -ENOMEM;
1819
1820         dev_set_drvdata(dev, priv);
1821
1822         mutex_init(&priv->mutex);       /* protect the page access */
1823         mutex_init(&priv->audio_mutex); /* protect access from audio thread */
1824         mutex_init(&priv->edid_mutex);
1825         INIT_LIST_HEAD(&priv->bridge.list);
1826         init_waitqueue_head(&priv->edid_delay_waitq);
1827         timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0);
1828         INIT_WORK(&priv->detect_work, tda998x_detect_work);
1829
1830         priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1831         priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1832         priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1833
1834         /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1835         priv->cec_addr = 0x34 + (client->addr & 0x03);
1836         priv->current_page = 0xff;
1837         priv->hdmi = client;
1838
1839         /* wake up the device: */
1840         cec_write(priv, REG_CEC_ENAMODS,
1841                         CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1842
1843         tda998x_reset(priv);
1844
1845         /* read version: */
1846         rev_lo = reg_read(priv, REG_VERSION_LSB);
1847         if (rev_lo < 0) {
1848                 dev_err(dev, "failed to read version: %d\n", rev_lo);
1849                 return rev_lo;
1850         }
1851
1852         rev_hi = reg_read(priv, REG_VERSION_MSB);
1853         if (rev_hi < 0) {
1854                 dev_err(dev, "failed to read version: %d\n", rev_hi);
1855                 return rev_hi;
1856         }
1857
1858         priv->rev = rev_lo | rev_hi << 8;
1859
1860         /* mask off feature bits: */
1861         priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1862
1863         switch (priv->rev) {
1864         case TDA9989N2:
1865                 dev_info(dev, "found TDA9989 n2");
1866                 break;
1867         case TDA19989:
1868                 dev_info(dev, "found TDA19989");
1869                 break;
1870         case TDA19989N2:
1871                 dev_info(dev, "found TDA19989 n2");
1872                 break;
1873         case TDA19988:
1874                 dev_info(dev, "found TDA19988");
1875                 break;
1876         default:
1877                 dev_err(dev, "found unsupported device: %04x\n", priv->rev);
1878                 return -ENXIO;
1879         }
1880
1881         /* after reset, enable DDC: */
1882         reg_write(priv, REG_DDC_DISABLE, 0x00);
1883
1884         /* set clock on DDC channel: */
1885         reg_write(priv, REG_TX3, 39);
1886
1887         /* if necessary, disable multi-master: */
1888         if (priv->rev == TDA19989)
1889                 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
1890
1891         cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
1892                         CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1893
1894         /* ensure interrupts are disabled */
1895         cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1896
1897         /* clear pending interrupts */
1898         cec_read(priv, REG_CEC_RXSHPDINT);
1899         reg_read(priv, REG_INT_FLAGS_0);
1900         reg_read(priv, REG_INT_FLAGS_1);
1901         reg_read(priv, REG_INT_FLAGS_2);
1902
1903         /* initialize the optional IRQ */
1904         if (client->irq) {
1905                 unsigned long irq_flags;
1906
1907                 /* init read EDID waitqueue and HDP work */
1908                 init_waitqueue_head(&priv->wq_edid);
1909
1910                 irq_flags =
1911                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1912
1913                 priv->cec_glue.irq_flags = irq_flags;
1914
1915                 irq_flags |= IRQF_SHARED | IRQF_ONESHOT;
1916                 ret = request_threaded_irq(client->irq, NULL,
1917                                            tda998x_irq_thread, irq_flags,
1918                                            "tda998x", priv);
1919                 if (ret) {
1920                         dev_err(dev, "failed to request IRQ#%u: %d\n",
1921                                 client->irq, ret);
1922                         goto err_irq;
1923                 }
1924
1925                 /* enable HPD irq */
1926                 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1927         }
1928
1929         priv->cec_notify = cec_notifier_conn_register(dev, NULL, NULL);
1930         if (!priv->cec_notify) {
1931                 ret = -ENOMEM;
1932                 goto fail;
1933         }
1934
1935         priv->cec_glue.parent = dev;
1936         priv->cec_glue.data = priv;
1937         priv->cec_glue.init = tda998x_cec_hook_init;
1938         priv->cec_glue.exit = tda998x_cec_hook_exit;
1939         priv->cec_glue.open = tda998x_cec_hook_open;
1940         priv->cec_glue.release = tda998x_cec_hook_release;
1941
1942         /*
1943          * Some TDA998x are actually two I2C devices merged onto one piece
1944          * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter
1945          * with a slightly modified TDA9950 CEC device.  The CEC device
1946          * is at the TDA9950 address, with the address pins strapped across
1947          * to the TDA998x address pins.  Hence, it always has the same
1948          * offset.
1949          */
1950         memset(&cec_info, 0, sizeof(cec_info));
1951         strlcpy(cec_info.type, "tda9950", sizeof(cec_info.type));
1952         cec_info.addr = priv->cec_addr;
1953         cec_info.platform_data = &priv->cec_glue;
1954         cec_info.irq = client->irq;
1955
1956         priv->cec = i2c_new_client_device(client->adapter, &cec_info);
1957         if (IS_ERR(priv->cec)) {
1958                 ret = PTR_ERR(priv->cec);
1959                 goto fail;
1960         }
1961
1962         /* enable EDID read irq: */
1963         reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1964
1965         if (np) {
1966                 /* get the device tree parameters */
1967                 ret = of_property_read_u32(np, "video-ports", &video);
1968                 if (ret == 0) {
1969                         priv->vip_cntrl_0 = video >> 16;
1970                         priv->vip_cntrl_1 = video >> 8;
1971                         priv->vip_cntrl_2 = video;
1972                 }
1973
1974                 ret = tda998x_get_audio_ports(priv, np);
1975                 if (ret)
1976                         goto fail;
1977
1978                 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] ||
1979                     priv->audio_port_enable[AUDIO_ROUTE_SPDIF])
1980                         tda998x_audio_codec_init(priv, &client->dev);
1981         } else if (dev->platform_data) {
1982                 ret = tda998x_set_config(priv, dev->platform_data);
1983                 if (ret)
1984                         goto fail;
1985         }
1986
1987         priv->bridge.funcs = &tda998x_bridge_funcs;
1988 #ifdef CONFIG_OF
1989         priv->bridge.of_node = dev->of_node;
1990 #endif
1991
1992         drm_bridge_add(&priv->bridge);
1993
1994         return 0;
1995
1996 fail:
1997         tda998x_destroy(dev);
1998 err_irq:
1999         return ret;
2000 }
2001
2002 /* DRM encoder functions */
2003
2004 static int tda998x_encoder_init(struct device *dev, struct drm_device *drm)
2005 {
2006         struct tda998x_priv *priv = dev_get_drvdata(dev);
2007         u32 crtcs = 0;
2008         int ret;
2009
2010         if (dev->of_node)
2011                 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
2012
2013         /* If no CRTCs were found, fall back to our old behaviour */
2014         if (crtcs == 0) {
2015                 dev_warn(dev, "Falling back to first CRTC\n");
2016                 crtcs = 1 << 0;
2017         }
2018
2019         priv->encoder.possible_crtcs = crtcs;
2020
2021         ret = drm_simple_encoder_init(drm, &priv->encoder,
2022                                       DRM_MODE_ENCODER_TMDS);
2023         if (ret)
2024                 goto err_encoder;
2025
2026         ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL, 0);
2027         if (ret)
2028                 goto err_bridge;
2029
2030         return 0;
2031
2032 err_bridge:
2033         drm_encoder_cleanup(&priv->encoder);
2034 err_encoder:
2035         return ret;
2036 }
2037
2038 static int tda998x_bind(struct device *dev, struct device *master, void *data)
2039 {
2040         struct drm_device *drm = data;
2041
2042         return tda998x_encoder_init(dev, drm);
2043 }
2044
2045 static void tda998x_unbind(struct device *dev, struct device *master,
2046                            void *data)
2047 {
2048         struct tda998x_priv *priv = dev_get_drvdata(dev);
2049
2050         drm_encoder_cleanup(&priv->encoder);
2051 }
2052
2053 static const struct component_ops tda998x_ops = {
2054         .bind = tda998x_bind,
2055         .unbind = tda998x_unbind,
2056 };
2057
2058 static int
2059 tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
2060 {
2061         int ret;
2062
2063         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
2064                 dev_warn(&client->dev, "adapter does not support I2C\n");
2065                 return -EIO;
2066         }
2067
2068         ret = tda998x_create(&client->dev);
2069         if (ret)
2070                 return ret;
2071
2072         ret = component_add(&client->dev, &tda998x_ops);
2073         if (ret)
2074                 tda998x_destroy(&client->dev);
2075         return ret;
2076 }
2077
2078 static int tda998x_remove(struct i2c_client *client)
2079 {
2080         component_del(&client->dev, &tda998x_ops);
2081         tda998x_destroy(&client->dev);
2082         return 0;
2083 }
2084
2085 #ifdef CONFIG_OF
2086 static const struct of_device_id tda998x_dt_ids[] = {
2087         { .compatible = "nxp,tda998x", },
2088         { }
2089 };
2090 MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
2091 #endif
2092
2093 static const struct i2c_device_id tda998x_ids[] = {
2094         { "tda998x", 0 },
2095         { }
2096 };
2097 MODULE_DEVICE_TABLE(i2c, tda998x_ids);
2098
2099 static struct i2c_driver tda998x_driver = {
2100         .probe = tda998x_probe,
2101         .remove = tda998x_remove,
2102         .driver = {
2103                 .name = "tda998x",
2104                 .of_match_table = of_match_ptr(tda998x_dt_ids),
2105         },
2106         .id_table = tda998x_ids,
2107 };
2108
2109 module_i2c_driver(tda998x_driver);
2110
2111 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
2112 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
2113 MODULE_LICENSE("GPL");