1 /**************************************************************************
2 * Copyright (c) 2007, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
19 * develop this driver.
21 **************************************************************************/
28 #include "psb_intel_reg.h"
31 #include "mdfld_output.h"
38 psb_pipestat(int pipe)
50 mid_pipe_event(int pipe)
53 return _PSB_PIPEA_EVENT_FLAG;
55 return _MDFLD_PIPEB_EVENT_FLAG;
57 return _MDFLD_PIPEC_EVENT_FLAG;
62 mid_pipe_vsync(int pipe)
65 return _PSB_VSYNC_PIPEA_FLAG;
67 return _PSB_VSYNC_PIPEB_FLAG;
69 return _MDFLD_PIPEC_VBLANK_FLAG;
74 mid_pipeconf(int pipe)
86 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
88 if ((dev_priv->pipestat[pipe] & mask) != mask) {
89 u32 reg = psb_pipestat(pipe);
90 dev_priv->pipestat[pipe] |= mask;
91 /* Enable the interrupt, clear any pending status */
92 if (gma_power_begin(dev_priv->dev, false)) {
93 u32 writeVal = PSB_RVDC32(reg);
94 writeVal |= (mask | (mask >> 16));
95 PSB_WVDC32(writeVal, reg);
96 (void) PSB_RVDC32(reg);
97 gma_power_end(dev_priv->dev);
103 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask)
105 if ((dev_priv->pipestat[pipe] & mask) != 0) {
106 u32 reg = psb_pipestat(pipe);
107 dev_priv->pipestat[pipe] &= ~mask;
108 if (gma_power_begin(dev_priv->dev, false)) {
109 u32 writeVal = PSB_RVDC32(reg);
111 PSB_WVDC32(writeVal, reg);
112 (void) PSB_RVDC32(reg);
113 gma_power_end(dev_priv->dev);
118 static void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
120 if (gma_power_begin(dev_priv->dev, false)) {
121 u32 pipe_event = mid_pipe_event(pipe);
122 dev_priv->vdc_irq_mask |= pipe_event;
123 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
124 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
125 gma_power_end(dev_priv->dev);
129 static void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
131 if (dev_priv->pipestat[pipe] == 0) {
132 if (gma_power_begin(dev_priv->dev, false)) {
133 u32 pipe_event = mid_pipe_event(pipe);
134 dev_priv->vdc_irq_mask &= ~pipe_event;
135 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
136 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
137 gma_power_end(dev_priv->dev);
143 * Display controller interrupt handler for pipe event.
146 static void mid_pipe_event_handler(struct drm_device *dev, int pipe)
148 struct drm_psb_private *dev_priv =
149 (struct drm_psb_private *) dev->dev_private;
151 uint32_t pipe_stat_val = 0;
152 uint32_t pipe_stat_reg = psb_pipestat(pipe);
153 uint32_t pipe_enable = dev_priv->pipestat[pipe];
154 uint32_t pipe_status = dev_priv->pipestat[pipe] >> 16;
158 spin_lock(&dev_priv->irqmask_lock);
160 pipe_stat_val = PSB_RVDC32(pipe_stat_reg);
161 pipe_stat_val &= pipe_enable | pipe_status;
162 pipe_stat_val &= pipe_stat_val >> 16;
164 spin_unlock(&dev_priv->irqmask_lock);
166 /* Clear the 2nd level interrupt status bits
167 * Sometimes the bits are very sticky so we repeat until they unstick */
168 for (i = 0; i < 0xffff; i++) {
169 PSB_WVDC32(PSB_RVDC32(pipe_stat_reg), pipe_stat_reg);
170 pipe_clear = PSB_RVDC32(pipe_stat_reg) & pipe_status;
178 "%s, can't clear status bits for pipe %d, its value = 0x%x.\n",
179 __func__, pipe, PSB_RVDC32(pipe_stat_reg));
181 if (pipe_stat_val & PIPE_VBLANK_STATUS)
182 drm_handle_vblank(dev, pipe);
184 if (pipe_stat_val & PIPE_TE_STATUS)
185 drm_handle_vblank(dev, pipe);
189 * Display controller interrupt handler.
191 static void psb_vdc_interrupt(struct drm_device *dev, uint32_t vdc_stat)
193 if (vdc_stat & _PSB_IRQ_ASLE)
194 psb_intel_opregion_asle_intr(dev);
196 if (vdc_stat & _PSB_VSYNC_PIPEA_FLAG)
197 mid_pipe_event_handler(dev, 0);
199 if (vdc_stat & _PSB_VSYNC_PIPEB_FLAG)
200 mid_pipe_event_handler(dev, 1);
204 * SGX interrupt handler
206 static void psb_sgx_interrupt(struct drm_device *dev, u32 stat_1, u32 stat_2)
208 struct drm_psb_private *dev_priv = dev->dev_private;
212 if (stat_1 & _PSB_CE_TWOD_COMPLETE)
213 val = PSB_RSGX32(PSB_CR_2D_BLIT_STATUS);
215 if (stat_2 & _PSB_CE2_BIF_REQUESTER_FAULT) {
216 val = PSB_RSGX32(PSB_CR_BIF_INT_STAT);
217 addr = PSB_RSGX32(PSB_CR_BIF_FAULT);
219 if (val & _PSB_CBI_STAT_PF_N_RW)
220 DRM_ERROR("SGX MMU page fault:");
222 DRM_ERROR("SGX MMU read / write protection fault:");
224 if (val & _PSB_CBI_STAT_FAULT_CACHE)
225 DRM_ERROR("\tCache requestor");
226 if (val & _PSB_CBI_STAT_FAULT_TA)
227 DRM_ERROR("\tTA requestor");
228 if (val & _PSB_CBI_STAT_FAULT_VDM)
229 DRM_ERROR("\tVDM requestor");
230 if (val & _PSB_CBI_STAT_FAULT_2D)
231 DRM_ERROR("\t2D requestor");
232 if (val & _PSB_CBI_STAT_FAULT_PBE)
233 DRM_ERROR("\tPBE requestor");
234 if (val & _PSB_CBI_STAT_FAULT_TSP)
235 DRM_ERROR("\tTSP requestor");
236 if (val & _PSB_CBI_STAT_FAULT_ISP)
237 DRM_ERROR("\tISP requestor");
238 if (val & _PSB_CBI_STAT_FAULT_USSEPDS)
239 DRM_ERROR("\tUSSEPDS requestor");
240 if (val & _PSB_CBI_STAT_FAULT_HOST)
241 DRM_ERROR("\tHost requestor");
243 DRM_ERROR("\tMMU failing address is 0x%08x.\n",
250 PSB_WSGX32(stat_1, PSB_CR_EVENT_HOST_CLEAR);
251 PSB_WSGX32(stat_2, PSB_CR_EVENT_HOST_CLEAR2);
252 PSB_RSGX32(PSB_CR_EVENT_HOST_CLEAR2);
255 irqreturn_t psb_irq_handler(int irq, void *arg)
257 struct drm_device *dev = arg;
258 struct drm_psb_private *dev_priv = dev->dev_private;
259 uint32_t vdc_stat, dsp_int = 0, sgx_int = 0, hotplug_int = 0;
260 u32 sgx_stat_1, sgx_stat_2;
263 spin_lock(&dev_priv->irqmask_lock);
265 vdc_stat = PSB_RVDC32(PSB_INT_IDENTITY_R);
267 if (vdc_stat & (_PSB_PIPE_EVENT_FLAG|_PSB_IRQ_ASLE))
270 /* FIXME: Handle Medfield
271 if (vdc_stat & _MDFLD_DISP_ALL_IRQ_FLAG)
275 if (vdc_stat & _PSB_IRQ_SGX_FLAG)
277 if (vdc_stat & _PSB_IRQ_DISP_HOTSYNC)
280 vdc_stat &= dev_priv->vdc_irq_mask;
281 spin_unlock(&dev_priv->irqmask_lock);
283 if (dsp_int && gma_power_is_on(dev)) {
284 psb_vdc_interrupt(dev, vdc_stat);
289 sgx_stat_1 = PSB_RSGX32(PSB_CR_EVENT_STATUS);
290 sgx_stat_2 = PSB_RSGX32(PSB_CR_EVENT_STATUS2);
291 psb_sgx_interrupt(dev, sgx_stat_1, sgx_stat_2);
295 /* Note: this bit has other meanings on some devices, so we will
296 need to address that later if it ever matters */
297 if (hotplug_int && dev_priv->ops->hotplug) {
298 handled = dev_priv->ops->hotplug(dev);
299 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
302 PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
303 (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
312 void psb_irq_preinstall(struct drm_device *dev)
314 struct drm_psb_private *dev_priv =
315 (struct drm_psb_private *) dev->dev_private;
316 unsigned long irqflags;
318 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
320 if (gma_power_is_on(dev)) {
321 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
322 PSB_WVDC32(0x00000000, PSB_INT_MASK_R);
323 PSB_WVDC32(0x00000000, PSB_INT_ENABLE_R);
324 PSB_WSGX32(0x00000000, PSB_CR_EVENT_HOST_ENABLE);
325 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE);
327 if (dev->vblank[0].enabled)
328 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
329 if (dev->vblank[1].enabled)
330 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
332 /* FIXME: Handle Medfield irq mask
333 if (dev->vblank[1].enabled)
334 dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
335 if (dev->vblank[2].enabled)
336 dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
339 /* Revisit this area - want per device masks ? */
340 if (dev_priv->ops->hotplug)
341 dev_priv->vdc_irq_mask |= _PSB_IRQ_DISP_HOTSYNC;
342 dev_priv->vdc_irq_mask |= _PSB_IRQ_ASLE | _PSB_IRQ_SGX_FLAG;
344 /* This register is safe even if display island is off */
345 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
346 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
349 int psb_irq_postinstall(struct drm_device *dev)
351 struct drm_psb_private *dev_priv = dev->dev_private;
352 unsigned long irqflags;
355 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
357 /* Enable 2D and MMU fault interrupts */
358 PSB_WSGX32(_PSB_CE2_BIF_REQUESTER_FAULT, PSB_CR_EVENT_HOST_ENABLE2);
359 PSB_WSGX32(_PSB_CE_TWOD_COMPLETE, PSB_CR_EVENT_HOST_ENABLE);
360 PSB_RSGX32(PSB_CR_EVENT_HOST_ENABLE); /* Post */
362 /* This register is safe even if display island is off */
363 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
364 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
366 for (i = 0; i < dev->num_crtcs; ++i) {
367 if (dev->vblank[i].enabled)
368 psb_enable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
370 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
373 if (dev_priv->ops->hotplug_enable)
374 dev_priv->ops->hotplug_enable(dev, true);
376 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
380 void psb_irq_uninstall(struct drm_device *dev)
382 struct drm_psb_private *dev_priv = dev->dev_private;
383 unsigned long irqflags;
386 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
388 if (dev_priv->ops->hotplug_enable)
389 dev_priv->ops->hotplug_enable(dev, false);
391 PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
393 for (i = 0; i < dev->num_crtcs; ++i) {
394 if (dev->vblank[i].enabled)
395 psb_disable_pipestat(dev_priv, i, PIPE_VBLANK_INTERRUPT_ENABLE);
398 dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
399 _PSB_IRQ_MSVDX_FLAG |
402 /* These two registers are safe even if display island is off */
403 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
404 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
408 /* This register is safe even if display island is off */
409 PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
410 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
413 void psb_irq_turn_on_dpst(struct drm_device *dev)
415 struct drm_psb_private *dev_priv =
416 (struct drm_psb_private *) dev->dev_private;
420 if (gma_power_begin(dev, false)) {
421 PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
422 hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
423 PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
424 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
426 PSB_WVDC32(0x80010100, PWM_CONTROL_LOGIC);
427 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
428 PSB_WVDC32(pwm_reg | PWM_PHASEIN_ENABLE
429 | PWM_PHASEIN_INT_ENABLE,
431 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
433 psb_enable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
435 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
436 PSB_WVDC32(hist_reg | HISTOGRAM_INT_CTRL_CLEAR,
437 HISTOGRAM_INT_CONTROL);
438 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
439 PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
446 int psb_irq_enable_dpst(struct drm_device *dev)
448 struct drm_psb_private *dev_priv =
449 (struct drm_psb_private *) dev->dev_private;
450 unsigned long irqflags;
452 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
455 mid_enable_pipe_event(dev_priv, 0);
456 psb_irq_turn_on_dpst(dev);
458 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
462 void psb_irq_turn_off_dpst(struct drm_device *dev)
464 struct drm_psb_private *dev_priv =
465 (struct drm_psb_private *) dev->dev_private;
469 if (gma_power_begin(dev, false)) {
470 PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
471 hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
473 psb_disable_pipestat(dev_priv, 0, PIPE_DPST_EVENT_ENABLE);
475 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
476 PSB_WVDC32(pwm_reg & ~PWM_PHASEIN_INT_ENABLE,
478 pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
484 int psb_irq_disable_dpst(struct drm_device *dev)
486 struct drm_psb_private *dev_priv =
487 (struct drm_psb_private *) dev->dev_private;
488 unsigned long irqflags;
490 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
492 mid_disable_pipe_event(dev_priv, 0);
493 psb_irq_turn_off_dpst(dev);
495 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
501 * It is used to enable VBLANK interrupt
503 int psb_enable_vblank(struct drm_device *dev, unsigned int pipe)
505 struct drm_psb_private *dev_priv = dev->dev_private;
506 unsigned long irqflags;
507 uint32_t reg_val = 0;
508 uint32_t pipeconf_reg = mid_pipeconf(pipe);
510 /* Medfield is different - we should perhaps extract out vblank
511 and blacklight etc ops */
513 return mdfld_enable_te(dev, pipe);
515 if (gma_power_begin(dev, false)) {
516 reg_val = REG_READ(pipeconf_reg);
520 if (!(reg_val & PIPEACONF_ENABLE))
523 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
526 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEA_FLAG;
528 dev_priv->vdc_irq_mask |= _PSB_VSYNC_PIPEB_FLAG;
530 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
531 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
532 psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
534 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
540 * It is used to disable VBLANK interrupt
542 void psb_disable_vblank(struct drm_device *dev, unsigned int pipe)
544 struct drm_psb_private *dev_priv = dev->dev_private;
545 unsigned long irqflags;
548 mdfld_disable_te(dev, pipe);
549 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
552 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEA_FLAG;
554 dev_priv->vdc_irq_mask &= ~_PSB_VSYNC_PIPEB_FLAG;
556 PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
557 PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
558 psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
560 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
564 * It is used to enable TE interrupt
566 int mdfld_enable_te(struct drm_device *dev, int pipe)
568 struct drm_psb_private *dev_priv =
569 (struct drm_psb_private *) dev->dev_private;
570 unsigned long irqflags;
571 uint32_t reg_val = 0;
572 uint32_t pipeconf_reg = mid_pipeconf(pipe);
574 if (gma_power_begin(dev, false)) {
575 reg_val = REG_READ(pipeconf_reg);
579 if (!(reg_val & PIPEACONF_ENABLE))
582 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
584 mid_enable_pipe_event(dev_priv, pipe);
585 psb_enable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
587 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
593 * It is used to disable TE interrupt
595 void mdfld_disable_te(struct drm_device *dev, int pipe)
597 struct drm_psb_private *dev_priv =
598 (struct drm_psb_private *) dev->dev_private;
599 unsigned long irqflags;
601 if (!dev_priv->dsr_enable)
604 spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
606 mid_disable_pipe_event(dev_priv, pipe);
607 psb_disable_pipestat(dev_priv, pipe, PIPE_TE_ENABLE);
609 spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
612 /* Called from drm generic code, passed a 'crtc', which
613 * we use as a pipe index
615 u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe)
617 uint32_t high_frame = PIPEAFRAMEHIGH;
618 uint32_t low_frame = PIPEAFRAMEPIXEL;
619 uint32_t pipeconf_reg = PIPEACONF;
620 uint32_t reg_val = 0;
621 uint32_t high1 = 0, high2 = 0, low = 0, count = 0;
627 high_frame = PIPEBFRAMEHIGH;
628 low_frame = PIPEBFRAMEPIXEL;
629 pipeconf_reg = PIPEBCONF;
632 high_frame = PIPECFRAMEHIGH;
633 low_frame = PIPECFRAMEPIXEL;
634 pipeconf_reg = PIPECCONF;
637 dev_err(dev->dev, "%s, invalid pipe.\n", __func__);
641 if (!gma_power_begin(dev, false))
644 reg_val = REG_READ(pipeconf_reg);
646 if (!(reg_val & PIPEACONF_ENABLE)) {
647 dev_err(dev->dev, "trying to get vblank count for disabled pipe %u\n",
649 goto psb_get_vblank_counter_exit;
653 * High & low register fields aren't synchronized, so make sure
654 * we get a low value that's stable across two reads of the high
658 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
659 PIPE_FRAME_HIGH_SHIFT);
660 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
661 PIPE_FRAME_LOW_SHIFT);
662 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
663 PIPE_FRAME_HIGH_SHIFT);
664 } while (high1 != high2);
666 count = (high1 << 8) | low;
668 psb_get_vblank_counter_exit: