drivers/gpu/drm/gma500/mid_bios.c

   1 /**************************************************************************
   2  * Copyright (c) 2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 /* TODO
  21  * - Split functions by vbt type
  22  * - Make them all take drm_device
  23  * - Check ioremap failures
  24  */
  25
  26 #include <drm/drmP.h>
  27 #include <drm/drm.h>
  28 #include <drm/gma_drm.h>
  29 #include "psb_drv.h"
  30 #include "mid_bios.h"
  31
  32 static void mid_get_fuse_settings(struct drm_device *dev)
  33 {
  34         struct drm_psb_private *dev_priv = dev->dev_private;
  35         struct pci_dev *pci_root =
  36                 pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
  37                                             0, 0);
  38         uint32_t fuse_value = 0;
  39         uint32_t fuse_value_tmp = 0;
  40
  41 #define FB_REG06 0xD0810600
  42 #define FB_MIPI_DISABLE  (1 << 11)
  43 #define FB_REG09 0xD0810900
  44 #define FB_SKU_MASK  0x7000
  45 #define FB_SKU_SHIFT 12
  46 #define FB_SKU_100 0
  47 #define FB_SKU_100L 1
  48 #define FB_SKU_83 2
  49         if (pci_root == NULL) {
  50                 WARN_ON(1);
  51                 return;
  52         }
  53
  54
  55         pci_write_config_dword(pci_root, 0xD0, FB_REG06);
  56         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
  57
  58         /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
  59         if (IS_MRST(dev))
  60                 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
  61
  62         DRM_INFO("internal display is %s\n",
  63                  dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
  64
  65          /* Prevent runtime suspend at start*/
  66          if (dev_priv->iLVDS_enable) {
  67                 dev_priv->is_lvds_on = true;
  68                 dev_priv->is_mipi_on = false;
  69         } else {
  70                 dev_priv->is_mipi_on = true;
  71                 dev_priv->is_lvds_on = false;
  72         }
  73
  74         dev_priv->video_device_fuse = fuse_value;
  75
  76         pci_write_config_dword(pci_root, 0xD0, FB_REG09);
  77         pci_read_config_dword(pci_root, 0xD4, &fuse_value);
  78
  79         dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
  80         fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
  81
  82         dev_priv->fuse_reg_value = fuse_value;
  83
  84         switch (fuse_value_tmp) {
  85         case FB_SKU_100:
  86                 dev_priv->core_freq = 200;
  87                 break;
  88         case FB_SKU_100L:
  89                 dev_priv->core_freq = 100;
  90                 break;
  91         case FB_SKU_83:
  92                 dev_priv->core_freq = 166;
  93                 break;
  94         default:
  95                 dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
  96                                                                 fuse_value_tmp);
  97                 dev_priv->core_freq = 0;
  98         }
  99         dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
 100         pci_dev_put(pci_root);
 101 }
 102
 103 /*
 104  *      Get the revison ID, B0:D2:F0;0x08
 105  */
 106 static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
 107 {
 108         uint32_t platform_rev_id = 0;
 109         int domain = pci_domain_nr(dev_priv->dev->pdev->bus);
 110         struct pci_dev *pci_gfx_root =
 111                 pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(2, 0));
 112
 113         if (pci_gfx_root == NULL) {
 114                 WARN_ON(1);
 115                 return;
 116         }
 117         pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
 118         dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
 119         pci_dev_put(pci_gfx_root);
 120         dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
 121                                         dev_priv->platform_rev_id);
 122 }
 123
 124 struct mid_vbt_header {
 125         u32 signature;
 126         u8 revision;
 127 } __packed;
 128
 129 /* The same for r0 and r1 */
 130 struct vbt_r0 {
 131         struct mid_vbt_header vbt_header;
 132         u8 size;
 133         u8 checksum;
 134 } __packed;
 135
 136 struct vbt_r10 {
 137         struct mid_vbt_header vbt_header;
 138         u8 checksum;
 139         u16 size;
 140         u8 panel_count;
 141         u8 primary_panel_idx;
 142         u8 secondary_panel_idx;
 143         u8 __reserved[5];
 144 } __packed;
 145
 146 static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt)
 147 {
 148         void __iomem *vbt_virtual;
 149
 150         vbt_virtual = ioremap(addr, sizeof(*vbt));
 151         if (vbt_virtual == NULL)
 152                 return -1;
 153
 154         memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
 155         iounmap(vbt_virtual);
 156
 157         return 0;
 158 }
 159
 160 static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt)
 161 {
 162         void __iomem *vbt_virtual;
 163
 164         vbt_virtual = ioremap(addr, sizeof(*vbt));
 165         if (!vbt_virtual)
 166                 return -1;
 167
 168         memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
 169         iounmap(vbt_virtual);
 170
 171         return 0;
 172 }
 173
 174 static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr)
 175 {
 176         struct vbt_r0 vbt;
 177         void __iomem *gct_virtual;
 178         struct gct_r0 gct;
 179         u8 bpi;
 180
 181         if (read_vbt_r0(addr, &vbt))
 182                 return -1;
 183
 184         gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
 185         if (!gct_virtual)
 186                 return -1;
 187         memcpy_fromio(&gct, gct_virtual, sizeof(gct));
 188         iounmap(gct_virtual);
 189
 190         bpi = gct.PD.BootPanelIndex;
 191         dev_priv->gct_data.bpi = bpi;
 192         dev_priv->gct_data.pt = gct.PD.PanelType;
 193         dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
 194         dev_priv->gct_data.Panel_Port_Control =
 195                 gct.panel[bpi].Panel_Port_Control;
 196         dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 197                 gct.panel[bpi].Panel_MIPI_Display_Descriptor;
 198
 199         return 0;
 200 }
 201
 202 static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr)
 203 {
 204         struct vbt_r0 vbt;
 205         void __iomem *gct_virtual;
 206         struct gct_r1 gct;
 207         u8 bpi;
 208
 209         if (read_vbt_r0(addr, &vbt))
 210                 return -1;
 211
 212         gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
 213         if (!gct_virtual)
 214                 return -1;
 215         memcpy_fromio(&gct, gct_virtual, sizeof(gct));
 216         iounmap(gct_virtual);
 217
 218         bpi = gct.PD.BootPanelIndex;
 219         dev_priv->gct_data.bpi = bpi;
 220         dev_priv->gct_data.pt = gct.PD.PanelType;
 221         dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
 222         dev_priv->gct_data.Panel_Port_Control =
 223                 gct.panel[bpi].Panel_Port_Control;
 224         dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 225                 gct.panel[bpi].Panel_MIPI_Display_Descriptor;
 226
 227         return 0;
 228 }
 229
 230 static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)
 231 {
 232         struct vbt_r10 vbt;
 233         void __iomem *gct_virtual;
 234         struct gct_r10 *gct;
 235         struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
 236         struct gct_r10_timing_info *ti;
 237         int ret = -1;
 238
 239         if (read_vbt_r10(addr, &vbt))
 240                 return -1;
 241
 242         gct = kmalloc_array(vbt.panel_count, sizeof(*gct), GFP_KERNEL);
 243         if (!gct)
 244                 return -ENOMEM;
 245
 246         gct_virtual = ioremap(addr + sizeof(vbt),
 247                         sizeof(*gct) * vbt.panel_count);
 248         if (!gct_virtual)
 249                 goto out;
 250         memcpy_fromio(gct, gct_virtual, sizeof(*gct));
 251         iounmap(gct_virtual);
 252
 253         dev_priv->gct_data.bpi = vbt.primary_panel_idx;
 254         dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
 255                 gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor;
 256
 257         ti = &gct[vbt.primary_panel_idx].DTD;
 258         dp_ti->pixel_clock = ti->pixel_clock;
 259         dp_ti->hactive_hi = ti->hactive_hi;
 260         dp_ti->hactive_lo = ti->hactive_lo;
 261         dp_ti->hblank_hi = ti->hblank_hi;
 262         dp_ti->hblank_lo = ti->hblank_lo;
 263         dp_ti->hsync_offset_hi = ti->hsync_offset_hi;
 264         dp_ti->hsync_offset_lo = ti->hsync_offset_lo;
 265         dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi;
 266         dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo;
 267         dp_ti->vactive_hi = ti->vactive_hi;
 268         dp_ti->vactive_lo = ti->vactive_lo;
 269         dp_ti->vblank_hi = ti->vblank_hi;
 270         dp_ti->vblank_lo = ti->vblank_lo;
 271         dp_ti->vsync_offset_hi = ti->vsync_offset_hi;
 272         dp_ti->vsync_offset_lo = ti->vsync_offset_lo;
 273         dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi;
 274         dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo;
 275
 276         ret = 0;
 277 out:
 278         kfree(gct);
 279         return ret;
 280 }
 281
 282 static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
 283 {
 284         struct drm_device *dev = dev_priv->dev;
 285         u32 addr;
 286         u8 __iomem *vbt_virtual;
 287         struct mid_vbt_header vbt_header;
 288         struct pci_dev *pci_gfx_root =
 289                 pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
 290                                             0, PCI_DEVFN(2, 0));
 291         int ret = -1;
 292
 293         /* Get the address of the platform config vbt */
 294         pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
 295         pci_dev_put(pci_gfx_root);
 296
 297         dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
 298
 299         if (!addr)
 300                 goto out;
 301
 302         /* get the virtual address of the vbt */
 303         vbt_virtual = ioremap(addr, sizeof(vbt_header));
 304         if (!vbt_virtual)
 305                 goto out;
 306
 307         memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header));
 308         iounmap(vbt_virtual);
 309
 310         if (memcmp(&vbt_header.signature, "$GCT", 4))
 311                 goto out;
 312
 313         dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision);
 314
 315         switch (vbt_header.revision) {
 316         case 0x00:
 317                 ret = mid_get_vbt_data_r0(dev_priv, addr);
 318                 break;
 319         case 0x01:
 320                 ret = mid_get_vbt_data_r1(dev_priv, addr);
 321                 break;
 322         case 0x10:
 323                 ret = mid_get_vbt_data_r10(dev_priv, addr);
 324                 break;
 325         default:
 326                 dev_err(dev->dev, "Unknown revision of GCT!\n");
 327         }
 328
 329 out:
 330         if (ret)
 331                 dev_err(dev->dev, "Unable to read GCT!");
 332         else
 333                 dev_priv->has_gct = true;
 334 }
 335
 336 int mid_chip_setup(struct drm_device *dev)
 337 {
 338         struct drm_psb_private *dev_priv = dev->dev_private;
 339         mid_get_fuse_settings(dev);
 340         mid_get_vbt_data(dev_priv);
 341         mid_get_pci_revID(dev_priv);
 342         return 0;
 343 }