2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/module.h>
30 #include <linux/slab.h>
32 #include <drm/display/drm_dp_helper.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_simple_kms_helper.h>
37 #include "gma_display.h"
39 #include "psb_intel_drv.h"
40 #include "psb_intel_reg.h"
43 * struct i2c_algo_dp_aux_data - driver interface structure for i2c over dp
45 * @running: set by the algo indicating whether an i2c is ongoing or whether
46 * the i2c bus is quiescent
47 * @address: i2c target address for the currently ongoing transfer
48 * @aux_ch: driver callback to transfer a single byte of the i2c payload
50 struct i2c_algo_dp_aux_data {
53 int (*aux_ch) (struct i2c_adapter *adapter,
54 int mode, uint8_t write_byte,
58 /* Run a single AUX_CH I2C transaction, writing/reading data as necessary */
60 i2c_algo_dp_aux_transaction(struct i2c_adapter *adapter, int mode,
61 uint8_t write_byte, uint8_t *read_byte)
63 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
66 ret = (*algo_data->aux_ch)(adapter, mode,
67 write_byte, read_byte);
76 * Send the address. If the I2C link is running, this 'restarts'
77 * the connection with the new address, this is used for doing
78 * a write followed by a read (as needed for DDC)
81 i2c_algo_dp_aux_address(struct i2c_adapter *adapter, u16 address, bool reading)
83 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
84 int mode = MODE_I2C_START;
87 mode |= MODE_I2C_READ;
89 mode |= MODE_I2C_WRITE;
90 algo_data->address = address;
91 algo_data->running = true;
92 return i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
96 * Stop the I2C transaction. This closes out the link, sending
97 * a bare address packet with the MOT bit turned off
100 i2c_algo_dp_aux_stop(struct i2c_adapter *adapter, bool reading)
102 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
103 int mode = MODE_I2C_STOP;
106 mode |= MODE_I2C_READ;
108 mode |= MODE_I2C_WRITE;
109 if (algo_data->running) {
110 (void) i2c_algo_dp_aux_transaction(adapter, mode, 0, NULL);
111 algo_data->running = false;
116 * Write a single byte to the current I2C address, the
117 * the I2C link must be running or this returns -EIO
120 i2c_algo_dp_aux_put_byte(struct i2c_adapter *adapter, u8 byte)
122 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
124 if (!algo_data->running)
127 return i2c_algo_dp_aux_transaction(adapter, MODE_I2C_WRITE, byte, NULL);
131 * Read a single byte from the current I2C address, the
132 * I2C link must be running or this returns -EIO
135 i2c_algo_dp_aux_get_byte(struct i2c_adapter *adapter, u8 *byte_ret)
137 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
139 if (!algo_data->running)
142 return i2c_algo_dp_aux_transaction(adapter, MODE_I2C_READ, 0, byte_ret);
146 i2c_algo_dp_aux_xfer(struct i2c_adapter *adapter,
147 struct i2c_msg *msgs,
151 bool reading = false;
155 for (m = 0; m < num; m++) {
156 u16 len = msgs[m].len;
157 u8 *buf = msgs[m].buf;
158 reading = (msgs[m].flags & I2C_M_RD) != 0;
159 ret = i2c_algo_dp_aux_address(adapter, msgs[m].addr, reading);
163 for (b = 0; b < len; b++) {
164 ret = i2c_algo_dp_aux_get_byte(adapter, &buf[b]);
169 for (b = 0; b < len; b++) {
170 ret = i2c_algo_dp_aux_put_byte(adapter, buf[b]);
180 i2c_algo_dp_aux_stop(adapter, reading);
181 DRM_DEBUG_KMS("dp_aux_xfer return %d\n", ret);
186 i2c_algo_dp_aux_functionality(struct i2c_adapter *adapter)
188 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
189 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
190 I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
194 static const struct i2c_algorithm i2c_dp_aux_algo = {
195 .master_xfer = i2c_algo_dp_aux_xfer,
196 .functionality = i2c_algo_dp_aux_functionality,
200 i2c_dp_aux_reset_bus(struct i2c_adapter *adapter)
202 (void) i2c_algo_dp_aux_address(adapter, 0, false);
203 (void) i2c_algo_dp_aux_stop(adapter, false);
207 i2c_dp_aux_prepare_bus(struct i2c_adapter *adapter)
209 adapter->algo = &i2c_dp_aux_algo;
210 adapter->retries = 3;
211 i2c_dp_aux_reset_bus(adapter);
216 * FIXME: This is the old dp aux helper, gma500 is the last driver that needs to
217 * be ported over to the new helper code in drm_dp_helper.c like i915 or radeon.
220 i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
224 error = i2c_dp_aux_prepare_bus(adapter);
227 error = i2c_add_adapter(adapter);
231 #define _wait_for(COND, MS, W) ({ \
232 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
235 if (time_after(jiffies, timeout__)) { \
236 ret__ = -ETIMEDOUT; \
239 if (W && !in_dbg_master()) msleep(W); \
244 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
246 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
248 #define DP_LINK_CONFIGURATION_SIZE 9
250 #define CDV_FAST_LINK_TRAIN 1
252 struct cdv_intel_dp {
255 uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE];
258 uint32_t color_range;
262 struct gma_encoder *encoder;
263 struct i2c_adapter adapter;
264 struct i2c_algo_dp_aux_data algo;
265 uint8_t train_set[4];
266 uint8_t link_status[DP_LINK_STATUS_SIZE];
267 int panel_power_up_delay;
268 int panel_power_down_delay;
269 int panel_power_cycle_delay;
270 int backlight_on_delay;
271 int backlight_off_delay;
272 struct drm_display_mode *panel_fixed_mode; /* for eDP */
286 static struct ddi_regoff ddi_DP_train_table[] = {
287 {.PreEmph1 = 0x812c, .PreEmph2 = 0x8124, .VSwing1 = 0x8154,
288 .VSwing2 = 0x8148, .VSwing3 = 0x814C, .VSwing4 = 0x8150,
290 {.PreEmph1 = 0x822c, .PreEmph2 = 0x8224, .VSwing1 = 0x8254,
291 .VSwing2 = 0x8248, .VSwing3 = 0x824C, .VSwing4 = 0x8250,
295 static uint32_t dp_vswing_premph_table[] = {
302 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
303 * @encoder: GMA encoder struct
305 * If a CPU or PCH DP output is attached to an eDP panel, this function
306 * will return true, and false otherwise.
308 static bool is_edp(struct gma_encoder *encoder)
310 return encoder->type == INTEL_OUTPUT_EDP;
314 static void cdv_intel_dp_start_link_train(struct gma_encoder *encoder);
315 static void cdv_intel_dp_complete_link_train(struct gma_encoder *encoder);
316 static void cdv_intel_dp_link_down(struct gma_encoder *encoder);
319 cdv_intel_dp_max_lane_count(struct gma_encoder *encoder)
321 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
322 int max_lane_count = 4;
324 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
325 max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
326 switch (max_lane_count) {
327 case 1: case 2: case 4:
333 return max_lane_count;
337 cdv_intel_dp_max_link_bw(struct gma_encoder *encoder)
339 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
340 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
342 switch (max_link_bw) {
343 case DP_LINK_BW_1_62:
347 max_link_bw = DP_LINK_BW_1_62;
354 cdv_intel_dp_link_clock(uint8_t link_bw)
356 if (link_bw == DP_LINK_BW_2_7)
363 cdv_intel_dp_link_required(int pixel_clock, int bpp)
365 return (pixel_clock * bpp + 7) / 8;
369 cdv_intel_dp_max_data_rate(int max_link_clock, int max_lanes)
371 return (max_link_clock * max_lanes * 19) / 20;
374 static void cdv_intel_edp_panel_vdd_on(struct gma_encoder *intel_encoder)
376 struct drm_device *dev = intel_encoder->base.dev;
377 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
380 if (intel_dp->panel_on) {
381 DRM_DEBUG_KMS("Skip VDD on because of panel on\n");
386 pp = REG_READ(PP_CONTROL);
389 REG_WRITE(PP_CONTROL, pp);
390 REG_READ(PP_CONTROL);
391 msleep(intel_dp->panel_power_up_delay);
394 static void cdv_intel_edp_panel_vdd_off(struct gma_encoder *intel_encoder)
396 struct drm_device *dev = intel_encoder->base.dev;
400 pp = REG_READ(PP_CONTROL);
402 pp &= ~EDP_FORCE_VDD;
403 REG_WRITE(PP_CONTROL, pp);
404 REG_READ(PP_CONTROL);
408 /* Returns true if the panel was already on when called */
409 static bool cdv_intel_edp_panel_on(struct gma_encoder *intel_encoder)
411 struct drm_device *dev = intel_encoder->base.dev;
412 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
413 u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_NONE;
415 if (intel_dp->panel_on)
419 pp = REG_READ(PP_CONTROL);
420 pp &= ~PANEL_UNLOCK_MASK;
422 pp |= (PANEL_UNLOCK_REGS | POWER_TARGET_ON);
423 REG_WRITE(PP_CONTROL, pp);
424 REG_READ(PP_CONTROL);
426 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) {
427 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS));
428 intel_dp->panel_on = false;
430 intel_dp->panel_on = true;
431 msleep(intel_dp->panel_power_up_delay);
436 static void cdv_intel_edp_panel_off (struct gma_encoder *intel_encoder)
438 struct drm_device *dev = intel_encoder->base.dev;
439 u32 pp, idle_off_mask = PP_ON ;
440 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
444 pp = REG_READ(PP_CONTROL);
446 if ((pp & POWER_TARGET_ON) == 0)
449 intel_dp->panel_on = false;
450 pp &= ~PANEL_UNLOCK_MASK;
451 /* ILK workaround: disable reset around power sequence */
453 pp &= ~POWER_TARGET_ON;
454 pp &= ~EDP_FORCE_VDD;
455 pp &= ~EDP_BLC_ENABLE;
456 REG_WRITE(PP_CONTROL, pp);
457 REG_READ(PP_CONTROL);
458 DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS));
460 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) {
461 DRM_DEBUG_KMS("Error in turning off Panel\n");
464 msleep(intel_dp->panel_power_cycle_delay);
465 DRM_DEBUG_KMS("Over\n");
468 static void cdv_intel_edp_backlight_on (struct gma_encoder *intel_encoder)
470 struct drm_device *dev = intel_encoder->base.dev;
475 * If we enable the backlight right away following a panel power
476 * on, we may see slight flicker as the panel syncs with the eDP
477 * link. So delay a bit to make sure the image is solid before
478 * allowing it to appear.
481 pp = REG_READ(PP_CONTROL);
483 pp |= EDP_BLC_ENABLE;
484 REG_WRITE(PP_CONTROL, pp);
485 gma_backlight_enable(dev);
488 static void cdv_intel_edp_backlight_off (struct gma_encoder *intel_encoder)
490 struct drm_device *dev = intel_encoder->base.dev;
491 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
495 gma_backlight_disable(dev);
497 pp = REG_READ(PP_CONTROL);
499 pp &= ~EDP_BLC_ENABLE;
500 REG_WRITE(PP_CONTROL, pp);
501 msleep(intel_dp->backlight_off_delay);
504 static enum drm_mode_status
505 cdv_intel_dp_mode_valid(struct drm_connector *connector,
506 struct drm_display_mode *mode)
508 struct gma_encoder *encoder = gma_attached_encoder(connector);
509 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
510 int max_link_clock = cdv_intel_dp_link_clock(cdv_intel_dp_max_link_bw(encoder));
511 int max_lanes = cdv_intel_dp_max_lane_count(encoder);
512 struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);
514 if (is_edp(encoder) && intel_dp->panel_fixed_mode) {
515 if (mode->hdisplay > intel_dp->panel_fixed_mode->hdisplay)
517 if (mode->vdisplay > intel_dp->panel_fixed_mode->vdisplay)
521 /* only refuse the mode on non eDP since we have seen some weird eDP panels
522 which are outside spec tolerances but somehow work by magic */
523 if (!is_edp(encoder) &&
524 (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp)
525 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes)))
526 return MODE_CLOCK_HIGH;
528 if (is_edp(encoder)) {
529 if (cdv_intel_dp_link_required(mode->clock, 24)
530 > cdv_intel_dp_max_data_rate(max_link_clock, max_lanes))
531 return MODE_CLOCK_HIGH;
534 if (mode->clock < 10000)
535 return MODE_CLOCK_LOW;
541 pack_aux(uint8_t *src, int src_bytes)
548 for (i = 0; i < src_bytes; i++)
549 v |= ((uint32_t) src[i]) << ((3-i) * 8);
554 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
559 for (i = 0; i < dst_bytes; i++)
560 dst[i] = src >> ((3-i) * 8);
564 cdv_intel_dp_aux_ch(struct gma_encoder *encoder,
565 uint8_t *send, int send_bytes,
566 uint8_t *recv, int recv_size)
568 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
569 uint32_t output_reg = intel_dp->output_reg;
570 struct drm_device *dev = encoder->base.dev;
571 uint32_t ch_ctl = output_reg + 0x10;
572 uint32_t ch_data = ch_ctl + 4;
576 uint32_t aux_clock_divider;
579 /* The clock divider is based off the hrawclk,
580 * and would like to run at 2MHz. So, take the
581 * hrawclk value and divide by 2 and use that
582 * On CDV platform it uses 200MHz as hrawclk.
585 aux_clock_divider = 200 / 2;
591 if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
592 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
597 /* Must try at least 3 times according to DP spec */
598 for (try = 0; try < 5; try++) {
599 /* Load the send data into the aux channel data registers */
600 for (i = 0; i < send_bytes; i += 4)
601 REG_WRITE(ch_data + i,
602 pack_aux(send + i, send_bytes - i));
604 /* Send the command and wait for it to complete */
606 DP_AUX_CH_CTL_SEND_BUSY |
607 DP_AUX_CH_CTL_TIME_OUT_400us |
608 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
609 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
610 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
612 DP_AUX_CH_CTL_TIME_OUT_ERROR |
613 DP_AUX_CH_CTL_RECEIVE_ERROR);
615 status = REG_READ(ch_ctl);
616 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
621 /* Clear done status and any errors */
625 DP_AUX_CH_CTL_TIME_OUT_ERROR |
626 DP_AUX_CH_CTL_RECEIVE_ERROR);
627 if (status & DP_AUX_CH_CTL_DONE)
631 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
632 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
636 /* Check for timeout or receive error.
637 * Timeouts occur when the sink is not connected
639 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
640 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
644 /* Timeouts occur when the device isn't connected, so they're
645 * "normal" -- don't fill the kernel log with these */
646 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
647 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
651 /* Unload any bytes sent back from the other side */
652 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
653 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
654 if (recv_bytes > recv_size)
655 recv_bytes = recv_size;
657 for (i = 0; i < recv_bytes; i += 4)
658 unpack_aux(REG_READ(ch_data + i),
659 recv + i, recv_bytes - i);
664 /* Write data to the aux channel in native mode */
666 cdv_intel_dp_aux_native_write(struct gma_encoder *encoder,
667 uint16_t address, uint8_t *send, int send_bytes)
676 msg[0] = DP_AUX_NATIVE_WRITE << 4;
677 msg[1] = address >> 8;
678 msg[2] = address & 0xff;
679 msg[3] = send_bytes - 1;
680 memcpy(&msg[4], send, send_bytes);
681 msg_bytes = send_bytes + 4;
683 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes, &ack, 1);
687 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
689 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
697 /* Write a single byte to the aux channel in native mode */
699 cdv_intel_dp_aux_native_write_1(struct gma_encoder *encoder,
700 uint16_t address, uint8_t byte)
702 return cdv_intel_dp_aux_native_write(encoder, address, &byte, 1);
705 /* read bytes from a native aux channel */
707 cdv_intel_dp_aux_native_read(struct gma_encoder *encoder,
708 uint16_t address, uint8_t *recv, int recv_bytes)
717 msg[0] = DP_AUX_NATIVE_READ << 4;
718 msg[1] = address >> 8;
719 msg[2] = address & 0xff;
720 msg[3] = recv_bytes - 1;
723 reply_bytes = recv_bytes + 1;
726 ret = cdv_intel_dp_aux_ch(encoder, msg, msg_bytes,
733 if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
734 memcpy(recv, reply + 1, ret - 1);
737 else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
745 cdv_intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
746 uint8_t write_byte, uint8_t *read_byte)
748 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
749 struct cdv_intel_dp *intel_dp = container_of(adapter,
752 struct gma_encoder *encoder = intel_dp->encoder;
753 uint16_t address = algo_data->address;
761 /* Set up the command byte */
762 if (mode & MODE_I2C_READ)
763 msg[0] = DP_AUX_I2C_READ << 4;
765 msg[0] = DP_AUX_I2C_WRITE << 4;
767 if (!(mode & MODE_I2C_STOP))
768 msg[0] |= DP_AUX_I2C_MOT << 4;
770 msg[1] = address >> 8;
791 for (retry = 0; retry < 5; retry++) {
792 ret = cdv_intel_dp_aux_ch(encoder,
796 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
800 switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
801 case DP_AUX_NATIVE_REPLY_ACK:
802 /* I2C-over-AUX Reply field is only valid
803 * when paired with AUX ACK.
806 case DP_AUX_NATIVE_REPLY_NACK:
807 DRM_DEBUG_KMS("aux_ch native nack\n");
809 case DP_AUX_NATIVE_REPLY_DEFER:
813 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
818 switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
819 case DP_AUX_I2C_REPLY_ACK:
820 if (mode == MODE_I2C_READ) {
821 *read_byte = reply[1];
823 return reply_bytes - 1;
824 case DP_AUX_I2C_REPLY_NACK:
825 DRM_DEBUG_KMS("aux_i2c nack\n");
827 case DP_AUX_I2C_REPLY_DEFER:
828 DRM_DEBUG_KMS("aux_i2c defer\n");
832 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
837 DRM_ERROR("too many retries, giving up\n");
842 cdv_intel_dp_i2c_init(struct gma_connector *connector,
843 struct gma_encoder *encoder, const char *name)
845 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
848 DRM_DEBUG_KMS("i2c_init %s\n", name);
850 intel_dp->algo.running = false;
851 intel_dp->algo.address = 0;
852 intel_dp->algo.aux_ch = cdv_intel_dp_i2c_aux_ch;
854 memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
855 intel_dp->adapter.owner = THIS_MODULE;
856 intel_dp->adapter.class = I2C_CLASS_DDC;
857 strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
858 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
859 intel_dp->adapter.algo_data = &intel_dp->algo;
860 intel_dp->adapter.dev.parent = connector->base.kdev;
863 cdv_intel_edp_panel_vdd_on(encoder);
864 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
866 cdv_intel_edp_panel_vdd_off(encoder);
871 static void cdv_intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
872 struct drm_display_mode *adjusted_mode)
874 adjusted_mode->hdisplay = fixed_mode->hdisplay;
875 adjusted_mode->hsync_start = fixed_mode->hsync_start;
876 adjusted_mode->hsync_end = fixed_mode->hsync_end;
877 adjusted_mode->htotal = fixed_mode->htotal;
879 adjusted_mode->vdisplay = fixed_mode->vdisplay;
880 adjusted_mode->vsync_start = fixed_mode->vsync_start;
881 adjusted_mode->vsync_end = fixed_mode->vsync_end;
882 adjusted_mode->vtotal = fixed_mode->vtotal;
884 adjusted_mode->clock = fixed_mode->clock;
886 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
890 cdv_intel_dp_mode_fixup(struct drm_encoder *encoder, const struct drm_display_mode *mode,
891 struct drm_display_mode *adjusted_mode)
893 struct drm_psb_private *dev_priv = to_drm_psb_private(encoder->dev);
894 struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
895 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
896 int lane_count, clock;
897 int max_lane_count = cdv_intel_dp_max_lane_count(intel_encoder);
898 int max_clock = cdv_intel_dp_max_link_bw(intel_encoder) == DP_LINK_BW_2_7 ? 1 : 0;
899 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
900 int refclock = mode->clock;
903 if (is_edp(intel_encoder) && intel_dp->panel_fixed_mode) {
904 cdv_intel_fixed_panel_mode(intel_dp->panel_fixed_mode, adjusted_mode);
905 refclock = intel_dp->panel_fixed_mode->clock;
906 bpp = dev_priv->edp.bpp;
909 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
910 for (clock = max_clock; clock >= 0; clock--) {
911 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
913 if (cdv_intel_dp_link_required(refclock, bpp) <= link_avail) {
914 intel_dp->link_bw = bws[clock];
915 intel_dp->lane_count = lane_count;
916 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
917 DRM_DEBUG_KMS("Display port link bw %02x lane "
918 "count %d clock %d\n",
919 intel_dp->link_bw, intel_dp->lane_count,
920 adjusted_mode->clock);
925 if (is_edp(intel_encoder)) {
926 /* okay we failed just pick the highest */
927 intel_dp->lane_count = max_lane_count;
928 intel_dp->link_bw = bws[max_clock];
929 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw);
930 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
931 "count %d clock %d\n",
932 intel_dp->link_bw, intel_dp->lane_count,
933 adjusted_mode->clock);
940 struct cdv_intel_dp_m_n {
949 cdv_intel_reduce_ratio(uint32_t *num, uint32_t *den)
952 while (*num > 0xffffff || *den > 0xffffff) {
958 value = m * (0x800000);
959 m = do_div(value, *den);
965 cdv_intel_dp_compute_m_n(int bpp,
969 struct cdv_intel_dp_m_n *m_n)
972 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3;
973 m_n->gmch_n = link_clock * nlanes;
974 cdv_intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
975 m_n->link_m = pixel_clock;
976 m_n->link_n = link_clock;
977 cdv_intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
981 cdv_intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
982 struct drm_display_mode *adjusted_mode)
984 struct drm_device *dev = crtc->dev;
985 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
986 struct drm_mode_config *mode_config = &dev->mode_config;
987 struct drm_encoder *encoder;
988 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
989 int lane_count = 4, bpp = 24;
990 struct cdv_intel_dp_m_n m_n;
991 int pipe = gma_crtc->pipe;
994 * Find the lane count in the intel_encoder private
996 list_for_each_entry(encoder, &mode_config->encoder_list, head) {
997 struct gma_encoder *intel_encoder;
998 struct cdv_intel_dp *intel_dp;
1000 if (encoder->crtc != crtc)
1003 intel_encoder = to_gma_encoder(encoder);
1004 intel_dp = intel_encoder->dev_priv;
1005 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1006 lane_count = intel_dp->lane_count;
1008 } else if (is_edp(intel_encoder)) {
1009 lane_count = intel_dp->lane_count;
1010 bpp = dev_priv->edp.bpp;
1016 * Compute the GMCH and Link ratios. The '3' here is
1017 * the number of bytes_per_pixel post-LUT, which we always
1018 * set up for 8-bits of R/G/B, or 3 bytes total.
1020 cdv_intel_dp_compute_m_n(bpp, lane_count,
1021 mode->clock, adjusted_mode->clock, &m_n);
1024 REG_WRITE(PIPE_GMCH_DATA_M(pipe),
1025 ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
1027 REG_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
1028 REG_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
1029 REG_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
1034 cdv_intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1035 struct drm_display_mode *adjusted_mode)
1037 struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
1038 struct drm_crtc *crtc = encoder->crtc;
1039 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
1040 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
1041 struct drm_device *dev = encoder->dev;
1043 intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1044 intel_dp->DP |= intel_dp->color_range;
1046 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1047 intel_dp->DP |= DP_SYNC_HS_HIGH;
1048 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1049 intel_dp->DP |= DP_SYNC_VS_HIGH;
1051 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1053 switch (intel_dp->lane_count) {
1055 intel_dp->DP |= DP_PORT_WIDTH_1;
1058 intel_dp->DP |= DP_PORT_WIDTH_2;
1061 intel_dp->DP |= DP_PORT_WIDTH_4;
1064 if (intel_dp->has_audio)
1065 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1067 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
1068 intel_dp->link_configuration[0] = intel_dp->link_bw;
1069 intel_dp->link_configuration[1] = intel_dp->lane_count;
1072 * Check for DPCD version > 1.1 and enhanced framing support
1074 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
1075 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
1076 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
1077 intel_dp->DP |= DP_ENHANCED_FRAMING;
1080 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
1081 if (gma_crtc->pipe == 1)
1082 intel_dp->DP |= DP_PIPEB_SELECT;
1084 REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));
1085 DRM_DEBUG_KMS("DP expected reg is %x\n", intel_dp->DP);
1086 if (is_edp(intel_encoder)) {
1087 uint32_t pfit_control;
1088 cdv_intel_edp_panel_on(intel_encoder);
1090 if (mode->hdisplay != adjusted_mode->hdisplay ||
1091 mode->vdisplay != adjusted_mode->vdisplay)
1092 pfit_control = PFIT_ENABLE;
1096 pfit_control |= gma_crtc->pipe << PFIT_PIPE_SHIFT;
1098 REG_WRITE(PFIT_CONTROL, pfit_control);
1103 /* If the sink supports it, try to set the power state appropriately */
1104 static void cdv_intel_dp_sink_dpms(struct gma_encoder *encoder, int mode)
1106 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1109 /* Should have a valid DPCD by this point */
1110 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1113 if (mode != DRM_MODE_DPMS_ON) {
1114 ret = cdv_intel_dp_aux_native_write_1(encoder, DP_SET_POWER,
1117 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1120 * When turning on, we need to retry for 1ms to give the sink
1123 for (i = 0; i < 3; i++) {
1124 ret = cdv_intel_dp_aux_native_write_1(encoder,
1134 static void cdv_intel_dp_prepare(struct drm_encoder *encoder)
1136 struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
1137 int edp = is_edp(intel_encoder);
1140 cdv_intel_edp_backlight_off(intel_encoder);
1141 cdv_intel_edp_panel_off(intel_encoder);
1142 cdv_intel_edp_panel_vdd_on(intel_encoder);
1144 /* Wake up the sink first */
1145 cdv_intel_dp_sink_dpms(intel_encoder, DRM_MODE_DPMS_ON);
1146 cdv_intel_dp_link_down(intel_encoder);
1148 cdv_intel_edp_panel_vdd_off(intel_encoder);
1151 static void cdv_intel_dp_commit(struct drm_encoder *encoder)
1153 struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
1154 int edp = is_edp(intel_encoder);
1157 cdv_intel_edp_panel_on(intel_encoder);
1158 cdv_intel_dp_start_link_train(intel_encoder);
1159 cdv_intel_dp_complete_link_train(intel_encoder);
1161 cdv_intel_edp_backlight_on(intel_encoder);
1165 cdv_intel_dp_dpms(struct drm_encoder *encoder, int mode)
1167 struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
1168 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
1169 struct drm_device *dev = encoder->dev;
1170 uint32_t dp_reg = REG_READ(intel_dp->output_reg);
1171 int edp = is_edp(intel_encoder);
1173 if (mode != DRM_MODE_DPMS_ON) {
1175 cdv_intel_edp_backlight_off(intel_encoder);
1176 cdv_intel_edp_panel_vdd_on(intel_encoder);
1178 cdv_intel_dp_sink_dpms(intel_encoder, mode);
1179 cdv_intel_dp_link_down(intel_encoder);
1181 cdv_intel_edp_panel_vdd_off(intel_encoder);
1182 cdv_intel_edp_panel_off(intel_encoder);
1186 cdv_intel_edp_panel_on(intel_encoder);
1187 cdv_intel_dp_sink_dpms(intel_encoder, mode);
1188 if (!(dp_reg & DP_PORT_EN)) {
1189 cdv_intel_dp_start_link_train(intel_encoder);
1190 cdv_intel_dp_complete_link_train(intel_encoder);
1193 cdv_intel_edp_backlight_on(intel_encoder);
1198 * Native read with retry for link status and receiver capability reads for
1199 * cases where the sink may still be asleep.
1202 cdv_intel_dp_aux_native_read_retry(struct gma_encoder *encoder, uint16_t address,
1203 uint8_t *recv, int recv_bytes)
1208 * Sinks are *supposed* to come up within 1ms from an off state,
1209 * but we're also supposed to retry 3 times per the spec.
1211 for (i = 0; i < 3; i++) {
1212 ret = cdv_intel_dp_aux_native_read(encoder, address, recv,
1214 if (ret == recv_bytes)
1223 * Fetch AUX CH registers 0x202 - 0x207 which contain
1224 * link status information
1227 cdv_intel_dp_get_link_status(struct gma_encoder *encoder)
1229 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1230 return cdv_intel_dp_aux_native_read_retry(encoder,
1232 intel_dp->link_status,
1233 DP_LINK_STATUS_SIZE);
1237 cdv_intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1240 return link_status[r - DP_LANE0_1_STATUS];
1244 cdv_intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1247 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1248 int s = ((lane & 1) ?
1249 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1250 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1251 uint8_t l = cdv_intel_dp_link_status(link_status, i);
1253 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1257 cdv_intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1260 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1261 int s = ((lane & 1) ?
1262 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1263 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1264 uint8_t l = cdv_intel_dp_link_status(link_status, i);
1266 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1269 #define CDV_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
1272 cdv_intel_get_adjust_train(struct gma_encoder *encoder)
1274 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1279 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1280 uint8_t this_v = cdv_intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1281 uint8_t this_p = cdv_intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1289 if (v >= CDV_DP_VOLTAGE_MAX)
1290 v = CDV_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1292 if (p == DP_TRAIN_PRE_EMPHASIS_MASK)
1293 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1295 for (lane = 0; lane < 4; lane++)
1296 intel_dp->train_set[lane] = v | p;
1301 cdv_intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1304 int i = DP_LANE0_1_STATUS + (lane >> 1);
1305 int s = (lane & 1) * 4;
1306 uint8_t l = cdv_intel_dp_link_status(link_status, i);
1308 return (l >> s) & 0xf;
1311 /* Check for clock recovery is done on all channels */
1313 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1316 uint8_t lane_status;
1318 for (lane = 0; lane < lane_count; lane++) {
1319 lane_status = cdv_intel_get_lane_status(link_status, lane);
1320 if ((lane_status & DP_LANE_CR_DONE) == 0)
1326 /* Check to see if channel eq is done on all channels */
1327 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1328 DP_LANE_CHANNEL_EQ_DONE|\
1329 DP_LANE_SYMBOL_LOCKED)
1331 cdv_intel_channel_eq_ok(struct gma_encoder *encoder)
1333 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1335 uint8_t lane_status;
1338 lane_align = cdv_intel_dp_link_status(intel_dp->link_status,
1339 DP_LANE_ALIGN_STATUS_UPDATED);
1340 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1342 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1343 lane_status = cdv_intel_get_lane_status(intel_dp->link_status, lane);
1344 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1351 cdv_intel_dp_set_link_train(struct gma_encoder *encoder,
1352 uint32_t dp_reg_value,
1353 uint8_t dp_train_pat)
1355 struct drm_device *dev = encoder->base.dev;
1357 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1359 REG_WRITE(intel_dp->output_reg, dp_reg_value);
1360 REG_READ(intel_dp->output_reg);
1362 ret = cdv_intel_dp_aux_native_write_1(encoder,
1363 DP_TRAINING_PATTERN_SET,
1367 DRM_DEBUG_KMS("Failure in setting link pattern %x\n",
1377 cdv_intel_dplink_set_level(struct gma_encoder *encoder,
1378 uint8_t dp_train_pat)
1381 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1383 ret = cdv_intel_dp_aux_native_write(encoder,
1384 DP_TRAINING_LANE0_SET,
1385 intel_dp->train_set,
1386 intel_dp->lane_count);
1388 if (ret != intel_dp->lane_count) {
1389 DRM_DEBUG_KMS("Failure in setting level %d, lane_cnt= %d\n",
1390 intel_dp->train_set[0], intel_dp->lane_count);
1397 cdv_intel_dp_set_vswing_premph(struct gma_encoder *encoder, uint8_t signal_level)
1399 struct drm_device *dev = encoder->base.dev;
1400 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1401 struct ddi_regoff *ddi_reg;
1402 int vswing, premph, index;
1404 if (intel_dp->output_reg == DP_B)
1405 ddi_reg = &ddi_DP_train_table[0];
1407 ddi_reg = &ddi_DP_train_table[1];
1409 vswing = (signal_level & DP_TRAIN_VOLTAGE_SWING_MASK);
1410 premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >>
1411 DP_TRAIN_PRE_EMPHASIS_SHIFT;
1413 if (vswing + premph > 3)
1415 #ifdef CDV_FAST_LINK_TRAIN
1418 DRM_DEBUG_KMS("Test2\n");
1421 /* ;Swing voltage programming
1422 ;gfx_dpio_set_reg(0xc058, 0x0505313A) */
1423 cdv_sb_write(dev, ddi_reg->VSwing5, 0x0505313A);
1425 /* ;gfx_dpio_set_reg(0x8154, 0x43406055) */
1426 cdv_sb_write(dev, ddi_reg->VSwing1, 0x43406055);
1428 /* ;gfx_dpio_set_reg(0x8148, 0x55338954)
1429 * The VSwing_PreEmph table is also considered based on the vswing/premp
1431 index = (vswing + premph) * 2;
1432 if (premph == 1 && vswing == 1) {
1433 cdv_sb_write(dev, ddi_reg->VSwing2, 0x055738954);
1435 cdv_sb_write(dev, ddi_reg->VSwing2, dp_vswing_premph_table[index]);
1437 /* ;gfx_dpio_set_reg(0x814c, 0x40802040) */
1438 if ((vswing + premph) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3)
1439 cdv_sb_write(dev, ddi_reg->VSwing3, 0x70802040);
1441 cdv_sb_write(dev, ddi_reg->VSwing3, 0x40802040);
1443 /* ;gfx_dpio_set_reg(0x8150, 0x2b405555) */
1444 /* cdv_sb_write(dev, ddi_reg->VSwing4, 0x2b405555); */
1446 /* ;gfx_dpio_set_reg(0x8154, 0xc3406055) */
1447 cdv_sb_write(dev, ddi_reg->VSwing1, 0xc3406055);
1449 /* ;Pre emphasis programming
1450 * ;gfx_dpio_set_reg(0xc02c, 0x1f030040)
1452 cdv_sb_write(dev, ddi_reg->PreEmph1, 0x1f030040);
1454 /* ;gfx_dpio_set_reg(0x8124, 0x00004000) */
1455 index = 2 * premph + 1;
1456 cdv_sb_write(dev, ddi_reg->PreEmph2, dp_vswing_premph_table[index]);
1461 /* Enable corresponding port and start training pattern 1 */
1463 cdv_intel_dp_start_link_train(struct gma_encoder *encoder)
1465 struct drm_device *dev = encoder->base.dev;
1466 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1469 bool clock_recovery = false;
1472 uint32_t DP = intel_dp->DP;
1475 DP &= ~DP_LINK_TRAIN_MASK;
1478 reg |= DP_LINK_TRAIN_PAT_1;
1479 /* Enable output, wait for it to become active */
1480 REG_WRITE(intel_dp->output_reg, reg);
1481 REG_READ(intel_dp->output_reg);
1482 gma_wait_for_vblank(dev);
1484 DRM_DEBUG_KMS("Link config\n");
1485 /* Write the link configuration data */
1486 cdv_intel_dp_aux_native_write(encoder, DP_LINK_BW_SET,
1487 intel_dp->link_configuration,
1490 memset(intel_dp->train_set, 0, 4);
1493 clock_recovery = false;
1495 DRM_DEBUG_KMS("Start train\n");
1496 reg = DP | DP_LINK_TRAIN_PAT_1;
1499 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1500 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1501 intel_dp->train_set[0],
1502 intel_dp->link_configuration[0],
1503 intel_dp->link_configuration[1]);
1505 if (!cdv_intel_dp_set_link_train(encoder, reg, DP_TRAINING_PATTERN_1)) {
1506 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 1\n");
1508 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
1509 /* Set training pattern 1 */
1511 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_1);
1514 if (!cdv_intel_dp_get_link_status(encoder))
1517 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1518 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1519 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1521 if (cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1522 DRM_DEBUG_KMS("PT1 train is done\n");
1523 clock_recovery = true;
1527 /* Check to see if we've tried the max voltage */
1528 for (i = 0; i < intel_dp->lane_count; i++)
1529 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1531 if (i == intel_dp->lane_count)
1534 /* Check to see if we've tried the same voltage 5 times */
1535 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1541 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1543 /* Compute new intel_dp->train_set as requested by target */
1544 cdv_intel_get_adjust_train(encoder);
1548 if (!clock_recovery) {
1549 DRM_DEBUG_KMS("failure in DP patter 1 training, train set %x\n", intel_dp->train_set[0]);
1556 cdv_intel_dp_complete_link_train(struct gma_encoder *encoder)
1558 struct drm_device *dev = encoder->base.dev;
1559 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1560 int tries, cr_tries;
1562 uint32_t DP = intel_dp->DP;
1564 /* channel equalization */
1568 DRM_DEBUG_KMS("\n");
1569 reg = DP | DP_LINK_TRAIN_PAT_2;
1573 DRM_DEBUG_KMS("DP Link Train Set %x, Link_config %x, %x\n",
1574 intel_dp->train_set[0],
1575 intel_dp->link_configuration[0],
1576 intel_dp->link_configuration[1]);
1577 /* channel eq pattern */
1579 if (!cdv_intel_dp_set_link_train(encoder, reg,
1580 DP_TRAINING_PATTERN_2)) {
1581 DRM_DEBUG_KMS("Failure in aux-transfer setting pattern 2\n");
1583 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1586 DRM_ERROR("failed to train DP, aborting\n");
1587 cdv_intel_dp_link_down(encoder);
1591 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]);
1593 cdv_intel_dplink_set_level(encoder, DP_TRAINING_PATTERN_2);
1596 if (!cdv_intel_dp_get_link_status(encoder))
1599 DRM_DEBUG_KMS("DP Link status %x, %x, %x, %x, %x, %x\n",
1600 intel_dp->link_status[0], intel_dp->link_status[1], intel_dp->link_status[2],
1601 intel_dp->link_status[3], intel_dp->link_status[4], intel_dp->link_status[5]);
1603 /* Make sure clock is still ok */
1604 if (!cdv_intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1605 cdv_intel_dp_start_link_train(encoder);
1610 if (cdv_intel_channel_eq_ok(encoder)) {
1611 DRM_DEBUG_KMS("PT2 train is done\n");
1615 /* Try 5 times, then try clock recovery if that fails */
1617 cdv_intel_dp_link_down(encoder);
1618 cdv_intel_dp_start_link_train(encoder);
1624 /* Compute new intel_dp->train_set as requested by target */
1625 cdv_intel_get_adjust_train(encoder);
1630 reg = DP | DP_LINK_TRAIN_OFF;
1632 REG_WRITE(intel_dp->output_reg, reg);
1633 REG_READ(intel_dp->output_reg);
1634 cdv_intel_dp_aux_native_write_1(encoder,
1635 DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1639 cdv_intel_dp_link_down(struct gma_encoder *encoder)
1641 struct drm_device *dev = encoder->base.dev;
1642 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1643 uint32_t DP = intel_dp->DP;
1645 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1648 DRM_DEBUG_KMS("\n");
1652 DP &= ~DP_LINK_TRAIN_MASK;
1653 REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1655 REG_READ(intel_dp->output_reg);
1659 REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1660 REG_READ(intel_dp->output_reg);
1663 static enum drm_connector_status cdv_dp_detect(struct gma_encoder *encoder)
1665 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1666 enum drm_connector_status status;
1668 status = connector_status_disconnected;
1669 if (cdv_intel_dp_aux_native_read(encoder, 0x000, intel_dp->dpcd,
1670 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1672 if (intel_dp->dpcd[DP_DPCD_REV] != 0)
1673 status = connector_status_connected;
1675 if (status == connector_status_connected)
1676 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
1677 intel_dp->dpcd[0], intel_dp->dpcd[1],
1678 intel_dp->dpcd[2], intel_dp->dpcd[3]);
1683 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1685 * \return true if DP port is connected.
1686 * \return false if DP port is disconnected.
1688 static enum drm_connector_status
1689 cdv_intel_dp_detect(struct drm_connector *connector, bool force)
1691 struct gma_encoder *encoder = gma_attached_encoder(connector);
1692 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1693 enum drm_connector_status status;
1694 struct edid *edid = NULL;
1695 int edp = is_edp(encoder);
1697 intel_dp->has_audio = false;
1700 cdv_intel_edp_panel_vdd_on(encoder);
1701 status = cdv_dp_detect(encoder);
1702 if (status != connector_status_connected) {
1704 cdv_intel_edp_panel_vdd_off(encoder);
1708 if (intel_dp->force_audio) {
1709 intel_dp->has_audio = intel_dp->force_audio > 0;
1711 edid = drm_get_edid(connector, &intel_dp->adapter);
1713 intel_dp->has_audio = drm_detect_monitor_audio(edid);
1718 cdv_intel_edp_panel_vdd_off(encoder);
1720 return connector_status_connected;
1723 static int cdv_intel_dp_get_modes(struct drm_connector *connector)
1725 struct gma_encoder *intel_encoder = gma_attached_encoder(connector);
1726 struct cdv_intel_dp *intel_dp = intel_encoder->dev_priv;
1727 struct edid *edid = NULL;
1729 int edp = is_edp(intel_encoder);
1732 edid = drm_get_edid(connector, &intel_dp->adapter);
1734 drm_connector_update_edid_property(connector, edid);
1735 ret = drm_add_edid_modes(connector, edid);
1739 if (is_edp(intel_encoder)) {
1740 struct drm_device *dev = connector->dev;
1741 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1743 cdv_intel_edp_panel_vdd_off(intel_encoder);
1745 if (edp && !intel_dp->panel_fixed_mode) {
1746 struct drm_display_mode *newmode;
1747 list_for_each_entry(newmode, &connector->probed_modes,
1749 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1750 intel_dp->panel_fixed_mode =
1751 drm_mode_duplicate(dev, newmode);
1759 if (!intel_dp->panel_fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
1760 intel_dp->panel_fixed_mode =
1761 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1762 if (intel_dp->panel_fixed_mode) {
1763 intel_dp->panel_fixed_mode->type |=
1764 DRM_MODE_TYPE_PREFERRED;
1767 if (intel_dp->panel_fixed_mode != NULL) {
1768 struct drm_display_mode *mode;
1769 mode = drm_mode_duplicate(dev, intel_dp->panel_fixed_mode);
1770 drm_mode_probed_add(connector, mode);
1779 cdv_intel_dp_detect_audio(struct drm_connector *connector)
1781 struct gma_encoder *encoder = gma_attached_encoder(connector);
1782 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1784 bool has_audio = false;
1785 int edp = is_edp(encoder);
1788 cdv_intel_edp_panel_vdd_on(encoder);
1790 edid = drm_get_edid(connector, &intel_dp->adapter);
1792 has_audio = drm_detect_monitor_audio(edid);
1796 cdv_intel_edp_panel_vdd_off(encoder);
1802 cdv_intel_dp_set_property(struct drm_connector *connector,
1803 struct drm_property *property,
1806 struct drm_psb_private *dev_priv = to_drm_psb_private(connector->dev);
1807 struct gma_encoder *encoder = gma_attached_encoder(connector);
1808 struct cdv_intel_dp *intel_dp = encoder->dev_priv;
1811 ret = drm_object_property_set_value(&connector->base, property, val);
1815 if (property == dev_priv->force_audio_property) {
1819 if (i == intel_dp->force_audio)
1822 intel_dp->force_audio = i;
1825 has_audio = cdv_intel_dp_detect_audio(connector);
1829 if (has_audio == intel_dp->has_audio)
1832 intel_dp->has_audio = has_audio;
1836 if (property == dev_priv->broadcast_rgb_property) {
1837 if (val == !!intel_dp->color_range)
1840 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1847 if (encoder->base.crtc) {
1848 struct drm_crtc *crtc = encoder->base.crtc;
1849 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1858 cdv_intel_dp_destroy(struct drm_connector *connector)
1860 struct gma_connector *gma_connector = to_gma_connector(connector);
1861 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
1862 struct cdv_intel_dp *intel_dp = gma_encoder->dev_priv;
1864 if (is_edp(gma_encoder)) {
1865 /* cdv_intel_panel_destroy_backlight(connector->dev); */
1866 kfree(intel_dp->panel_fixed_mode);
1867 intel_dp->panel_fixed_mode = NULL;
1869 i2c_del_adapter(&intel_dp->adapter);
1870 drm_connector_cleanup(connector);
1871 kfree(gma_connector);
1874 static const struct drm_encoder_helper_funcs cdv_intel_dp_helper_funcs = {
1875 .dpms = cdv_intel_dp_dpms,
1876 .mode_fixup = cdv_intel_dp_mode_fixup,
1877 .prepare = cdv_intel_dp_prepare,
1878 .mode_set = cdv_intel_dp_mode_set,
1879 .commit = cdv_intel_dp_commit,
1882 static const struct drm_connector_funcs cdv_intel_dp_connector_funcs = {
1883 .dpms = drm_helper_connector_dpms,
1884 .detect = cdv_intel_dp_detect,
1885 .fill_modes = drm_helper_probe_single_connector_modes,
1886 .set_property = cdv_intel_dp_set_property,
1887 .destroy = cdv_intel_dp_destroy,
1890 static const struct drm_connector_helper_funcs cdv_intel_dp_connector_helper_funcs = {
1891 .get_modes = cdv_intel_dp_get_modes,
1892 .mode_valid = cdv_intel_dp_mode_valid,
1893 .best_encoder = gma_best_encoder,
1896 static void cdv_intel_dp_add_properties(struct drm_connector *connector)
1898 cdv_intel_attach_force_audio_property(connector);
1899 cdv_intel_attach_broadcast_rgb_property(connector);
1902 /* check the VBT to see whether the eDP is on DP-D port */
1903 static bool cdv_intel_dpc_is_edp(struct drm_device *dev)
1905 struct drm_psb_private *dev_priv = to_drm_psb_private(dev);
1906 struct child_device_config *p_child;
1909 if (!dev_priv->child_dev_num)
1912 for (i = 0; i < dev_priv->child_dev_num; i++) {
1913 p_child = dev_priv->child_dev + i;
1915 if (p_child->dvo_port == PORT_IDPC &&
1916 p_child->device_type == DEVICE_TYPE_eDP)
1922 /* Cedarview display clock gating
1924 We need this disable dot get correct behaviour while enabling
1925 DP/eDP. TODO - investigate if we can turn it back to normality
1927 static void cdv_disable_intel_clock_gating(struct drm_device *dev)
1930 reg_value = REG_READ(DSPCLK_GATE_D);
1932 reg_value |= (DPUNIT_PIPEB_GATE_DISABLE |
1933 DPUNIT_PIPEA_GATE_DISABLE |
1934 DPCUNIT_CLOCK_GATE_DISABLE |
1935 DPLSUNIT_CLOCK_GATE_DISABLE |
1936 DPOUNIT_CLOCK_GATE_DISABLE |
1937 DPIOUNIT_CLOCK_GATE_DISABLE);
1939 REG_WRITE(DSPCLK_GATE_D, reg_value);
1945 cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)
1947 struct gma_encoder *gma_encoder;
1948 struct gma_connector *gma_connector;
1949 struct drm_connector *connector;
1950 struct drm_encoder *encoder;
1951 struct cdv_intel_dp *intel_dp;
1952 const char *name = NULL;
1953 int type = DRM_MODE_CONNECTOR_DisplayPort;
1955 gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
1958 gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
1961 intel_dp = kzalloc(sizeof(struct cdv_intel_dp), GFP_KERNEL);
1965 if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev))
1966 type = DRM_MODE_CONNECTOR_eDP;
1968 connector = &gma_connector->base;
1969 encoder = &gma_encoder->base;
1971 drm_connector_init(dev, connector, &cdv_intel_dp_connector_funcs, type);
1972 drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_TMDS);
1974 gma_connector_attach_encoder(gma_connector, gma_encoder);
1976 if (type == DRM_MODE_CONNECTOR_DisplayPort)
1977 gma_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1979 gma_encoder->type = INTEL_OUTPUT_EDP;
1982 gma_encoder->dev_priv=intel_dp;
1983 intel_dp->encoder = gma_encoder;
1984 intel_dp->output_reg = output_reg;
1986 drm_encoder_helper_add(encoder, &cdv_intel_dp_helper_funcs);
1987 drm_connector_helper_add(connector, &cdv_intel_dp_connector_helper_funcs);
1989 connector->polled = DRM_CONNECTOR_POLL_HPD;
1990 connector->interlace_allowed = false;
1991 connector->doublescan_allowed = false;
1993 /* Set up the DDC bus. */
1994 switch (output_reg) {
1997 gma_encoder->ddi_select = (DP_MASK | DDI0_SELECT);
2001 gma_encoder->ddi_select = (DP_MASK | DDI1_SELECT);
2005 cdv_disable_intel_clock_gating(dev);
2007 cdv_intel_dp_i2c_init(gma_connector, gma_encoder, name);
2008 /* FIXME:fail check */
2009 cdv_intel_dp_add_properties(connector);
2011 if (is_edp(gma_encoder)) {
2013 struct edp_power_seq cur;
2014 u32 pp_on, pp_off, pp_div;
2017 pp_on = REG_READ(PP_CONTROL);
2018 pp_on &= ~PANEL_UNLOCK_MASK;
2019 pp_on |= PANEL_UNLOCK_REGS;
2021 REG_WRITE(PP_CONTROL, pp_on);
2023 pwm_ctrl = REG_READ(BLC_PWM_CTL2);
2024 pwm_ctrl |= PWM_PIPE_B;
2025 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl);
2027 pp_on = REG_READ(PP_ON_DELAYS);
2028 pp_off = REG_READ(PP_OFF_DELAYS);
2029 pp_div = REG_READ(PP_DIVISOR);
2031 /* Pull timing values out of registers */
2032 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2033 PANEL_POWER_UP_DELAY_SHIFT;
2035 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2036 PANEL_LIGHT_ON_DELAY_SHIFT;
2038 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2039 PANEL_LIGHT_OFF_DELAY_SHIFT;
2041 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2042 PANEL_POWER_DOWN_DELAY_SHIFT;
2044 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2045 PANEL_POWER_CYCLE_DELAY_SHIFT);
2047 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2048 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2051 intel_dp->panel_power_up_delay = cur.t1_t3 / 10;
2052 intel_dp->backlight_on_delay = cur.t8 / 10;
2053 intel_dp->backlight_off_delay = cur.t9 / 10;
2054 intel_dp->panel_power_down_delay = cur.t10 / 10;
2055 intel_dp->panel_power_cycle_delay = (cur.t11_t12 - 1) * 100;
2057 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2058 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2059 intel_dp->panel_power_cycle_delay);
2061 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2062 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2065 cdv_intel_edp_panel_vdd_on(gma_encoder);
2066 ret = cdv_intel_dp_aux_native_read(gma_encoder, DP_DPCD_REV,
2068 sizeof(intel_dp->dpcd));
2069 cdv_intel_edp_panel_vdd_off(gma_encoder);
2071 /* if this fails, presume the device is a ghost */
2072 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2073 drm_encoder_cleanup(encoder);
2074 cdv_intel_dp_destroy(connector);
2077 DRM_DEBUG_KMS("DPCD: Rev=%x LN_Rate=%x LN_CNT=%x LN_DOWNSP=%x\n",
2078 intel_dp->dpcd[0], intel_dp->dpcd[1],
2079 intel_dp->dpcd[2], intel_dp->dpcd[3]);
2082 /* The CDV reference driver moves pnale backlight setup into the displays that
2083 have a backlight: this is a good idea and one we should probably adopt, however
2084 we need to migrate all the drivers before we can do that */
2085 /*cdv_intel_panel_setup_backlight(dev); */
2090 kfree(gma_connector);