2 * Copyright (C) 2012 Samsung Electronics Co.Ltd
4 * Eunchul Kim <chulspro.kim@samsung.com>
5 * Jinyoung Jeon <jy0.jeon@samsung.com>
6 * Sangmin Lee <lsmin.lee@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/platform_device.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <plat/map-base.h>
21 #include <drm/exynos_drm.h>
23 #include "exynos_drm_drv.h"
24 #include "exynos_drm_ipp.h"
25 #include "exynos_drm_gsc.h"
28 * GSC stands for General SCaler and
29 * supports image scaler/rotator and input/output DMA operations.
30 * input DMA reads image data from the memory.
31 * output DMA writes image data to memory.
32 * GSC supports image rotation and image effect functions.
34 * M2M operation : supports crop/scale/rotation/csc so on.
35 * Memory ----> GSC H/W ----> Memory.
36 * Writeback operation : supports cloned screen with FIMD.
37 * FIMD ----> GSC H/W ----> Memory.
38 * Output operation : supports direct display using local path.
39 * Memory ----> GSC H/W ----> FIMD, Mixer.
44 * 1. check suspend/resume api if needed.
45 * 2. need to check use case platform_device_id.
46 * 3. check src/dst size with, height.
47 * 4. added check_prepare api for right register.
48 * 5. need to add supported list in prop_list.
49 * 6. check prescaler/scaler optimization.
52 #define GSC_MAX_DEVS 4
54 #define GSC_MAX_DST 16
55 #define GSC_RESET_TIMEOUT 50
56 #define GSC_BUF_STOP 1
57 #define GSC_BUF_START 2
59 #define GSC_WIDTH_ITU_709 1280
60 #define GSC_SC_UP_MAX_RATIO 65536
61 #define GSC_SC_DOWN_RATIO_7_8 74898
62 #define GSC_SC_DOWN_RATIO_6_8 87381
63 #define GSC_SC_DOWN_RATIO_5_8 104857
64 #define GSC_SC_DOWN_RATIO_4_8 131072
65 #define GSC_SC_DOWN_RATIO_3_8 174762
66 #define GSC_SC_DOWN_RATIO_2_8 262144
67 #define GSC_REFRESH_MIN 12
68 #define GSC_REFRESH_MAX 60
69 #define GSC_CROP_MAX 8192
70 #define GSC_CROP_MIN 32
71 #define GSC_SCALE_MAX 4224
72 #define GSC_SCALE_MIN 32
73 #define GSC_COEF_RATIO 7
74 #define GSC_COEF_PHASE 9
75 #define GSC_COEF_ATTR 16
76 #define GSC_COEF_H_8T 8
77 #define GSC_COEF_V_4T 4
78 #define GSC_COEF_DEPTH 3
80 #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev))
81 #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\
82 struct gsc_context, ippdrv);
83 #define gsc_read(offset) readl(ctx->regs + (offset))
84 #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
87 * A structure of scaler.
89 * @range: narrow, wide.
90 * @pre_shfactor: pre sclaer shift factor.
91 * @pre_hratio: horizontal ratio of the prescaler.
92 * @pre_vratio: vertical ratio of the prescaler.
93 * @main_hratio: the main scaler's horizontal ratio.
94 * @main_vratio: the main scaler's vertical ratio.
101 unsigned long main_hratio;
102 unsigned long main_vratio;
106 * A structure of scaler capability.
108 * find user manual 49.2 features.
109 * @tile_w: tile mode or rotation width.
110 * @tile_h: tile mode or rotation height.
111 * @w: other cases width.
112 * @h: other cases height.
114 struct gsc_capability {
115 /* tile or rotation */
124 * A structure of gsc context.
126 * @ippdrv: prepare initialization using ippdrv.
127 * @regs_res: register resources.
128 * @regs: memory mapped io registers.
129 * @lock: locking of operations.
130 * @gsc_clk: gsc gate clock.
131 * @sc: scaler infomations.
134 * @rotation: supports rotation of src.
135 * @suspended: qos operations.
138 struct exynos_drm_ippdrv ippdrv;
139 struct resource *regs_res;
143 struct gsc_scaler sc;
150 /* 8-tap Filter Coefficient */
151 static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = {
152 { /* Ratio <= 65536 (~8:8) */
153 { 0, 0, 0, 128, 0, 0, 0, 0 },
154 { -1, 2, -6, 127, 7, -2, 1, 0 },
155 { -1, 4, -12, 125, 16, -5, 1, 0 },
156 { -1, 5, -15, 120, 25, -8, 2, 0 },
157 { -1, 6, -18, 114, 35, -10, 3, -1 },
158 { -1, 6, -20, 107, 46, -13, 4, -1 },
159 { -2, 7, -21, 99, 57, -16, 5, -1 },
160 { -1, 6, -20, 89, 68, -18, 5, -1 },
161 { -1, 6, -20, 79, 79, -20, 6, -1 },
162 { -1, 5, -18, 68, 89, -20, 6, -1 },
163 { -1, 5, -16, 57, 99, -21, 7, -2 },
164 { -1, 4, -13, 46, 107, -20, 6, -1 },
165 { -1, 3, -10, 35, 114, -18, 6, -1 },
166 { 0, 2, -8, 25, 120, -15, 5, -1 },
167 { 0, 1, -5, 16, 125, -12, 4, -1 },
168 { 0, 1, -2, 7, 127, -6, 2, -1 }
169 }, { /* 65536 < Ratio <= 74898 (~8:7) */
170 { 3, -8, 14, 111, 13, -8, 3, 0 },
171 { 2, -6, 7, 112, 21, -10, 3, -1 },
172 { 2, -4, 1, 110, 28, -12, 4, -1 },
173 { 1, -2, -3, 106, 36, -13, 4, -1 },
174 { 1, -1, -7, 103, 44, -15, 4, -1 },
175 { 1, 1, -11, 97, 53, -16, 4, -1 },
176 { 0, 2, -13, 91, 61, -16, 4, -1 },
177 { 0, 3, -15, 85, 69, -17, 4, -1 },
178 { 0, 3, -16, 77, 77, -16, 3, 0 },
179 { -1, 4, -17, 69, 85, -15, 3, 0 },
180 { -1, 4, -16, 61, 91, -13, 2, 0 },
181 { -1, 4, -16, 53, 97, -11, 1, 1 },
182 { -1, 4, -15, 44, 103, -7, -1, 1 },
183 { -1, 4, -13, 36, 106, -3, -2, 1 },
184 { -1, 4, -12, 28, 110, 1, -4, 2 },
185 { -1, 3, -10, 21, 112, 7, -6, 2 }
186 }, { /* 74898 < Ratio <= 87381 (~8:6) */
187 { 2, -11, 25, 96, 25, -11, 2, 0 },
188 { 2, -10, 19, 96, 31, -12, 2, 0 },
189 { 2, -9, 14, 94, 37, -12, 2, 0 },
190 { 2, -8, 10, 92, 43, -12, 1, 0 },
191 { 2, -7, 5, 90, 49, -12, 1, 0 },
192 { 2, -5, 1, 86, 55, -12, 0, 1 },
193 { 2, -4, -2, 82, 61, -11, -1, 1 },
194 { 1, -3, -5, 77, 67, -9, -1, 1 },
195 { 1, -2, -7, 72, 72, -7, -2, 1 },
196 { 1, -1, -9, 67, 77, -5, -3, 1 },
197 { 1, -1, -11, 61, 82, -2, -4, 2 },
198 { 1, 0, -12, 55, 86, 1, -5, 2 },
199 { 0, 1, -12, 49, 90, 5, -7, 2 },
200 { 0, 1, -12, 43, 92, 10, -8, 2 },
201 { 0, 2, -12, 37, 94, 14, -9, 2 },
202 { 0, 2, -12, 31, 96, 19, -10, 2 }
203 }, { /* 87381 < Ratio <= 104857 (~8:5) */
204 { -1, -8, 33, 80, 33, -8, -1, 0 },
205 { -1, -8, 28, 80, 37, -7, -2, 1 },
206 { 0, -8, 24, 79, 41, -7, -2, 1 },
207 { 0, -8, 20, 78, 46, -6, -3, 1 },
208 { 0, -8, 16, 76, 50, -4, -3, 1 },
209 { 0, -7, 13, 74, 54, -3, -4, 1 },
210 { 1, -7, 10, 71, 58, -1, -5, 1 },
211 { 1, -6, 6, 68, 62, 1, -5, 1 },
212 { 1, -6, 4, 65, 65, 4, -6, 1 },
213 { 1, -5, 1, 62, 68, 6, -6, 1 },
214 { 1, -5, -1, 58, 71, 10, -7, 1 },
215 { 1, -4, -3, 54, 74, 13, -7, 0 },
216 { 1, -3, -4, 50, 76, 16, -8, 0 },
217 { 1, -3, -6, 46, 78, 20, -8, 0 },
218 { 1, -2, -7, 41, 79, 24, -8, 0 },
219 { 1, -2, -7, 37, 80, 28, -8, -1 }
220 }, { /* 104857 < Ratio <= 131072 (~8:4) */
221 { -3, 0, 35, 64, 35, 0, -3, 0 },
222 { -3, -1, 32, 64, 38, 1, -3, 0 },
223 { -2, -2, 29, 63, 41, 2, -3, 0 },
224 { -2, -3, 27, 63, 43, 4, -4, 0 },
225 { -2, -3, 24, 61, 46, 6, -4, 0 },
226 { -2, -3, 21, 60, 49, 7, -4, 0 },
227 { -1, -4, 19, 59, 51, 9, -4, -1 },
228 { -1, -4, 16, 57, 53, 12, -4, -1 },
229 { -1, -4, 14, 55, 55, 14, -4, -1 },
230 { -1, -4, 12, 53, 57, 16, -4, -1 },
231 { -1, -4, 9, 51, 59, 19, -4, -1 },
232 { 0, -4, 7, 49, 60, 21, -3, -2 },
233 { 0, -4, 6, 46, 61, 24, -3, -2 },
234 { 0, -4, 4, 43, 63, 27, -3, -2 },
235 { 0, -3, 2, 41, 63, 29, -2, -2 },
236 { 0, -3, 1, 38, 64, 32, -1, -3 }
237 }, { /* 131072 < Ratio <= 174762 (~8:3) */
238 { -1, 8, 33, 48, 33, 8, -1, 0 },
239 { -1, 7, 31, 49, 35, 9, -1, -1 },
240 { -1, 6, 30, 49, 36, 10, -1, -1 },
241 { -1, 5, 28, 48, 38, 12, -1, -1 },
242 { -1, 4, 26, 48, 39, 13, 0, -1 },
243 { -1, 3, 24, 47, 41, 15, 0, -1 },
244 { -1, 2, 23, 47, 42, 16, 0, -1 },
245 { -1, 2, 21, 45, 43, 18, 1, -1 },
246 { -1, 1, 19, 45, 45, 19, 1, -1 },
247 { -1, 1, 18, 43, 45, 21, 2, -1 },
248 { -1, 0, 16, 42, 47, 23, 2, -1 },
249 { -1, 0, 15, 41, 47, 24, 3, -1 },
250 { -1, 0, 13, 39, 48, 26, 4, -1 },
251 { -1, -1, 12, 38, 48, 28, 5, -1 },
252 { -1, -1, 10, 36, 49, 30, 6, -1 },
253 { -1, -1, 9, 35, 49, 31, 7, -1 }
254 }, { /* 174762 < Ratio <= 262144 (~8:2) */
255 { 2, 13, 30, 38, 30, 13, 2, 0 },
256 { 2, 12, 29, 38, 30, 14, 3, 0 },
257 { 2, 11, 28, 38, 31, 15, 3, 0 },
258 { 2, 10, 26, 38, 32, 16, 4, 0 },
259 { 1, 10, 26, 37, 33, 17, 4, 0 },
260 { 1, 9, 24, 37, 34, 18, 5, 0 },
261 { 1, 8, 24, 37, 34, 19, 5, 0 },
262 { 1, 7, 22, 36, 35, 20, 6, 1 },
263 { 1, 6, 21, 36, 36, 21, 6, 1 },
264 { 1, 6, 20, 35, 36, 22, 7, 1 },
265 { 0, 5, 19, 34, 37, 24, 8, 1 },
266 { 0, 5, 18, 34, 37, 24, 9, 1 },
267 { 0, 4, 17, 33, 37, 26, 10, 1 },
268 { 0, 4, 16, 32, 38, 26, 10, 2 },
269 { 0, 3, 15, 31, 38, 28, 11, 2 },
270 { 0, 3, 14, 30, 38, 29, 12, 2 }
274 /* 4-tap Filter Coefficient */
275 static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = {
276 { /* Ratio <= 65536 (~8:8) */
293 }, { /* 65536 < Ratio <= 74898 (~8:7) */
310 }, { /* 74898 < Ratio <= 87381 (~8:6) */
327 }, { /* 87381 < Ratio <= 104857 (~8:5) */
344 }, { /* 104857 < Ratio <= 131072 (~8:4) */
361 }, { /* 131072 < Ratio <= 174762 (~8:3) */
378 }, { /* 174762 < Ratio <= 262144 (~8:2) */
398 static int gsc_sw_reset(struct gsc_context *ctx)
401 int count = GSC_RESET_TIMEOUT;
404 cfg = (GSC_SW_RESET_SRESET);
405 gsc_write(cfg, GSC_SW_RESET);
407 /* wait s/w reset complete */
409 cfg = gsc_read(GSC_SW_RESET);
412 usleep_range(1000, 2000);
416 DRM_ERROR("failed to reset gsc h/w.\n");
421 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
422 cfg |= (GSC_IN_BASE_ADDR_MASK |
423 GSC_IN_BASE_ADDR_PINGPONG(0));
424 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
425 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
426 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
428 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
429 cfg |= (GSC_OUT_BASE_ADDR_MASK |
430 GSC_OUT_BASE_ADDR_PINGPONG(0));
431 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
432 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
433 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
438 static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable)
442 gscblk_cfg = readl(SYSREG_GSCBLK_CFG1);
445 gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) |
446 GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) |
447 GSC_BLK_SW_RESET_WB_DEST(ctx->id);
449 gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id);
451 writel(gscblk_cfg, SYSREG_GSCBLK_CFG1);
454 static void gsc_handle_irq(struct gsc_context *ctx, bool enable,
455 bool overflow, bool done)
459 DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n",
460 enable, overflow, done);
462 cfg = gsc_read(GSC_IRQ);
463 cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK);
466 cfg |= GSC_IRQ_ENABLE;
468 cfg &= ~GSC_IRQ_ENABLE;
471 cfg &= ~GSC_IRQ_OR_MASK;
473 cfg |= GSC_IRQ_OR_MASK;
476 cfg &= ~GSC_IRQ_FRMDONE_MASK;
478 cfg |= GSC_IRQ_FRMDONE_MASK;
480 gsc_write(cfg, GSC_IRQ);
484 static int gsc_src_set_fmt(struct device *dev, u32 fmt)
486 struct gsc_context *ctx = get_gsc_context(dev);
487 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
490 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
492 cfg = gsc_read(GSC_IN_CON);
493 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
494 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
495 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE |
496 GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK);
499 case DRM_FORMAT_RGB565:
500 cfg |= GSC_IN_RGB565;
502 case DRM_FORMAT_XRGB8888:
503 cfg |= GSC_IN_XRGB8888;
505 case DRM_FORMAT_BGRX8888:
506 cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP);
508 case DRM_FORMAT_YUYV:
509 cfg |= (GSC_IN_YUV422_1P |
510 GSC_IN_YUV422_1P_ORDER_LSB_Y |
511 GSC_IN_CHROMA_ORDER_CBCR);
513 case DRM_FORMAT_YVYU:
514 cfg |= (GSC_IN_YUV422_1P |
515 GSC_IN_YUV422_1P_ORDER_LSB_Y |
516 GSC_IN_CHROMA_ORDER_CRCB);
518 case DRM_FORMAT_UYVY:
519 cfg |= (GSC_IN_YUV422_1P |
520 GSC_IN_YUV422_1P_OEDER_LSB_C |
521 GSC_IN_CHROMA_ORDER_CBCR);
523 case DRM_FORMAT_VYUY:
524 cfg |= (GSC_IN_YUV422_1P |
525 GSC_IN_YUV422_1P_OEDER_LSB_C |
526 GSC_IN_CHROMA_ORDER_CRCB);
528 case DRM_FORMAT_NV21:
529 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_2P);
531 case DRM_FORMAT_NV61:
532 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV422_2P);
534 case DRM_FORMAT_YUV422:
535 cfg |= GSC_IN_YUV422_3P;
537 case DRM_FORMAT_YUV420:
538 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_3P);
540 case DRM_FORMAT_YVU420:
541 cfg |= (GSC_IN_CHROMA_ORDER_CRCB | GSC_IN_YUV420_3P);
543 case DRM_FORMAT_NV12:
544 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV420_2P);
546 case DRM_FORMAT_NV16:
547 cfg |= (GSC_IN_CHROMA_ORDER_CBCR | GSC_IN_YUV422_2P);
550 dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt);
554 gsc_write(cfg, GSC_IN_CON);
559 static int gsc_src_set_transf(struct device *dev,
560 enum drm_exynos_degree degree,
561 enum drm_exynos_flip flip, bool *swap)
563 struct gsc_context *ctx = get_gsc_context(dev);
564 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
567 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
569 cfg = gsc_read(GSC_IN_CON);
570 cfg &= ~GSC_IN_ROT_MASK;
573 case EXYNOS_DRM_DEGREE_0:
574 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
575 cfg |= GSC_IN_ROT_XFLIP;
576 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
577 cfg |= GSC_IN_ROT_YFLIP;
579 case EXYNOS_DRM_DEGREE_90:
580 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
581 cfg |= GSC_IN_ROT_90_XFLIP;
582 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
583 cfg |= GSC_IN_ROT_90_YFLIP;
585 cfg |= GSC_IN_ROT_90;
587 case EXYNOS_DRM_DEGREE_180:
588 cfg |= GSC_IN_ROT_180;
589 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
590 cfg &= ~GSC_IN_ROT_XFLIP;
591 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
592 cfg &= ~GSC_IN_ROT_YFLIP;
594 case EXYNOS_DRM_DEGREE_270:
595 cfg |= GSC_IN_ROT_270;
596 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
597 cfg &= ~GSC_IN_ROT_XFLIP;
598 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
599 cfg &= ~GSC_IN_ROT_YFLIP;
602 dev_err(ippdrv->dev, "invalid degree value %d.\n", degree);
606 gsc_write(cfg, GSC_IN_CON);
608 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
609 *swap = ctx->rotation;
614 static int gsc_src_set_size(struct device *dev, int swap,
615 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
617 struct gsc_context *ctx = get_gsc_context(dev);
618 struct drm_exynos_pos img_pos = *pos;
619 struct gsc_scaler *sc = &ctx->sc;
622 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
623 swap, pos->x, pos->y, pos->w, pos->h);
631 cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) |
632 GSC_SRCIMG_OFFSET_Y(img_pos.y));
633 gsc_write(cfg, GSC_SRCIMG_OFFSET);
636 cfg = (GSC_CROPPED_WIDTH(img_pos.w) |
637 GSC_CROPPED_HEIGHT(img_pos.h));
638 gsc_write(cfg, GSC_CROPPED_SIZE);
640 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
643 cfg = gsc_read(GSC_SRCIMG_SIZE);
644 cfg &= ~(GSC_SRCIMG_HEIGHT_MASK |
645 GSC_SRCIMG_WIDTH_MASK);
647 cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) |
648 GSC_SRCIMG_HEIGHT(sz->vsize));
650 gsc_write(cfg, GSC_SRCIMG_SIZE);
652 cfg = gsc_read(GSC_IN_CON);
653 cfg &= ~GSC_IN_RGB_TYPE_MASK;
655 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
657 if (pos->w >= GSC_WIDTH_ITU_709)
659 cfg |= GSC_IN_RGB_HD_WIDE;
661 cfg |= GSC_IN_RGB_HD_NARROW;
664 cfg |= GSC_IN_RGB_SD_WIDE;
666 cfg |= GSC_IN_RGB_SD_NARROW;
668 gsc_write(cfg, GSC_IN_CON);
673 static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
674 enum drm_exynos_ipp_buf_type buf_type)
676 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
679 u32 mask = 0x00000001 << buf_id;
681 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
683 /* mask register set */
684 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
687 case IPP_BUF_ENQUEUE:
690 case IPP_BUF_DEQUEUE:
694 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
700 cfg |= masked << buf_id;
701 gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK);
702 gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK);
703 gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK);
708 static int gsc_src_set_addr(struct device *dev,
709 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
710 enum drm_exynos_ipp_buf_type buf_type)
712 struct gsc_context *ctx = get_gsc_context(dev);
713 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
714 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
715 struct drm_exynos_ipp_property *property;
718 DRM_ERROR("failed to get c_node.\n");
722 property = &c_node->property;
724 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
725 property->prop_id, buf_id, buf_type);
727 if (buf_id > GSC_MAX_SRC) {
728 dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id);
732 /* address register set */
734 case IPP_BUF_ENQUEUE:
735 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
736 GSC_IN_BASE_ADDR_Y(buf_id));
737 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
738 GSC_IN_BASE_ADDR_CB(buf_id));
739 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
740 GSC_IN_BASE_ADDR_CR(buf_id));
742 case IPP_BUF_DEQUEUE:
743 gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id));
744 gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id));
745 gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id));
752 return gsc_src_set_buf_seq(ctx, buf_id, buf_type);
755 static struct exynos_drm_ipp_ops gsc_src_ops = {
756 .set_fmt = gsc_src_set_fmt,
757 .set_transf = gsc_src_set_transf,
758 .set_size = gsc_src_set_size,
759 .set_addr = gsc_src_set_addr,
762 static int gsc_dst_set_fmt(struct device *dev, u32 fmt)
764 struct gsc_context *ctx = get_gsc_context(dev);
765 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
768 DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
770 cfg = gsc_read(GSC_OUT_CON);
771 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
772 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
773 GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK |
774 GSC_OUT_GLOBAL_ALPHA_MASK);
777 case DRM_FORMAT_RGB565:
778 cfg |= GSC_OUT_RGB565;
780 case DRM_FORMAT_XRGB8888:
781 cfg |= GSC_OUT_XRGB8888;
783 case DRM_FORMAT_BGRX8888:
784 cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP);
786 case DRM_FORMAT_YUYV:
787 cfg |= (GSC_OUT_YUV422_1P |
788 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
789 GSC_OUT_CHROMA_ORDER_CBCR);
791 case DRM_FORMAT_YVYU:
792 cfg |= (GSC_OUT_YUV422_1P |
793 GSC_OUT_YUV422_1P_ORDER_LSB_Y |
794 GSC_OUT_CHROMA_ORDER_CRCB);
796 case DRM_FORMAT_UYVY:
797 cfg |= (GSC_OUT_YUV422_1P |
798 GSC_OUT_YUV422_1P_OEDER_LSB_C |
799 GSC_OUT_CHROMA_ORDER_CBCR);
801 case DRM_FORMAT_VYUY:
802 cfg |= (GSC_OUT_YUV422_1P |
803 GSC_OUT_YUV422_1P_OEDER_LSB_C |
804 GSC_OUT_CHROMA_ORDER_CRCB);
806 case DRM_FORMAT_NV21:
807 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P);
809 case DRM_FORMAT_NV61:
810 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV422_2P);
812 case DRM_FORMAT_YUV422:
813 cfg |= GSC_OUT_YUV422_3P;
815 case DRM_FORMAT_YUV420:
816 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_3P);
818 case DRM_FORMAT_YVU420:
819 cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_3P);
821 case DRM_FORMAT_NV12:
822 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV420_2P);
824 case DRM_FORMAT_NV16:
825 cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | GSC_OUT_YUV422_2P);
828 dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt);
832 gsc_write(cfg, GSC_OUT_CON);
837 static int gsc_dst_set_transf(struct device *dev,
838 enum drm_exynos_degree degree,
839 enum drm_exynos_flip flip, bool *swap)
841 struct gsc_context *ctx = get_gsc_context(dev);
842 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
845 DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
847 cfg = gsc_read(GSC_IN_CON);
848 cfg &= ~GSC_IN_ROT_MASK;
851 case EXYNOS_DRM_DEGREE_0:
852 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
853 cfg |= GSC_IN_ROT_XFLIP;
854 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
855 cfg |= GSC_IN_ROT_YFLIP;
857 case EXYNOS_DRM_DEGREE_90:
858 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
859 cfg |= GSC_IN_ROT_90_XFLIP;
860 else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
861 cfg |= GSC_IN_ROT_90_YFLIP;
863 cfg |= GSC_IN_ROT_90;
865 case EXYNOS_DRM_DEGREE_180:
866 cfg |= GSC_IN_ROT_180;
867 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
868 cfg &= ~GSC_IN_ROT_XFLIP;
869 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
870 cfg &= ~GSC_IN_ROT_YFLIP;
872 case EXYNOS_DRM_DEGREE_270:
873 cfg |= GSC_IN_ROT_270;
874 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
875 cfg &= ~GSC_IN_ROT_XFLIP;
876 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
877 cfg &= ~GSC_IN_ROT_YFLIP;
880 dev_err(ippdrv->dev, "invalid degree value %d.\n", degree);
884 gsc_write(cfg, GSC_IN_CON);
886 ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0;
887 *swap = ctx->rotation;
892 static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio)
894 DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst);
896 if (src >= dst * 8) {
897 DRM_ERROR("failed to make ratio and shift.\n");
899 } else if (src >= dst * 4)
901 else if (src >= dst * 2)
909 static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor)
911 if (hratio == 4 && vratio == 4)
913 else if ((hratio == 4 && vratio == 2) ||
914 (hratio == 2 && vratio == 4))
916 else if ((hratio == 4 && vratio == 1) ||
917 (hratio == 1 && vratio == 4) ||
918 (hratio == 2 && vratio == 2))
920 else if (hratio == 1 && vratio == 1)
926 static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc,
927 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
929 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
931 u32 src_w, src_h, dst_w, dst_h;
945 ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio);
947 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
951 ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio);
953 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
957 DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n",
958 sc->pre_hratio, sc->pre_vratio);
960 sc->main_hratio = (src_w << 16) / dst_w;
961 sc->main_vratio = (src_h << 16) / dst_h;
963 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
964 sc->main_hratio, sc->main_vratio);
966 gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio,
969 DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor);
971 cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) |
972 GSC_PRESC_H_RATIO(sc->pre_hratio) |
973 GSC_PRESC_V_RATIO(sc->pre_vratio));
974 gsc_write(cfg, GSC_PRE_SCALE_RATIO);
979 static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio)
981 int i, j, k, sc_ratio;
983 if (main_hratio <= GSC_SC_UP_MAX_RATIO)
985 else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8)
987 else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8)
989 else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8)
991 else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8)
993 else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8)
998 for (i = 0; i < GSC_COEF_PHASE; i++)
999 for (j = 0; j < GSC_COEF_H_8T; j++)
1000 for (k = 0; k < GSC_COEF_DEPTH; k++)
1001 gsc_write(h_coef_8t[sc_ratio][i][j],
1002 GSC_HCOEF(i, j, k));
1005 static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio)
1007 int i, j, k, sc_ratio;
1009 if (main_vratio <= GSC_SC_UP_MAX_RATIO)
1011 else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8)
1013 else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8)
1015 else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8)
1017 else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8)
1019 else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8)
1024 for (i = 0; i < GSC_COEF_PHASE; i++)
1025 for (j = 0; j < GSC_COEF_V_4T; j++)
1026 for (k = 0; k < GSC_COEF_DEPTH; k++)
1027 gsc_write(v_coef_4t[sc_ratio][i][j],
1028 GSC_VCOEF(i, j, k));
1031 static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc)
1035 DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n",
1036 sc->main_hratio, sc->main_vratio);
1038 gsc_set_h_coef(ctx, sc->main_hratio);
1039 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
1040 gsc_write(cfg, GSC_MAIN_H_RATIO);
1042 gsc_set_v_coef(ctx, sc->main_vratio);
1043 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
1044 gsc_write(cfg, GSC_MAIN_V_RATIO);
1047 static int gsc_dst_set_size(struct device *dev, int swap,
1048 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1050 struct gsc_context *ctx = get_gsc_context(dev);
1051 struct drm_exynos_pos img_pos = *pos;
1052 struct gsc_scaler *sc = &ctx->sc;
1055 DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n",
1056 swap, pos->x, pos->y, pos->w, pos->h);
1064 cfg = (GSC_DSTIMG_OFFSET_X(pos->x) |
1065 GSC_DSTIMG_OFFSET_Y(pos->y));
1066 gsc_write(cfg, GSC_DSTIMG_OFFSET);
1069 cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h));
1070 gsc_write(cfg, GSC_SCALED_SIZE);
1072 DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize);
1075 cfg = gsc_read(GSC_DSTIMG_SIZE);
1076 cfg &= ~(GSC_DSTIMG_HEIGHT_MASK |
1077 GSC_DSTIMG_WIDTH_MASK);
1078 cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) |
1079 GSC_DSTIMG_HEIGHT(sz->vsize));
1080 gsc_write(cfg, GSC_DSTIMG_SIZE);
1082 cfg = gsc_read(GSC_OUT_CON);
1083 cfg &= ~GSC_OUT_RGB_TYPE_MASK;
1085 DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range);
1087 if (pos->w >= GSC_WIDTH_ITU_709)
1089 cfg |= GSC_OUT_RGB_HD_WIDE;
1091 cfg |= GSC_OUT_RGB_HD_NARROW;
1094 cfg |= GSC_OUT_RGB_SD_WIDE;
1096 cfg |= GSC_OUT_RGB_SD_NARROW;
1098 gsc_write(cfg, GSC_OUT_CON);
1103 static int gsc_dst_get_buf_seq(struct gsc_context *ctx)
1105 u32 cfg, i, buf_num = GSC_REG_SZ;
1106 u32 mask = 0x00000001;
1108 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1110 for (i = 0; i < GSC_REG_SZ; i++)
1111 if (cfg & (mask << i))
1114 DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
1119 static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id,
1120 enum drm_exynos_ipp_buf_type buf_type)
1122 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1125 u32 mask = 0x00000001 << buf_id;
1128 DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1130 mutex_lock(&ctx->lock);
1132 /* mask register set */
1133 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1136 case IPP_BUF_ENQUEUE:
1139 case IPP_BUF_DEQUEUE:
1143 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1150 cfg |= masked << buf_id;
1151 gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK);
1152 gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK);
1153 gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK);
1155 /* interrupt enable */
1156 if (buf_type == IPP_BUF_ENQUEUE &&
1157 gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START)
1158 gsc_handle_irq(ctx, true, false, true);
1160 /* interrupt disable */
1161 if (buf_type == IPP_BUF_DEQUEUE &&
1162 gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP)
1163 gsc_handle_irq(ctx, false, false, true);
1166 mutex_unlock(&ctx->lock);
1170 static int gsc_dst_set_addr(struct device *dev,
1171 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1172 enum drm_exynos_ipp_buf_type buf_type)
1174 struct gsc_context *ctx = get_gsc_context(dev);
1175 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1176 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1177 struct drm_exynos_ipp_property *property;
1180 DRM_ERROR("failed to get c_node.\n");
1184 property = &c_node->property;
1186 DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1187 property->prop_id, buf_id, buf_type);
1189 if (buf_id > GSC_MAX_DST) {
1190 dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id);
1194 /* address register set */
1196 case IPP_BUF_ENQUEUE:
1197 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1198 GSC_OUT_BASE_ADDR_Y(buf_id));
1199 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1200 GSC_OUT_BASE_ADDR_CB(buf_id));
1201 gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1202 GSC_OUT_BASE_ADDR_CR(buf_id));
1204 case IPP_BUF_DEQUEUE:
1205 gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id));
1206 gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id));
1207 gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id));
1214 return gsc_dst_set_buf_seq(ctx, buf_id, buf_type);
1217 static struct exynos_drm_ipp_ops gsc_dst_ops = {
1218 .set_fmt = gsc_dst_set_fmt,
1219 .set_transf = gsc_dst_set_transf,
1220 .set_size = gsc_dst_set_size,
1221 .set_addr = gsc_dst_set_addr,
1224 static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable)
1226 DRM_DEBUG_KMS("enable[%d]\n", enable);
1229 clk_enable(ctx->gsc_clk);
1230 ctx->suspended = false;
1232 clk_disable(ctx->gsc_clk);
1233 ctx->suspended = true;
1239 static int gsc_get_src_buf_index(struct gsc_context *ctx)
1241 u32 cfg, curr_index, i;
1242 u32 buf_id = GSC_MAX_SRC;
1245 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1247 cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK);
1248 curr_index = GSC_IN_CURR_GET_INDEX(cfg);
1250 for (i = curr_index; i < GSC_MAX_SRC; i++) {
1251 if (!((cfg >> i) & 0x1)) {
1257 if (buf_id == GSC_MAX_SRC) {
1258 DRM_ERROR("failed to get in buffer index.\n");
1262 ret = gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1264 DRM_ERROR("failed to dequeue.\n");
1268 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1269 curr_index, buf_id);
1274 static int gsc_get_dst_buf_index(struct gsc_context *ctx)
1276 u32 cfg, curr_index, i;
1277 u32 buf_id = GSC_MAX_DST;
1280 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1282 cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK);
1283 curr_index = GSC_OUT_CURR_GET_INDEX(cfg);
1285 for (i = curr_index; i < GSC_MAX_DST; i++) {
1286 if (!((cfg >> i) & 0x1)) {
1292 if (buf_id == GSC_MAX_DST) {
1293 DRM_ERROR("failed to get out buffer index.\n");
1297 ret = gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE);
1299 DRM_ERROR("failed to dequeue.\n");
1303 DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg,
1304 curr_index, buf_id);
1309 static irqreturn_t gsc_irq_handler(int irq, void *dev_id)
1311 struct gsc_context *ctx = dev_id;
1312 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1313 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1314 struct drm_exynos_ipp_event_work *event_work =
1317 int buf_id[EXYNOS_DRM_OPS_MAX];
1319 DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id);
1321 status = gsc_read(GSC_IRQ);
1322 if (status & GSC_IRQ_STATUS_OR_IRQ) {
1323 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
1328 if (status & GSC_IRQ_STATUS_OR_FRM_DONE) {
1329 dev_dbg(ippdrv->dev, "occurred frame done at %d, status 0x%x.\n",
1332 buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx);
1333 if (buf_id[EXYNOS_DRM_OPS_SRC] < 0)
1336 buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx);
1337 if (buf_id[EXYNOS_DRM_OPS_DST] < 0)
1340 DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n",
1341 buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]);
1343 event_work->ippdrv = ippdrv;
1344 event_work->buf_id[EXYNOS_DRM_OPS_SRC] =
1345 buf_id[EXYNOS_DRM_OPS_SRC];
1346 event_work->buf_id[EXYNOS_DRM_OPS_DST] =
1347 buf_id[EXYNOS_DRM_OPS_DST];
1348 queue_work(ippdrv->event_workq, &event_work->work);
1354 static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1356 struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1358 prop_list->version = 1;
1359 prop_list->writeback = 1;
1360 prop_list->refresh_min = GSC_REFRESH_MIN;
1361 prop_list->refresh_max = GSC_REFRESH_MAX;
1362 prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1363 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1364 prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1365 (1 << EXYNOS_DRM_DEGREE_90) |
1366 (1 << EXYNOS_DRM_DEGREE_180) |
1367 (1 << EXYNOS_DRM_DEGREE_270);
1369 prop_list->crop = 1;
1370 prop_list->crop_max.hsize = GSC_CROP_MAX;
1371 prop_list->crop_max.vsize = GSC_CROP_MAX;
1372 prop_list->crop_min.hsize = GSC_CROP_MIN;
1373 prop_list->crop_min.vsize = GSC_CROP_MIN;
1374 prop_list->scale = 1;
1375 prop_list->scale_max.hsize = GSC_SCALE_MAX;
1376 prop_list->scale_max.vsize = GSC_SCALE_MAX;
1377 prop_list->scale_min.hsize = GSC_SCALE_MIN;
1378 prop_list->scale_min.vsize = GSC_SCALE_MIN;
1383 static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip)
1386 case EXYNOS_DRM_FLIP_NONE:
1387 case EXYNOS_DRM_FLIP_VERTICAL:
1388 case EXYNOS_DRM_FLIP_HORIZONTAL:
1389 case EXYNOS_DRM_FLIP_BOTH:
1392 DRM_DEBUG_KMS("invalid flip\n");
1397 static int gsc_ippdrv_check_property(struct device *dev,
1398 struct drm_exynos_ipp_property *property)
1400 struct gsc_context *ctx = get_gsc_context(dev);
1401 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1402 struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1403 struct drm_exynos_ipp_config *config;
1404 struct drm_exynos_pos *pos;
1405 struct drm_exynos_sz *sz;
1409 for_each_ipp_ops(i) {
1410 if ((i == EXYNOS_DRM_OPS_SRC) &&
1411 (property->cmd == IPP_CMD_WB))
1414 config = &property->config[i];
1418 /* check for flip */
1419 if (!gsc_check_drm_flip(config->flip)) {
1420 DRM_ERROR("invalid flip.\n");
1424 /* check for degree */
1425 switch (config->degree) {
1426 case EXYNOS_DRM_DEGREE_90:
1427 case EXYNOS_DRM_DEGREE_270:
1430 case EXYNOS_DRM_DEGREE_0:
1431 case EXYNOS_DRM_DEGREE_180:
1435 DRM_ERROR("invalid degree.\n");
1439 /* check for buffer bound */
1440 if ((pos->x + pos->w > sz->hsize) ||
1441 (pos->y + pos->h > sz->vsize)) {
1442 DRM_ERROR("out of buf bound.\n");
1446 /* check for crop */
1447 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1449 if ((pos->h < pp->crop_min.hsize) ||
1450 (sz->vsize > pp->crop_max.hsize) ||
1451 (pos->w < pp->crop_min.vsize) ||
1452 (sz->hsize > pp->crop_max.vsize)) {
1453 DRM_ERROR("out of crop size.\n");
1457 if ((pos->w < pp->crop_min.hsize) ||
1458 (sz->hsize > pp->crop_max.hsize) ||
1459 (pos->h < pp->crop_min.vsize) ||
1460 (sz->vsize > pp->crop_max.vsize)) {
1461 DRM_ERROR("out of crop size.\n");
1467 /* check for scale */
1468 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1470 if ((pos->h < pp->scale_min.hsize) ||
1471 (sz->vsize > pp->scale_max.hsize) ||
1472 (pos->w < pp->scale_min.vsize) ||
1473 (sz->hsize > pp->scale_max.vsize)) {
1474 DRM_ERROR("out of scale size.\n");
1478 if ((pos->w < pp->scale_min.hsize) ||
1479 (sz->hsize > pp->scale_max.hsize) ||
1480 (pos->h < pp->scale_min.vsize) ||
1481 (sz->vsize > pp->scale_max.vsize)) {
1482 DRM_ERROR("out of scale size.\n");
1492 for_each_ipp_ops(i) {
1493 if ((i == EXYNOS_DRM_OPS_SRC) &&
1494 (property->cmd == IPP_CMD_WB))
1497 config = &property->config[i];
1501 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1502 i ? "dst" : "src", config->flip, config->degree,
1503 pos->x, pos->y, pos->w, pos->h,
1504 sz->hsize, sz->vsize);
1511 static int gsc_ippdrv_reset(struct device *dev)
1513 struct gsc_context *ctx = get_gsc_context(dev);
1514 struct gsc_scaler *sc = &ctx->sc;
1517 /* reset h/w block */
1518 ret = gsc_sw_reset(ctx);
1520 dev_err(dev, "failed to reset hardware.\n");
1524 /* scaler setting */
1525 memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1531 static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1533 struct gsc_context *ctx = get_gsc_context(dev);
1534 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1535 struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1536 struct drm_exynos_ipp_property *property;
1537 struct drm_exynos_ipp_config *config;
1538 struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX];
1539 struct drm_exynos_ipp_set_wb set_wb;
1543 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1546 DRM_ERROR("failed to get c_node.\n");
1550 property = &c_node->property;
1552 gsc_handle_irq(ctx, true, false, true);
1554 for_each_ipp_ops(i) {
1555 config = &property->config[i];
1556 img_pos[i] = config->pos;
1561 /* enable one shot */
1562 cfg = gsc_read(GSC_ENABLE);
1563 cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK |
1564 GSC_ENABLE_CLK_GATE_MODE_MASK);
1565 cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT;
1566 gsc_write(cfg, GSC_ENABLE);
1568 /* src dma memory */
1569 cfg = gsc_read(GSC_IN_CON);
1570 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1571 cfg |= GSC_IN_PATH_MEMORY;
1572 gsc_write(cfg, GSC_IN_CON);
1574 /* dst dma memory */
1575 cfg = gsc_read(GSC_OUT_CON);
1576 cfg |= GSC_OUT_PATH_MEMORY;
1577 gsc_write(cfg, GSC_OUT_CON);
1581 set_wb.refresh = property->refresh_rate;
1582 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1583 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1585 /* src local path */
1586 cfg = gsc_read(GSC_IN_CON);
1587 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1588 cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB);
1589 gsc_write(cfg, GSC_IN_CON);
1591 /* dst dma memory */
1592 cfg = gsc_read(GSC_OUT_CON);
1593 cfg |= GSC_OUT_PATH_MEMORY;
1594 gsc_write(cfg, GSC_OUT_CON);
1596 case IPP_CMD_OUTPUT:
1597 /* src dma memory */
1598 cfg = gsc_read(GSC_IN_CON);
1599 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
1600 cfg |= GSC_IN_PATH_MEMORY;
1601 gsc_write(cfg, GSC_IN_CON);
1603 /* dst local path */
1604 cfg = gsc_read(GSC_OUT_CON);
1605 cfg |= GSC_OUT_PATH_MEMORY;
1606 gsc_write(cfg, GSC_OUT_CON);
1610 dev_err(dev, "invalid operations.\n");
1614 ret = gsc_set_prescaler(ctx, &ctx->sc,
1615 &img_pos[EXYNOS_DRM_OPS_SRC],
1616 &img_pos[EXYNOS_DRM_OPS_DST]);
1618 dev_err(dev, "failed to set precalser.\n");
1622 gsc_set_scaler(ctx, &ctx->sc);
1624 cfg = gsc_read(GSC_ENABLE);
1625 cfg |= GSC_ENABLE_ON;
1626 gsc_write(cfg, GSC_ENABLE);
1631 static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1633 struct gsc_context *ctx = get_gsc_context(dev);
1634 struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1637 DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1644 gsc_set_gscblk_fimd_wb(ctx, set_wb.enable);
1645 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1647 case IPP_CMD_OUTPUT:
1649 dev_err(dev, "invalid operations.\n");
1653 gsc_handle_irq(ctx, false, false, true);
1655 /* reset sequence */
1656 gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK);
1657 gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK);
1658 gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK);
1660 cfg = gsc_read(GSC_ENABLE);
1661 cfg &= ~GSC_ENABLE_ON;
1662 gsc_write(cfg, GSC_ENABLE);
1665 static int gsc_probe(struct platform_device *pdev)
1667 struct device *dev = &pdev->dev;
1668 struct gsc_context *ctx;
1669 struct resource *res;
1670 struct exynos_drm_ippdrv *ippdrv;
1673 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1678 ctx->gsc_clk = devm_clk_get(dev, "gscl");
1679 if (IS_ERR(ctx->gsc_clk)) {
1680 dev_err(dev, "failed to get gsc clock.\n");
1681 return PTR_ERR(ctx->gsc_clk);
1684 /* resource memory */
1685 ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1686 ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1687 if (IS_ERR(ctx->regs))
1688 return PTR_ERR(ctx->regs);
1691 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1693 dev_err(dev, "failed to request irq resource.\n");
1697 ctx->irq = res->start;
1698 ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler,
1699 IRQF_ONESHOT, "drm_gsc", ctx);
1701 dev_err(dev, "failed to request irq.\n");
1705 /* context initailization */
1708 ippdrv = &ctx->ippdrv;
1710 ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops;
1711 ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops;
1712 ippdrv->check_property = gsc_ippdrv_check_property;
1713 ippdrv->reset = gsc_ippdrv_reset;
1714 ippdrv->start = gsc_ippdrv_start;
1715 ippdrv->stop = gsc_ippdrv_stop;
1716 ret = gsc_init_prop_list(ippdrv);
1718 dev_err(dev, "failed to init property list.\n");
1722 DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1724 mutex_init(&ctx->lock);
1725 platform_set_drvdata(pdev, ctx);
1727 pm_runtime_set_active(dev);
1728 pm_runtime_enable(dev);
1730 ret = exynos_drm_ippdrv_register(ippdrv);
1732 dev_err(dev, "failed to register drm gsc device.\n");
1733 goto err_ippdrv_register;
1736 dev_info(dev, "drm gsc registered successfully.\n");
1740 err_ippdrv_register:
1741 pm_runtime_disable(dev);
1745 static int gsc_remove(struct platform_device *pdev)
1747 struct device *dev = &pdev->dev;
1748 struct gsc_context *ctx = get_gsc_context(dev);
1749 struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1751 exynos_drm_ippdrv_unregister(ippdrv);
1752 mutex_destroy(&ctx->lock);
1754 pm_runtime_set_suspended(dev);
1755 pm_runtime_disable(dev);
1760 #ifdef CONFIG_PM_SLEEP
1761 static int gsc_suspend(struct device *dev)
1763 struct gsc_context *ctx = get_gsc_context(dev);
1765 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1767 if (pm_runtime_suspended(dev))
1770 return gsc_clk_ctrl(ctx, false);
1773 static int gsc_resume(struct device *dev)
1775 struct gsc_context *ctx = get_gsc_context(dev);
1777 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1779 if (!pm_runtime_suspended(dev))
1780 return gsc_clk_ctrl(ctx, true);
1787 static int gsc_runtime_suspend(struct device *dev)
1789 struct gsc_context *ctx = get_gsc_context(dev);
1791 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1793 return gsc_clk_ctrl(ctx, false);
1796 static int gsc_runtime_resume(struct device *dev)
1798 struct gsc_context *ctx = get_gsc_context(dev);
1800 DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1802 return gsc_clk_ctrl(ctx, true);
1806 static const struct dev_pm_ops gsc_pm_ops = {
1807 SET_SYSTEM_SLEEP_PM_OPS(gsc_suspend, gsc_resume)
1808 SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL)
1811 struct platform_driver gsc_driver = {
1813 .remove = gsc_remove,
1815 .name = "exynos-drm-gsc",
1816 .owner = THIS_MODULE,