drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/irq.h>
  18 #include <linux/mfd/syscon.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/regmap.h>
  23
  24 #include <video/exynos5433_decon.h>
  25
  26 #include "exynos_drm_drv.h"
  27 #include "exynos_drm_crtc.h"
  28 #include "exynos_drm_fb.h"
  29 #include "exynos_drm_plane.h"
  30 #include "exynos_drm_iommu.h"
  31
  32 #define DSD_CFG_MUX 0x1004
  33 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  34
  35 #define WINDOWS_NR      3
  36 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  37
  38 #define I80_HW_TRG      (1 << 0)
  39 #define IFTYPE_HDMI     (1 << 1)
  40
  41 static const char * const decon_clks_name[] = {
  42         "pclk",
  43         "aclk_decon",
  44         "aclk_smmu_decon0x",
  45         "aclk_xiu_decon0x",
  46         "pclk_smmu_decon0x",
  47         "sclk_decon_vclk",
  48         "sclk_decon_eclk",
  49 };
  50
  51 struct decon_context {
  52         struct device                   *dev;
  53         struct drm_device               *drm_dev;
  54         struct exynos_drm_crtc          *crtc;
  55         struct exynos_drm_plane         planes[WINDOWS_NR];
  56         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  57         void __iomem                    *addr;
  58         struct regmap                   *sysreg;
  59         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  60         unsigned int                    irq;
  61         unsigned int                    irq_vsync;
  62         unsigned int                    irq_lcd_sys;
  63         unsigned int                    te_irq;
  64         unsigned long                   out_type;
  65         int                             first_win;
  66         spinlock_t                      vblank_lock;
  67         u32                             frame_id;
  68 };
  69
  70 static const uint32_t decon_formats[] = {
  71         DRM_FORMAT_XRGB1555,
  72         DRM_FORMAT_RGB565,
  73         DRM_FORMAT_XRGB8888,
  74         DRM_FORMAT_ARGB8888,
  75 };
  76
  77 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  78         DRM_PLANE_TYPE_PRIMARY,
  79         DRM_PLANE_TYPE_OVERLAY,
  80         DRM_PLANE_TYPE_CURSOR,
  81 };
  82
  83 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  84                                   u32 val)
  85 {
  86         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  87         writel(val, ctx->addr + reg);
  88 }
  89
  90 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  91 {
  92         struct decon_context *ctx = crtc->ctx;
  93         u32 val;
  94
  95         val = VIDINTCON0_INTEN;
  96         if (crtc->i80_mode)
  97                 val |= VIDINTCON0_FRAMEDONE;
  98         else
  99                 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
 100
 101         writel(val, ctx->addr + DECON_VIDINTCON0);
 102
 103         enable_irq(ctx->irq);
 104         if (!(ctx->out_type & I80_HW_TRG))
 105                 enable_irq(ctx->te_irq);
 106
 107         return 0;
 108 }
 109
 110 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 111 {
 112         struct decon_context *ctx = crtc->ctx;
 113
 114         if (!(ctx->out_type & I80_HW_TRG))
 115                 disable_irq_nosync(ctx->te_irq);
 116         disable_irq_nosync(ctx->irq);
 117
 118         writel(0, ctx->addr + DECON_VIDINTCON0);
 119 }
 120
 121 /* return number of starts/ends of frame transmissions since reset */
 122 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
 123 {
 124         u32 frm, pfrm, status, cnt = 2;
 125
 126         /* To get consistent result repeat read until frame id is stable.
 127          * Usually the loop will be executed once, in rare cases when the loop
 128          * is executed at frame change time 2nd pass will be needed.
 129          */
 130         frm = readl(ctx->addr + DECON_CRFMID);
 131         do {
 132                 status = readl(ctx->addr + DECON_VIDCON1);
 133                 pfrm = frm;
 134                 frm = readl(ctx->addr + DECON_CRFMID);
 135         } while (frm != pfrm && --cnt);
 136
 137         /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
 138          * of RGB, it should be taken into account.
 139          */
 140         if (!frm)
 141                 return 0;
 142
 143         switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
 144         case VIDCON1_VSTATUS_VS:
 145                 if (!(ctx->crtc->i80_mode))
 146                         --frm;
 147                 break;
 148         case VIDCON1_VSTATUS_BP:
 149                 --frm;
 150                 break;
 151         case VIDCON1_I80_ACTIVE:
 152         case VIDCON1_VSTATUS_AC:
 153                 if (end)
 154                         --frm;
 155                 break;
 156         default:
 157                 break;
 158         }
 159
 160         return frm;
 161 }
 162
 163 static void decon_setup_trigger(struct decon_context *ctx)
 164 {
 165         if (!ctx->crtc->i80_mode && !(ctx->out_type & I80_HW_TRG))
 166                 return;
 167
 168         if (!(ctx->out_type & I80_HW_TRG)) {
 169                 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 170                        TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 171                        ctx->addr + DECON_TRIGCON);
 172                 return;
 173         }
 174
 175         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 176                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 177
 178         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 179                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 180                 DRM_ERROR("Cannot update sysreg.\n");
 181 }
 182
 183 static void decon_commit(struct exynos_drm_crtc *crtc)
 184 {
 185         struct decon_context *ctx = crtc->ctx;
 186         struct drm_display_mode *m = &crtc->base.mode;
 187         bool interlaced = false;
 188         u32 val;
 189
 190         if (ctx->out_type & IFTYPE_HDMI) {
 191                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 192                 m->crtc_hsync_end = m->crtc_htotal - 92;
 193                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 194                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 195                 if (m->flags & DRM_MODE_FLAG_INTERLACE)
 196                         interlaced = true;
 197         }
 198
 199         decon_setup_trigger(ctx);
 200
 201         /* lcd on and use command if */
 202         val = VIDOUT_LCD_ON;
 203         if (interlaced)
 204                 val |= VIDOUT_INTERLACE_EN_F;
 205         if (crtc->i80_mode) {
 206                 val |= VIDOUT_COMMAND_IF;
 207         } else {
 208                 val |= VIDOUT_RGB_IF;
 209         }
 210
 211         writel(val, ctx->addr + DECON_VIDOUTCON0);
 212
 213         if (interlaced)
 214                 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
 215                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 216         else
 217                 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 218                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 219         writel(val, ctx->addr + DECON_VIDTCON2);
 220
 221         if (!crtc->i80_mode) {
 222                 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
 223                 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
 224
 225                 if (interlaced)
 226                         vbp = vbp / 2 - 1;
 227                 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
 228                 writel(val, ctx->addr + DECON_VIDTCON00);
 229
 230                 val = VIDTCON01_VSPW_F(
 231                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 232                 writel(val, ctx->addr + DECON_VIDTCON01);
 233
 234                 val = VIDTCON10_HBPD_F(
 235                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 236                         VIDTCON10_HFPD_F(
 237                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 238                 writel(val, ctx->addr + DECON_VIDTCON10);
 239
 240                 val = VIDTCON11_HSPW_F(
 241                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 242                 writel(val, ctx->addr + DECON_VIDTCON11);
 243         }
 244
 245         /* enable output and display signal */
 246         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 247
 248         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 249 }
 250
 251 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 252                                  struct drm_framebuffer *fb)
 253 {
 254         unsigned long val;
 255
 256         val = readl(ctx->addr + DECON_WINCONx(win));
 257         val &= WINCONx_ENWIN_F;
 258
 259         switch (fb->format->format) {
 260         case DRM_FORMAT_XRGB1555:
 261                 val |= WINCONx_BPPMODE_16BPP_I1555;
 262                 val |= WINCONx_HAWSWP_F;
 263                 val |= WINCONx_BURSTLEN_16WORD;
 264                 break;
 265         case DRM_FORMAT_RGB565:
 266                 val |= WINCONx_BPPMODE_16BPP_565;
 267                 val |= WINCONx_HAWSWP_F;
 268                 val |= WINCONx_BURSTLEN_16WORD;
 269                 break;
 270         case DRM_FORMAT_XRGB8888:
 271                 val |= WINCONx_BPPMODE_24BPP_888;
 272                 val |= WINCONx_WSWP_F;
 273                 val |= WINCONx_BURSTLEN_16WORD;
 274                 break;
 275         case DRM_FORMAT_ARGB8888:
 276         default:
 277                 val |= WINCONx_BPPMODE_32BPP_A8888;
 278                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 279                 val |= WINCONx_BURSTLEN_16WORD;
 280                 break;
 281         }
 282
 283         DRM_DEBUG_KMS("cpp = %u\n", fb->format->cpp[0]);
 284
 285         /*
 286          * In case of exynos, setting dma-burst to 16Word causes permanent
 287          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 288          * switching which is based on plane size is not recommended as
 289          * plane size varies a lot towards the end of the screen and rapid
 290          * movement causes unstable DMA which results into iommu crash/tear.
 291          */
 292
 293         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 294                 val &= ~WINCONx_BURSTLEN_MASK;
 295                 val |= WINCONx_BURSTLEN_8WORD;
 296         }
 297
 298         writel(val, ctx->addr + DECON_WINCONx(win));
 299 }
 300
 301 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
 302 {
 303         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
 304                        protect ? ~0 : 0);
 305 }
 306
 307 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 308 {
 309         struct decon_context *ctx = crtc->ctx;
 310
 311         decon_shadow_protect(ctx, true);
 312 }
 313
 314 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 315 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 316 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 317
 318 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 319                                struct exynos_drm_plane *plane)
 320 {
 321         struct exynos_drm_plane_state *state =
 322                                 to_exynos_plane_state(plane->base.state);
 323         struct decon_context *ctx = crtc->ctx;
 324         struct drm_framebuffer *fb = state->base.fb;
 325         unsigned int win = plane->index;
 326         unsigned int cpp = fb->format->cpp[0];
 327         unsigned int pitch = fb->pitches[0];
 328         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 329         u32 val;
 330
 331         if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
 332                 val = COORDINATE_X(state->crtc.x) |
 333                         COORDINATE_Y(state->crtc.y / 2);
 334                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 335
 336                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 337                         COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
 338                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 339         } else {
 340                 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 341                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 342
 343                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 344                                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 345                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 346         }
 347
 348         val = VIDOSD_Wx_ALPHA_R_F(0xff) | VIDOSD_Wx_ALPHA_G_F(0xff) |
 349                 VIDOSD_Wx_ALPHA_B_F(0xff);
 350         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 351
 352         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 353                 VIDOSD_Wx_ALPHA_B_F(0x0);
 354         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 355
 356         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 357
 358         val = dma_addr + pitch * state->src.h;
 359         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 360
 361         if (!(ctx->out_type & IFTYPE_HDMI))
 362                 val = BIT_VAL(pitch - state->crtc.w * cpp, 27, 14)
 363                         | BIT_VAL(state->crtc.w * cpp, 13, 0);
 364         else
 365                 val = BIT_VAL(pitch - state->crtc.w * cpp, 29, 15)
 366                         | BIT_VAL(state->crtc.w * cpp, 14, 0);
 367         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 368
 369         decon_win_set_pixfmt(ctx, win, fb);
 370
 371         /* window enable */
 372         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 373 }
 374
 375 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 376                                 struct exynos_drm_plane *plane)
 377 {
 378         struct decon_context *ctx = crtc->ctx;
 379         unsigned int win = plane->index;
 380
 381         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 382 }
 383
 384 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 385 {
 386         struct decon_context *ctx = crtc->ctx;
 387         unsigned long flags;
 388
 389         spin_lock_irqsave(&ctx->vblank_lock, flags);
 390
 391         decon_shadow_protect(ctx, false);
 392
 393         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 394
 395         ctx->frame_id = decon_get_frame_count(ctx, true);
 396
 397         exynos_crtc_handle_event(crtc);
 398
 399         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 400 }
 401
 402 static void decon_swreset(struct decon_context *ctx)
 403 {
 404         unsigned long flags;
 405         u32 val;
 406         int ret;
 407
 408         writel(0, ctx->addr + DECON_VIDCON0);
 409         readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
 410                            ~val & VIDCON0_STOP_STATUS, 12, 20000);
 411
 412         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 413         ret = readl_poll_timeout(ctx->addr + DECON_VIDCON0, val,
 414                                  ~val & VIDCON0_SWRESET, 12, 20000);
 415
 416         WARN(ret < 0, "failed to software reset DECON\n");
 417
 418         spin_lock_irqsave(&ctx->vblank_lock, flags);
 419         ctx->frame_id = 0;
 420         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 421
 422         if (!(ctx->out_type & IFTYPE_HDMI))
 423                 return;
 424
 425         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 426         decon_set_bits(ctx, DECON_CMU,
 427                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 428         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 429         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 430                ctx->addr + DECON_CRCCTRL);
 431 }
 432
 433 static void decon_enable(struct exynos_drm_crtc *crtc)
 434 {
 435         struct decon_context *ctx = crtc->ctx;
 436
 437         pm_runtime_get_sync(ctx->dev);
 438
 439         exynos_drm_pipe_clk_enable(crtc, true);
 440
 441         decon_swreset(ctx);
 442
 443         decon_commit(ctx->crtc);
 444 }
 445
 446 static void decon_disable(struct exynos_drm_crtc *crtc)
 447 {
 448         struct decon_context *ctx = crtc->ctx;
 449         int i;
 450
 451         if (!(ctx->out_type & I80_HW_TRG))
 452                 synchronize_irq(ctx->te_irq);
 453         synchronize_irq(ctx->irq);
 454
 455         /*
 456          * We need to make sure that all windows are disabled before we
 457          * suspend that connector. Otherwise we might try to scan from
 458          * a destroyed buffer later.
 459          */
 460         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 461                 decon_disable_plane(crtc, &ctx->planes[i]);
 462
 463         decon_swreset(ctx);
 464
 465         exynos_drm_pipe_clk_enable(crtc, false);
 466
 467         pm_runtime_put_sync(ctx->dev);
 468 }
 469
 470 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
 471 {
 472         struct decon_context *ctx = dev_id;
 473
 474         decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 475
 476         return IRQ_HANDLED;
 477 }
 478
 479 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 480 {
 481         struct decon_context *ctx = crtc->ctx;
 482         int win, i, ret;
 483
 484         DRM_DEBUG_KMS("%s\n", __FILE__);
 485
 486         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 487                 ret = clk_prepare_enable(ctx->clks[i]);
 488                 if (ret < 0)
 489                         goto err;
 490         }
 491
 492         decon_shadow_protect(ctx, true);
 493         for (win = 0; win < WINDOWS_NR; win++)
 494                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 495         decon_shadow_protect(ctx, false);
 496
 497         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 498
 499         /* TODO: wait for possible vsync */
 500         msleep(50);
 501
 502 err:
 503         while (--i >= 0)
 504                 clk_disable_unprepare(ctx->clks[i]);
 505 }
 506
 507 static enum drm_mode_status decon_mode_valid(struct exynos_drm_crtc *crtc,
 508                 const struct drm_display_mode *mode)
 509 {
 510         struct decon_context *ctx = crtc->ctx;
 511
 512         ctx->irq = crtc->i80_mode ? ctx->irq_lcd_sys : ctx->irq_vsync;
 513
 514         if (ctx->irq)
 515                 return MODE_OK;
 516
 517         dev_info(ctx->dev, "Sink requires %s mode, but appropriate interrupt is not provided.\n",
 518                         crtc->i80_mode ? "command" : "video");
 519
 520         return MODE_BAD;
 521 }
 522
 523 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 524         .enable                 = decon_enable,
 525         .disable                = decon_disable,
 526         .enable_vblank          = decon_enable_vblank,
 527         .disable_vblank         = decon_disable_vblank,
 528         .atomic_begin           = decon_atomic_begin,
 529         .update_plane           = decon_update_plane,
 530         .disable_plane          = decon_disable_plane,
 531         .mode_valid             = decon_mode_valid,
 532         .atomic_flush           = decon_atomic_flush,
 533 };
 534
 535 static int decon_bind(struct device *dev, struct device *master, void *data)
 536 {
 537         struct decon_context *ctx = dev_get_drvdata(dev);
 538         struct drm_device *drm_dev = data;
 539         struct exynos_drm_plane *exynos_plane;
 540         enum exynos_drm_output_type out_type;
 541         unsigned int win;
 542         int ret;
 543
 544         ctx->drm_dev = drm_dev;
 545
 546         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 547                 int tmp = (win == ctx->first_win) ? 0 : win;
 548
 549                 ctx->configs[win].pixel_formats = decon_formats;
 550                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 551                 ctx->configs[win].zpos = win;
 552                 ctx->configs[win].type = decon_win_types[tmp];
 553
 554                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 555                                         &ctx->configs[win]);
 556                 if (ret)
 557                         return ret;
 558         }
 559
 560         exynos_plane = &ctx->planes[ctx->first_win];
 561         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 562                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 563         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 564                         out_type, &decon_crtc_ops, ctx);
 565         if (IS_ERR(ctx->crtc))
 566                 return PTR_ERR(ctx->crtc);
 567
 568         decon_clear_channels(ctx->crtc);
 569
 570         return drm_iommu_attach_device(drm_dev, dev);
 571 }
 572
 573 static void decon_unbind(struct device *dev, struct device *master, void *data)
 574 {
 575         struct decon_context *ctx = dev_get_drvdata(dev);
 576
 577         decon_disable(ctx->crtc);
 578
 579         /* detach this sub driver from iommu mapping if supported. */
 580         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 581 }
 582
 583 static const struct component_ops decon_component_ops = {
 584         .bind   = decon_bind,
 585         .unbind = decon_unbind,
 586 };
 587
 588 static void decon_handle_vblank(struct decon_context *ctx)
 589 {
 590         u32 frm;
 591
 592         spin_lock(&ctx->vblank_lock);
 593
 594         frm = decon_get_frame_count(ctx, true);
 595
 596         if (frm != ctx->frame_id) {
 597                 /* handle only if incremented, take care of wrap-around */
 598                 if ((s32)(frm - ctx->frame_id) > 0)
 599                         drm_crtc_handle_vblank(&ctx->crtc->base);
 600                 ctx->frame_id = frm;
 601         }
 602
 603         spin_unlock(&ctx->vblank_lock);
 604 }
 605
 606 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 607 {
 608         struct decon_context *ctx = dev_id;
 609         u32 val;
 610
 611         val = readl(ctx->addr + DECON_VIDINTCON1);
 612         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 613
 614         if (val) {
 615                 writel(val, ctx->addr + DECON_VIDINTCON1);
 616                 if (ctx->out_type & IFTYPE_HDMI) {
 617                         val = readl(ctx->addr + DECON_VIDOUTCON0);
 618                         val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
 619                         if (val ==
 620                             (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 621                                 return IRQ_HANDLED;
 622                 }
 623                 decon_handle_vblank(ctx);
 624         }
 625
 626         return IRQ_HANDLED;
 627 }
 628
 629 #ifdef CONFIG_PM
 630 static int exynos5433_decon_suspend(struct device *dev)
 631 {
 632         struct decon_context *ctx = dev_get_drvdata(dev);
 633         int i = ARRAY_SIZE(decon_clks_name);
 634
 635         while (--i >= 0)
 636                 clk_disable_unprepare(ctx->clks[i]);
 637
 638         return 0;
 639 }
 640
 641 static int exynos5433_decon_resume(struct device *dev)
 642 {
 643         struct decon_context *ctx = dev_get_drvdata(dev);
 644         int i, ret;
 645
 646         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 647                 ret = clk_prepare_enable(ctx->clks[i]);
 648                 if (ret < 0)
 649                         goto err;
 650         }
 651
 652         return 0;
 653
 654 err:
 655         while (--i >= 0)
 656                 clk_disable_unprepare(ctx->clks[i]);
 657
 658         return ret;
 659 }
 660 #endif
 661
 662 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 663         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 664                            NULL)
 665 };
 666
 667 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 668         {
 669                 .compatible = "samsung,exynos5433-decon",
 670                 .data = (void *)I80_HW_TRG
 671         },
 672         {
 673                 .compatible = "samsung,exynos5433-decon-tv",
 674                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 675         },
 676         {},
 677 };
 678 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 679
 680 static int decon_conf_irq(struct decon_context *ctx, const char *name,
 681                 irq_handler_t handler, unsigned long int flags)
 682 {
 683         struct platform_device *pdev = to_platform_device(ctx->dev);
 684         int ret, irq = platform_get_irq_byname(pdev, name);
 685
 686         if (irq < 0) {
 687                 switch (irq) {
 688                 case -EPROBE_DEFER:
 689                         return irq;
 690                 case -ENODATA:
 691                 case -ENXIO:
 692                         return 0;
 693                 default:
 694                         dev_err(ctx->dev, "IRQ %s get failed, %d\n", name, irq);
 695                         return irq;
 696                 }
 697         }
 698         irq_set_status_flags(irq, IRQ_NOAUTOEN);
 699         ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx);
 700         if (ret < 0) {
 701                 dev_err(ctx->dev, "IRQ %s request failed\n", name);
 702                 return ret;
 703         }
 704
 705         return irq;
 706 }
 707
 708 static int exynos5433_decon_probe(struct platform_device *pdev)
 709 {
 710         struct device *dev = &pdev->dev;
 711         struct decon_context *ctx;
 712         struct resource *res;
 713         int ret;
 714         int i;
 715
 716         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 717         if (!ctx)
 718                 return -ENOMEM;
 719
 720         ctx->dev = dev;
 721         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 722         spin_lock_init(&ctx->vblank_lock);
 723
 724         if (ctx->out_type & IFTYPE_HDMI)
 725                 ctx->first_win = 1;
 726
 727         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 728                 struct clk *clk;
 729
 730                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 731                 if (IS_ERR(clk))
 732                         return PTR_ERR(clk);
 733
 734                 ctx->clks[i] = clk;
 735         }
 736
 737         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 738         if (!res) {
 739                 dev_err(dev, "cannot find IO resource\n");
 740                 return -ENXIO;
 741         }
 742
 743         ctx->addr = devm_ioremap_resource(dev, res);
 744         if (IS_ERR(ctx->addr)) {
 745                 dev_err(dev, "ioremap failed\n");
 746                 return PTR_ERR(ctx->addr);
 747         }
 748
 749         ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0);
 750         if (ret < 0)
 751                 return ret;
 752         ctx->irq_vsync = ret;
 753
 754         ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0);
 755         if (ret < 0)
 756                 return ret;
 757         ctx->irq_lcd_sys = ret;
 758
 759         ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
 760                         IRQF_TRIGGER_RISING);
 761         if (ret < 0)
 762                         return ret;
 763         if (ret) {
 764                 ctx->te_irq = ret;
 765                 ctx->out_type &= ~I80_HW_TRG;
 766         }
 767
 768         if (ctx->out_type & I80_HW_TRG) {
 769                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 770                                                         "samsung,disp-sysreg");
 771                 if (IS_ERR(ctx->sysreg)) {
 772                         dev_err(dev, "failed to get system register\n");
 773                         return PTR_ERR(ctx->sysreg);
 774                 }
 775         }
 776
 777         platform_set_drvdata(pdev, ctx);
 778
 779         pm_runtime_enable(dev);
 780
 781         ret = component_add(dev, &decon_component_ops);
 782         if (ret)
 783                 goto err_disable_pm_runtime;
 784
 785         return 0;
 786
 787 err_disable_pm_runtime:
 788         pm_runtime_disable(dev);
 789
 790         return ret;
 791 }
 792
 793 static int exynos5433_decon_remove(struct platform_device *pdev)
 794 {
 795         pm_runtime_disable(&pdev->dev);
 796
 797         component_del(&pdev->dev, &decon_component_ops);
 798
 799         return 0;
 800 }
 801
 802 struct platform_driver exynos5433_decon_driver = {
 803         .probe          = exynos5433_decon_probe,
 804         .remove         = exynos5433_decon_remove,
 805         .driver         = {
 806                 .name   = "exynos5433-decon",
 807                 .pm     = &exynos5433_decon_pm_ops,
 808                 .of_match_table = exynos5433_decon_driver_dt_match,
 809         },
 810 };