1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2015-2018 Etnaviv Project
6 #ifndef __ETNAVIV_GPU_H__
7 #define __ETNAVIV_GPU_H__
10 #include <linux/regulator/consumer.h>
12 #include "etnaviv_cmdbuf.h"
13 #include "etnaviv_drv.h"
15 struct etnaviv_gem_submit;
16 struct etnaviv_vram_mapping;
18 struct etnaviv_chip_identity {
25 /* Supported feature fields. */
28 /* Supported minor feature fields. */
42 /* Number of streams supported. */
45 /* Total number of temporary registers per thread. */
48 /* Maximum number of threads. */
51 /* Number of shader cores. */
52 u32 shader_core_count;
54 /* Size of the vertex cache. */
55 u32 vertex_cache_size;
57 /* Number of entries in the vertex output buffer. */
58 u32 vertex_output_buffer_size;
60 /* Number of pixel pipes. */
63 /* Number of instructions. */
64 u32 instruction_count;
66 /* Number of constants. */
72 /* Number of varyings */
76 enum etnaviv_sec_mode {
82 struct etnaviv_event {
83 struct dma_fence *fence;
84 struct etnaviv_gem_submit *submit;
86 void (*sync_point)(struct etnaviv_gpu *gpu, struct etnaviv_event *event);
89 struct etnaviv_cmdbuf_suballoc;
90 struct etnaviv_cmdbuf;
92 #define ETNA_NR_EVENTS 30
95 struct drm_device *drm;
96 struct thermal_cooling_device *cooling;
99 struct etnaviv_chip_identity identity;
100 enum etnaviv_sec_mode sec_mode;
101 struct etnaviv_file_private *lastctx;
102 struct workqueue_struct *wq;
103 struct drm_gpu_scheduler sched;
106 struct etnaviv_cmdbuf buffer;
109 /* bus base address of memory */
112 /* event management: */
113 DECLARE_BITMAP(event_bitmap, ETNA_NR_EVENTS);
114 struct etnaviv_event event[ETNA_NR_EVENTS];
115 struct completion event_free;
116 spinlock_t event_spinlock;
120 /* Fencing support */
121 struct mutex fence_lock;
122 struct idr fence_idr;
126 wait_queue_head_t fence_event;
128 spinlock_t fence_spinlock;
130 /* worker for handling 'sync' points: */
131 struct work_struct sync_point_work;
132 int sync_point_event;
135 u32 hangcheck_dma_addr;
140 struct etnaviv_iommu *mmu;
141 struct etnaviv_cmdbuf_suballoc *cmdbuf_suballoc;
142 unsigned int flush_seq;
147 struct clk *clk_core;
148 struct clk *clk_shader;
150 unsigned int freq_scale;
151 unsigned long base_rate_core;
152 unsigned long base_rate_shader;
155 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data)
157 writel(data, gpu->mmio + reg);
160 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg)
162 return readl(gpu->mmio + reg);
165 static inline bool fence_completed(struct etnaviv_gpu *gpu, u32 fence)
167 return fence_after_eq(gpu->completed_fence, fence);
170 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value);
172 int etnaviv_gpu_init(struct etnaviv_gpu *gpu);
173 bool etnaviv_fill_identity_from_hwdb(struct etnaviv_gpu *gpu);
175 #ifdef CONFIG_DEBUG_FS
176 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m);
179 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu);
180 void etnaviv_gpu_retire(struct etnaviv_gpu *gpu);
181 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
182 u32 fence, struct timespec *timeout);
183 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
184 struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout);
185 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit);
186 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu);
187 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu);
188 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms);
189 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch);
191 extern struct platform_driver etnaviv_gpu_driver;
193 #endif /* __ETNAVIV_GPU_H__ */