2 * Copyright (c) 2006 Luc Verhaegen (quirks list)
3 * Copyright (c) 2007-2008 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 * Copyright 2010 Red Hat, Inc.
7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from
9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com>
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sub license,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/hdmi.h>
33 #include <linux/i2c.h>
34 #include <linux/module.h>
35 #include <linux/vga_switcheroo.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_displayid.h>
40 #include <drm/drm_scdc_helper.h>
42 #include "drm_crtc_internal.h"
44 #define version_greater(edid, maj, min) \
45 (((edid)->version > (maj)) || \
46 ((edid)->version == (maj) && (edid)->revision > (min)))
48 #define EDID_EST_TIMINGS 16
49 #define EDID_STD_TIMINGS 8
50 #define EDID_DETAILED_TIMINGS 4
53 * EDID blocks out in the wild have a variety of bugs, try to collect
54 * them here (note that userspace may work around broken monitors first,
55 * but fixes should make their way here so that the kernel "just works"
56 * on as many displays as possible).
59 /* First detailed mode wrong, use largest 60Hz mode */
60 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0)
61 /* Reported 135MHz pixel clock is too high, needs adjustment */
62 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1)
63 /* Prefer the largest mode at 75 Hz */
64 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2)
65 /* Detail timing is in cm not mm */
66 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3)
67 /* Detailed timing descriptors have bogus size values, so just take the
68 * maximum size and use that.
70 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4)
71 /* Monitor forgot to set the first detailed is preferred bit. */
72 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5)
73 /* use +hsync +vsync for detailed mode */
74 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6)
75 /* Force reduced-blanking timings for detailed modes */
76 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7)
78 #define EDID_QUIRK_FORCE_8BPC (1 << 8)
80 #define EDID_QUIRK_FORCE_12BPC (1 << 9)
82 #define EDID_QUIRK_FORCE_6BPC (1 << 10)
84 #define EDID_QUIRK_FORCE_10BPC (1 << 11)
86 struct detailed_mode_closure {
87 struct drm_connector *connector;
99 static const struct edid_quirk {
103 } edid_quirk_list[] = {
105 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 },
107 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 },
109 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
111 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */
112 { "AEO", 0, EDID_QUIRK_FORCE_6BPC },
114 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */
115 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC },
117 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */
118 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC },
120 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */
121 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC },
123 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */
124 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC },
126 /* Belinea 10 15 55 */
127 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 },
128 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 },
130 /* Envision Peripherals, Inc. EN-7100e */
131 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH },
132 /* Envision EN2028 */
133 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 },
135 /* Funai Electronics PM36B */
136 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 |
137 EDID_QUIRK_DETAILED_IN_CM },
139 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */
140 { "LGD", 764, EDID_QUIRK_FORCE_10BPC },
142 /* LG Philips LCD LP154W01-A5 */
143 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
144 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE },
146 /* Philips 107p5 CRT */
147 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
150 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED },
152 /* Samsung SyncMaster 205BW. Note: irony */
153 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP },
154 /* Samsung SyncMaster 22[5-6]BW */
155 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 },
156 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 },
158 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */
159 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC },
161 /* ViewSonic VA2026w */
162 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING },
164 /* Medion MD 30217 PG */
165 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 },
168 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC },
170 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */
171 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC },
173 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/
174 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC },
178 * Autogenerated from the DMT spec.
179 * This table is copied from xfree86/modes/xf86EdidModes.c.
181 static const struct drm_display_mode drm_dmt_modes[] = {
182 /* 0x01 - 640x350@85Hz */
183 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
184 736, 832, 0, 350, 382, 385, 445, 0,
185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
186 /* 0x02 - 640x400@85Hz */
187 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672,
188 736, 832, 0, 400, 401, 404, 445, 0,
189 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
190 /* 0x03 - 720x400@85Hz */
191 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756,
192 828, 936, 0, 400, 401, 404, 446, 0,
193 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
194 /* 0x04 - 640x480@60Hz */
195 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
196 752, 800, 0, 480, 490, 492, 525, 0,
197 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
198 /* 0x05 - 640x480@72Hz */
199 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
200 704, 832, 0, 480, 489, 492, 520, 0,
201 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
202 /* 0x06 - 640x480@75Hz */
203 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
204 720, 840, 0, 480, 481, 484, 500, 0,
205 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
206 /* 0x07 - 640x480@85Hz */
207 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696,
208 752, 832, 0, 480, 481, 484, 509, 0,
209 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
210 /* 0x08 - 800x600@56Hz */
211 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
212 896, 1024, 0, 600, 601, 603, 625, 0,
213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
214 /* 0x09 - 800x600@60Hz */
215 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
216 968, 1056, 0, 600, 601, 605, 628, 0,
217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
218 /* 0x0a - 800x600@72Hz */
219 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
220 976, 1040, 0, 600, 637, 643, 666, 0,
221 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
222 /* 0x0b - 800x600@75Hz */
223 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
224 896, 1056, 0, 600, 601, 604, 625, 0,
225 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
226 /* 0x0c - 800x600@85Hz */
227 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832,
228 896, 1048, 0, 600, 601, 604, 631, 0,
229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
230 /* 0x0d - 800x600@120Hz RB */
231 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848,
232 880, 960, 0, 600, 603, 607, 636, 0,
233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
234 /* 0x0e - 848x480@60Hz */
235 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864,
236 976, 1088, 0, 480, 486, 494, 517, 0,
237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
238 /* 0x0f - 1024x768@43Hz, interlace */
239 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032,
240 1208, 1264, 0, 768, 768, 776, 817, 0,
241 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
242 DRM_MODE_FLAG_INTERLACE) },
243 /* 0x10 - 1024x768@60Hz */
244 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
245 1184, 1344, 0, 768, 771, 777, 806, 0,
246 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
247 /* 0x11 - 1024x768@70Hz */
248 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
249 1184, 1328, 0, 768, 771, 777, 806, 0,
250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
251 /* 0x12 - 1024x768@75Hz */
252 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
253 1136, 1312, 0, 768, 769, 772, 800, 0,
254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
255 /* 0x13 - 1024x768@85Hz */
256 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072,
257 1168, 1376, 0, 768, 769, 772, 808, 0,
258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
259 /* 0x14 - 1024x768@120Hz RB */
260 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072,
261 1104, 1184, 0, 768, 771, 775, 813, 0,
262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
263 /* 0x15 - 1152x864@75Hz */
264 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
265 1344, 1600, 0, 864, 865, 868, 900, 0,
266 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
267 /* 0x55 - 1280x720@60Hz */
268 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
269 1430, 1650, 0, 720, 725, 730, 750, 0,
270 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
271 /* 0x16 - 1280x768@60Hz RB */
272 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328,
273 1360, 1440, 0, 768, 771, 778, 790, 0,
274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
275 /* 0x17 - 1280x768@60Hz */
276 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344,
277 1472, 1664, 0, 768, 771, 778, 798, 0,
278 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
279 /* 0x18 - 1280x768@75Hz */
280 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360,
281 1488, 1696, 0, 768, 771, 778, 805, 0,
282 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
283 /* 0x19 - 1280x768@85Hz */
284 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360,
285 1496, 1712, 0, 768, 771, 778, 809, 0,
286 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
287 /* 0x1a - 1280x768@120Hz RB */
288 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328,
289 1360, 1440, 0, 768, 771, 778, 813, 0,
290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
291 /* 0x1b - 1280x800@60Hz RB */
292 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328,
293 1360, 1440, 0, 800, 803, 809, 823, 0,
294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
295 /* 0x1c - 1280x800@60Hz */
296 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352,
297 1480, 1680, 0, 800, 803, 809, 831, 0,
298 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
299 /* 0x1d - 1280x800@75Hz */
300 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360,
301 1488, 1696, 0, 800, 803, 809, 838, 0,
302 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
303 /* 0x1e - 1280x800@85Hz */
304 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360,
305 1496, 1712, 0, 800, 803, 809, 843, 0,
306 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
307 /* 0x1f - 1280x800@120Hz RB */
308 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328,
309 1360, 1440, 0, 800, 803, 809, 847, 0,
310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
311 /* 0x20 - 1280x960@60Hz */
312 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376,
313 1488, 1800, 0, 960, 961, 964, 1000, 0,
314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
315 /* 0x21 - 1280x960@85Hz */
316 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344,
317 1504, 1728, 0, 960, 961, 964, 1011, 0,
318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
319 /* 0x22 - 1280x960@120Hz RB */
320 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328,
321 1360, 1440, 0, 960, 963, 967, 1017, 0,
322 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
323 /* 0x23 - 1280x1024@60Hz */
324 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328,
325 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
326 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
327 /* 0x24 - 1280x1024@75Hz */
328 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
329 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
331 /* 0x25 - 1280x1024@85Hz */
332 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344,
333 1504, 1728, 0, 1024, 1025, 1028, 1072, 0,
334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
335 /* 0x26 - 1280x1024@120Hz RB */
336 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328,
337 1360, 1440, 0, 1024, 1027, 1034, 1084, 0,
338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
339 /* 0x27 - 1360x768@60Hz */
340 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424,
341 1536, 1792, 0, 768, 771, 777, 795, 0,
342 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
343 /* 0x28 - 1360x768@120Hz RB */
344 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408,
345 1440, 1520, 0, 768, 771, 776, 813, 0,
346 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
347 /* 0x51 - 1366x768@60Hz */
348 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436,
349 1579, 1792, 0, 768, 771, 774, 798, 0,
350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
351 /* 0x56 - 1366x768@60Hz */
352 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380,
353 1436, 1500, 0, 768, 769, 772, 800, 0,
354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
355 /* 0x29 - 1400x1050@60Hz RB */
356 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448,
357 1480, 1560, 0, 1050, 1053, 1057, 1080, 0,
358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
359 /* 0x2a - 1400x1050@60Hz */
360 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488,
361 1632, 1864, 0, 1050, 1053, 1057, 1089, 0,
362 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
363 /* 0x2b - 1400x1050@75Hz */
364 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504,
365 1648, 1896, 0, 1050, 1053, 1057, 1099, 0,
366 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
367 /* 0x2c - 1400x1050@85Hz */
368 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504,
369 1656, 1912, 0, 1050, 1053, 1057, 1105, 0,
370 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
371 /* 0x2d - 1400x1050@120Hz RB */
372 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448,
373 1480, 1560, 0, 1050, 1053, 1057, 1112, 0,
374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
375 /* 0x2e - 1440x900@60Hz RB */
376 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488,
377 1520, 1600, 0, 900, 903, 909, 926, 0,
378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
379 /* 0x2f - 1440x900@60Hz */
380 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520,
381 1672, 1904, 0, 900, 903, 909, 934, 0,
382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
383 /* 0x30 - 1440x900@75Hz */
384 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536,
385 1688, 1936, 0, 900, 903, 909, 942, 0,
386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
387 /* 0x31 - 1440x900@85Hz */
388 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544,
389 1696, 1952, 0, 900, 903, 909, 948, 0,
390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
391 /* 0x32 - 1440x900@120Hz RB */
392 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488,
393 1520, 1600, 0, 900, 903, 909, 953, 0,
394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
395 /* 0x53 - 1600x900@60Hz */
396 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624,
397 1704, 1800, 0, 900, 901, 904, 1000, 0,
398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
399 /* 0x33 - 1600x1200@60Hz */
400 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664,
401 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
403 /* 0x34 - 1600x1200@65Hz */
404 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664,
405 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
407 /* 0x35 - 1600x1200@70Hz */
408 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664,
409 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
410 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
411 /* 0x36 - 1600x1200@75Hz */
412 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664,
413 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
414 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
415 /* 0x37 - 1600x1200@85Hz */
416 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664,
417 1856, 2160, 0, 1200, 1201, 1204, 1250, 0,
418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
419 /* 0x38 - 1600x1200@120Hz RB */
420 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648,
421 1680, 1760, 0, 1200, 1203, 1207, 1271, 0,
422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
423 /* 0x39 - 1680x1050@60Hz RB */
424 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728,
425 1760, 1840, 0, 1050, 1053, 1059, 1080, 0,
426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
427 /* 0x3a - 1680x1050@60Hz */
428 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784,
429 1960, 2240, 0, 1050, 1053, 1059, 1089, 0,
430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
431 /* 0x3b - 1680x1050@75Hz */
432 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800,
433 1976, 2272, 0, 1050, 1053, 1059, 1099, 0,
434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
435 /* 0x3c - 1680x1050@85Hz */
436 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808,
437 1984, 2288, 0, 1050, 1053, 1059, 1105, 0,
438 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
439 /* 0x3d - 1680x1050@120Hz RB */
440 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728,
441 1760, 1840, 0, 1050, 1053, 1059, 1112, 0,
442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
443 /* 0x3e - 1792x1344@60Hz */
444 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920,
445 2120, 2448, 0, 1344, 1345, 1348, 1394, 0,
446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
447 /* 0x3f - 1792x1344@75Hz */
448 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888,
449 2104, 2456, 0, 1344, 1345, 1348, 1417, 0,
450 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
451 /* 0x40 - 1792x1344@120Hz RB */
452 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840,
453 1872, 1952, 0, 1344, 1347, 1351, 1423, 0,
454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
455 /* 0x41 - 1856x1392@60Hz */
456 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952,
457 2176, 2528, 0, 1392, 1393, 1396, 1439, 0,
458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
459 /* 0x42 - 1856x1392@75Hz */
460 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984,
461 2208, 2560, 0, 1392, 1393, 1396, 1500, 0,
462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
463 /* 0x43 - 1856x1392@120Hz RB */
464 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904,
465 1936, 2016, 0, 1392, 1395, 1399, 1474, 0,
466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
467 /* 0x52 - 1920x1080@60Hz */
468 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
469 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
470 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) },
471 /* 0x44 - 1920x1200@60Hz RB */
472 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968,
473 2000, 2080, 0, 1200, 1203, 1209, 1235, 0,
474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
475 /* 0x45 - 1920x1200@60Hz */
476 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056,
477 2256, 2592, 0, 1200, 1203, 1209, 1245, 0,
478 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
479 /* 0x46 - 1920x1200@75Hz */
480 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056,
481 2264, 2608, 0, 1200, 1203, 1209, 1255, 0,
482 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
483 /* 0x47 - 1920x1200@85Hz */
484 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064,
485 2272, 2624, 0, 1200, 1203, 1209, 1262, 0,
486 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
487 /* 0x48 - 1920x1200@120Hz RB */
488 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968,
489 2000, 2080, 0, 1200, 1203, 1209, 1271, 0,
490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
491 /* 0x49 - 1920x1440@60Hz */
492 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048,
493 2256, 2600, 0, 1440, 1441, 1444, 1500, 0,
494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
495 /* 0x4a - 1920x1440@75Hz */
496 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064,
497 2288, 2640, 0, 1440, 1441, 1444, 1500, 0,
498 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
499 /* 0x4b - 1920x1440@120Hz RB */
500 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968,
501 2000, 2080, 0, 1440, 1443, 1447, 1525, 0,
502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
503 /* 0x54 - 2048x1152@60Hz */
504 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074,
505 2154, 2250, 0, 1152, 1153, 1156, 1200, 0,
506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
507 /* 0x4c - 2560x1600@60Hz RB */
508 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608,
509 2640, 2720, 0, 1600, 1603, 1609, 1646, 0,
510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
511 /* 0x4d - 2560x1600@60Hz */
512 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752,
513 3032, 3504, 0, 1600, 1603, 1609, 1658, 0,
514 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
515 /* 0x4e - 2560x1600@75Hz */
516 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768,
517 3048, 3536, 0, 1600, 1603, 1609, 1672, 0,
518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
519 /* 0x4f - 2560x1600@85Hz */
520 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768,
521 3048, 3536, 0, 1600, 1603, 1609, 1682, 0,
522 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) },
523 /* 0x50 - 2560x1600@120Hz RB */
524 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608,
525 2640, 2720, 0, 1600, 1603, 1609, 1694, 0,
526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
527 /* 0x57 - 4096x2160@60Hz RB */
528 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104,
529 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
531 /* 0x58 - 4096x2160@59.94Hz RB */
532 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104,
533 4136, 4176, 0, 2160, 2208, 2216, 2222, 0,
534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) },
538 * These more or less come from the DMT spec. The 720x400 modes are
539 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75
540 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode
541 * should be 1152x870, again for the Mac, but instead we use the x864 DMT
544 * The DMT modes have been fact-checked; the rest are mild guesses.
546 static const struct drm_display_mode edid_est_modes[] = {
547 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840,
548 968, 1056, 0, 600, 601, 605, 628, 0,
549 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */
550 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824,
551 896, 1024, 0, 600, 601, 603, 625, 0,
552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */
553 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656,
554 720, 840, 0, 480, 481, 484, 500, 0,
555 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */
556 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664,
557 704, 832, 0, 480, 489, 492, 520, 0,
558 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */
559 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704,
560 768, 864, 0, 480, 483, 486, 525, 0,
561 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */
562 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
563 752, 800, 0, 480, 490, 492, 525, 0,
564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */
565 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738,
566 846, 900, 0, 400, 421, 423, 449, 0,
567 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */
568 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738,
569 846, 900, 0, 400, 412, 414, 449, 0,
570 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */
571 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296,
572 1440, 1688, 0, 1024, 1025, 1028, 1066, 0,
573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */
574 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040,
575 1136, 1312, 0, 768, 769, 772, 800, 0,
576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */
577 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048,
578 1184, 1328, 0, 768, 771, 777, 806, 0,
579 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */
580 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
581 1184, 1344, 0, 768, 771, 777, 806, 0,
582 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */
583 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032,
584 1208, 1264, 0, 768, 768, 776, 817, 0,
585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */
586 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864,
587 928, 1152, 0, 624, 625, 628, 667, 0,
588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */
589 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816,
590 896, 1056, 0, 600, 601, 604, 625, 0,
591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */
592 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856,
593 976, 1040, 0, 600, 637, 643, 666, 0,
594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */
595 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216,
596 1344, 1600, 0, 864, 865, 868, 900, 0,
597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */
607 static const struct minimode est3_modes[] = {
615 { 1024, 768, 85, 0 },
616 { 1152, 864, 75, 0 },
618 { 1280, 768, 60, 1 },
619 { 1280, 768, 60, 0 },
620 { 1280, 768, 75, 0 },
621 { 1280, 768, 85, 0 },
622 { 1280, 960, 60, 0 },
623 { 1280, 960, 85, 0 },
624 { 1280, 1024, 60, 0 },
625 { 1280, 1024, 85, 0 },
627 { 1360, 768, 60, 0 },
628 { 1440, 900, 60, 1 },
629 { 1440, 900, 60, 0 },
630 { 1440, 900, 75, 0 },
631 { 1440, 900, 85, 0 },
632 { 1400, 1050, 60, 1 },
633 { 1400, 1050, 60, 0 },
634 { 1400, 1050, 75, 0 },
636 { 1400, 1050, 85, 0 },
637 { 1680, 1050, 60, 1 },
638 { 1680, 1050, 60, 0 },
639 { 1680, 1050, 75, 0 },
640 { 1680, 1050, 85, 0 },
641 { 1600, 1200, 60, 0 },
642 { 1600, 1200, 65, 0 },
643 { 1600, 1200, 70, 0 },
645 { 1600, 1200, 75, 0 },
646 { 1600, 1200, 85, 0 },
647 { 1792, 1344, 60, 0 },
648 { 1792, 1344, 75, 0 },
649 { 1856, 1392, 60, 0 },
650 { 1856, 1392, 75, 0 },
651 { 1920, 1200, 60, 1 },
652 { 1920, 1200, 60, 0 },
654 { 1920, 1200, 75, 0 },
655 { 1920, 1200, 85, 0 },
656 { 1920, 1440, 60, 0 },
657 { 1920, 1440, 75, 0 },
660 static const struct minimode extra_modes[] = {
661 { 1024, 576, 60, 0 },
662 { 1366, 768, 60, 0 },
663 { 1600, 900, 60, 0 },
664 { 1680, 945, 60, 0 },
665 { 1920, 1080, 60, 0 },
666 { 2048, 1152, 60, 0 },
667 { 2048, 1536, 60, 0 },
671 * Probably taken from CEA-861 spec.
672 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c.
674 * Index using the VIC.
676 static const struct drm_display_mode edid_cea_modes[] = {
677 /* 0 - dummy, VICs start at 1 */
679 /* 1 - 640x480@60Hz */
680 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
681 752, 800, 0, 480, 490, 492, 525, 0,
682 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
683 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
684 /* 2 - 720x480@60Hz */
685 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
686 798, 858, 0, 480, 489, 495, 525, 0,
687 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
688 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
689 /* 3 - 720x480@60Hz */
690 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736,
691 798, 858, 0, 480, 489, 495, 525, 0,
692 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
693 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
694 /* 4 - 1280x720@60Hz */
695 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
696 1430, 1650, 0, 720, 725, 730, 750, 0,
697 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
698 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
699 /* 5 - 1920x1080i@60Hz */
700 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
701 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
702 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
703 DRM_MODE_FLAG_INTERLACE),
704 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
705 /* 6 - 720(1440)x480i@60Hz */
706 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
707 801, 858, 0, 480, 488, 494, 525, 0,
708 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
709 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
710 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
711 /* 7 - 720(1440)x480i@60Hz */
712 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
713 801, 858, 0, 480, 488, 494, 525, 0,
714 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
715 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
716 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
717 /* 8 - 720(1440)x240@60Hz */
718 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
719 801, 858, 0, 240, 244, 247, 262, 0,
720 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
721 DRM_MODE_FLAG_DBLCLK),
722 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
723 /* 9 - 720(1440)x240@60Hz */
724 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739,
725 801, 858, 0, 240, 244, 247, 262, 0,
726 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
727 DRM_MODE_FLAG_DBLCLK),
728 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
729 /* 10 - 2880x480i@60Hz */
730 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
731 3204, 3432, 0, 480, 488, 494, 525, 0,
732 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
733 DRM_MODE_FLAG_INTERLACE),
734 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
735 /* 11 - 2880x480i@60Hz */
736 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
737 3204, 3432, 0, 480, 488, 494, 525, 0,
738 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
739 DRM_MODE_FLAG_INTERLACE),
740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
741 /* 12 - 2880x240@60Hz */
742 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
743 3204, 3432, 0, 240, 244, 247, 262, 0,
744 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
746 /* 13 - 2880x240@60Hz */
747 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956,
748 3204, 3432, 0, 240, 244, 247, 262, 0,
749 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
750 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
751 /* 14 - 1440x480@60Hz */
752 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
753 1596, 1716, 0, 480, 489, 495, 525, 0,
754 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
755 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
756 /* 15 - 1440x480@60Hz */
757 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472,
758 1596, 1716, 0, 480, 489, 495, 525, 0,
759 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
760 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
761 /* 16 - 1920x1080@60Hz */
762 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
763 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
764 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
765 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
766 /* 17 - 720x576@50Hz */
767 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
768 796, 864, 0, 576, 581, 586, 625, 0,
769 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
770 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
771 /* 18 - 720x576@50Hz */
772 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
773 796, 864, 0, 576, 581, 586, 625, 0,
774 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
775 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
776 /* 19 - 1280x720@50Hz */
777 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
778 1760, 1980, 0, 720, 725, 730, 750, 0,
779 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
780 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
781 /* 20 - 1920x1080i@50Hz */
782 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
783 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
785 DRM_MODE_FLAG_INTERLACE),
786 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
787 /* 21 - 720(1440)x576i@50Hz */
788 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
789 795, 864, 0, 576, 580, 586, 625, 0,
790 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
791 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
792 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
793 /* 22 - 720(1440)x576i@50Hz */
794 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
795 795, 864, 0, 576, 580, 586, 625, 0,
796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
797 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
798 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
799 /* 23 - 720(1440)x288@50Hz */
800 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
801 795, 864, 0, 288, 290, 293, 312, 0,
802 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
803 DRM_MODE_FLAG_DBLCLK),
804 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
805 /* 24 - 720(1440)x288@50Hz */
806 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732,
807 795, 864, 0, 288, 290, 293, 312, 0,
808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
809 DRM_MODE_FLAG_DBLCLK),
810 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
811 /* 25 - 2880x576i@50Hz */
812 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
813 3180, 3456, 0, 576, 580, 586, 625, 0,
814 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
815 DRM_MODE_FLAG_INTERLACE),
816 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
817 /* 26 - 2880x576i@50Hz */
818 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
819 3180, 3456, 0, 576, 580, 586, 625, 0,
820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
821 DRM_MODE_FLAG_INTERLACE),
822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
823 /* 27 - 2880x288@50Hz */
824 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
825 3180, 3456, 0, 288, 290, 293, 312, 0,
826 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
828 /* 28 - 2880x288@50Hz */
829 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928,
830 3180, 3456, 0, 288, 290, 293, 312, 0,
831 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
832 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
833 /* 29 - 1440x576@50Hz */
834 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
835 1592, 1728, 0, 576, 581, 586, 625, 0,
836 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
837 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
838 /* 30 - 1440x576@50Hz */
839 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464,
840 1592, 1728, 0, 576, 581, 586, 625, 0,
841 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
842 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
843 /* 31 - 1920x1080@50Hz */
844 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
845 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
847 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
848 /* 32 - 1920x1080@24Hz */
849 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
850 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
852 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
853 /* 33 - 1920x1080@25Hz */
854 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
855 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
856 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
857 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
858 /* 34 - 1920x1080@30Hz */
859 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
860 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
862 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
863 /* 35 - 2880x480@60Hz */
864 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
865 3192, 3432, 0, 480, 489, 495, 525, 0,
866 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
867 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
868 /* 36 - 2880x480@60Hz */
869 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944,
870 3192, 3432, 0, 480, 489, 495, 525, 0,
871 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
872 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
873 /* 37 - 2880x576@50Hz */
874 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
875 3184, 3456, 0, 576, 581, 586, 625, 0,
876 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
877 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
878 /* 38 - 2880x576@50Hz */
879 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928,
880 3184, 3456, 0, 576, 581, 586, 625, 0,
881 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
882 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
883 /* 39 - 1920x1080i@50Hz */
884 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952,
885 2120, 2304, 0, 1080, 1126, 1136, 1250, 0,
886 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC |
887 DRM_MODE_FLAG_INTERLACE),
888 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
889 /* 40 - 1920x1080i@100Hz */
890 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
891 2492, 2640, 0, 1080, 1084, 1094, 1125, 0,
892 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
893 DRM_MODE_FLAG_INTERLACE),
894 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
895 /* 41 - 1280x720@100Hz */
896 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
897 1760, 1980, 0, 720, 725, 730, 750, 0,
898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
899 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
900 /* 42 - 720x576@100Hz */
901 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
902 796, 864, 0, 576, 581, 586, 625, 0,
903 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
904 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
905 /* 43 - 720x576@100Hz */
906 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
907 796, 864, 0, 576, 581, 586, 625, 0,
908 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
909 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
910 /* 44 - 720(1440)x576i@100Hz */
911 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
912 795, 864, 0, 576, 580, 586, 625, 0,
913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
914 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
915 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
916 /* 45 - 720(1440)x576i@100Hz */
917 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732,
918 795, 864, 0, 576, 580, 586, 625, 0,
919 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
920 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
921 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
922 /* 46 - 1920x1080i@120Hz */
923 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
924 2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
925 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
926 DRM_MODE_FLAG_INTERLACE),
927 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
928 /* 47 - 1280x720@120Hz */
929 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
930 1430, 1650, 0, 720, 725, 730, 750, 0,
931 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
932 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
933 /* 48 - 720x480@120Hz */
934 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
935 798, 858, 0, 480, 489, 495, 525, 0,
936 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
937 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
938 /* 49 - 720x480@120Hz */
939 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736,
940 798, 858, 0, 480, 489, 495, 525, 0,
941 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
942 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
943 /* 50 - 720(1440)x480i@120Hz */
944 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
945 801, 858, 0, 480, 488, 494, 525, 0,
946 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
947 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
948 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
949 /* 51 - 720(1440)x480i@120Hz */
950 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739,
951 801, 858, 0, 480, 488, 494, 525, 0,
952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
953 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
954 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
955 /* 52 - 720x576@200Hz */
956 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
957 796, 864, 0, 576, 581, 586, 625, 0,
958 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
959 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
960 /* 53 - 720x576@200Hz */
961 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732,
962 796, 864, 0, 576, 581, 586, 625, 0,
963 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
964 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
965 /* 54 - 720(1440)x576i@200Hz */
966 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
967 795, 864, 0, 576, 580, 586, 625, 0,
968 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
969 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
970 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
971 /* 55 - 720(1440)x576i@200Hz */
972 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732,
973 795, 864, 0, 576, 580, 586, 625, 0,
974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
975 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
976 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
977 /* 56 - 720x480@240Hz */
978 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
979 798, 858, 0, 480, 489, 495, 525, 0,
980 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
981 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
982 /* 57 - 720x480@240Hz */
983 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736,
984 798, 858, 0, 480, 489, 495, 525, 0,
985 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
986 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
987 /* 58 - 720(1440)x480i@240Hz */
988 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
989 801, 858, 0, 480, 488, 494, 525, 0,
990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
991 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
992 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, },
993 /* 59 - 720(1440)x480i@240Hz */
994 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739,
995 801, 858, 0, 480, 488, 494, 525, 0,
996 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
997 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
998 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
999 /* 60 - 1280x720@24Hz */
1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1001 3080, 3300, 0, 720, 725, 730, 750, 0,
1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1003 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1004 /* 61 - 1280x720@25Hz */
1005 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1006 3740, 3960, 0, 720, 725, 730, 750, 0,
1007 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1008 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1009 /* 62 - 1280x720@30Hz */
1010 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1011 3080, 3300, 0, 720, 725, 730, 750, 0,
1012 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1013 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1014 /* 63 - 1920x1080@120Hz */
1015 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1016 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1017 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1018 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1019 /* 64 - 1920x1080@100Hz */
1020 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1021 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1022 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1023 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1024 /* 65 - 1280x720@24Hz */
1025 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040,
1026 3080, 3300, 0, 720, 725, 730, 750, 0,
1027 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1028 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1029 /* 66 - 1280x720@25Hz */
1030 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700,
1031 3740, 3960, 0, 720, 725, 730, 750, 0,
1032 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1033 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1034 /* 67 - 1280x720@30Hz */
1035 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040,
1036 3080, 3300, 0, 720, 725, 730, 750, 0,
1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1038 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1039 /* 68 - 1280x720@50Hz */
1040 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
1041 1760, 1980, 0, 720, 725, 730, 750, 0,
1042 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1043 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1044 /* 69 - 1280x720@60Hz */
1045 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
1046 1430, 1650, 0, 720, 725, 730, 750, 0,
1047 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1048 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1049 /* 70 - 1280x720@100Hz */
1050 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720,
1051 1760, 1980, 0, 720, 725, 730, 750, 0,
1052 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1053 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1054 /* 71 - 1280x720@120Hz */
1055 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390,
1056 1430, 1650, 0, 720, 725, 730, 750, 0,
1057 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1058 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1059 /* 72 - 1920x1080@24Hz */
1060 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558,
1061 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
1062 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1063 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1064 /* 73 - 1920x1080@25Hz */
1065 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448,
1066 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1067 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1068 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1069 /* 74 - 1920x1080@30Hz */
1070 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008,
1071 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1072 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1073 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1074 /* 75 - 1920x1080@50Hz */
1075 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448,
1076 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1077 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1078 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1079 /* 76 - 1920x1080@60Hz */
1080 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008,
1081 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1082 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1083 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1084 /* 77 - 1920x1080@100Hz */
1085 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448,
1086 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
1087 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1088 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1089 /* 78 - 1920x1080@120Hz */
1090 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008,
1091 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
1092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1093 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1094 /* 79 - 1680x720@24Hz */
1095 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040,
1096 3080, 3300, 0, 720, 725, 730, 750, 0,
1097 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1098 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1099 /* 80 - 1680x720@25Hz */
1100 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908,
1101 2948, 3168, 0, 720, 725, 730, 750, 0,
1102 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1103 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1104 /* 81 - 1680x720@30Hz */
1105 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380,
1106 2420, 2640, 0, 720, 725, 730, 750, 0,
1107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1108 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1109 /* 82 - 1680x720@50Hz */
1110 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940,
1111 1980, 2200, 0, 720, 725, 730, 750, 0,
1112 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1113 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1114 /* 83 - 1680x720@60Hz */
1115 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940,
1116 1980, 2200, 0, 720, 725, 730, 750, 0,
1117 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1118 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1119 /* 84 - 1680x720@100Hz */
1120 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740,
1121 1780, 2000, 0, 720, 725, 730, 825, 0,
1122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1123 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1124 /* 85 - 1680x720@120Hz */
1125 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740,
1126 1780, 2000, 0, 720, 725, 730, 825, 0,
1127 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1128 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1129 /* 86 - 2560x1080@24Hz */
1130 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558,
1131 3602, 3750, 0, 1080, 1084, 1089, 1100, 0,
1132 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1133 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1134 /* 87 - 2560x1080@25Hz */
1135 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008,
1136 3052, 3200, 0, 1080, 1084, 1089, 1125, 0,
1137 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1138 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1139 /* 88 - 2560x1080@30Hz */
1140 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328,
1141 3372, 3520, 0, 1080, 1084, 1089, 1125, 0,
1142 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1143 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1144 /* 89 - 2560x1080@50Hz */
1145 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108,
1146 3152, 3300, 0, 1080, 1084, 1089, 1125, 0,
1147 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1148 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1149 /* 90 - 2560x1080@60Hz */
1150 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808,
1151 2852, 3000, 0, 1080, 1084, 1089, 1100, 0,
1152 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1153 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1154 /* 91 - 2560x1080@100Hz */
1155 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778,
1156 2822, 2970, 0, 1080, 1084, 1089, 1250, 0,
1157 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1158 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1159 /* 92 - 2560x1080@120Hz */
1160 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108,
1161 3152, 3300, 0, 1080, 1084, 1089, 1250, 0,
1162 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1163 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1164 /* 93 - 3840x2160p@24Hz 16:9 */
1165 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1166 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1167 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1168 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1169 /* 94 - 3840x2160p@25Hz 16:9 */
1170 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1171 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1172 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1173 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1174 /* 95 - 3840x2160p@30Hz 16:9 */
1175 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1176 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1177 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1178 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1179 /* 96 - 3840x2160p@50Hz 16:9 */
1180 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1181 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1182 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1183 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1184 /* 97 - 3840x2160p@60Hz 16:9 */
1185 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1186 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1187 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1188 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, },
1189 /* 98 - 4096x2160p@24Hz 256:135 */
1190 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116,
1191 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1192 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1193 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1194 /* 99 - 4096x2160p@25Hz 256:135 */
1195 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064,
1196 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1198 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1199 /* 100 - 4096x2160p@30Hz 256:135 */
1200 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184,
1201 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1202 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1203 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1204 /* 101 - 4096x2160p@50Hz 256:135 */
1205 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064,
1206 5152, 5280, 0, 2160, 2168, 2178, 2250, 0,
1207 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1208 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1209 /* 102 - 4096x2160p@60Hz 256:135 */
1210 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184,
1211 4272, 4400, 0, 2160, 2168, 2178, 2250, 0,
1212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1213 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, },
1214 /* 103 - 3840x2160p@24Hz 64:27 */
1215 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116,
1216 5204, 5500, 0, 2160, 2168, 2178, 2250, 0,
1217 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1218 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1219 /* 104 - 3840x2160p@25Hz 64:27 */
1220 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896,
1221 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1223 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1224 /* 105 - 3840x2160p@30Hz 64:27 */
1225 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016,
1226 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1227 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1228 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1229 /* 106 - 3840x2160p@50Hz 64:27 */
1230 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896,
1231 4984, 5280, 0, 2160, 2168, 2178, 2250, 0,
1232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1233 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1234 /* 107 - 3840x2160p@60Hz 64:27 */
1235 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016,
1236 4104, 4400, 0, 2160, 2168, 2178, 2250, 0,
1237 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1238 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, },
1242 * HDMI 1.4 4k modes. Index using the VIC.
1244 static const struct drm_display_mode edid_4k_modes[] = {
1245 /* 0 - dummy, VICs start at 1 */
1247 /* 1 - 3840x2160@30Hz */
1248 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1249 3840, 4016, 4104, 4400, 0,
1250 2160, 2168, 2178, 2250, 0,
1251 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1253 /* 2 - 3840x2160@25Hz */
1254 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1255 3840, 4896, 4984, 5280, 0,
1256 2160, 2168, 2178, 2250, 0,
1257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1259 /* 3 - 3840x2160@24Hz */
1260 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000,
1261 3840, 5116, 5204, 5500, 0,
1262 2160, 2168, 2178, 2250, 0,
1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1265 /* 4 - 4096x2160@24Hz (SMPTE) */
1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000,
1267 4096, 5116, 5204, 5500, 0,
1268 2160, 2168, 2178, 2250, 0,
1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC),
1273 /*** DDC fetch and block validation ***/
1275 static const u8 edid_header[] = {
1276 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
1280 * drm_edid_header_is_valid - sanity check the header of the base EDID block
1281 * @raw_edid: pointer to raw base EDID block
1283 * Sanity check the header of the base EDID block.
1285 * Return: 8 if the header is perfect, down to 0 if it's totally wrong.
1287 int drm_edid_header_is_valid(const u8 *raw_edid)
1291 for (i = 0; i < sizeof(edid_header); i++)
1292 if (raw_edid[i] == edid_header[i])
1297 EXPORT_SYMBOL(drm_edid_header_is_valid);
1299 static int edid_fixup __read_mostly = 6;
1300 module_param_named(edid_fixup, edid_fixup, int, 0400);
1301 MODULE_PARM_DESC(edid_fixup,
1302 "Minimum number of valid EDID header bytes (0-8, default 6)");
1304 static void drm_get_displayid(struct drm_connector *connector,
1307 static int drm_edid_block_checksum(const u8 *raw_edid)
1311 for (i = 0; i < EDID_LENGTH; i++)
1312 csum += raw_edid[i];
1317 static bool drm_edid_is_zero(const u8 *in_edid, int length)
1319 if (memchr_inv(in_edid, 0, length))
1326 * drm_edid_block_valid - Sanity check the EDID block (base or extension)
1327 * @raw_edid: pointer to raw EDID block
1328 * @block: type of block to validate (0 for base, extension otherwise)
1329 * @print_bad_edid: if true, dump bad EDID blocks to the console
1330 * @edid_corrupt: if true, the header or checksum is invalid
1332 * Validate a base or extension EDID block and optionally dump bad blocks to
1335 * Return: True if the block is valid, false otherwise.
1337 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid,
1341 struct edid *edid = (struct edid *)raw_edid;
1343 if (WARN_ON(!raw_edid))
1346 if (edid_fixup > 8 || edid_fixup < 0)
1350 int score = drm_edid_header_is_valid(raw_edid);
1353 *edid_corrupt = false;
1354 } else if (score >= edid_fixup) {
1355 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6
1356 * The corrupt flag needs to be set here otherwise, the
1357 * fix-up code here will correct the problem, the
1358 * checksum is correct and the test fails
1361 *edid_corrupt = true;
1362 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n");
1363 memcpy(raw_edid, edid_header, sizeof(edid_header));
1366 *edid_corrupt = true;
1371 csum = drm_edid_block_checksum(raw_edid);
1374 *edid_corrupt = true;
1376 /* allow CEA to slide through, switches mangle this */
1377 if (raw_edid[0] == CEA_EXT) {
1378 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum);
1379 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n");
1382 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum);
1388 /* per-block-type checks */
1389 switch (raw_edid[0]) {
1391 if (edid->version != 1) {
1392 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version);
1396 if (edid->revision > 4)
1397 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n");
1407 if (print_bad_edid) {
1408 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) {
1409 pr_notice("EDID block is all zeroes\n");
1411 pr_notice("Raw EDID:\n");
1412 print_hex_dump(KERN_NOTICE,
1413 " \t", DUMP_PREFIX_NONE, 16, 1,
1414 raw_edid, EDID_LENGTH, false);
1419 EXPORT_SYMBOL(drm_edid_block_valid);
1422 * drm_edid_is_valid - sanity check EDID data
1425 * Sanity-check an entire EDID record (including extensions)
1427 * Return: True if the EDID data is valid, false otherwise.
1429 bool drm_edid_is_valid(struct edid *edid)
1432 u8 *raw = (u8 *)edid;
1437 for (i = 0; i <= edid->extensions; i++)
1438 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL))
1443 EXPORT_SYMBOL(drm_edid_is_valid);
1445 #define DDC_SEGMENT_ADDR 0x30
1447 * drm_do_probe_ddc_edid() - get EDID information via I2C
1448 * @data: I2C device adapter
1449 * @buf: EDID data buffer to be filled
1450 * @block: 128 byte EDID block to start fetching from
1451 * @len: EDID data buffer length to fetch
1453 * Try to fetch EDID information by calling I2C driver functions.
1455 * Return: 0 on success or -1 on failure.
1458 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len)
1460 struct i2c_adapter *adapter = data;
1461 unsigned char start = block * EDID_LENGTH;
1462 unsigned char segment = block >> 1;
1463 unsigned char xfers = segment ? 3 : 2;
1464 int ret, retries = 5;
1467 * The core I2C driver will automatically retry the transfer if the
1468 * adapter reports EAGAIN. However, we find that bit-banging transfers
1469 * are susceptible to errors under a heavily loaded machine and
1470 * generate spurious NAKs and timeouts. Retrying the transfer
1471 * of the individual block a few times seems to overcome this.
1474 struct i2c_msg msgs[] = {
1476 .addr = DDC_SEGMENT_ADDR,
1494 * Avoid sending the segment addr to not upset non-compliant
1497 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers);
1499 if (ret == -ENXIO) {
1500 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n",
1504 } while (ret != xfers && --retries);
1506 return ret == xfers ? 0 : -1;
1509 static void connector_bad_edid(struct drm_connector *connector,
1510 u8 *edid, int num_blocks)
1514 if (connector->bad_edid_counter++ && !(drm_debug & DRM_UT_KMS))
1517 dev_warn(connector->dev->dev,
1518 "%s: EDID is invalid:\n",
1520 for (i = 0; i < num_blocks; i++) {
1521 u8 *block = edid + i * EDID_LENGTH;
1524 if (drm_edid_is_zero(block, EDID_LENGTH))
1525 sprintf(prefix, "\t[%02x] ZERO ", i);
1526 else if (!drm_edid_block_valid(block, i, false, NULL))
1527 sprintf(prefix, "\t[%02x] BAD ", i);
1529 sprintf(prefix, "\t[%02x] GOOD ", i);
1531 print_hex_dump(KERN_WARNING,
1532 prefix, DUMP_PREFIX_NONE, 16, 1,
1533 block, EDID_LENGTH, false);
1538 * drm_do_get_edid - get EDID data using a custom EDID block read function
1539 * @connector: connector we're probing
1540 * @get_edid_block: EDID block read function
1541 * @data: private data passed to the block read function
1543 * When the I2C adapter connected to the DDC bus is hidden behind a device that
1544 * exposes a different interface to read EDID blocks this function can be used
1545 * to get EDID data using a custom block read function.
1547 * As in the general case the DDC bus is accessible by the kernel at the I2C
1548 * level, drivers must make all reasonable efforts to expose it as an I2C
1549 * adapter and use drm_get_edid() instead of abusing this function.
1551 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1553 struct edid *drm_do_get_edid(struct drm_connector *connector,
1554 int (*get_edid_block)(void *data, u8 *buf, unsigned int block,
1558 int i, j = 0, valid_extensions = 0;
1561 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL)
1564 /* base block fetch */
1565 for (i = 0; i < 4; i++) {
1566 if (get_edid_block(data, edid, 0, EDID_LENGTH))
1568 if (drm_edid_block_valid(edid, 0, false,
1569 &connector->edid_corrupt))
1571 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) {
1572 connector->null_edid_counter++;
1579 /* if there's no extensions, we're done */
1580 valid_extensions = edid[0x7e];
1581 if (valid_extensions == 0)
1582 return (struct edid *)edid;
1584 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1589 for (j = 1; j <= edid[0x7e]; j++) {
1590 u8 *block = edid + j * EDID_LENGTH;
1592 for (i = 0; i < 4; i++) {
1593 if (get_edid_block(data, block, j, EDID_LENGTH))
1595 if (drm_edid_block_valid(block, j, false, NULL))
1603 if (valid_extensions != edid[0x7e]) {
1606 connector_bad_edid(connector, edid, edid[0x7e] + 1);
1608 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions;
1609 edid[0x7e] = valid_extensions;
1611 new = kmalloc((valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1616 for (i = 0; i <= edid[0x7e]; i++) {
1617 u8 *block = edid + i * EDID_LENGTH;
1619 if (!drm_edid_block_valid(block, i, false, NULL))
1622 memcpy(base, block, EDID_LENGTH);
1623 base += EDID_LENGTH;
1630 return (struct edid *)edid;
1633 connector_bad_edid(connector, edid, 1);
1638 EXPORT_SYMBOL_GPL(drm_do_get_edid);
1641 * drm_probe_ddc() - probe DDC presence
1642 * @adapter: I2C adapter to probe
1644 * Return: True on success, false on failure.
1647 drm_probe_ddc(struct i2c_adapter *adapter)
1651 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0);
1653 EXPORT_SYMBOL(drm_probe_ddc);
1656 * drm_get_edid - get EDID data, if available
1657 * @connector: connector we're probing
1658 * @adapter: I2C adapter to use for DDC
1660 * Poke the given I2C channel to grab EDID data if possible. If found,
1661 * attach it to the connector.
1663 * Return: Pointer to valid EDID or NULL if we couldn't find any.
1665 struct edid *drm_get_edid(struct drm_connector *connector,
1666 struct i2c_adapter *adapter)
1670 if (connector->force == DRM_FORCE_OFF)
1673 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter))
1676 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter);
1678 drm_get_displayid(connector, edid);
1681 EXPORT_SYMBOL(drm_get_edid);
1684 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output
1685 * @connector: connector we're probing
1686 * @adapter: I2C adapter to use for DDC
1688 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of
1689 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily
1690 * switch DDC to the GPU which is retrieving EDID.
1692 * Return: Pointer to valid EDID or %NULL if we couldn't find any.
1694 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector,
1695 struct i2c_adapter *adapter)
1697 struct pci_dev *pdev = connector->dev->pdev;
1700 vga_switcheroo_lock_ddc(pdev);
1701 edid = drm_get_edid(connector, adapter);
1702 vga_switcheroo_unlock_ddc(pdev);
1706 EXPORT_SYMBOL(drm_get_edid_switcheroo);
1709 * drm_edid_duplicate - duplicate an EDID and the extensions
1710 * @edid: EDID to duplicate
1712 * Return: Pointer to duplicated EDID or NULL on allocation failure.
1714 struct edid *drm_edid_duplicate(const struct edid *edid)
1716 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL);
1718 EXPORT_SYMBOL(drm_edid_duplicate);
1720 /*** EDID parsing ***/
1723 * edid_vendor - match a string against EDID's obfuscated vendor field
1724 * @edid: EDID to match
1725 * @vendor: vendor string
1727 * Returns true if @vendor is in @edid, false otherwise
1729 static bool edid_vendor(struct edid *edid, const char *vendor)
1731 char edid_vendor[3];
1733 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@';
1734 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) |
1735 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@';
1736 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@';
1738 return !strncmp(edid_vendor, vendor, 3);
1742 * edid_get_quirks - return quirk flags for a given EDID
1743 * @edid: EDID to process
1745 * This tells subsequent routines what fixes they need to apply.
1747 static u32 edid_get_quirks(struct edid *edid)
1749 const struct edid_quirk *quirk;
1752 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) {
1753 quirk = &edid_quirk_list[i];
1755 if (edid_vendor(edid, quirk->vendor) &&
1756 (EDID_PRODUCT_ID(edid) == quirk->product_id))
1757 return quirk->quirks;
1763 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1764 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t)))
1767 * edid_fixup_preferred - set preferred modes based on quirk list
1768 * @connector: has mode list to fix up
1769 * @quirks: quirks list
1771 * Walk the mode list for @connector, clearing the preferred status
1772 * on existing modes and setting it anew for the right mode ala @quirks.
1774 static void edid_fixup_preferred(struct drm_connector *connector,
1777 struct drm_display_mode *t, *cur_mode, *preferred_mode;
1778 int target_refresh = 0;
1779 int cur_vrefresh, preferred_vrefresh;
1781 if (list_empty(&connector->probed_modes))
1784 if (quirks & EDID_QUIRK_PREFER_LARGE_60)
1785 target_refresh = 60;
1786 if (quirks & EDID_QUIRK_PREFER_LARGE_75)
1787 target_refresh = 75;
1789 preferred_mode = list_first_entry(&connector->probed_modes,
1790 struct drm_display_mode, head);
1792 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) {
1793 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED;
1795 if (cur_mode == preferred_mode)
1798 /* Largest mode is preferred */
1799 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode))
1800 preferred_mode = cur_mode;
1802 cur_vrefresh = cur_mode->vrefresh ?
1803 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode);
1804 preferred_vrefresh = preferred_mode->vrefresh ?
1805 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode);
1806 /* At a given size, try to get closest to target refresh */
1807 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) &&
1808 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) <
1809 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) {
1810 preferred_mode = cur_mode;
1814 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED;
1818 mode_is_rb(const struct drm_display_mode *mode)
1820 return (mode->htotal - mode->hdisplay == 160) &&
1821 (mode->hsync_end - mode->hdisplay == 80) &&
1822 (mode->hsync_end - mode->hsync_start == 32) &&
1823 (mode->vsync_start - mode->vdisplay == 3);
1827 * drm_mode_find_dmt - Create a copy of a mode if present in DMT
1828 * @dev: Device to duplicate against
1829 * @hsize: Mode width
1830 * @vsize: Mode height
1831 * @fresh: Mode refresh rate
1832 * @rb: Mode reduced-blanking-ness
1834 * Walk the DMT mode list looking for a match for the given parameters.
1836 * Return: A newly allocated copy of the mode, or NULL if not found.
1838 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev,
1839 int hsize, int vsize, int fresh,
1844 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
1845 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
1846 if (hsize != ptr->hdisplay)
1848 if (vsize != ptr->vdisplay)
1850 if (fresh != drm_mode_vrefresh(ptr))
1852 if (rb != mode_is_rb(ptr))
1855 return drm_mode_duplicate(dev, ptr);
1860 EXPORT_SYMBOL(drm_mode_find_dmt);
1862 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1865 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1869 u8 *det_base = ext + d;
1872 for (i = 0; i < n; i++)
1873 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1877 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure)
1879 unsigned int i, n = min((int)ext[0x02], 6);
1880 u8 *det_base = ext + 5;
1883 return; /* unknown version */
1885 for (i = 0; i < n; i++)
1886 cb((struct detailed_timing *)(det_base + 18 * i), closure);
1890 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure)
1893 struct edid *edid = (struct edid *)raw_edid;
1898 for (i = 0; i < EDID_DETAILED_TIMINGS; i++)
1899 cb(&(edid->detailed_timings[i]), closure);
1901 for (i = 1; i <= raw_edid[0x7e]; i++) {
1902 u8 *ext = raw_edid + (i * EDID_LENGTH);
1905 cea_for_each_detailed_block(ext, cb, closure);
1908 vtb_for_each_detailed_block(ext, cb, closure);
1917 is_rb(struct detailed_timing *t, void *data)
1920 if (r[3] == EDID_DETAIL_MONITOR_RANGE)
1922 *(bool *)data = true;
1925 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */
1927 drm_monitor_supports_rb(struct edid *edid)
1929 if (edid->revision >= 4) {
1931 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret);
1935 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0);
1939 find_gtf2(struct detailed_timing *t, void *data)
1942 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02)
1946 /* Secondary GTF curve kicks in above some break frequency */
1948 drm_gtf2_hbreak(struct edid *edid)
1951 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1952 return r ? (r[12] * 2) : 0;
1956 drm_gtf2_2c(struct edid *edid)
1959 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1960 return r ? r[13] : 0;
1964 drm_gtf2_m(struct edid *edid)
1967 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1968 return r ? (r[15] << 8) + r[14] : 0;
1972 drm_gtf2_k(struct edid *edid)
1975 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1976 return r ? r[16] : 0;
1980 drm_gtf2_2j(struct edid *edid)
1983 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r);
1984 return r ? r[17] : 0;
1988 * standard_timing_level - get std. timing level(CVT/GTF/DMT)
1989 * @edid: EDID block to scan
1991 static int standard_timing_level(struct edid *edid)
1993 if (edid->revision >= 2) {
1994 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF))
1996 if (drm_gtf2_hbreak(edid))
2004 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old
2005 * monitors fill with ascii space (0x20) instead.
2008 bad_std_timing(u8 a, u8 b)
2010 return (a == 0x00 && b == 0x00) ||
2011 (a == 0x01 && b == 0x01) ||
2012 (a == 0x20 && b == 0x20);
2016 * drm_mode_std - convert standard mode info (width, height, refresh) into mode
2017 * @connector: connector of for the EDID block
2018 * @edid: EDID block to scan
2019 * @t: standard timing params
2021 * Take the standard timing params (in this case width, aspect, and refresh)
2022 * and convert them into a real mode using CVT/GTF/DMT.
2024 static struct drm_display_mode *
2025 drm_mode_std(struct drm_connector *connector, struct edid *edid,
2026 struct std_timing *t)
2028 struct drm_device *dev = connector->dev;
2029 struct drm_display_mode *m, *mode = NULL;
2032 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK)
2033 >> EDID_TIMING_ASPECT_SHIFT;
2034 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK)
2035 >> EDID_TIMING_VFREQ_SHIFT;
2036 int timing_level = standard_timing_level(edid);
2038 if (bad_std_timing(t->hsize, t->vfreq_aspect))
2041 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */
2042 hsize = t->hsize * 8 + 248;
2043 /* vrefresh_rate = vfreq + 60 */
2044 vrefresh_rate = vfreq + 60;
2045 /* the vdisplay is calculated based on the aspect ratio */
2046 if (aspect_ratio == 0) {
2047 if (edid->revision < 3)
2050 vsize = (hsize * 10) / 16;
2051 } else if (aspect_ratio == 1)
2052 vsize = (hsize * 3) / 4;
2053 else if (aspect_ratio == 2)
2054 vsize = (hsize * 4) / 5;
2056 vsize = (hsize * 9) / 16;
2058 /* HDTV hack, part 1 */
2059 if (vrefresh_rate == 60 &&
2060 ((hsize == 1360 && vsize == 765) ||
2061 (hsize == 1368 && vsize == 769))) {
2067 * If this connector already has a mode for this size and refresh
2068 * rate (because it came from detailed or CVT info), use that
2069 * instead. This way we don't have to guess at interlace or
2072 list_for_each_entry(m, &connector->probed_modes, head)
2073 if (m->hdisplay == hsize && m->vdisplay == vsize &&
2074 drm_mode_vrefresh(m) == vrefresh_rate)
2077 /* HDTV hack, part 2 */
2078 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) {
2079 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0,
2081 mode->hdisplay = 1366;
2082 mode->hsync_start = mode->hsync_start - 1;
2083 mode->hsync_end = mode->hsync_end - 1;
2087 /* check whether it can be found in default mode table */
2088 if (drm_monitor_supports_rb(edid)) {
2089 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate,
2094 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false);
2098 /* okay, generate it */
2099 switch (timing_level) {
2103 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2107 * This is potentially wrong if there's ever a monitor with
2108 * more than one ranges section, each claiming a different
2109 * secondary GTF curve. Please don't do that.
2111 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0);
2114 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) {
2115 drm_mode_destroy(dev, mode);
2116 mode = drm_gtf_mode_complex(dev, hsize, vsize,
2117 vrefresh_rate, 0, 0,
2125 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0,
2133 * EDID is delightfully ambiguous about how interlaced modes are to be
2134 * encoded. Our internal representation is of frame height, but some
2135 * HDTV detailed timings are encoded as field height.
2137 * The format list here is from CEA, in frame size. Technically we
2138 * should be checking refresh rate too. Whatever.
2141 drm_mode_do_interlace_quirk(struct drm_display_mode *mode,
2142 struct detailed_pixel_timing *pt)
2145 static const struct {
2147 } cea_interlaced[] = {
2157 if (!(pt->misc & DRM_EDID_PT_INTERLACED))
2160 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) {
2161 if ((mode->hdisplay == cea_interlaced[i].w) &&
2162 (mode->vdisplay == cea_interlaced[i].h / 2)) {
2163 mode->vdisplay *= 2;
2164 mode->vsync_start *= 2;
2165 mode->vsync_end *= 2;
2171 mode->flags |= DRM_MODE_FLAG_INTERLACE;
2175 * drm_mode_detailed - create a new mode from an EDID detailed timing section
2176 * @dev: DRM device (needed to create new mode)
2178 * @timing: EDID detailed timing info
2179 * @quirks: quirks to apply
2181 * An EDID detailed timing block contains enough info for us to create and
2182 * return a new struct drm_display_mode.
2184 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev,
2186 struct detailed_timing *timing,
2189 struct drm_display_mode *mode;
2190 struct detailed_pixel_timing *pt = &timing->data.pixel_data;
2191 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo;
2192 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo;
2193 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo;
2194 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo;
2195 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo;
2196 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo;
2197 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4;
2198 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
2200 /* ignore tiny modes */
2201 if (hactive < 64 || vactive < 64)
2204 if (pt->misc & DRM_EDID_PT_STEREO) {
2205 DRM_DEBUG_KMS("stereo mode not supported\n");
2208 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) {
2209 DRM_DEBUG_KMS("composite sync not supported\n");
2212 /* it is incorrect if hsync/vsync width is zero */
2213 if (!hsync_pulse_width || !vsync_pulse_width) {
2214 DRM_DEBUG_KMS("Incorrect Detailed timing. "
2215 "Wrong Hsync/Vsync pulse width\n");
2219 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) {
2220 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false);
2227 mode = drm_mode_create(dev);
2231 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH)
2232 timing->pixel_clock = cpu_to_le16(1088);
2234 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2236 mode->hdisplay = hactive;
2237 mode->hsync_start = mode->hdisplay + hsync_offset;
2238 mode->hsync_end = mode->hsync_start + hsync_pulse_width;
2239 mode->htotal = mode->hdisplay + hblank;
2241 mode->vdisplay = vactive;
2242 mode->vsync_start = mode->vdisplay + vsync_offset;
2243 mode->vsync_end = mode->vsync_start + vsync_pulse_width;
2244 mode->vtotal = mode->vdisplay + vblank;
2246 /* Some EDIDs have bogus h/vtotal values */
2247 if (mode->hsync_end > mode->htotal)
2248 mode->htotal = mode->hsync_end + 1;
2249 if (mode->vsync_end > mode->vtotal)
2250 mode->vtotal = mode->vsync_end + 1;
2252 drm_mode_do_interlace_quirk(mode, pt);
2254 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) {
2255 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE;
2258 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ?
2259 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
2260 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ?
2261 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
2264 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4;
2265 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8;
2267 if (quirks & EDID_QUIRK_DETAILED_IN_CM) {
2268 mode->width_mm *= 10;
2269 mode->height_mm *= 10;
2272 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) {
2273 mode->width_mm = edid->width_cm * 10;
2274 mode->height_mm = edid->height_cm * 10;
2277 mode->type = DRM_MODE_TYPE_DRIVER;
2278 mode->vrefresh = drm_mode_vrefresh(mode);
2279 drm_mode_set_name(mode);
2285 mode_in_hsync_range(const struct drm_display_mode *mode,
2286 struct edid *edid, u8 *t)
2288 int hsync, hmin, hmax;
2291 if (edid->revision >= 4)
2292 hmin += ((t[4] & 0x04) ? 255 : 0);
2294 if (edid->revision >= 4)
2295 hmax += ((t[4] & 0x08) ? 255 : 0);
2296 hsync = drm_mode_hsync(mode);
2298 return (hsync <= hmax && hsync >= hmin);
2302 mode_in_vsync_range(const struct drm_display_mode *mode,
2303 struct edid *edid, u8 *t)
2305 int vsync, vmin, vmax;
2308 if (edid->revision >= 4)
2309 vmin += ((t[4] & 0x01) ? 255 : 0);
2311 if (edid->revision >= 4)
2312 vmax += ((t[4] & 0x02) ? 255 : 0);
2313 vsync = drm_mode_vrefresh(mode);
2315 return (vsync <= vmax && vsync >= vmin);
2319 range_pixel_clock(struct edid *edid, u8 *t)
2322 if (t[9] == 0 || t[9] == 255)
2325 /* 1.4 with CVT support gives us real precision, yay */
2326 if (edid->revision >= 4 && t[10] == 0x04)
2327 return (t[9] * 10000) - ((t[12] >> 2) * 250);
2329 /* 1.3 is pathetic, so fuzz up a bit */
2330 return t[9] * 10000 + 5001;
2334 mode_in_range(const struct drm_display_mode *mode, struct edid *edid,
2335 struct detailed_timing *timing)
2338 u8 *t = (u8 *)timing;
2340 if (!mode_in_hsync_range(mode, edid, t))
2343 if (!mode_in_vsync_range(mode, edid, t))
2346 if ((max_clock = range_pixel_clock(edid, t)))
2347 if (mode->clock > max_clock)
2350 /* 1.4 max horizontal check */
2351 if (edid->revision >= 4 && t[10] == 0x04)
2352 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3))))
2355 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid))
2361 static bool valid_inferred_mode(const struct drm_connector *connector,
2362 const struct drm_display_mode *mode)
2364 const struct drm_display_mode *m;
2367 list_for_each_entry(m, &connector->probed_modes, head) {
2368 if (mode->hdisplay == m->hdisplay &&
2369 mode->vdisplay == m->vdisplay &&
2370 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m))
2371 return false; /* duplicated */
2372 if (mode->hdisplay <= m->hdisplay &&
2373 mode->vdisplay <= m->vdisplay)
2380 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2381 struct detailed_timing *timing)
2384 struct drm_display_mode *newmode;
2385 struct drm_device *dev = connector->dev;
2387 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) {
2388 if (mode_in_range(drm_dmt_modes + i, edid, timing) &&
2389 valid_inferred_mode(connector, drm_dmt_modes + i)) {
2390 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]);
2392 drm_mode_probed_add(connector, newmode);
2401 /* fix up 1366x768 mode from 1368x768;
2402 * GFT/CVT can't express 1366 width which isn't dividable by 8
2404 void drm_mode_fixup_1366x768(struct drm_display_mode *mode)
2406 if (mode->hdisplay == 1368 && mode->vdisplay == 768) {
2407 mode->hdisplay = 1366;
2408 mode->hsync_start--;
2410 drm_mode_set_name(mode);
2415 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid,
2416 struct detailed_timing *timing)
2419 struct drm_display_mode *newmode;
2420 struct drm_device *dev = connector->dev;
2422 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2423 const struct minimode *m = &extra_modes[i];
2424 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0);
2428 drm_mode_fixup_1366x768(newmode);
2429 if (!mode_in_range(newmode, edid, timing) ||
2430 !valid_inferred_mode(connector, newmode)) {
2431 drm_mode_destroy(dev, newmode);
2435 drm_mode_probed_add(connector, newmode);
2443 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid,
2444 struct detailed_timing *timing)
2447 struct drm_display_mode *newmode;
2448 struct drm_device *dev = connector->dev;
2449 bool rb = drm_monitor_supports_rb(edid);
2451 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) {
2452 const struct minimode *m = &extra_modes[i];
2453 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0);
2457 drm_mode_fixup_1366x768(newmode);
2458 if (!mode_in_range(newmode, edid, timing) ||
2459 !valid_inferred_mode(connector, newmode)) {
2460 drm_mode_destroy(dev, newmode);
2464 drm_mode_probed_add(connector, newmode);
2472 do_inferred_modes(struct detailed_timing *timing, void *c)
2474 struct detailed_mode_closure *closure = c;
2475 struct detailed_non_pixel *data = &timing->data.other_data;
2476 struct detailed_data_monitor_range *range = &data->data.range;
2478 if (data->type != EDID_DETAIL_MONITOR_RANGE)
2481 closure->modes += drm_dmt_modes_for_range(closure->connector,
2485 if (!version_greater(closure->edid, 1, 1))
2486 return; /* GTF not defined yet */
2488 switch (range->flags) {
2489 case 0x02: /* secondary gtf, XXX could do more */
2490 case 0x00: /* default gtf */
2491 closure->modes += drm_gtf_modes_for_range(closure->connector,
2495 case 0x04: /* cvt, only in 1.4+ */
2496 if (!version_greater(closure->edid, 1, 3))
2499 closure->modes += drm_cvt_modes_for_range(closure->connector,
2503 case 0x01: /* just the ranges, no formula */
2510 add_inferred_modes(struct drm_connector *connector, struct edid *edid)
2512 struct detailed_mode_closure closure = {
2513 .connector = connector,
2517 if (version_greater(edid, 1, 0))
2518 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes,
2521 return closure.modes;
2525 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing)
2527 int i, j, m, modes = 0;
2528 struct drm_display_mode *mode;
2529 u8 *est = ((u8 *)timing) + 6;
2531 for (i = 0; i < 6; i++) {
2532 for (j = 7; j >= 0; j--) {
2533 m = (i * 8) + (7 - j);
2534 if (m >= ARRAY_SIZE(est3_modes))
2536 if (est[i] & (1 << j)) {
2537 mode = drm_mode_find_dmt(connector->dev,
2543 drm_mode_probed_add(connector, mode);
2554 do_established_modes(struct detailed_timing *timing, void *c)
2556 struct detailed_mode_closure *closure = c;
2557 struct detailed_non_pixel *data = &timing->data.other_data;
2559 if (data->type == EDID_DETAIL_EST_TIMINGS)
2560 closure->modes += drm_est3_modes(closure->connector, timing);
2564 * add_established_modes - get est. modes from EDID and add them
2565 * @connector: connector to add mode(s) to
2566 * @edid: EDID block to scan
2568 * Each EDID block contains a bitmap of the supported "established modes" list
2569 * (defined above). Tease them out and add them to the global modes list.
2572 add_established_modes(struct drm_connector *connector, struct edid *edid)
2574 struct drm_device *dev = connector->dev;
2575 unsigned long est_bits = edid->established_timings.t1 |
2576 (edid->established_timings.t2 << 8) |
2577 ((edid->established_timings.mfg_rsvd & 0x80) << 9);
2579 struct detailed_mode_closure closure = {
2580 .connector = connector,
2584 for (i = 0; i <= EDID_EST_TIMINGS; i++) {
2585 if (est_bits & (1<<i)) {
2586 struct drm_display_mode *newmode;
2587 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]);
2589 drm_mode_probed_add(connector, newmode);
2595 if (version_greater(edid, 1, 0))
2596 drm_for_each_detailed_block((u8 *)edid,
2597 do_established_modes, &closure);
2599 return modes + closure.modes;
2603 do_standard_modes(struct detailed_timing *timing, void *c)
2605 struct detailed_mode_closure *closure = c;
2606 struct detailed_non_pixel *data = &timing->data.other_data;
2607 struct drm_connector *connector = closure->connector;
2608 struct edid *edid = closure->edid;
2610 if (data->type == EDID_DETAIL_STD_MODES) {
2612 for (i = 0; i < 6; i++) {
2613 struct std_timing *std;
2614 struct drm_display_mode *newmode;
2616 std = &data->data.timings[i];
2617 newmode = drm_mode_std(connector, edid, std);
2619 drm_mode_probed_add(connector, newmode);
2627 * add_standard_modes - get std. modes from EDID and add them
2628 * @connector: connector to add mode(s) to
2629 * @edid: EDID block to scan
2631 * Standard modes can be calculated using the appropriate standard (DMT,
2632 * GTF or CVT. Grab them from @edid and add them to the list.
2635 add_standard_modes(struct drm_connector *connector, struct edid *edid)
2638 struct detailed_mode_closure closure = {
2639 .connector = connector,
2643 for (i = 0; i < EDID_STD_TIMINGS; i++) {
2644 struct drm_display_mode *newmode;
2646 newmode = drm_mode_std(connector, edid,
2647 &edid->standard_timings[i]);
2649 drm_mode_probed_add(connector, newmode);
2654 if (version_greater(edid, 1, 0))
2655 drm_for_each_detailed_block((u8 *)edid, do_standard_modes,
2658 /* XXX should also look for standard codes in VTB blocks */
2660 return modes + closure.modes;
2663 static int drm_cvt_modes(struct drm_connector *connector,
2664 struct detailed_timing *timing)
2666 int i, j, modes = 0;
2667 struct drm_display_mode *newmode;
2668 struct drm_device *dev = connector->dev;
2669 struct cvt_timing *cvt;
2670 const int rates[] = { 60, 85, 75, 60, 50 };
2671 const u8 empty[3] = { 0, 0, 0 };
2673 for (i = 0; i < 4; i++) {
2674 int uninitialized_var(width), height;
2675 cvt = &(timing->data.other_data.data.cvt[i]);
2677 if (!memcmp(cvt->code, empty, 3))
2680 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2;
2681 switch (cvt->code[1] & 0x0c) {
2683 width = height * 4 / 3;
2686 width = height * 16 / 9;
2689 width = height * 16 / 10;
2692 width = height * 15 / 9;
2696 for (j = 1; j < 5; j++) {
2697 if (cvt->code[2] & (1 << j)) {
2698 newmode = drm_cvt_mode(dev, width, height,
2702 drm_mode_probed_add(connector, newmode);
2713 do_cvt_mode(struct detailed_timing *timing, void *c)
2715 struct detailed_mode_closure *closure = c;
2716 struct detailed_non_pixel *data = &timing->data.other_data;
2718 if (data->type == EDID_DETAIL_CVT_3BYTE)
2719 closure->modes += drm_cvt_modes(closure->connector, timing);
2723 add_cvt_modes(struct drm_connector *connector, struct edid *edid)
2725 struct detailed_mode_closure closure = {
2726 .connector = connector,
2730 if (version_greater(edid, 1, 2))
2731 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure);
2733 /* XXX should also look for CVT codes in VTB blocks */
2735 return closure.modes;
2738 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode);
2741 do_detailed_mode(struct detailed_timing *timing, void *c)
2743 struct detailed_mode_closure *closure = c;
2744 struct drm_display_mode *newmode;
2746 if (timing->pixel_clock) {
2747 newmode = drm_mode_detailed(closure->connector->dev,
2748 closure->edid, timing,
2753 if (closure->preferred)
2754 newmode->type |= DRM_MODE_TYPE_PREFERRED;
2757 * Detailed modes are limited to 10kHz pixel clock resolution,
2758 * so fix up anything that looks like CEA/HDMI mode, but the clock
2759 * is just slightly off.
2761 fixup_detailed_cea_mode_clock(newmode);
2763 drm_mode_probed_add(closure->connector, newmode);
2765 closure->preferred = 0;
2770 * add_detailed_modes - Add modes from detailed timings
2771 * @connector: attached connector
2772 * @edid: EDID block to scan
2773 * @quirks: quirks to apply
2776 add_detailed_modes(struct drm_connector *connector, struct edid *edid,
2779 struct detailed_mode_closure closure = {
2780 .connector = connector,
2786 if (closure.preferred && !version_greater(edid, 1, 3))
2788 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING);
2790 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure);
2792 return closure.modes;
2795 #define AUDIO_BLOCK 0x01
2796 #define VIDEO_BLOCK 0x02
2797 #define VENDOR_BLOCK 0x03
2798 #define SPEAKER_BLOCK 0x04
2799 #define USE_EXTENDED_TAG 0x07
2800 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00
2801 #define EXT_VIDEO_DATA_BLOCK_420 0x0E
2802 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F
2803 #define EDID_BASIC_AUDIO (1 << 6)
2804 #define EDID_CEA_YCRCB444 (1 << 5)
2805 #define EDID_CEA_YCRCB422 (1 << 4)
2806 #define EDID_CEA_VCDB_QS (1 << 6)
2809 * Search EDID for CEA extension block.
2811 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id)
2813 u8 *edid_ext = NULL;
2816 /* No EDID or EDID extensions */
2817 if (edid == NULL || edid->extensions == 0)
2820 /* Find CEA extension */
2821 for (i = 0; i < edid->extensions; i++) {
2822 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1);
2823 if (edid_ext[0] == ext_id)
2827 if (i == edid->extensions)
2833 static u8 *drm_find_cea_extension(struct edid *edid)
2835 return drm_find_edid_extension(edid, CEA_EXT);
2838 static u8 *drm_find_displayid_extension(struct edid *edid)
2840 return drm_find_edid_extension(edid, DISPLAYID_EXT);
2844 * Calculate the alternate clock for the CEA mode
2845 * (60Hz vs. 59.94Hz etc.)
2848 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode)
2850 unsigned int clock = cea_mode->clock;
2852 if (cea_mode->vrefresh % 6 != 0)
2856 * edid_cea_modes contains the 59.94Hz
2857 * variant for 240 and 480 line modes,
2858 * and the 60Hz variant otherwise.
2860 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480)
2861 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
2863 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
2869 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode)
2872 * For certain VICs the spec allows the vertical
2873 * front porch to vary by one or two lines.
2875 * cea_modes[] stores the variant with the shortest
2876 * vertical front porch. We can adjust the mode to
2877 * get the other variants by simply increasing the
2878 * vertical front porch length.
2880 BUILD_BUG_ON(edid_cea_modes[8].vtotal != 262 ||
2881 edid_cea_modes[9].vtotal != 262 ||
2882 edid_cea_modes[12].vtotal != 262 ||
2883 edid_cea_modes[13].vtotal != 262 ||
2884 edid_cea_modes[23].vtotal != 312 ||
2885 edid_cea_modes[24].vtotal != 312 ||
2886 edid_cea_modes[27].vtotal != 312 ||
2887 edid_cea_modes[28].vtotal != 312);
2889 if (((vic == 8 || vic == 9 ||
2890 vic == 12 || vic == 13) && mode->vtotal < 263) ||
2891 ((vic == 23 || vic == 24 ||
2892 vic == 27 || vic == 28) && mode->vtotal < 314)) {
2893 mode->vsync_start++;
2903 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match,
2904 unsigned int clock_tolerance)
2908 if (!to_match->clock)
2911 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2912 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2913 unsigned int clock1, clock2;
2915 /* Check both 60Hz and 59.94Hz */
2916 clock1 = cea_mode.clock;
2917 clock2 = cea_mode_alternate_clock(&cea_mode);
2919 if (abs(to_match->clock - clock1) > clock_tolerance &&
2920 abs(to_match->clock - clock2) > clock_tolerance)
2924 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2926 } while (cea_mode_alternate_timings(vic, &cea_mode));
2933 * drm_match_cea_mode - look for a CEA mode matching given mode
2934 * @to_match: display mode
2936 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861
2939 u8 drm_match_cea_mode(const struct drm_display_mode *to_match)
2943 if (!to_match->clock)
2946 for (vic = 1; vic < ARRAY_SIZE(edid_cea_modes); vic++) {
2947 struct drm_display_mode cea_mode = edid_cea_modes[vic];
2948 unsigned int clock1, clock2;
2950 /* Check both 60Hz and 59.94Hz */
2951 clock1 = cea_mode.clock;
2952 clock2 = cea_mode_alternate_clock(&cea_mode);
2954 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
2955 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
2959 if (drm_mode_equal_no_clocks_no_stereo(to_match, &cea_mode))
2961 } while (cea_mode_alternate_timings(vic, &cea_mode));
2966 EXPORT_SYMBOL(drm_match_cea_mode);
2968 static bool drm_valid_cea_vic(u8 vic)
2970 return vic > 0 && vic < ARRAY_SIZE(edid_cea_modes);
2974 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to
2975 * the input VIC from the CEA mode list
2976 * @video_code: ID given to each of the CEA modes
2978 * Returns picture aspect ratio
2980 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code)
2982 return edid_cea_modes[video_code].picture_aspect_ratio;
2984 EXPORT_SYMBOL(drm_get_cea_aspect_ratio);
2987 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
2990 * It's almost like cea_mode_alternate_clock(), we just need to add an
2991 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this
2995 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode)
2997 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160)
2998 return hdmi_mode->clock;
3000 return cea_mode_alternate_clock(hdmi_mode);
3003 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match,
3004 unsigned int clock_tolerance)
3008 if (!to_match->clock)
3011 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3012 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3013 unsigned int clock1, clock2;
3015 /* Make sure to also match alternate clocks */
3016 clock1 = hdmi_mode->clock;
3017 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3019 if (abs(to_match->clock - clock1) > clock_tolerance &&
3020 abs(to_match->clock - clock2) > clock_tolerance)
3023 if (drm_mode_equal_no_clocks(to_match, hdmi_mode))
3031 * drm_match_hdmi_mode - look for a HDMI mode matching given mode
3032 * @to_match: display mode
3034 * An HDMI mode is one defined in the HDMI vendor specific block.
3036 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one.
3038 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match)
3042 if (!to_match->clock)
3045 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) {
3046 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic];
3047 unsigned int clock1, clock2;
3049 /* Make sure to also match alternate clocks */
3050 clock1 = hdmi_mode->clock;
3051 clock2 = hdmi_mode_alternate_clock(hdmi_mode);
3053 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3054 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3055 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode))
3061 static bool drm_valid_hdmi_vic(u8 vic)
3063 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes);
3067 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid)
3069 struct drm_device *dev = connector->dev;
3070 struct drm_display_mode *mode, *tmp;
3074 /* Don't add CEA modes if the CEA extension block is missing */
3075 if (!drm_find_cea_extension(edid))
3079 * Go through all probed modes and create a new mode
3080 * with the alternate clock for certain CEA modes.
3082 list_for_each_entry(mode, &connector->probed_modes, head) {
3083 const struct drm_display_mode *cea_mode = NULL;
3084 struct drm_display_mode *newmode;
3085 u8 vic = drm_match_cea_mode(mode);
3086 unsigned int clock1, clock2;
3088 if (drm_valid_cea_vic(vic)) {
3089 cea_mode = &edid_cea_modes[vic];
3090 clock2 = cea_mode_alternate_clock(cea_mode);
3092 vic = drm_match_hdmi_mode(mode);
3093 if (drm_valid_hdmi_vic(vic)) {
3094 cea_mode = &edid_4k_modes[vic];
3095 clock2 = hdmi_mode_alternate_clock(cea_mode);
3102 clock1 = cea_mode->clock;
3104 if (clock1 == clock2)
3107 if (mode->clock != clock1 && mode->clock != clock2)
3110 newmode = drm_mode_duplicate(dev, cea_mode);
3114 /* Carry over the stereo flags */
3115 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK;
3118 * The current mode could be either variant. Make
3119 * sure to pick the "other" clock for the new mode.
3121 if (mode->clock != clock1)
3122 newmode->clock = clock1;
3124 newmode->clock = clock2;
3126 list_add_tail(&newmode->head, &list);
3129 list_for_each_entry_safe(mode, tmp, &list, head) {
3130 list_del(&mode->head);
3131 drm_mode_probed_add(connector, mode);
3138 static u8 svd_to_vic(u8 svd)
3140 /* 0-6 bit vic, 7th bit native mode indicator */
3141 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192))
3147 static struct drm_display_mode *
3148 drm_display_mode_from_vic_index(struct drm_connector *connector,
3149 const u8 *video_db, u8 video_len,
3152 struct drm_device *dev = connector->dev;
3153 struct drm_display_mode *newmode;
3156 if (video_db == NULL || video_index >= video_len)
3159 /* CEA modes are numbered 1..127 */
3160 vic = svd_to_vic(video_db[video_index]);
3161 if (!drm_valid_cea_vic(vic))
3164 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3168 newmode->vrefresh = 0;
3174 * do_y420vdb_modes - Parse YCBCR 420 only modes
3175 * @connector: connector corresponding to the HDMI sink
3176 * @svds: start of the data block of CEA YCBCR 420 VDB
3177 * @len: length of the CEA YCBCR 420 VDB
3179 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB)
3180 * which contains modes which can be supported in YCBCR 420
3181 * output format only.
3183 static int do_y420vdb_modes(struct drm_connector *connector,
3184 const u8 *svds, u8 svds_len)
3187 struct drm_device *dev = connector->dev;
3188 struct drm_display_info *info = &connector->display_info;
3189 struct drm_hdmi_info *hdmi = &info->hdmi;
3191 for (i = 0; i < svds_len; i++) {
3192 u8 vic = svd_to_vic(svds[i]);
3193 struct drm_display_mode *newmode;
3195 if (!drm_valid_cea_vic(vic))
3198 newmode = drm_mode_duplicate(dev, &edid_cea_modes[vic]);
3201 bitmap_set(hdmi->y420_vdb_modes, vic, 1);
3202 drm_mode_probed_add(connector, newmode);
3207 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3212 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap
3213 * @connector: connector corresponding to the HDMI sink
3214 * @vic: CEA vic for the video mode to be added in the map
3216 * Makes an entry for a videomode in the YCBCR 420 bitmap
3219 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd)
3221 u8 vic = svd_to_vic(svd);
3222 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3224 if (!drm_valid_cea_vic(vic))
3227 bitmap_set(hdmi->y420_cmdb_modes, vic, 1);
3231 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len)
3234 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3236 for (i = 0; i < len; i++) {
3237 struct drm_display_mode *mode;
3238 mode = drm_display_mode_from_vic_index(connector, db, len, i);
3241 * YCBCR420 capability block contains a bitmap which
3242 * gives the index of CEA modes from CEA VDB, which
3243 * can support YCBCR 420 sampling output also (apart
3244 * from RGB/YCBCR444 etc).
3245 * For example, if the bit 0 in bitmap is set,
3246 * first mode in VDB can support YCBCR420 output too.
3247 * Add YCBCR420 modes only if sink is HDMI 2.0 capable.
3249 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i))
3250 drm_add_cmdb_modes(connector, db[i]);
3252 drm_mode_probed_add(connector, mode);
3260 struct stereo_mandatory_mode {
3261 int width, height, vrefresh;
3265 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = {
3266 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3267 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING },
3269 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3271 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF },
3272 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3273 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING },
3274 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM },
3275 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING }
3279 stereo_match_mandatory(const struct drm_display_mode *mode,
3280 const struct stereo_mandatory_mode *stereo_mode)
3282 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
3284 return mode->hdisplay == stereo_mode->width &&
3285 mode->vdisplay == stereo_mode->height &&
3286 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) &&
3287 drm_mode_vrefresh(mode) == stereo_mode->vrefresh;
3290 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector)
3292 struct drm_device *dev = connector->dev;
3293 const struct drm_display_mode *mode;
3294 struct list_head stereo_modes;
3297 INIT_LIST_HEAD(&stereo_modes);
3299 list_for_each_entry(mode, &connector->probed_modes, head) {
3300 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) {
3301 const struct stereo_mandatory_mode *mandatory;
3302 struct drm_display_mode *new_mode;
3304 if (!stereo_match_mandatory(mode,
3305 &stereo_mandatory_modes[i]))
3308 mandatory = &stereo_mandatory_modes[i];
3309 new_mode = drm_mode_duplicate(dev, mode);
3313 new_mode->flags |= mandatory->flags;
3314 list_add_tail(&new_mode->head, &stereo_modes);
3319 list_splice_tail(&stereo_modes, &connector->probed_modes);
3324 static int add_hdmi_mode(struct drm_connector *connector, u8 vic)
3326 struct drm_device *dev = connector->dev;
3327 struct drm_display_mode *newmode;
3329 if (!drm_valid_hdmi_vic(vic)) {
3330 DRM_ERROR("Unknown HDMI VIC: %d\n", vic);
3334 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]);
3338 drm_mode_probed_add(connector, newmode);
3343 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure,
3344 const u8 *video_db, u8 video_len, u8 video_index)
3346 struct drm_display_mode *newmode;
3349 if (structure & (1 << 0)) {
3350 newmode = drm_display_mode_from_vic_index(connector, video_db,
3354 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING;
3355 drm_mode_probed_add(connector, newmode);
3359 if (structure & (1 << 6)) {
3360 newmode = drm_display_mode_from_vic_index(connector, video_db,
3364 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3365 drm_mode_probed_add(connector, newmode);
3369 if (structure & (1 << 8)) {
3370 newmode = drm_display_mode_from_vic_index(connector, video_db,
3374 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3375 drm_mode_probed_add(connector, newmode);
3384 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block
3385 * @connector: connector corresponding to the HDMI sink
3386 * @db: start of the CEA vendor specific block
3387 * @len: length of the CEA block payload, ie. one can access up to db[len]
3389 * Parses the HDMI VSDB looking for modes to add to @connector. This function
3390 * also adds the stereo 3d modes when applicable.
3393 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len,
3394 const u8 *video_db, u8 video_len)
3396 int modes = 0, offset = 0, i, multi_present = 0, multi_len;
3397 u8 vic_len, hdmi_3d_len = 0;
3404 /* no HDMI_Video_Present */
3405 if (!(db[8] & (1 << 5)))
3408 /* Latency_Fields_Present */
3409 if (db[8] & (1 << 7))
3412 /* I_Latency_Fields_Present */
3413 if (db[8] & (1 << 6))
3416 /* the declared length is not long enough for the 2 first bytes
3417 * of additional video format capabilities */
3418 if (len < (8 + offset + 2))
3423 if (db[8 + offset] & (1 << 7)) {
3424 modes += add_hdmi_mandatory_stereo_modes(connector);
3426 /* 3D_Multi_present */
3427 multi_present = (db[8 + offset] & 0x60) >> 5;
3431 vic_len = db[8 + offset] >> 5;
3432 hdmi_3d_len = db[8 + offset] & 0x1f;
3434 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) {
3437 vic = db[9 + offset + i];
3438 modes += add_hdmi_mode(connector, vic);
3440 offset += 1 + vic_len;
3442 if (multi_present == 1)
3444 else if (multi_present == 2)
3449 if (len < (8 + offset + hdmi_3d_len - 1))
3452 if (hdmi_3d_len < multi_len)
3455 if (multi_present == 1 || multi_present == 2) {
3456 /* 3D_Structure_ALL */
3457 structure_all = (db[8 + offset] << 8) | db[9 + offset];
3459 /* check if 3D_MASK is present */
3460 if (multi_present == 2)
3461 mask = (db[10 + offset] << 8) | db[11 + offset];
3465 for (i = 0; i < 16; i++) {
3466 if (mask & (1 << i))
3467 modes += add_3d_struct_modes(connector,
3474 offset += multi_len;
3476 for (i = 0; i < (hdmi_3d_len - multi_len); i++) {
3478 struct drm_display_mode *newmode = NULL;
3479 unsigned int newflag = 0;
3480 bool detail_present;
3482 detail_present = ((db[8 + offset + i] & 0x0f) > 7);
3484 if (detail_present && (i + 1 == hdmi_3d_len - multi_len))
3487 /* 2D_VIC_order_X */
3488 vic_index = db[8 + offset + i] >> 4;
3490 /* 3D_Structure_X */
3491 switch (db[8 + offset + i] & 0x0f) {
3493 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING;
3496 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM;
3500 if ((db[9 + offset + i] >> 4) == 1)
3501 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF;
3506 newmode = drm_display_mode_from_vic_index(connector,
3512 newmode->flags |= newflag;
3513 drm_mode_probed_add(connector, newmode);
3527 cea_db_payload_len(const u8 *db)
3529 return db[0] & 0x1f;
3533 cea_db_extended_tag(const u8 *db)
3539 cea_db_tag(const u8 *db)
3545 cea_revision(const u8 *cea)
3551 cea_db_offsets(const u8 *cea, int *start, int *end)
3553 /* Data block offset in CEA extension block */
3558 if (*end < 4 || *end > 127)
3563 static bool cea_db_is_hdmi_vsdb(const u8 *db)
3567 if (cea_db_tag(db) != VENDOR_BLOCK)
3570 if (cea_db_payload_len(db) < 5)
3573 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16);
3575 return hdmi_id == HDMI_IEEE_OUI;
3578 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db)
3582 if (cea_db_tag(db) != VENDOR_BLOCK)
3585 if (cea_db_payload_len(db) < 7)
3588 oui = db[3] << 16 | db[2] << 8 | db[1];
3590 return oui == HDMI_FORUM_IEEE_OUI;
3593 static bool cea_db_is_y420cmdb(const u8 *db)
3595 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3598 if (!cea_db_payload_len(db))
3601 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB)
3607 static bool cea_db_is_y420vdb(const u8 *db)
3609 if (cea_db_tag(db) != USE_EXTENDED_TAG)
3612 if (!cea_db_payload_len(db))
3615 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420)
3621 #define for_each_cea_db(cea, i, start, end) \
3622 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1)
3624 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector,
3627 struct drm_display_info *info = &connector->display_info;
3628 struct drm_hdmi_info *hdmi = &info->hdmi;
3629 u8 map_len = cea_db_payload_len(db) - 1;
3634 /* All CEA modes support ycbcr420 sampling also.*/
3635 hdmi->y420_cmdb_map = U64_MAX;
3636 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3641 * This map indicates which of the existing CEA block modes
3642 * from VDB can support YCBCR420 output too. So if bit=0 is
3643 * set, first mode from VDB can support YCBCR420 output too.
3644 * We will parse and keep this map, before parsing VDB itself
3645 * to avoid going through the same block again and again.
3647 * Spec is not clear about max possible size of this block.
3648 * Clamping max bitmap block size at 8 bytes. Every byte can
3649 * address 8 CEA modes, in this way this map can address
3650 * 8*8 = first 64 SVDs.
3652 if (WARN_ON_ONCE(map_len > 8))
3655 for (count = 0; count < map_len; count++)
3656 map |= (u64)db[2 + count] << (8 * count);
3659 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420;
3661 hdmi->y420_cmdb_map = map;
3665 add_cea_modes(struct drm_connector *connector, struct edid *edid)
3667 const u8 *cea = drm_find_cea_extension(edid);
3668 const u8 *db, *hdmi = NULL, *video = NULL;
3669 u8 dbl, hdmi_len, video_len = 0;
3672 if (cea && cea_revision(cea) >= 3) {
3675 if (cea_db_offsets(cea, &start, &end))
3678 for_each_cea_db(cea, i, start, end) {
3680 dbl = cea_db_payload_len(db);
3682 if (cea_db_tag(db) == VIDEO_BLOCK) {
3685 modes += do_cea_modes(connector, video, dbl);
3686 } else if (cea_db_is_hdmi_vsdb(db)) {
3689 } else if (cea_db_is_y420vdb(db)) {
3690 const u8 *vdb420 = &db[2];
3692 /* Add 4:2:0(only) modes present in EDID */
3693 modes += do_y420vdb_modes(connector,
3701 * We parse the HDMI VSDB after having added the cea modes as we will
3702 * be patching their flags when the sink supports stereo 3D.
3705 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video,
3711 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode)
3713 const struct drm_display_mode *cea_mode;
3714 int clock1, clock2, clock;
3719 * allow 5kHz clock difference either way to account for
3720 * the 10kHz clock resolution limit of detailed timings.
3722 vic = drm_match_cea_mode_clock_tolerance(mode, 5);
3723 if (drm_valid_cea_vic(vic)) {
3725 cea_mode = &edid_cea_modes[vic];
3726 clock1 = cea_mode->clock;
3727 clock2 = cea_mode_alternate_clock(cea_mode);
3729 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5);
3730 if (drm_valid_hdmi_vic(vic)) {
3732 cea_mode = &edid_4k_modes[vic];
3733 clock1 = cea_mode->clock;
3734 clock2 = hdmi_mode_alternate_clock(cea_mode);
3740 /* pick whichever is closest */
3741 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
3746 if (mode->clock == clock)
3749 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
3750 type, vic, mode->clock, clock);
3751 mode->clock = clock;
3755 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db)
3757 u8 len = cea_db_payload_len(db);
3760 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */
3762 connector->latency_present[0] = db[8] >> 7;
3763 connector->latency_present[1] = (db[8] >> 6) & 1;
3766 connector->video_latency[0] = db[9];
3768 connector->audio_latency[0] = db[10];
3770 connector->video_latency[1] = db[11];
3772 connector->audio_latency[1] = db[12];
3774 DRM_DEBUG_KMS("HDMI: latency present %d %d, "
3775 "video latency %d %d, "
3776 "audio latency %d %d\n",
3777 connector->latency_present[0],
3778 connector->latency_present[1],
3779 connector->video_latency[0],
3780 connector->video_latency[1],
3781 connector->audio_latency[0],
3782 connector->audio_latency[1]);
3786 monitor_name(struct detailed_timing *t, void *data)
3788 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME)
3789 *(u8 **)data = t->data.other_data.data.str.str;
3792 static int get_monitor_name(struct edid *edid, char name[13])
3794 char *edid_name = NULL;
3800 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name);
3801 for (mnl = 0; edid_name && mnl < 13; mnl++) {
3802 if (edid_name[mnl] == 0x0a)
3805 name[mnl] = edid_name[mnl];
3812 * drm_edid_get_monitor_name - fetch the monitor name from the edid
3813 * @edid: monitor EDID information
3814 * @name: pointer to a character array to hold the name of the monitor
3815 * @bufsize: The size of the name buffer (should be at least 14 chars.)
3818 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize)
3826 name_length = min(get_monitor_name(edid, buf), bufsize - 1);
3827 memcpy(name, buf, name_length);
3828 name[name_length] = '\0';
3830 EXPORT_SYMBOL(drm_edid_get_monitor_name);
3833 * drm_edid_to_eld - build ELD from EDID
3834 * @connector: connector corresponding to the HDMI/DP sink
3835 * @edid: EDID to parse
3837 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The
3838 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in.
3840 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
3842 uint8_t *eld = connector->eld;
3845 int total_sad_count = 0;
3849 memset(eld, 0, sizeof(connector->eld));
3851 connector->latency_present[0] = false;
3852 connector->latency_present[1] = false;
3853 connector->video_latency[0] = 0;
3854 connector->audio_latency[0] = 0;
3855 connector->video_latency[1] = 0;
3856 connector->audio_latency[1] = 0;
3861 cea = drm_find_cea_extension(edid);
3863 DRM_DEBUG_KMS("ELD: no CEA Extension found\n");
3867 mnl = get_monitor_name(edid, eld + 20);
3869 eld[4] = (cea[1] << 5) | mnl;
3870 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20);
3872 eld[0] = 2 << 3; /* ELD version: 2 */
3874 eld[16] = edid->mfg_id[0];
3875 eld[17] = edid->mfg_id[1];
3876 eld[18] = edid->prod_code[0];
3877 eld[19] = edid->prod_code[1];
3879 if (cea_revision(cea) >= 3) {
3882 if (cea_db_offsets(cea, &start, &end)) {
3887 for_each_cea_db(cea, i, start, end) {
3889 dbl = cea_db_payload_len(db);
3891 switch (cea_db_tag(db)) {
3895 /* Audio Data Block, contains SADs */
3896 sad_count = min(dbl / 3, 15 - total_sad_count);
3898 memcpy(eld + 20 + mnl + total_sad_count * 3,
3899 &db[1], sad_count * 3);
3900 total_sad_count += sad_count;
3903 /* Speaker Allocation Data Block */
3908 /* HDMI Vendor-Specific Data Block */
3909 if (cea_db_is_hdmi_vsdb(db))
3910 drm_parse_hdmi_vsdb_audio(connector, db);
3917 eld[5] |= total_sad_count << 4;
3919 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
3920 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3921 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP;
3923 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI;
3925 eld[DRM_ELD_BASELINE_ELD_LEN] =
3926 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
3928 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
3929 drm_eld_size(eld), total_sad_count);
3931 EXPORT_SYMBOL(drm_edid_to_eld);
3934 * drm_edid_to_sad - extracts SADs from EDID
3935 * @edid: EDID to parse
3936 * @sads: pointer that will be set to the extracted SADs
3938 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
3940 * Note: The returned pointer needs to be freed using kfree().
3942 * Return: The number of found SADs or negative number on error.
3944 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
3947 int i, start, end, dbl;
3950 cea = drm_find_cea_extension(edid);
3952 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
3956 if (cea_revision(cea) < 3) {
3957 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
3961 if (cea_db_offsets(cea, &start, &end)) {
3962 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
3966 for_each_cea_db(cea, i, start, end) {
3969 if (cea_db_tag(db) == AUDIO_BLOCK) {
3971 dbl = cea_db_payload_len(db);
3973 count = dbl / 3; /* SAD is 3B */
3974 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
3977 for (j = 0; j < count; j++) {
3978 u8 *sad = &db[1 + j * 3];
3980 (*sads)[j].format = (sad[0] & 0x78) >> 3;
3981 (*sads)[j].channels = sad[0] & 0x7;
3982 (*sads)[j].freq = sad[1] & 0x7F;
3983 (*sads)[j].byte2 = sad[2];
3991 EXPORT_SYMBOL(drm_edid_to_sad);
3994 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID
3995 * @edid: EDID to parse
3996 * @sadb: pointer to the speaker block
3998 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it.
4000 * Note: The returned pointer needs to be freed using kfree().
4002 * Return: The number of found Speaker Allocation Blocks or negative number on
4005 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb)
4008 int i, start, end, dbl;
4011 cea = drm_find_cea_extension(edid);
4013 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
4017 if (cea_revision(cea) < 3) {
4018 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
4022 if (cea_db_offsets(cea, &start, &end)) {
4023 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
4027 for_each_cea_db(cea, i, start, end) {
4028 const u8 *db = &cea[i];
4030 if (cea_db_tag(db) == SPEAKER_BLOCK) {
4031 dbl = cea_db_payload_len(db);
4033 /* Speaker Allocation Data Block */
4035 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL);
4046 EXPORT_SYMBOL(drm_edid_to_speaker_allocation);
4049 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay
4050 * @connector: connector associated with the HDMI/DP sink
4051 * @mode: the display mode
4053 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if
4054 * the sink doesn't support audio or video.
4056 int drm_av_sync_delay(struct drm_connector *connector,
4057 const struct drm_display_mode *mode)
4059 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
4062 if (!connector->latency_present[0])
4064 if (!connector->latency_present[1])
4067 a = connector->audio_latency[i];
4068 v = connector->video_latency[i];
4071 * HDMI/DP sink doesn't support audio or video?
4073 if (a == 255 || v == 255)
4077 * Convert raw EDID values to millisecond.
4078 * Treat unknown latency as 0ms.
4081 a = min(2 * (a - 1), 500);
4083 v = min(2 * (v - 1), 500);
4085 return max(v - a, 0);
4087 EXPORT_SYMBOL(drm_av_sync_delay);
4090 * drm_detect_hdmi_monitor - detect whether monitor is HDMI
4091 * @edid: monitor EDID information
4093 * Parse the CEA extension according to CEA-861-B.
4095 * Return: True if the monitor is HDMI, false if not or unknown.
4097 bool drm_detect_hdmi_monitor(struct edid *edid)
4101 int start_offset, end_offset;
4103 edid_ext = drm_find_cea_extension(edid);
4107 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4111 * Because HDMI identifier is in Vendor Specific Block,
4112 * search it from all data blocks of CEA extension.
4114 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4115 if (cea_db_is_hdmi_vsdb(&edid_ext[i]))
4121 EXPORT_SYMBOL(drm_detect_hdmi_monitor);
4124 * drm_detect_monitor_audio - check monitor audio capability
4125 * @edid: EDID block to scan
4127 * Monitor should have CEA extension block.
4128 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic
4129 * audio' only. If there is any audio extension block and supported
4130 * audio format, assume at least 'basic audio' support, even if 'basic
4131 * audio' is not defined in EDID.
4133 * Return: True if the monitor supports audio, false otherwise.
4135 bool drm_detect_monitor_audio(struct edid *edid)
4139 bool has_audio = false;
4140 int start_offset, end_offset;
4142 edid_ext = drm_find_cea_extension(edid);
4146 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0);
4149 DRM_DEBUG_KMS("Monitor has basic audio support\n");
4153 if (cea_db_offsets(edid_ext, &start_offset, &end_offset))
4156 for_each_cea_db(edid_ext, i, start_offset, end_offset) {
4157 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) {
4159 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3)
4160 DRM_DEBUG_KMS("CEA audio format %d\n",
4161 (edid_ext[i + j] >> 3) & 0xf);
4168 EXPORT_SYMBOL(drm_detect_monitor_audio);
4171 * drm_rgb_quant_range_selectable - is RGB quantization range selectable?
4172 * @edid: EDID block to scan
4174 * Check whether the monitor reports the RGB quantization range selection
4175 * as supported. The AVI infoframe can then be used to inform the monitor
4176 * which quantization range (full or limited) is used.
4178 * Return: True if the RGB quantization range is selectable, false otherwise.
4180 bool drm_rgb_quant_range_selectable(struct edid *edid)
4185 edid_ext = drm_find_cea_extension(edid);
4189 if (cea_db_offsets(edid_ext, &start, &end))
4192 for_each_cea_db(edid_ext, i, start, end) {
4193 if (cea_db_tag(&edid_ext[i]) == USE_EXTENDED_TAG &&
4194 cea_db_payload_len(&edid_ext[i]) == 2 &&
4195 cea_db_extended_tag(&edid_ext[i]) ==
4196 EXT_VIDEO_CAPABILITY_BLOCK) {
4197 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]);
4198 return edid_ext[i + 2] & EDID_CEA_VCDB_QS;
4204 EXPORT_SYMBOL(drm_rgb_quant_range_selectable);
4207 * drm_default_rgb_quant_range - default RGB quantization range
4208 * @mode: display mode
4210 * Determine the default RGB quantization range for the mode,
4211 * as specified in CEA-861.
4213 * Return: The default RGB quantization range for the mode
4215 enum hdmi_quantization_range
4216 drm_default_rgb_quant_range(const struct drm_display_mode *mode)
4218 /* All CEA modes other than VIC 1 use limited quantization range. */
4219 return drm_match_cea_mode(mode) > 1 ?
4220 HDMI_QUANTIZATION_RANGE_LIMITED :
4221 HDMI_QUANTIZATION_RANGE_FULL;
4223 EXPORT_SYMBOL(drm_default_rgb_quant_range);
4225 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector,
4229 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
4231 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK;
4232 hdmi->y420_dc_modes = dc_mask;
4235 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector,
4238 struct drm_display_info *display = &connector->display_info;
4239 struct drm_hdmi_info *hdmi = &display->hdmi;
4241 if (hf_vsdb[6] & 0x80) {
4242 hdmi->scdc.supported = true;
4243 if (hf_vsdb[6] & 0x40)
4244 hdmi->scdc.read_request = true;
4248 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz.
4249 * And as per the spec, three factors confirm this:
4250 * * Availability of a HF-VSDB block in EDID (check)
4251 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check)
4252 * * SCDC support available (let's check)
4253 * Lets check it out.
4257 /* max clock is 5000 KHz times block value */
4258 u32 max_tmds_clock = hf_vsdb[5] * 5000;
4259 struct drm_scdc *scdc = &hdmi->scdc;
4261 if (max_tmds_clock > 340000) {
4262 display->max_tmds_clock = max_tmds_clock;
4263 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4264 display->max_tmds_clock);
4267 if (scdc->supported) {
4268 scdc->scrambling.supported = true;
4270 /* Few sinks support scrambling for cloks < 340M */
4271 if ((hf_vsdb[6] & 0x8))
4272 scdc->scrambling.low_rates = true;
4276 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb);
4279 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector,
4282 struct drm_display_info *info = &connector->display_info;
4283 unsigned int dc_bpc = 0;
4285 /* HDMI supports at least 8 bpc */
4288 if (cea_db_payload_len(hdmi) < 6)
4291 if (hdmi[6] & DRM_EDID_HDMI_DC_30) {
4293 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30;
4294 DRM_DEBUG("%s: HDMI sink does deep color 30.\n",
4298 if (hdmi[6] & DRM_EDID_HDMI_DC_36) {
4300 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36;
4301 DRM_DEBUG("%s: HDMI sink does deep color 36.\n",
4305 if (hdmi[6] & DRM_EDID_HDMI_DC_48) {
4307 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48;
4308 DRM_DEBUG("%s: HDMI sink does deep color 48.\n",
4313 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n",
4318 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n",
4319 connector->name, dc_bpc);
4323 * Deep color support mandates RGB444 support for all video
4324 * modes and forbids YCRCB422 support for all video modes per
4327 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4329 /* YCRCB444 is optional according to spec. */
4330 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) {
4331 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4332 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n",
4337 * Spec says that if any deep color mode is supported at all,
4338 * then deep color 36 bit must be supported.
4340 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) {
4341 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n",
4347 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db)
4349 struct drm_display_info *info = &connector->display_info;
4350 u8 len = cea_db_payload_len(db);
4353 info->dvi_dual = db[6] & 1;
4355 info->max_tmds_clock = db[7] * 5000;
4357 DRM_DEBUG_KMS("HDMI: DVI dual %d, "
4358 "max TMDS clock %d kHz\n",
4360 info->max_tmds_clock);
4362 drm_parse_hdmi_deep_color_info(connector, db);
4365 static void drm_parse_cea_ext(struct drm_connector *connector,
4368 struct drm_display_info *info = &connector->display_info;
4372 edid_ext = drm_find_cea_extension(edid);
4376 info->cea_rev = edid_ext[1];
4378 /* The existence of a CEA block should imply RGB support */
4379 info->color_formats = DRM_COLOR_FORMAT_RGB444;
4380 if (edid_ext[3] & EDID_CEA_YCRCB444)
4381 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4382 if (edid_ext[3] & EDID_CEA_YCRCB422)
4383 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4385 if (cea_db_offsets(edid_ext, &start, &end))
4388 for_each_cea_db(edid_ext, i, start, end) {
4389 const u8 *db = &edid_ext[i];
4391 if (cea_db_is_hdmi_vsdb(db))
4392 drm_parse_hdmi_vsdb_video(connector, db);
4393 if (cea_db_is_hdmi_forum_vsdb(db))
4394 drm_parse_hdmi_forum_vsdb(connector, db);
4395 if (cea_db_is_y420cmdb(db))
4396 drm_parse_y420cmdb_bitmap(connector, db);
4400 static void drm_add_display_info(struct drm_connector *connector,
4403 struct drm_display_info *info = &connector->display_info;
4405 info->width_mm = edid->width_cm * 10;
4406 info->height_mm = edid->height_cm * 10;
4408 /* driver figures it out in this case */
4410 info->color_formats = 0;
4412 info->max_tmds_clock = 0;
4413 info->dvi_dual = false;
4415 if (edid->revision < 3)
4418 if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
4421 drm_parse_cea_ext(connector, edid);
4424 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3?
4426 * For such displays, the DFP spec 1.0, section 3.10 "EDID support"
4427 * tells us to assume 8 bpc color depth if the EDID doesn't have
4428 * extensions which tell otherwise.
4430 if ((info->bpc == 0) && (edid->revision < 4) &&
4431 (edid->input & DRM_EDID_DIGITAL_TYPE_DVI)) {
4433 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n",
4434 connector->name, info->bpc);
4437 /* Only defined for 1.4 with digital displays */
4438 if (edid->revision < 4)
4441 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
4442 case DRM_EDID_DIGITAL_DEPTH_6:
4445 case DRM_EDID_DIGITAL_DEPTH_8:
4448 case DRM_EDID_DIGITAL_DEPTH_10:
4451 case DRM_EDID_DIGITAL_DEPTH_12:
4454 case DRM_EDID_DIGITAL_DEPTH_14:
4457 case DRM_EDID_DIGITAL_DEPTH_16:
4460 case DRM_EDID_DIGITAL_DEPTH_UNDEF:
4466 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n",
4467 connector->name, info->bpc);
4469 info->color_formats |= DRM_COLOR_FORMAT_RGB444;
4470 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444)
4471 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444;
4472 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422)
4473 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422;
4476 static int validate_displayid(u8 *displayid, int length, int idx)
4480 struct displayid_hdr *base;
4482 base = (struct displayid_hdr *)&displayid[idx];
4484 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
4485 base->rev, base->bytes, base->prod_id, base->ext_count);
4487 if (base->bytes + 5 > length - idx)
4489 for (i = idx; i <= base->bytes + 5; i++) {
4490 csum += displayid[i];
4493 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum);
4499 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev,
4500 struct displayid_detailed_timings_1 *timings)
4502 struct drm_display_mode *mode;
4503 unsigned pixel_clock = (timings->pixel_clock[0] |
4504 (timings->pixel_clock[1] << 8) |
4505 (timings->pixel_clock[2] << 16)) + 1;
4506 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1;
4507 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1;
4508 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1;
4509 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1;
4510 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1;
4511 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1;
4512 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1;
4513 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1;
4514 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1;
4515 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1;
4516 mode = drm_mode_create(dev);
4520 mode->clock = pixel_clock * 10;
4521 mode->hdisplay = hactive;
4522 mode->hsync_start = mode->hdisplay + hsync;
4523 mode->hsync_end = mode->hsync_start + hsync_width;
4524 mode->htotal = mode->hdisplay + hblank;
4526 mode->vdisplay = vactive;
4527 mode->vsync_start = mode->vdisplay + vsync;
4528 mode->vsync_end = mode->vsync_start + vsync_width;
4529 mode->vtotal = mode->vdisplay + vblank;
4532 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4533 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4534 mode->type = DRM_MODE_TYPE_DRIVER;
4536 if (timings->flags & 0x80)
4537 mode->type |= DRM_MODE_TYPE_PREFERRED;
4538 mode->vrefresh = drm_mode_vrefresh(mode);
4539 drm_mode_set_name(mode);
4544 static int add_displayid_detailed_1_modes(struct drm_connector *connector,
4545 struct displayid_block *block)
4547 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block;
4550 struct drm_display_mode *newmode;
4552 /* blocks must be multiple of 20 bytes length */
4553 if (block->num_bytes % 20)
4556 num_timings = block->num_bytes / 20;
4557 for (i = 0; i < num_timings; i++) {
4558 struct displayid_detailed_timings_1 *timings = &det->timings[i];
4560 newmode = drm_mode_displayid_detailed(connector->dev, timings);
4564 drm_mode_probed_add(connector, newmode);
4570 static int add_displayid_detailed_modes(struct drm_connector *connector,
4576 int length = EDID_LENGTH;
4577 struct displayid_block *block;
4580 displayid = drm_find_displayid_extension(edid);
4584 ret = validate_displayid(displayid, length, idx);
4588 idx += sizeof(struct displayid_hdr);
4589 while (block = (struct displayid_block *)&displayid[idx],
4590 idx + sizeof(struct displayid_block) <= length &&
4591 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
4592 block->num_bytes > 0) {
4593 idx += block->num_bytes + sizeof(struct displayid_block);
4594 switch (block->tag) {
4595 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
4596 num_modes += add_displayid_detailed_1_modes(connector, block);
4604 * drm_add_edid_modes - add modes from EDID data, if available
4605 * @connector: connector we're probing
4608 * Add the specified modes to the connector's mode list. Also fills out the
4609 * &drm_display_info structure in @connector with any information which can be
4610 * derived from the edid.
4612 * Return: The number of modes added or 0 if we couldn't find any.
4614 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid)
4622 if (!drm_edid_is_valid(edid)) {
4623 dev_warn(connector->dev->dev, "%s: EDID invalid.\n",
4628 quirks = edid_get_quirks(edid);
4631 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks.
4632 * To avoid multiple parsing of same block, lets parse that map
4633 * from sink info, before parsing CEA modes.
4635 drm_add_display_info(connector, edid);
4638 * EDID spec says modes should be preferred in this order:
4639 * - preferred detailed mode
4640 * - other detailed modes from base block
4641 * - detailed modes from extension blocks
4642 * - CVT 3-byte code modes
4643 * - standard timing codes
4644 * - established timing codes
4645 * - modes inferred from GTF or CVT range information
4647 * We get this pretty much right.
4649 * XXX order for additional mode types in extension blocks?
4651 num_modes += add_detailed_modes(connector, edid, quirks);
4652 num_modes += add_cvt_modes(connector, edid);
4653 num_modes += add_standard_modes(connector, edid);
4654 num_modes += add_established_modes(connector, edid);
4655 num_modes += add_cea_modes(connector, edid);
4656 num_modes += add_alternate_cea_modes(connector, edid);
4657 num_modes += add_displayid_detailed_modes(connector, edid);
4658 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)
4659 num_modes += add_inferred_modes(connector, edid);
4661 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
4662 edid_fixup_preferred(connector, quirks);
4664 if (quirks & EDID_QUIRK_FORCE_6BPC)
4665 connector->display_info.bpc = 6;
4667 if (quirks & EDID_QUIRK_FORCE_8BPC)
4668 connector->display_info.bpc = 8;
4670 if (quirks & EDID_QUIRK_FORCE_10BPC)
4671 connector->display_info.bpc = 10;
4673 if (quirks & EDID_QUIRK_FORCE_12BPC)
4674 connector->display_info.bpc = 12;
4678 EXPORT_SYMBOL(drm_add_edid_modes);
4681 * drm_add_modes_noedid - add modes for the connectors without EDID
4682 * @connector: connector we're probing
4683 * @hdisplay: the horizontal display limit
4684 * @vdisplay: the vertical display limit
4686 * Add the specified modes to the connector's mode list. Only when the
4687 * hdisplay/vdisplay is not beyond the given limit, it will be added.
4689 * Return: The number of modes added or 0 if we couldn't find any.
4691 int drm_add_modes_noedid(struct drm_connector *connector,
4692 int hdisplay, int vdisplay)
4694 int i, count, num_modes = 0;
4695 struct drm_display_mode *mode;
4696 struct drm_device *dev = connector->dev;
4698 count = ARRAY_SIZE(drm_dmt_modes);
4704 for (i = 0; i < count; i++) {
4705 const struct drm_display_mode *ptr = &drm_dmt_modes[i];
4706 if (hdisplay && vdisplay) {
4708 * Only when two are valid, they will be used to check
4709 * whether the mode should be added to the mode list of
4712 if (ptr->hdisplay > hdisplay ||
4713 ptr->vdisplay > vdisplay)
4716 if (drm_mode_vrefresh(ptr) > 61)
4718 mode = drm_mode_duplicate(dev, ptr);
4720 drm_mode_probed_add(connector, mode);
4726 EXPORT_SYMBOL(drm_add_modes_noedid);
4729 * drm_set_preferred_mode - Sets the preferred mode of a connector
4730 * @connector: connector whose mode list should be processed
4731 * @hpref: horizontal resolution of preferred mode
4732 * @vpref: vertical resolution of preferred mode
4734 * Marks a mode as preferred if it matches the resolution specified by @hpref
4737 void drm_set_preferred_mode(struct drm_connector *connector,
4738 int hpref, int vpref)
4740 struct drm_display_mode *mode;
4742 list_for_each_entry(mode, &connector->probed_modes, head) {
4743 if (mode->hdisplay == hpref &&
4744 mode->vdisplay == vpref)
4745 mode->type |= DRM_MODE_TYPE_PREFERRED;
4748 EXPORT_SYMBOL(drm_set_preferred_mode);
4751 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with
4752 * data from a DRM display mode
4753 * @frame: HDMI AVI infoframe
4754 * @mode: DRM display mode
4755 * @is_hdmi2_sink: Sink is HDMI 2.0 compliant
4757 * Return: 0 on success or a negative error code on failure.
4760 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame,
4761 const struct drm_display_mode *mode,
4766 if (!frame || !mode)
4769 err = hdmi_avi_infoframe_init(frame);
4773 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
4774 frame->pixel_repeat = 1;
4776 frame->video_code = drm_match_cea_mode(mode);
4779 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but
4780 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we
4781 * have to make sure we dont break HDMI 1.4 sinks.
4783 if (!is_hdmi2_sink && frame->video_code > 64)
4784 frame->video_code = 0;
4787 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes
4788 * we should send its VIC in vendor infoframes, else send the
4789 * VIC in AVI infoframes. Lets check if this mode is present in
4790 * HDMI 1.4b 4K modes
4792 if (frame->video_code) {
4793 u8 vendor_if_vic = drm_match_hdmi_mode(mode);
4794 bool is_s3d = mode->flags & DRM_MODE_FLAG_3D_MASK;
4796 if (drm_valid_hdmi_vic(vendor_if_vic) && !is_s3d)
4797 frame->video_code = 0;
4800 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE;
4803 * Populate picture aspect ratio from either
4804 * user input (if specified) or from the CEA mode list.
4806 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 ||
4807 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9)
4808 frame->picture_aspect = mode->picture_aspect_ratio;
4809 else if (frame->video_code > 0)
4810 frame->picture_aspect = drm_get_cea_aspect_ratio(
4813 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE;
4814 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
4818 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode);
4821 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe
4822 * quantization range information
4823 * @frame: HDMI AVI infoframe
4824 * @mode: DRM display mode
4825 * @rgb_quant_range: RGB quantization range (Q)
4826 * @rgb_quant_range_selectable: Sink support selectable RGB quantization range (QS)
4829 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
4830 const struct drm_display_mode *mode,
4831 enum hdmi_quantization_range rgb_quant_range,
4832 bool rgb_quant_range_selectable,
4837 * "A Source shall not send a non-zero Q value that does not correspond
4838 * to the default RGB Quantization Range for the transmitted Picture
4839 * unless the Sink indicates support for the Q bit in a Video
4840 * Capabilities Data Block."
4842 * HDMI 2.0 recommends sending non-zero Q when it does match the
4843 * default RGB quantization range for the mode, even when QS=0.
4845 if (rgb_quant_range_selectable ||
4846 rgb_quant_range == drm_default_rgb_quant_range(mode))
4847 frame->quantization_range = rgb_quant_range;
4849 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
4853 * "When transmitting any RGB colorimetry, the Source should set the
4854 * YQ-field to match the RGB Quantization Range being transmitted
4855 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB,
4856 * set YQ=1) and the Sink shall ignore the YQ-field."
4858 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused
4859 * by non-zero YQ when receiving RGB. There doesn't seem to be any
4860 * good way to tell which version of CEA-861 the sink supports, so
4861 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based
4864 if (!is_hdmi2_sink ||
4865 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED)
4866 frame->ycc_quantization_range =
4867 HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
4869 frame->ycc_quantization_range =
4870 HDMI_YCC_QUANTIZATION_RANGE_FULL;
4872 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range);
4874 static enum hdmi_3d_structure
4875 s3d_structure_from_display_mode(const struct drm_display_mode *mode)
4877 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK;
4880 case DRM_MODE_FLAG_3D_FRAME_PACKING:
4881 return HDMI_3D_STRUCTURE_FRAME_PACKING;
4882 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE:
4883 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE;
4884 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE:
4885 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE;
4886 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL:
4887 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL;
4888 case DRM_MODE_FLAG_3D_L_DEPTH:
4889 return HDMI_3D_STRUCTURE_L_DEPTH;
4890 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH:
4891 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH;
4892 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM:
4893 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM;
4894 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF:
4895 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF;
4897 return HDMI_3D_STRUCTURE_INVALID;
4902 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with
4903 * data from a DRM display mode
4904 * @frame: HDMI vendor infoframe
4905 * @mode: DRM display mode
4907 * Note that there's is a need to send HDMI vendor infoframes only when using a
4908 * 4k or stereoscopic 3D mode. So when giving any other mode as input this
4909 * function will return -EINVAL, error that can be safely ignored.
4911 * Return: 0 on success or a negative error code on failure.
4914 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame,
4915 const struct drm_display_mode *mode)
4921 if (!frame || !mode)
4924 vic = drm_match_hdmi_mode(mode);
4925 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK;
4927 if (!vic && !s3d_flags)
4930 if (vic && s3d_flags)
4933 err = hdmi_vendor_infoframe_init(frame);
4940 frame->s3d_struct = s3d_structure_from_display_mode(mode);
4944 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode);
4946 static int drm_parse_tiled_block(struct drm_connector *connector,
4947 struct displayid_block *block)
4949 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block;
4951 u8 tile_v_loc, tile_h_loc;
4952 u8 num_v_tile, num_h_tile;
4953 struct drm_tile_group *tg;
4955 w = tile->tile_size[0] | tile->tile_size[1] << 8;
4956 h = tile->tile_size[2] | tile->tile_size[3] << 8;
4958 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30);
4959 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30);
4960 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4);
4961 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4);
4963 connector->has_tile = true;
4964 if (tile->tile_cap & 0x80)
4965 connector->tile_is_single_monitor = true;
4967 connector->num_h_tile = num_h_tile + 1;
4968 connector->num_v_tile = num_v_tile + 1;
4969 connector->tile_h_loc = tile_h_loc;
4970 connector->tile_v_loc = tile_v_loc;
4971 connector->tile_h_size = w + 1;
4972 connector->tile_v_size = h + 1;
4974 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap);
4975 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1);
4976 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n",
4977 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc);
4978 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]);
4980 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id);
4982 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id);
4987 if (connector->tile_group != tg) {
4988 /* if we haven't got a pointer,
4989 take the reference, drop ref to old tile group */
4990 if (connector->tile_group) {
4991 drm_mode_put_tile_group(connector->dev, connector->tile_group);
4993 connector->tile_group = tg;
4995 /* if same tile group, then release the ref we just took. */
4996 drm_mode_put_tile_group(connector->dev, tg);
5000 static int drm_parse_display_id(struct drm_connector *connector,
5001 u8 *displayid, int length,
5002 bool is_edid_extension)
5004 /* if this is an EDID extension the first byte will be 0x70 */
5006 struct displayid_block *block;
5009 if (is_edid_extension)
5012 ret = validate_displayid(displayid, length, idx);
5016 idx += sizeof(struct displayid_hdr);
5017 while (block = (struct displayid_block *)&displayid[idx],
5018 idx + sizeof(struct displayid_block) <= length &&
5019 idx + sizeof(struct displayid_block) + block->num_bytes <= length &&
5020 block->num_bytes > 0) {
5021 idx += block->num_bytes + sizeof(struct displayid_block);
5022 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n",
5023 block->tag, block->rev, block->num_bytes);
5025 switch (block->tag) {
5026 case DATA_BLOCK_TILED_DISPLAY:
5027 ret = drm_parse_tiled_block(connector, block);
5031 case DATA_BLOCK_TYPE_1_DETAILED_TIMING:
5032 /* handled in mode gathering code. */
5035 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag);
5042 static void drm_get_displayid(struct drm_connector *connector,
5045 void *displayid = NULL;
5047 connector->has_tile = false;
5048 displayid = drm_find_displayid_extension(edid);
5050 /* drop reference to any tile group we had */
5054 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true);
5057 if (!connector->has_tile)
5061 if (connector->tile_group) {
5062 drm_mode_put_tile_group(connector->dev, connector->tile_group);
5063 connector->tile_group = NULL;
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