drivers/gpu/drm/bridge/ti-sn65dsi86.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
   5  */
   6
   7 #include <linux/atomic.h>
   8 #include <linux/auxiliary_bus.h>
   9 #include <linux/bitfield.h>
  10 #include <linux/bits.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/i2c.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/module.h>
  18 #include <linux/of_graph.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/pwm.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <asm/unaligned.h>
  25
  26 #include <drm/display/drm_dp_aux_bus.h>
  27 #include <drm/display/drm_dp_helper.h>
  28 #include <drm/drm_atomic.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_bridge.h>
  31 #include <drm/drm_bridge_connector.h>
  32 #include <drm/drm_mipi_dsi.h>
  33 #include <drm/drm_of.h>
  34 #include <drm/drm_panel.h>
  35 #include <drm/drm_print.h>
  36 #include <drm/drm_probe_helper.h>
  37
  38 #define SN_DEVICE_REV_REG                       0x08
  39 #define SN_DPPLL_SRC_REG                        0x0A
  40 #define  DPPLL_CLK_SRC_DSICLK                   BIT(0)
  41 #define  REFCLK_FREQ_MASK                       GENMASK(3, 1)
  42 #define  REFCLK_FREQ(x)                         ((x) << 1)
  43 #define  DPPLL_SRC_DP_PLL_LOCK                  BIT(7)
  44 #define SN_PLL_ENABLE_REG                       0x0D
  45 #define SN_DSI_LANES_REG                        0x10
  46 #define  CHA_DSI_LANES_MASK                     GENMASK(4, 3)
  47 #define  CHA_DSI_LANES(x)                       ((x) << 3)
  48 #define SN_DSIA_CLK_FREQ_REG                    0x12
  49 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG       0x20
  50 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG    0x24
  51 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG        0x2C
  52 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG       0x2D
  53 #define  CHA_HSYNC_POLARITY                     BIT(7)
  54 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG        0x30
  55 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG       0x31
  56 #define  CHA_VSYNC_POLARITY                     BIT(7)
  57 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG        0x34
  58 #define SN_CHA_VERTICAL_BACK_PORCH_REG          0x36
  59 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG       0x38
  60 #define SN_CHA_VERTICAL_FRONT_PORCH_REG         0x3A
  61 #define SN_LN_ASSIGN_REG                        0x59
  62 #define  LN_ASSIGN_WIDTH                        2
  63 #define SN_ENH_FRAME_REG                        0x5A
  64 #define  VSTREAM_ENABLE                         BIT(3)
  65 #define  LN_POLRS_OFFSET                        4
  66 #define  LN_POLRS_MASK                          0xf0
  67 #define SN_DATA_FORMAT_REG                      0x5B
  68 #define  BPP_18_RGB                             BIT(0)
  69 #define SN_HPD_DISABLE_REG                      0x5C
  70 #define  HPD_DISABLE                            BIT(0)
  71 #define SN_GPIO_IO_REG                          0x5E
  72 #define  SN_GPIO_INPUT_SHIFT                    4
  73 #define  SN_GPIO_OUTPUT_SHIFT                   0
  74 #define SN_GPIO_CTRL_REG                        0x5F
  75 #define  SN_GPIO_MUX_INPUT                      0
  76 #define  SN_GPIO_MUX_OUTPUT                     1
  77 #define  SN_GPIO_MUX_SPECIAL                    2
  78 #define  SN_GPIO_MUX_MASK                       0x3
  79 #define SN_AUX_WDATA_REG(x)                     (0x64 + (x))
  80 #define SN_AUX_ADDR_19_16_REG                   0x74
  81 #define SN_AUX_ADDR_15_8_REG                    0x75
  82 #define SN_AUX_ADDR_7_0_REG                     0x76
  83 #define SN_AUX_ADDR_MASK                        GENMASK(19, 0)
  84 #define SN_AUX_LENGTH_REG                       0x77
  85 #define SN_AUX_CMD_REG                          0x78
  86 #define  AUX_CMD_SEND                           BIT(0)
  87 #define  AUX_CMD_REQ(x)                         ((x) << 4)
  88 #define SN_AUX_RDATA_REG(x)                     (0x79 + (x))
  89 #define SN_SSC_CONFIG_REG                       0x93
  90 #define  DP_NUM_LANES_MASK                      GENMASK(5, 4)
  91 #define  DP_NUM_LANES(x)                        ((x) << 4)
  92 #define SN_DATARATE_CONFIG_REG                  0x94
  93 #define  DP_DATARATE_MASK                       GENMASK(7, 5)
  94 #define  DP_DATARATE(x)                         ((x) << 5)
  95 #define SN_ML_TX_MODE_REG                       0x96
  96 #define  ML_TX_MAIN_LINK_OFF                    0
  97 #define  ML_TX_NORMAL_MODE                      BIT(0)
  98 #define SN_PWM_PRE_DIV_REG                      0xA0
  99 #define SN_BACKLIGHT_SCALE_REG                  0xA1
 100 #define  BACKLIGHT_SCALE_MAX                    0xFFFF
 101 #define SN_BACKLIGHT_REG                        0xA3
 102 #define SN_PWM_EN_INV_REG                       0xA5
 103 #define  SN_PWM_INV_MASK                        BIT(0)
 104 #define  SN_PWM_EN_MASK                         BIT(1)
 105 #define SN_AUX_CMD_STATUS_REG                   0xF4
 106 #define  AUX_IRQ_STATUS_AUX_RPLY_TOUT           BIT(3)
 107 #define  AUX_IRQ_STATUS_AUX_SHORT               BIT(5)
 108 #define  AUX_IRQ_STATUS_NAT_I2C_FAIL            BIT(6)
 109
 110 #define MIN_DSI_CLK_FREQ_MHZ    40
 111
 112 /* fudge factor required to account for 8b/10b encoding */
 113 #define DP_CLK_FUDGE_NUM        10
 114 #define DP_CLK_FUDGE_DEN        8
 115
 116 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
 117 #define SN_AUX_MAX_PAYLOAD_BYTES        16
 118
 119 #define SN_REGULATOR_SUPPLY_NUM         4
 120
 121 #define SN_MAX_DP_LANES                 4
 122 #define SN_NUM_GPIOS                    4
 123 #define SN_GPIO_PHYSICAL_OFFSET         1
 124
 125 #define SN_LINK_TRAINING_TRIES          10
 126
 127 #define SN_PWM_GPIO_IDX                 3 /* 4th GPIO */
 128
 129 /**
 130  * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
 131  * @bridge_aux:   AUX-bus sub device for MIPI-to-eDP bridge functionality.
 132  * @gpio_aux:     AUX-bus sub device for GPIO controller functionality.
 133  * @aux_aux:      AUX-bus sub device for eDP AUX channel functionality.
 134  * @pwm_aux:      AUX-bus sub device for PWM controller functionality.
 135  *
 136  * @dev:          Pointer to the top level (i2c) device.
 137  * @regmap:       Regmap for accessing i2c.
 138  * @aux:          Our aux channel.
 139  * @bridge:       Our bridge.
 140  * @connector:    Our connector.
 141  * @host_node:    Remote DSI node.
 142  * @dsi:          Our MIPI DSI source.
 143  * @refclk:       Our reference clock.
 144  * @next_bridge:  The bridge on the eDP side.
 145  * @enable_gpio:  The GPIO we toggle to enable the bridge.
 146  * @supplies:     Data for bulk enabling/disabling our regulators.
 147  * @dp_lanes:     Count of dp_lanes we're using.
 148  * @ln_assign:    Value to program to the LN_ASSIGN register.
 149  * @ln_polrs:     Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
 150  * @comms_enabled: If true then communication over the aux channel is enabled.
 151  * @comms_mutex:   Protects modification of comms_enabled.
 152  *
 153  * @gchip:        If we expose our GPIOs, this is used.
 154  * @gchip_output: A cache of whether we've set GPIOs to output.  This
 155  *                serves double-duty of keeping track of the direction and
 156  *                also keeping track of whether we've incremented the
 157  *                pm_runtime reference count for this pin, which we do
 158  *                whenever a pin is configured as an output.  This is a
 159  *                bitmap so we can do atomic ops on it without an extra
 160  *                lock so concurrent users of our 4 GPIOs don't stomp on
 161  *                each other's read-modify-write.
 162  *
 163  * @pchip:        pwm_chip if the PWM is exposed.
 164  * @pwm_enabled:  Used to track if the PWM signal is currently enabled.
 165  * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
 166  * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
 167  */
 168 struct ti_sn65dsi86 {
 169         struct auxiliary_device         bridge_aux;
 170         struct auxiliary_device         gpio_aux;
 171         struct auxiliary_device         aux_aux;
 172         struct auxiliary_device         pwm_aux;
 173
 174         struct device                   *dev;
 175         struct regmap                   *regmap;
 176         struct drm_dp_aux               aux;
 177         struct drm_bridge               bridge;
 178         struct drm_connector            *connector;
 179         struct device_node              *host_node;
 180         struct mipi_dsi_device          *dsi;
 181         struct clk                      *refclk;
 182         struct drm_bridge               *next_bridge;
 183         struct gpio_desc                *enable_gpio;
 184         struct regulator_bulk_data      supplies[SN_REGULATOR_SUPPLY_NUM];
 185         int                             dp_lanes;
 186         u8                              ln_assign;
 187         u8                              ln_polrs;
 188         bool                            comms_enabled;
 189         struct mutex                    comms_mutex;
 190
 191 #if defined(CONFIG_OF_GPIO)
 192         struct gpio_chip                gchip;
 193         DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
 194 #endif
 195 #if defined(CONFIG_PWM)
 196         struct pwm_chip                 pchip;
 197         bool                            pwm_enabled;
 198         atomic_t                        pwm_pin_busy;
 199 #endif
 200         unsigned int                    pwm_refclk_freq;
 201 };
 202
 203 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
 204         { .range_min = 0, .range_max = 0xFF },
 205 };
 206
 207 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
 208         .yes_ranges = ti_sn65dsi86_volatile_ranges,
 209         .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
 210 };
 211
 212 static const struct regmap_config ti_sn65dsi86_regmap_config = {
 213         .reg_bits = 8,
 214         .val_bits = 8,
 215         .volatile_table = &ti_sn_bridge_volatile_table,
 216         .cache_type = REGCACHE_NONE,
 217         .max_register = 0xFF,
 218 };
 219
 220 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
 221                                                 unsigned int reg, u16 *val)
 222 {
 223         u8 buf[2];
 224         int ret;
 225
 226         ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
 227         if (ret)
 228                 return ret;
 229
 230         *val = buf[0] | (buf[1] << 8);
 231
 232         return 0;
 233 }
 234
 235 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
 236                                    unsigned int reg, u16 val)
 237 {
 238         u8 buf[2] = { val & 0xff, val >> 8 };
 239
 240         regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
 241 }
 242
 243 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
 244 {
 245         u32 bit_rate_khz, clk_freq_khz;
 246         struct drm_display_mode *mode =
 247                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 248
 249         bit_rate_khz = mode->clock *
 250                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 251         clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
 252
 253         return clk_freq_khz;
 254 }
 255
 256 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
 257 static const u32 ti_sn_bridge_refclk_lut[] = {
 258         12000000,
 259         19200000,
 260         26000000,
 261         27000000,
 262         38400000,
 263 };
 264
 265 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
 266 static const u32 ti_sn_bridge_dsiclk_lut[] = {
 267         468000000,
 268         384000000,
 269         416000000,
 270         486000000,
 271         460800000,
 272 };
 273
 274 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
 275 {
 276         int i;
 277         u32 refclk_rate;
 278         const u32 *refclk_lut;
 279         size_t refclk_lut_size;
 280
 281         if (pdata->refclk) {
 282                 refclk_rate = clk_get_rate(pdata->refclk);
 283                 refclk_lut = ti_sn_bridge_refclk_lut;
 284                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
 285                 clk_prepare_enable(pdata->refclk);
 286         } else {
 287                 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
 288                 refclk_lut = ti_sn_bridge_dsiclk_lut;
 289                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
 290         }
 291
 292         /* for i equals to refclk_lut_size means default frequency */
 293         for (i = 0; i < refclk_lut_size; i++)
 294                 if (refclk_lut[i] == refclk_rate)
 295                         break;
 296
 297         regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
 298                            REFCLK_FREQ(i));
 299
 300         /*
 301          * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
 302          * regardless of its actual sourcing.
 303          */
 304         pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
 305 }
 306
 307 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
 308 {
 309         mutex_lock(&pdata->comms_mutex);
 310
 311         /* configure bridge ref_clk */
 312         ti_sn_bridge_set_refclk_freq(pdata);
 313
 314         /*
 315          * HPD on this bridge chip is a bit useless.  This is an eDP bridge
 316          * so the HPD is an internal signal that's only there to signal that
 317          * the panel is done powering up.  ...but the bridge chip debounces
 318          * this signal by between 100 ms and 400 ms (depending on process,
 319          * voltage, and temperate--I measured it at about 200 ms).  One
 320          * particular panel asserted HPD 84 ms after it was powered on meaning
 321          * that we saw HPD 284 ms after power on.  ...but the same panel said
 322          * that instead of looking at HPD you could just hardcode a delay of
 323          * 200 ms.  We'll assume that the panel driver will have the hardcoded
 324          * delay in its prepare and always disable HPD.
 325          *
 326          * If HPD somehow makes sense on some future panel we'll have to
 327          * change this to be conditional on someone specifying that HPD should
 328          * be used.
 329          */
 330         regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
 331                            HPD_DISABLE);
 332
 333         pdata->comms_enabled = true;
 334
 335         mutex_unlock(&pdata->comms_mutex);
 336 }
 337
 338 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
 339 {
 340         mutex_lock(&pdata->comms_mutex);
 341
 342         pdata->comms_enabled = false;
 343         clk_disable_unprepare(pdata->refclk);
 344
 345         mutex_unlock(&pdata->comms_mutex);
 346 }
 347
 348 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
 349 {
 350         struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
 351         int ret;
 352
 353         ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 354         if (ret) {
 355                 DRM_ERROR("failed to enable supplies %d\n", ret);
 356                 return ret;
 357         }
 358
 359         /* td2: min 100 us after regulators before enabling the GPIO */
 360         usleep_range(100, 110);
 361
 362         gpiod_set_value(pdata->enable_gpio, 1);
 363
 364         /*
 365          * If we have a reference clock we can enable communication w/ the
 366          * panel (including the aux channel) w/out any need for an input clock
 367          * so we can do it in resume which lets us read the EDID before
 368          * pre_enable(). Without a reference clock we need the MIPI reference
 369          * clock so reading early doesn't work.
 370          */
 371         if (pdata->refclk)
 372                 ti_sn65dsi86_enable_comms(pdata);
 373
 374         return ret;
 375 }
 376
 377 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
 378 {
 379         struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
 380         int ret;
 381
 382         if (pdata->refclk)
 383                 ti_sn65dsi86_disable_comms(pdata);
 384
 385         gpiod_set_value(pdata->enable_gpio, 0);
 386
 387         ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 388         if (ret)
 389                 DRM_ERROR("failed to disable supplies %d\n", ret);
 390
 391         return ret;
 392 }
 393
 394 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
 395         SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
 396         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 397                                 pm_runtime_force_resume)
 398 };
 399
 400 static int status_show(struct seq_file *s, void *data)
 401 {
 402         struct ti_sn65dsi86 *pdata = s->private;
 403         unsigned int reg, val;
 404
 405         seq_puts(s, "STATUS REGISTERS:\n");
 406
 407         pm_runtime_get_sync(pdata->dev);
 408
 409         /* IRQ Status Registers, see Table 31 in datasheet */
 410         for (reg = 0xf0; reg <= 0xf8; reg++) {
 411                 regmap_read(pdata->regmap, reg, &val);
 412                 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
 413         }
 414
 415         pm_runtime_put_autosuspend(pdata->dev);
 416
 417         return 0;
 418 }
 419
 420 DEFINE_SHOW_ATTRIBUTE(status);
 421
 422 static void ti_sn65dsi86_debugfs_remove(void *data)
 423 {
 424         debugfs_remove_recursive(data);
 425 }
 426
 427 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata)
 428 {
 429         struct device *dev = pdata->dev;
 430         struct dentry *debugfs;
 431         int ret;
 432
 433         debugfs = debugfs_create_dir(dev_name(dev), NULL);
 434
 435         /*
 436          * We might get an error back if debugfs wasn't enabled in the kernel
 437          * so let's just silently return upon failure.
 438          */
 439         if (IS_ERR_OR_NULL(debugfs))
 440                 return;
 441
 442         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs);
 443         if (ret)
 444                 return;
 445
 446         debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
 447 }
 448
 449 /* -----------------------------------------------------------------------------
 450  * Auxiliary Devices (*not* AUX)
 451  */
 452
 453 static void ti_sn65dsi86_uninit_aux(void *data)
 454 {
 455         auxiliary_device_uninit(data);
 456 }
 457
 458 static void ti_sn65dsi86_delete_aux(void *data)
 459 {
 460         auxiliary_device_delete(data);
 461 }
 462
 463 /*
 464  * AUX bus docs say that a non-NULL release is mandatory, but it makes no
 465  * sense for the model used here where all of the aux devices are allocated
 466  * in the single shared structure. We'll use this noop as a workaround.
 467  */
 468 static void ti_sn65dsi86_noop(struct device *dev) {}
 469
 470 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
 471                                        struct auxiliary_device *aux,
 472                                        const char *name)
 473 {
 474         struct device *dev = pdata->dev;
 475         int ret;
 476
 477         aux->name = name;
 478         aux->dev.parent = dev;
 479         aux->dev.release = ti_sn65dsi86_noop;
 480         device_set_of_node_from_dev(&aux->dev, dev);
 481         ret = auxiliary_device_init(aux);
 482         if (ret)
 483                 return ret;
 484         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
 485         if (ret)
 486                 return ret;
 487
 488         ret = auxiliary_device_add(aux);
 489         if (ret)
 490                 return ret;
 491         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
 492
 493         return ret;
 494 }
 495
 496 /* -----------------------------------------------------------------------------
 497  * AUX Adapter
 498  */
 499
 500 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
 501 {
 502         return container_of(aux, struct ti_sn65dsi86, aux);
 503 }
 504
 505 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
 506                                   struct drm_dp_aux_msg *msg)
 507 {
 508         struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
 509         u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
 510         u32 request_val = AUX_CMD_REQ(msg->request);
 511         u8 *buf = msg->buffer;
 512         unsigned int len = msg->size;
 513         unsigned int val;
 514         int ret;
 515         u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
 516
 517         if (len > SN_AUX_MAX_PAYLOAD_BYTES)
 518                 return -EINVAL;
 519
 520         pm_runtime_get_sync(pdata->dev);
 521         mutex_lock(&pdata->comms_mutex);
 522
 523         /*
 524          * If someone tries to do a DDC over AUX transaction before pre_enable()
 525          * on a device without a dedicated reference clock then we just can't
 526          * do it. Fail right away. This prevents non-refclk users from reading
 527          * the EDID before enabling the panel but such is life.
 528          */
 529         if (!pdata->comms_enabled) {
 530                 ret = -EIO;
 531                 goto exit;
 532         }
 533
 534         switch (request) {
 535         case DP_AUX_NATIVE_WRITE:
 536         case DP_AUX_I2C_WRITE:
 537         case DP_AUX_NATIVE_READ:
 538         case DP_AUX_I2C_READ:
 539                 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
 540                 /* Assume it's good */
 541                 msg->reply = 0;
 542                 break;
 543         default:
 544                 ret = -EINVAL;
 545                 goto exit;
 546         }
 547
 548         BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
 549         put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
 550                            addr_len);
 551         regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
 552                           ARRAY_SIZE(addr_len));
 553
 554         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
 555                 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
 556
 557         /* Clear old status bits before start so we don't get confused */
 558         regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
 559                      AUX_IRQ_STATUS_NAT_I2C_FAIL |
 560                      AUX_IRQ_STATUS_AUX_RPLY_TOUT |
 561                      AUX_IRQ_STATUS_AUX_SHORT);
 562
 563         regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
 564
 565         /* Zero delay loop because i2c transactions are slow already */
 566         ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
 567                                        !(val & AUX_CMD_SEND), 0, 50 * 1000);
 568         if (ret)
 569                 goto exit;
 570
 571         ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
 572         if (ret)
 573                 goto exit;
 574
 575         if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
 576                 /*
 577                  * The hardware tried the message seven times per the DP spec
 578                  * but it hit a timeout. We ignore defers here because they're
 579                  * handled in hardware.
 580                  */
 581                 ret = -ETIMEDOUT;
 582                 goto exit;
 583         }
 584
 585         if (val & AUX_IRQ_STATUS_AUX_SHORT) {
 586                 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len);
 587                 if (ret)
 588                         goto exit;
 589         } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
 590                 switch (request) {
 591                 case DP_AUX_I2C_WRITE:
 592                 case DP_AUX_I2C_READ:
 593                         msg->reply |= DP_AUX_I2C_REPLY_NACK;
 594                         break;
 595                 case DP_AUX_NATIVE_READ:
 596                 case DP_AUX_NATIVE_WRITE:
 597                         msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
 598                         break;
 599                 }
 600                 len = 0;
 601                 goto exit;
 602         }
 603
 604         if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
 605                 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
 606
 607 exit:
 608         mutex_unlock(&pdata->comms_mutex);
 609         pm_runtime_mark_last_busy(pdata->dev);
 610         pm_runtime_put_autosuspend(pdata->dev);
 611
 612         if (ret)
 613                 return ret;
 614         return len;
 615 }
 616
 617 static int ti_sn_aux_probe(struct auxiliary_device *adev,
 618                            const struct auxiliary_device_id *id)
 619 {
 620         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
 621         int ret;
 622
 623         pdata->aux.name = "ti-sn65dsi86-aux";
 624         pdata->aux.dev = &adev->dev;
 625         pdata->aux.transfer = ti_sn_aux_transfer;
 626         drm_dp_aux_init(&pdata->aux);
 627
 628         ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
 629         if (ret)
 630                 return ret;
 631
 632         /*
 633          * The eDP to MIPI bridge parts don't work until the AUX channel is
 634          * setup so we don't add it in the main driver probe, we add it now.
 635          */
 636         return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
 637 }
 638
 639 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
 640         { .name = "ti_sn65dsi86.aux", },
 641         {},
 642 };
 643
 644 static struct auxiliary_driver ti_sn_aux_driver = {
 645         .name = "aux",
 646         .probe = ti_sn_aux_probe,
 647         .id_table = ti_sn_aux_id_table,
 648 };
 649
 650 /*------------------------------------------------------------------------------
 651  * DRM Bridge
 652  */
 653
 654 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
 655 {
 656         return container_of(bridge, struct ti_sn65dsi86, bridge);
 657 }
 658
 659 static int ti_sn_attach_host(struct ti_sn65dsi86 *pdata)
 660 {
 661         int val;
 662         struct mipi_dsi_host *host;
 663         struct mipi_dsi_device *dsi;
 664         struct device *dev = pdata->dev;
 665         const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
 666                                                    .channel = 0,
 667                                                    .node = NULL,
 668         };
 669
 670         host = of_find_mipi_dsi_host_by_node(pdata->host_node);
 671         if (!host)
 672                 return -EPROBE_DEFER;
 673
 674         dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
 675         if (IS_ERR(dsi))
 676                 return PTR_ERR(dsi);
 677
 678         /* TODO: setting to 4 MIPI lanes always for now */
 679         dsi->lanes = 4;
 680         dsi->format = MIPI_DSI_FMT_RGB888;
 681         dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
 682
 683         /* check if continuous dsi clock is required or not */
 684         pm_runtime_get_sync(dev);
 685         regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
 686         pm_runtime_put_autosuspend(dev);
 687         if (!(val & DPPLL_CLK_SRC_DSICLK))
 688                 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
 689
 690         pdata->dsi = dsi;
 691
 692         return devm_mipi_dsi_attach(dev, dsi);
 693 }
 694
 695 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
 696                                enum drm_bridge_attach_flags flags)
 697 {
 698         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
 699         int ret;
 700
 701         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
 702                 DRM_ERROR("Fix bridge driver to make connector optional!");
 703                 return -EINVAL;
 704         }
 705
 706         pdata->aux.drm_dev = bridge->dev;
 707         ret = drm_dp_aux_register(&pdata->aux);
 708         if (ret < 0) {
 709                 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
 710                 return ret;
 711         }
 712
 713         /* We never want the next bridge to *also* create a connector: */
 714         flags |= DRM_BRIDGE_ATTACH_NO_CONNECTOR;
 715
 716         /* Attach the next bridge */
 717         ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
 718                                 &pdata->bridge, flags);
 719         if (ret < 0)
 720                 goto err_initted_aux;
 721
 722         pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
 723                                                      pdata->bridge.encoder);
 724         if (IS_ERR(pdata->connector)) {
 725                 ret = PTR_ERR(pdata->connector);
 726                 goto err_initted_aux;
 727         }
 728
 729         drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
 730
 731         return 0;
 732
 733 err_initted_aux:
 734         drm_dp_aux_unregister(&pdata->aux);
 735         return ret;
 736 }
 737
 738 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
 739 {
 740         drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
 741 }
 742
 743 static enum drm_mode_status
 744 ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
 745                         const struct drm_display_info *info,
 746                         const struct drm_display_mode *mode)
 747 {
 748         /* maximum supported resolution is 4K at 60 fps */
 749         if (mode->clock > 594000)
 750                 return MODE_CLOCK_HIGH;
 751
 752         return MODE_OK;
 753 }
 754
 755 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
 756 {
 757         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
 758
 759         /* disable video stream */
 760         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
 761 }
 762
 763 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
 764 {
 765         unsigned int bit_rate_mhz, clk_freq_mhz;
 766         unsigned int val;
 767         struct drm_display_mode *mode =
 768                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 769
 770         /* set DSIA clk frequency */
 771         bit_rate_mhz = (mode->clock / 1000) *
 772                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 773         clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
 774
 775         /* for each increment in val, frequency increases by 5MHz */
 776         val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
 777                 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
 778         regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
 779 }
 780
 781 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn65dsi86 *pdata)
 782 {
 783         if (pdata->connector->display_info.bpc <= 6)
 784                 return 18;
 785         else
 786                 return 24;
 787 }
 788
 789 /*
 790  * LUT index corresponds to register value and
 791  * LUT values corresponds to dp data rate supported
 792  * by the bridge in Mbps unit.
 793  */
 794 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
 795         0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 796 };
 797
 798 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata)
 799 {
 800         unsigned int bit_rate_khz, dp_rate_mhz;
 801         unsigned int i;
 802         struct drm_display_mode *mode =
 803                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 804
 805         /* Calculate minimum bit rate based on our pixel clock. */
 806         bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
 807
 808         /* Calculate minimum DP data rate, taking 80% as per DP spec */
 809         dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
 810                                    1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
 811
 812         for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
 813                 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
 814                         break;
 815
 816         return i;
 817 }
 818
 819 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
 820 {
 821         unsigned int valid_rates = 0;
 822         unsigned int rate_per_200khz;
 823         unsigned int rate_mhz;
 824         u8 dpcd_val;
 825         int ret;
 826         int i, j;
 827
 828         ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
 829         if (ret != 1) {
 830                 DRM_DEV_ERROR(pdata->dev,
 831                               "Can't read eDP rev (%d), assuming 1.1\n", ret);
 832                 dpcd_val = DP_EDP_11;
 833         }
 834
 835         if (dpcd_val >= DP_EDP_14) {
 836                 /* eDP 1.4 devices must provide a custom table */
 837                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 838
 839                 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
 840                                        sink_rates, sizeof(sink_rates));
 841
 842                 if (ret != sizeof(sink_rates)) {
 843                         DRM_DEV_ERROR(pdata->dev,
 844                                 "Can't read supported rate table (%d)\n", ret);
 845
 846                         /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
 847                         memset(sink_rates, 0, sizeof(sink_rates));
 848                 }
 849
 850                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
 851                         rate_per_200khz = le16_to_cpu(sink_rates[i]);
 852
 853                         if (!rate_per_200khz)
 854                                 break;
 855
 856                         rate_mhz = rate_per_200khz * 200 / 1000;
 857                         for (j = 0;
 858                              j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
 859                              j++) {
 860                                 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
 861                                         valid_rates |= BIT(j);
 862                         }
 863                 }
 864
 865                 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
 866                         if (valid_rates & BIT(i))
 867                                 return valid_rates;
 868                 }
 869                 DRM_DEV_ERROR(pdata->dev,
 870                               "No matching eDP rates in table; falling back\n");
 871         }
 872
 873         /* On older versions best we can do is use DP_MAX_LINK_RATE */
 874         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
 875         if (ret != 1) {
 876                 DRM_DEV_ERROR(pdata->dev,
 877                               "Can't read max rate (%d); assuming 5.4 GHz\n",
 878                               ret);
 879                 dpcd_val = DP_LINK_BW_5_4;
 880         }
 881
 882         switch (dpcd_val) {
 883         default:
 884                 DRM_DEV_ERROR(pdata->dev,
 885                               "Unexpected max rate (%#x); assuming 5.4 GHz\n",
 886                               (int)dpcd_val);
 887                 fallthrough;
 888         case DP_LINK_BW_5_4:
 889                 valid_rates |= BIT(7);
 890                 fallthrough;
 891         case DP_LINK_BW_2_7:
 892                 valid_rates |= BIT(4);
 893                 fallthrough;
 894         case DP_LINK_BW_1_62:
 895                 valid_rates |= BIT(1);
 896                 break;
 897         }
 898
 899         return valid_rates;
 900 }
 901
 902 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
 903 {
 904         struct drm_display_mode *mode =
 905                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 906         u8 hsync_polarity = 0, vsync_polarity = 0;
 907
 908         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 909                 hsync_polarity = CHA_HSYNC_POLARITY;
 910         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 911                 vsync_polarity = CHA_VSYNC_POLARITY;
 912
 913         ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
 914                                mode->hdisplay);
 915         ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
 916                                mode->vdisplay);
 917         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
 918                      (mode->hsync_end - mode->hsync_start) & 0xFF);
 919         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
 920                      (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
 921                      hsync_polarity);
 922         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
 923                      (mode->vsync_end - mode->vsync_start) & 0xFF);
 924         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
 925                      (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
 926                      vsync_polarity);
 927
 928         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
 929                      (mode->htotal - mode->hsync_end) & 0xFF);
 930         regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
 931                      (mode->vtotal - mode->vsync_end) & 0xFF);
 932
 933         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
 934                      (mode->hsync_start - mode->hdisplay) & 0xFF);
 935         regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
 936                      (mode->vsync_start - mode->vdisplay) & 0xFF);
 937
 938         usleep_range(10000, 10500); /* 10ms delay recommended by spec */
 939 }
 940
 941 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
 942 {
 943         u8 data;
 944         int ret;
 945
 946         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
 947         if (ret != 1) {
 948                 DRM_DEV_ERROR(pdata->dev,
 949                               "Can't read lane count (%d); assuming 4\n", ret);
 950                 return 4;
 951         }
 952
 953         return data & DP_LANE_COUNT_MASK;
 954 }
 955
 956 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
 957                                const char **last_err_str)
 958 {
 959         unsigned int val;
 960         int ret;
 961         int i;
 962
 963         /* set dp clk frequency value */
 964         regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
 965                            DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
 966
 967         /* enable DP PLL */
 968         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
 969
 970         ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
 971                                        val & DPPLL_SRC_DP_PLL_LOCK, 1000,
 972                                        50 * 1000);
 973         if (ret) {
 974                 *last_err_str = "DP_PLL_LOCK polling failed";
 975                 goto exit;
 976         }
 977
 978         /*
 979          * We'll try to link train several times.  As part of link training
 980          * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER.  If
 981          * the panel isn't ready quite it might respond NAK here which means
 982          * we need to try again.
 983          */
 984         for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
 985                 /* Semi auto link training mode */
 986                 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
 987                 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
 988                                                val == ML_TX_MAIN_LINK_OFF ||
 989                                                val == ML_TX_NORMAL_MODE, 1000,
 990                                                500 * 1000);
 991                 if (ret) {
 992                         *last_err_str = "Training complete polling failed";
 993                 } else if (val == ML_TX_MAIN_LINK_OFF) {
 994                         *last_err_str = "Link training failed, link is off";
 995                         ret = -EIO;
 996                         continue;
 997                 }
 998
 999                 break;
1000         }
1001
1002         /* If we saw quite a few retries, add a note about it */
1003         if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1004                 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1005
1006 exit:
1007         /* Disable the PLL if we failed */
1008         if (ret)
1009                 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1010
1011         return ret;
1012 }
1013
1014 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
1015 {
1016         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1017         const char *last_err_str = "No supported DP rate";
1018         unsigned int valid_rates;
1019         int dp_rate_idx;
1020         unsigned int val;
1021         int ret = -EINVAL;
1022         int max_dp_lanes;
1023
1024         max_dp_lanes = ti_sn_get_max_lanes(pdata);
1025         pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1026
1027         /* DSI_A lane config */
1028         val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1029         regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1030                            CHA_DSI_LANES_MASK, val);
1031
1032         regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1033         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1034                            pdata->ln_polrs << LN_POLRS_OFFSET);
1035
1036         /* set dsi clk frequency value */
1037         ti_sn_bridge_set_dsi_rate(pdata);
1038
1039         /*
1040          * The SN65DSI86 only supports ASSR Display Authentication method and
1041          * this method is enabled by default. An eDP panel must support this
1042          * authentication method. We need to enable this method in the eDP panel
1043          * at DisplayPort address 0x0010A prior to link training.
1044          */
1045         drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1046                            DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1047
1048         /* Set the DP output format (18 bpp or 24 bpp) */
1049         val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
1050         regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1051
1052         /* DP lane config */
1053         val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1054         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1055                            val);
1056
1057         valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1058
1059         /* Train until we run out of rates */
1060         for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
1061              dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1062              dp_rate_idx++) {
1063                 if (!(valid_rates & BIT(dp_rate_idx)))
1064                         continue;
1065
1066                 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1067                 if (!ret)
1068                         break;
1069         }
1070         if (ret) {
1071                 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1072                 return;
1073         }
1074
1075         /* config video parameters */
1076         ti_sn_bridge_set_video_timings(pdata);
1077
1078         /* enable video stream */
1079         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1080                            VSTREAM_ENABLE);
1081 }
1082
1083 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
1084 {
1085         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1086
1087         pm_runtime_get_sync(pdata->dev);
1088
1089         if (!pdata->refclk)
1090                 ti_sn65dsi86_enable_comms(pdata);
1091
1092         /* td7: min 100 us after enable before DSI data */
1093         usleep_range(100, 110);
1094 }
1095
1096 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
1097 {
1098         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1099
1100         /* semi auto link training mode OFF */
1101         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1102         /* Num lanes to 0 as per power sequencing in data sheet */
1103         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1104         /* disable DP PLL */
1105         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1106
1107         if (!pdata->refclk)
1108                 ti_sn65dsi86_disable_comms(pdata);
1109
1110         pm_runtime_put_sync(pdata->dev);
1111 }
1112
1113 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1114         .attach = ti_sn_bridge_attach,
1115         .detach = ti_sn_bridge_detach,
1116         .mode_valid = ti_sn_bridge_mode_valid,
1117         .pre_enable = ti_sn_bridge_pre_enable,
1118         .enable = ti_sn_bridge_enable,
1119         .disable = ti_sn_bridge_disable,
1120         .post_disable = ti_sn_bridge_post_disable,
1121 };
1122
1123 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1124                                      struct device_node *np)
1125 {
1126         u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1127         u32 lane_polarities[SN_MAX_DP_LANES] = { };
1128         struct device_node *endpoint;
1129         u8 ln_assign = 0;
1130         u8 ln_polrs = 0;
1131         int dp_lanes;
1132         int i;
1133
1134         /*
1135          * Read config from the device tree about lane remapping and lane
1136          * polarities.  These are optional and we assume identity map and
1137          * normal polarity if nothing is specified.  It's OK to specify just
1138          * data-lanes but not lane-polarities but not vice versa.
1139          *
1140          * Error checking is light (we just make sure we don't crash or
1141          * buffer overrun) and we assume dts is well formed and specifying
1142          * mappings that the hardware supports.
1143          */
1144         endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1145         dp_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
1146         if (dp_lanes > 0 && dp_lanes <= SN_MAX_DP_LANES) {
1147                 of_property_read_u32_array(endpoint, "data-lanes",
1148                                            lane_assignments, dp_lanes);
1149                 of_property_read_u32_array(endpoint, "lane-polarities",
1150                                            lane_polarities, dp_lanes);
1151         } else {
1152                 dp_lanes = SN_MAX_DP_LANES;
1153         }
1154         of_node_put(endpoint);
1155
1156         /*
1157          * Convert into register format.  Loop over all lanes even if
1158          * data-lanes had fewer elements so that we nicely initialize
1159          * the LN_ASSIGN register.
1160          */
1161         for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1162                 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1163                 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1164         }
1165
1166         /* Stash in our struct for when we power on */
1167         pdata->dp_lanes = dp_lanes;
1168         pdata->ln_assign = ln_assign;
1169         pdata->ln_polrs = ln_polrs;
1170 }
1171
1172 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1173 {
1174         struct device_node *np = pdata->dev->of_node;
1175
1176         pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1177
1178         if (!pdata->host_node) {
1179                 DRM_ERROR("remote dsi host node not found\n");
1180                 return -ENODEV;
1181         }
1182
1183         return 0;
1184 }
1185
1186 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1187                               const struct auxiliary_device_id *id)
1188 {
1189         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1190         struct device_node *np = pdata->dev->of_node;
1191         int ret;
1192
1193         pdata->next_bridge = devm_drm_of_get_bridge(pdata->dev, np, 1, 0);
1194         if (IS_ERR(pdata->next_bridge)) {
1195                 DRM_ERROR("failed to create panel bridge\n");
1196                 return PTR_ERR(pdata->next_bridge);
1197         }
1198
1199         ti_sn_bridge_parse_lanes(pdata, np);
1200
1201         ret = ti_sn_bridge_parse_dsi_host(pdata);
1202         if (ret)
1203                 return ret;
1204
1205         pdata->bridge.funcs = &ti_sn_bridge_funcs;
1206         pdata->bridge.of_node = np;
1207
1208         drm_bridge_add(&pdata->bridge);
1209
1210         ret = ti_sn_attach_host(pdata);
1211         if (ret) {
1212                 dev_err_probe(pdata->dev, ret, "failed to attach dsi host\n");
1213                 goto err_remove_bridge;
1214         }
1215
1216         return 0;
1217
1218 err_remove_bridge:
1219         drm_bridge_remove(&pdata->bridge);
1220         return ret;
1221 }
1222
1223 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1224 {
1225         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1226
1227         if (!pdata)
1228                 return;
1229
1230         drm_bridge_remove(&pdata->bridge);
1231
1232         of_node_put(pdata->host_node);
1233 }
1234
1235 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1236         { .name = "ti_sn65dsi86.bridge", },
1237         {},
1238 };
1239
1240 static struct auxiliary_driver ti_sn_bridge_driver = {
1241         .name = "bridge",
1242         .probe = ti_sn_bridge_probe,
1243         .remove = ti_sn_bridge_remove,
1244         .id_table = ti_sn_bridge_id_table,
1245 };
1246
1247 /* -----------------------------------------------------------------------------
1248  * PWM Controller
1249  */
1250 #if defined(CONFIG_PWM)
1251 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1252 {
1253         return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1254 }
1255
1256 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1257 {
1258         atomic_set(&pdata->pwm_pin_busy, 0);
1259 }
1260
1261 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1262 {
1263         return container_of(chip, struct ti_sn65dsi86, pchip);
1264 }
1265
1266 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1267 {
1268         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1269
1270         return ti_sn_pwm_pin_request(pdata);
1271 }
1272
1273 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1274 {
1275         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1276
1277         ti_sn_pwm_pin_release(pdata);
1278 }
1279
1280 /*
1281  * Limitations:
1282  * - The PWM signal is not driven when the chip is powered down, or in its
1283  *   reset state and the driver does not implement the "suspend state"
1284  *   described in the documentation. In order to save power, state->enabled is
1285  *   interpreted as denoting if the signal is expected to be valid, and is used
1286  *   to determine if the chip needs to be kept powered.
1287  * - Changing both period and duty_cycle is not done atomically, neither is the
1288  *   multi-byte register updates, so the output might briefly be undefined
1289  *   during update.
1290  */
1291 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1292                            const struct pwm_state *state)
1293 {
1294         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1295         unsigned int pwm_en_inv;
1296         unsigned int backlight;
1297         unsigned int pre_div;
1298         unsigned int scale;
1299         u64 period_max;
1300         u64 period;
1301         int ret;
1302
1303         if (!pdata->pwm_enabled) {
1304                 ret = pm_runtime_get_sync(pdata->dev);
1305                 if (ret < 0) {
1306                         pm_runtime_put_sync(pdata->dev);
1307                         return ret;
1308                 }
1309         }
1310
1311         if (state->enabled) {
1312                 if (!pdata->pwm_enabled) {
1313                         /*
1314                          * The chip might have been powered down while we
1315                          * didn't hold a PM runtime reference, so mux in the
1316                          * PWM function on the GPIO pin again.
1317                          */
1318                         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1319                                                  SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1320                                                  SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1321                         if (ret) {
1322                                 dev_err(pdata->dev, "failed to mux in PWM function\n");
1323                                 goto out;
1324                         }
1325                 }
1326
1327                 /*
1328                  * Per the datasheet the PWM frequency is given by:
1329                  *
1330                  *                          REFCLK_FREQ
1331                  *   PWM_FREQ = -----------------------------------
1332                  *               PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1333                  *
1334                  * However, after careful review the author is convinced that
1335                  * the documentation has lost some parenthesis around
1336                  * "BACKLIGHT_SCALE + 1".
1337                  *
1338                  * With the period T_pwm = 1/PWM_FREQ this can be written:
1339                  *
1340                  *   T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1341                  *
1342                  * In order to keep BACKLIGHT_SCALE within its 16 bits,
1343                  * PWM_PRE_DIV must be:
1344                  *
1345                  *                     T_pwm * REFCLK_FREQ
1346                  *   PWM_PRE_DIV >= -------------------------
1347                  *                   BACKLIGHT_SCALE_MAX + 1
1348                  *
1349                  * To simplify the search and to favour higher resolution of
1350                  * the duty cycle over accuracy of the period, the lowest
1351                  * possible PWM_PRE_DIV is used. Finally the scale is
1352                  * calculated as:
1353                  *
1354                  *                      T_pwm * REFCLK_FREQ
1355                  *   BACKLIGHT_SCALE = ---------------------- - 1
1356                  *                          PWM_PRE_DIV
1357                  *
1358                  * Here T_pwm is represented in seconds, so appropriate scaling
1359                  * to nanoseconds is necessary.
1360                  */
1361
1362                 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1363                 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1364                         ret = -EINVAL;
1365                         goto out;
1366                 }
1367
1368                 /*
1369                  * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1370                  * Limit period to this to avoid overflows
1371                  */
1372                 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1373                                      pdata->pwm_refclk_freq);
1374                 period = min(state->period, period_max);
1375
1376                 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1377                                              (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1378                 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1379
1380                 /*
1381                  * The documentation has the duty ratio given as:
1382                  *
1383                  *     duty          BACKLIGHT
1384                  *   ------- = ---------------------
1385                  *    period    BACKLIGHT_SCALE + 1
1386                  *
1387                  * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1388                  * to definition above and adjusting for nanosecond
1389                  * representation of duty cycle gives us:
1390                  */
1391                 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1392                                       (u64)NSEC_PER_SEC * pre_div);
1393                 if (backlight > scale)
1394                         backlight = scale;
1395
1396                 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1397                 if (ret) {
1398                         dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n");
1399                         goto out;
1400                 }
1401
1402                 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1403                 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1404         }
1405
1406         pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1407                      FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1408         ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1409         if (ret) {
1410                 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n");
1411                 goto out;
1412         }
1413
1414         pdata->pwm_enabled = state->enabled;
1415 out:
1416
1417         if (!pdata->pwm_enabled)
1418                 pm_runtime_put_sync(pdata->dev);
1419
1420         return ret;
1421 }
1422
1423 static void ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1424                                 struct pwm_state *state)
1425 {
1426         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1427         unsigned int pwm_en_inv;
1428         unsigned int pre_div;
1429         u16 backlight;
1430         u16 scale;
1431         int ret;
1432
1433         ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1434         if (ret)
1435                 return;
1436
1437         ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1438         if (ret)
1439                 return;
1440
1441         ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1442         if (ret)
1443                 return;
1444
1445         ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1446         if (ret)
1447                 return;
1448
1449         state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1450         if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1451                 state->polarity = PWM_POLARITY_INVERSED;
1452         else
1453                 state->polarity = PWM_POLARITY_NORMAL;
1454
1455         state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1456                                          pdata->pwm_refclk_freq);
1457         state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1458                                              pdata->pwm_refclk_freq);
1459
1460         if (state->duty_cycle > state->period)
1461                 state->duty_cycle = state->period;
1462 }
1463
1464 static const struct pwm_ops ti_sn_pwm_ops = {
1465         .request = ti_sn_pwm_request,
1466         .free = ti_sn_pwm_free,
1467         .apply = ti_sn_pwm_apply,
1468         .get_state = ti_sn_pwm_get_state,
1469         .owner = THIS_MODULE,
1470 };
1471
1472 static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1473                            const struct auxiliary_device_id *id)
1474 {
1475         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1476
1477         pdata->pchip.dev = pdata->dev;
1478         pdata->pchip.ops = &ti_sn_pwm_ops;
1479         pdata->pchip.npwm = 1;
1480         pdata->pchip.of_xlate = of_pwm_single_xlate;
1481         pdata->pchip.of_pwm_n_cells = 1;
1482
1483         return pwmchip_add(&pdata->pchip);
1484 }
1485
1486 static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1487 {
1488         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1489
1490         pwmchip_remove(&pdata->pchip);
1491
1492         if (pdata->pwm_enabled)
1493                 pm_runtime_put_sync(pdata->dev);
1494 }
1495
1496 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1497         { .name = "ti_sn65dsi86.pwm", },
1498         {},
1499 };
1500
1501 static struct auxiliary_driver ti_sn_pwm_driver = {
1502         .name = "pwm",
1503         .probe = ti_sn_pwm_probe,
1504         .remove = ti_sn_pwm_remove,
1505         .id_table = ti_sn_pwm_id_table,
1506 };
1507
1508 static int __init ti_sn_pwm_register(void)
1509 {
1510         return auxiliary_driver_register(&ti_sn_pwm_driver);
1511 }
1512
1513 static void ti_sn_pwm_unregister(void)
1514 {
1515         auxiliary_driver_unregister(&ti_sn_pwm_driver);
1516 }
1517
1518 #else
1519 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
1520 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1521
1522 static inline int ti_sn_pwm_register(void) { return 0; }
1523 static inline void ti_sn_pwm_unregister(void) {}
1524 #endif
1525
1526 /* -----------------------------------------------------------------------------
1527  * GPIO Controller
1528  */
1529 #if defined(CONFIG_OF_GPIO)
1530
1531 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1532                                  const struct of_phandle_args *gpiospec,
1533                                  u32 *flags)
1534 {
1535         if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1536                 return -EINVAL;
1537
1538         if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1539                 return -EINVAL;
1540
1541         if (flags)
1542                 *flags = gpiospec->args[1];
1543
1544         return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1545 }
1546
1547 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1548                                            unsigned int offset)
1549 {
1550         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1551
1552         /*
1553          * We already have to keep track of the direction because we use
1554          * that to figure out whether we've powered the device.  We can
1555          * just return that rather than (maybe) powering up the device
1556          * to ask its direction.
1557          */
1558         return test_bit(offset, pdata->gchip_output) ?
1559                 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1560 }
1561
1562 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1563 {
1564         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1565         unsigned int val;
1566         int ret;
1567
1568         /*
1569          * When the pin is an input we don't forcibly keep the bridge
1570          * powered--we just power it on to read the pin.  NOTE: part of
1571          * the reason this works is that the bridge defaults (when
1572          * powered back on) to all 4 GPIOs being configured as GPIO input.
1573          * Also note that if something else is keeping the chip powered the
1574          * pm_runtime functions are lightweight increments of a refcount.
1575          */
1576         pm_runtime_get_sync(pdata->dev);
1577         ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1578         pm_runtime_put_autosuspend(pdata->dev);
1579
1580         if (ret)
1581                 return ret;
1582
1583         return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1584 }
1585
1586 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1587                                   int val)
1588 {
1589         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1590         int ret;
1591
1592         if (!test_bit(offset, pdata->gchip_output)) {
1593                 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1594                 return;
1595         }
1596
1597         val &= 1;
1598         ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1599                                  BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1600                                  val << (SN_GPIO_OUTPUT_SHIFT + offset));
1601         if (ret)
1602                 dev_warn(pdata->dev,
1603                          "Failed to set bridge GPIO %u: %d\n", offset, ret);
1604 }
1605
1606 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1607                                              unsigned int offset)
1608 {
1609         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1610         int shift = offset * 2;
1611         int ret;
1612
1613         if (!test_and_clear_bit(offset, pdata->gchip_output))
1614                 return 0;
1615
1616         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1617                                  SN_GPIO_MUX_MASK << shift,
1618                                  SN_GPIO_MUX_INPUT << shift);
1619         if (ret) {
1620                 set_bit(offset, pdata->gchip_output);
1621                 return ret;
1622         }
1623
1624         /*
1625          * NOTE: if nobody else is powering the device this may fully power
1626          * it off and when it comes back it will have lost all state, but
1627          * that's OK because the default is input and we're now an input.
1628          */
1629         pm_runtime_put_autosuspend(pdata->dev);
1630
1631         return 0;
1632 }
1633
1634 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1635                                               unsigned int offset, int val)
1636 {
1637         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1638         int shift = offset * 2;
1639         int ret;
1640
1641         if (test_and_set_bit(offset, pdata->gchip_output))
1642                 return 0;
1643
1644         pm_runtime_get_sync(pdata->dev);
1645
1646         /* Set value first to avoid glitching */
1647         ti_sn_bridge_gpio_set(chip, offset, val);
1648
1649         /* Set direction */
1650         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1651                                  SN_GPIO_MUX_MASK << shift,
1652                                  SN_GPIO_MUX_OUTPUT << shift);
1653         if (ret) {
1654                 clear_bit(offset, pdata->gchip_output);
1655                 pm_runtime_put_autosuspend(pdata->dev);
1656         }
1657
1658         return ret;
1659 }
1660
1661 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1662 {
1663         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1664
1665         if (offset == SN_PWM_GPIO_IDX)
1666                 return ti_sn_pwm_pin_request(pdata);
1667
1668         return 0;
1669 }
1670
1671 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1672 {
1673         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1674
1675         /* We won't keep pm_runtime if we're input, so switch there on free */
1676         ti_sn_bridge_gpio_direction_input(chip, offset);
1677
1678         if (offset == SN_PWM_GPIO_IDX)
1679                 ti_sn_pwm_pin_release(pdata);
1680 }
1681
1682 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1683         "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1684 };
1685
1686 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1687                             const struct auxiliary_device_id *id)
1688 {
1689         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1690         int ret;
1691
1692         /* Only init if someone is going to use us as a GPIO controller */
1693         if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1694                 return 0;
1695
1696         pdata->gchip.label = dev_name(pdata->dev);
1697         pdata->gchip.parent = pdata->dev;
1698         pdata->gchip.owner = THIS_MODULE;
1699         pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1700         pdata->gchip.of_gpio_n_cells = 2;
1701         pdata->gchip.request = ti_sn_bridge_gpio_request;
1702         pdata->gchip.free = ti_sn_bridge_gpio_free;
1703         pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1704         pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1705         pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1706         pdata->gchip.get = ti_sn_bridge_gpio_get;
1707         pdata->gchip.set = ti_sn_bridge_gpio_set;
1708         pdata->gchip.can_sleep = true;
1709         pdata->gchip.names = ti_sn_bridge_gpio_names;
1710         pdata->gchip.ngpio = SN_NUM_GPIOS;
1711         pdata->gchip.base = -1;
1712         ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1713         if (ret)
1714                 dev_err(pdata->dev, "can't add gpio chip\n");
1715
1716         return ret;
1717 }
1718
1719 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1720         { .name = "ti_sn65dsi86.gpio", },
1721         {},
1722 };
1723
1724 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1725
1726 static struct auxiliary_driver ti_sn_gpio_driver = {
1727         .name = "gpio",
1728         .probe = ti_sn_gpio_probe,
1729         .id_table = ti_sn_gpio_id_table,
1730 };
1731
1732 static int __init ti_sn_gpio_register(void)
1733 {
1734         return auxiliary_driver_register(&ti_sn_gpio_driver);
1735 }
1736
1737 static void ti_sn_gpio_unregister(void)
1738 {
1739         auxiliary_driver_unregister(&ti_sn_gpio_driver);
1740 }
1741
1742 #else
1743
1744 static inline int ti_sn_gpio_register(void) { return 0; }
1745 static inline void ti_sn_gpio_unregister(void) {}
1746
1747 #endif
1748
1749 /* -----------------------------------------------------------------------------
1750  * Probe & Remove
1751  */
1752
1753 static void ti_sn65dsi86_runtime_disable(void *data)
1754 {
1755         pm_runtime_dont_use_autosuspend(data);
1756         pm_runtime_disable(data);
1757 }
1758
1759 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1760 {
1761         unsigned int i;
1762         const char * const ti_sn_bridge_supply_names[] = {
1763                 "vcca", "vcc", "vccio", "vpll",
1764         };
1765
1766         for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1767                 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1768
1769         return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1770                                        pdata->supplies);
1771 }
1772
1773 static int ti_sn65dsi86_probe(struct i2c_client *client,
1774                               const struct i2c_device_id *id)
1775 {
1776         struct device *dev = &client->dev;
1777         struct ti_sn65dsi86 *pdata;
1778         int ret;
1779
1780         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1781                 DRM_ERROR("device doesn't support I2C\n");
1782                 return -ENODEV;
1783         }
1784
1785         pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1786         if (!pdata)
1787                 return -ENOMEM;
1788         dev_set_drvdata(dev, pdata);
1789         pdata->dev = dev;
1790
1791         mutex_init(&pdata->comms_mutex);
1792
1793         pdata->regmap = devm_regmap_init_i2c(client,
1794                                              &ti_sn65dsi86_regmap_config);
1795         if (IS_ERR(pdata->regmap))
1796                 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1797                                      "regmap i2c init failed\n");
1798
1799         pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1800                                                      GPIOD_OUT_LOW);
1801         if (IS_ERR(pdata->enable_gpio))
1802                 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1803                                      "failed to get enable gpio from DT\n");
1804
1805         ret = ti_sn65dsi86_parse_regulators(pdata);
1806         if (ret)
1807                 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1808
1809         pdata->refclk = devm_clk_get_optional(dev, "refclk");
1810         if (IS_ERR(pdata->refclk))
1811                 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1812                                      "failed to get reference clock\n");
1813
1814         pm_runtime_enable(dev);
1815         pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1816         pm_runtime_use_autosuspend(pdata->dev);
1817         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1818         if (ret)
1819                 return ret;
1820
1821         ti_sn65dsi86_debugfs_init(pdata);
1822
1823         /*
1824          * Break ourselves up into a collection of aux devices. The only real
1825          * motiviation here is to solve the chicken-and-egg problem of probe
1826          * ordering. The bridge wants the panel to be there when it probes.
1827          * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1828          * when it probes. The panel and maybe backlight might want the DDC
1829          * bus or the pwm_chip. Having sub-devices allows the some sub devices
1830          * to finish probing even if others return -EPROBE_DEFER and gets us
1831          * around the problems.
1832          */
1833
1834         if (IS_ENABLED(CONFIG_OF_GPIO)) {
1835                 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1836                 if (ret)
1837                         return ret;
1838         }
1839
1840         if (IS_ENABLED(CONFIG_PWM)) {
1841                 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
1842                 if (ret)
1843                         return ret;
1844         }
1845
1846         /*
1847          * NOTE: At the end of the AUX channel probe we'll add the aux device
1848          * for the bridge. This is because the bridge can't be used until the
1849          * AUX channel is there and this is a very simple solution to the
1850          * dependency problem.
1851          */
1852         return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
1853 }
1854
1855 static struct i2c_device_id ti_sn65dsi86_id[] = {
1856         { "ti,sn65dsi86", 0},
1857         {},
1858 };
1859 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
1860
1861 static const struct of_device_id ti_sn65dsi86_match_table[] = {
1862         {.compatible = "ti,sn65dsi86"},
1863         {},
1864 };
1865 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
1866
1867 static struct i2c_driver ti_sn65dsi86_driver = {
1868         .driver = {
1869                 .name = "ti_sn65dsi86",
1870                 .of_match_table = ti_sn65dsi86_match_table,
1871                 .pm = &ti_sn65dsi86_pm_ops,
1872         },
1873         .probe = ti_sn65dsi86_probe,
1874         .id_table = ti_sn65dsi86_id,
1875 };
1876
1877 static int __init ti_sn65dsi86_init(void)
1878 {
1879         int ret;
1880
1881         ret = i2c_add_driver(&ti_sn65dsi86_driver);
1882         if (ret)
1883                 return ret;
1884
1885         ret = ti_sn_gpio_register();
1886         if (ret)
1887                 goto err_main_was_registered;
1888
1889         ret = ti_sn_pwm_register();
1890         if (ret)
1891                 goto err_gpio_was_registered;
1892
1893         ret = auxiliary_driver_register(&ti_sn_aux_driver);
1894         if (ret)
1895                 goto err_pwm_was_registered;
1896
1897         ret = auxiliary_driver_register(&ti_sn_bridge_driver);
1898         if (ret)
1899                 goto err_aux_was_registered;
1900
1901         return 0;
1902
1903 err_aux_was_registered:
1904         auxiliary_driver_unregister(&ti_sn_aux_driver);
1905 err_pwm_was_registered:
1906         ti_sn_pwm_unregister();
1907 err_gpio_was_registered:
1908         ti_sn_gpio_unregister();
1909 err_main_was_registered:
1910         i2c_del_driver(&ti_sn65dsi86_driver);
1911
1912         return ret;
1913 }
1914 module_init(ti_sn65dsi86_init);
1915
1916 static void __exit ti_sn65dsi86_exit(void)
1917 {
1918         auxiliary_driver_unregister(&ti_sn_bridge_driver);
1919         auxiliary_driver_unregister(&ti_sn_aux_driver);
1920         ti_sn_pwm_unregister();
1921         ti_sn_gpio_unregister();
1922         i2c_del_driver(&ti_sn65dsi86_driver);
1923 }
1924 module_exit(ti_sn65dsi86_exit);
1925
1926 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>");
1927 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1928 MODULE_LICENSE("GPL v2");