drivers/gpu/drm/bridge/tc358768.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
   4  *  Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/device.h>
   9 #include <linux/gpio/consumer.h>
  10 #include <linux/i2c.h>
  11 #include <linux/kernel.h>
  12 #include <linux/media-bus-format.h>
  13 #include <linux/minmax.h>
  14 #include <linux/module.h>
  15 #include <linux/regmap.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/slab.h>
  18
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_crtc_helper.h>
  21 #include <drm/drm_drv.h>
  22 #include <drm/drm_mipi_dsi.h>
  23 #include <drm/drm_of.h>
  24 #include <drm/drm_panel.h>
  25 #include <video/mipi_display.h>
  26 #include <video/videomode.h>
  27
  28 /* Global (16-bit addressable) */
  29 #define TC358768_CHIPID                 0x0000
  30 #define TC358768_SYSCTL                 0x0002
  31 #define TC358768_CONFCTL                0x0004
  32 #define TC358768_VSDLY                  0x0006
  33 #define TC358768_DATAFMT                0x0008
  34 #define TC358768_GPIOEN                 0x000E
  35 #define TC358768_GPIODIR                0x0010
  36 #define TC358768_GPIOIN                 0x0012
  37 #define TC358768_GPIOOUT                0x0014
  38 #define TC358768_PLLCTL0                0x0016
  39 #define TC358768_PLLCTL1                0x0018
  40 #define TC358768_CMDBYTE                0x0022
  41 #define TC358768_PP_MISC                0x0032
  42 #define TC358768_DSITX_DT               0x0050
  43 #define TC358768_FIFOSTATUS             0x00F8
  44
  45 /* Debug (16-bit addressable) */
  46 #define TC358768_VBUFCTRL               0x00E0
  47 #define TC358768_DBG_WIDTH              0x00E2
  48 #define TC358768_DBG_VBLANK             0x00E4
  49 #define TC358768_DBG_DATA               0x00E8
  50
  51 /* TX PHY (32-bit addressable) */
  52 #define TC358768_CLW_DPHYCONTTX         0x0100
  53 #define TC358768_D0W_DPHYCONTTX         0x0104
  54 #define TC358768_D1W_DPHYCONTTX         0x0108
  55 #define TC358768_D2W_DPHYCONTTX         0x010C
  56 #define TC358768_D3W_DPHYCONTTX         0x0110
  57 #define TC358768_CLW_CNTRL              0x0140
  58 #define TC358768_D0W_CNTRL              0x0144
  59 #define TC358768_D1W_CNTRL              0x0148
  60 #define TC358768_D2W_CNTRL              0x014C
  61 #define TC358768_D3W_CNTRL              0x0150
  62
  63 /* TX PPI (32-bit addressable) */
  64 #define TC358768_STARTCNTRL             0x0204
  65 #define TC358768_DSITXSTATUS            0x0208
  66 #define TC358768_LINEINITCNT            0x0210
  67 #define TC358768_LPTXTIMECNT            0x0214
  68 #define TC358768_TCLK_HEADERCNT         0x0218
  69 #define TC358768_TCLK_TRAILCNT          0x021C
  70 #define TC358768_THS_HEADERCNT          0x0220
  71 #define TC358768_TWAKEUP                0x0224
  72 #define TC358768_TCLK_POSTCNT           0x0228
  73 #define TC358768_THS_TRAILCNT           0x022C
  74 #define TC358768_HSTXVREGCNT            0x0230
  75 #define TC358768_HSTXVREGEN             0x0234
  76 #define TC358768_TXOPTIONCNTRL          0x0238
  77 #define TC358768_BTACNTRL1              0x023C
  78
  79 /* TX CTRL (32-bit addressable) */
  80 #define TC358768_DSI_CONTROL            0x040C
  81 #define TC358768_DSI_STATUS             0x0410
  82 #define TC358768_DSI_INT                0x0414
  83 #define TC358768_DSI_INT_ENA            0x0418
  84 #define TC358768_DSICMD_RDFIFO          0x0430
  85 #define TC358768_DSI_ACKERR             0x0434
  86 #define TC358768_DSI_ACKERR_INTENA      0x0438
  87 #define TC358768_DSI_ACKERR_HALT        0x043c
  88 #define TC358768_DSI_RXERR              0x0440
  89 #define TC358768_DSI_RXERR_INTENA       0x0444
  90 #define TC358768_DSI_RXERR_HALT         0x0448
  91 #define TC358768_DSI_ERR                0x044C
  92 #define TC358768_DSI_ERR_INTENA         0x0450
  93 #define TC358768_DSI_ERR_HALT           0x0454
  94 #define TC358768_DSI_CONFW              0x0500
  95 #define TC358768_DSI_LPCMD              0x0500
  96 #define TC358768_DSI_RESET              0x0504
  97 #define TC358768_DSI_INT_CLR            0x050C
  98 #define TC358768_DSI_START              0x0518
  99
 100 /* DSITX CTRL (16-bit addressable) */
 101 #define TC358768_DSICMD_TX              0x0600
 102 #define TC358768_DSICMD_TYPE            0x0602
 103 #define TC358768_DSICMD_WC              0x0604
 104 #define TC358768_DSICMD_WD0             0x0610
 105 #define TC358768_DSICMD_WD1             0x0612
 106 #define TC358768_DSICMD_WD2             0x0614
 107 #define TC358768_DSICMD_WD3             0x0616
 108 #define TC358768_DSI_EVENT              0x0620
 109 #define TC358768_DSI_VSW                0x0622
 110 #define TC358768_DSI_VBPR               0x0624
 111 #define TC358768_DSI_VACT               0x0626
 112 #define TC358768_DSI_HSW                0x0628
 113 #define TC358768_DSI_HBPR               0x062A
 114 #define TC358768_DSI_HACT               0x062C
 115
 116 /* TC358768_DSI_CONTROL (0x040C) register */
 117 #define TC358768_DSI_CONTROL_DIS_MODE   BIT(15)
 118 #define TC358768_DSI_CONTROL_TXMD       BIT(7)
 119 #define TC358768_DSI_CONTROL_HSCKMD     BIT(5)
 120 #define TC358768_DSI_CONTROL_EOTDIS     BIT(0)
 121
 122 /* TC358768_DSI_CONFW (0x0500) register */
 123 #define TC358768_DSI_CONFW_MODE_SET     (5 << 29)
 124 #define TC358768_DSI_CONFW_MODE_CLR     (6 << 29)
 125 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL     (0x3 << 24)
 126
 127 static const char * const tc358768_supplies[] = {
 128         "vddc", "vddmipi", "vddio"
 129 };
 130
 131 struct tc358768_dsi_output {
 132         struct mipi_dsi_device *dev;
 133         struct drm_panel *panel;
 134         struct drm_bridge *bridge;
 135 };
 136
 137 struct tc358768_priv {
 138         struct device *dev;
 139         struct regmap *regmap;
 140         struct gpio_desc *reset_gpio;
 141         struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)];
 142         struct clk *refclk;
 143         int enabled;
 144         int error;
 145
 146         struct mipi_dsi_host dsi_host;
 147         struct drm_bridge bridge;
 148         struct tc358768_dsi_output output;
 149
 150         u32 pd_lines; /* number of Parallel Port Input Data Lines */
 151         u32 dsi_lanes; /* number of DSI Lanes */
 152         u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
 153
 154         /* Parameters for PLL programming */
 155         u32 fbd;        /* PLL feedback divider */
 156         u32 prd;        /* PLL input divider */
 157         u32 frs;        /* PLL Freqency range for HSCK (post divider) */
 158
 159         u32 dsiclk;     /* pll_clk / 2 */
 160 };
 161
 162 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host
 163                                                          *host)
 164 {
 165         return container_of(host, struct tc358768_priv, dsi_host);
 166 }
 167
 168 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge
 169                                                        *bridge)
 170 {
 171         return container_of(bridge, struct tc358768_priv, bridge);
 172 }
 173
 174 static int tc358768_clear_error(struct tc358768_priv *priv)
 175 {
 176         int ret = priv->error;
 177
 178         priv->error = 0;
 179         return ret;
 180 }
 181
 182 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val)
 183 {
 184         /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */
 185         int tmpval = val;
 186         size_t count = 2;
 187
 188         if (priv->error)
 189                 return;
 190
 191         /* 16-bit register? */
 192         if (reg < 0x100 || reg >= 0x600)
 193                 count = 1;
 194
 195         priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count);
 196 }
 197
 198 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val)
 199 {
 200         size_t count = 2;
 201
 202         if (priv->error)
 203                 return;
 204
 205         /* 16-bit register? */
 206         if (reg < 0x100 || reg >= 0x600) {
 207                 *val = 0;
 208                 count = 1;
 209         }
 210
 211         priv->error = regmap_bulk_read(priv->regmap, reg, val, count);
 212 }
 213
 214 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask,
 215                                  u32 val)
 216 {
 217         u32 tmp, orig;
 218
 219         tc358768_read(priv, reg, &orig);
 220
 221         if (priv->error)
 222                 return;
 223
 224         tmp = orig & ~mask;
 225         tmp |= val & mask;
 226         if (tmp != orig)
 227                 tc358768_write(priv, reg, tmp);
 228 }
 229
 230 static int tc358768_sw_reset(struct tc358768_priv *priv)
 231 {
 232         /* Assert Reset */
 233         tc358768_write(priv, TC358768_SYSCTL, 1);
 234         /* Release Reset, Exit Sleep */
 235         tc358768_write(priv, TC358768_SYSCTL, 0);
 236
 237         return tc358768_clear_error(priv);
 238 }
 239
 240 static void tc358768_hw_enable(struct tc358768_priv *priv)
 241 {
 242         int ret;
 243
 244         if (priv->enabled)
 245                 return;
 246
 247         ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
 248         if (ret < 0)
 249                 dev_err(priv->dev, "error enabling regulators (%d)\n", ret);
 250
 251         if (priv->reset_gpio)
 252                 usleep_range(200, 300);
 253
 254         /*
 255          * The RESX is active low (GPIO_ACTIVE_LOW).
 256          * DEASSERT (value = 0) the reset_gpio to enable the chip
 257          */
 258         gpiod_set_value_cansleep(priv->reset_gpio, 0);
 259
 260         /* wait for encoder clocks to stabilize */
 261         usleep_range(1000, 2000);
 262
 263         priv->enabled = true;
 264 }
 265
 266 static void tc358768_hw_disable(struct tc358768_priv *priv)
 267 {
 268         int ret;
 269
 270         if (!priv->enabled)
 271                 return;
 272
 273         /*
 274          * The RESX is active low (GPIO_ACTIVE_LOW).
 275          * ASSERT (value = 1) the reset_gpio to disable the chip
 276          */
 277         gpiod_set_value_cansleep(priv->reset_gpio, 1);
 278
 279         ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
 280                                      priv->supplies);
 281         if (ret < 0)
 282                 dev_err(priv->dev, "error disabling regulators (%d)\n", ret);
 283
 284         priv->enabled = false;
 285 }
 286
 287 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
 288 {
 289         return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp);
 290 }
 291
 292 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
 293 {
 294         return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
 295 }
 296
 297 static int tc358768_calc_pll(struct tc358768_priv *priv,
 298                              const struct drm_display_mode *mode,
 299                              bool verify_only)
 300 {
 301         const u32 frs_limits[] = {
 302                 1000000000,
 303                 500000000,
 304                 250000000,
 305                 125000000,
 306                 62500000
 307         };
 308         unsigned long refclk;
 309         u32 prd, target_pll, i, max_pll, min_pll;
 310         u32 frs, best_diff, best_pll, best_prd, best_fbd;
 311
 312         target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000);
 313
 314         /* pll_clk = RefClk * [(FBD + 1)/ (PRD + 1)] * [1 / (2^FRS)] */
 315
 316         for (i = 0; i < ARRAY_SIZE(frs_limits); i++)
 317                 if (target_pll >= frs_limits[i])
 318                         break;
 319
 320         if (i == ARRAY_SIZE(frs_limits) || i == 0)
 321                 return -EINVAL;
 322
 323         frs = i - 1;
 324         max_pll = frs_limits[i - 1];
 325         min_pll = frs_limits[i];
 326
 327         refclk = clk_get_rate(priv->refclk);
 328
 329         best_diff = UINT_MAX;
 330         best_pll = 0;
 331         best_prd = 0;
 332         best_fbd = 0;
 333
 334         for (prd = 0; prd < 16; ++prd) {
 335                 u32 divisor = (prd + 1) * (1 << frs);
 336                 u32 fbd;
 337
 338                 for (fbd = 0; fbd < 512; ++fbd) {
 339                         u32 pll, diff, pll_in;
 340
 341                         pll = (u32)div_u64((u64)refclk * (fbd + 1), divisor);
 342
 343                         if (pll >= max_pll || pll < min_pll)
 344                                 continue;
 345
 346                         pll_in = (u32)div_u64((u64)refclk, prd + 1);
 347                         if (pll_in < 4000000)
 348                                 continue;
 349
 350                         diff = max(pll, target_pll) - min(pll, target_pll);
 351
 352                         if (diff < best_diff) {
 353                                 best_diff = diff;
 354                                 best_pll = pll;
 355                                 best_prd = prd;
 356                                 best_fbd = fbd;
 357
 358                                 if (best_diff == 0)
 359                                         goto found;
 360                         }
 361                 }
 362         }
 363
 364         if (best_diff == UINT_MAX) {
 365                 dev_err(priv->dev, "could not find suitable PLL setup\n");
 366                 return -EINVAL;
 367         }
 368
 369 found:
 370         if (verify_only)
 371                 return 0;
 372
 373         priv->fbd = best_fbd;
 374         priv->prd = best_prd;
 375         priv->frs = frs;
 376         priv->dsiclk = best_pll / 2;
 377
 378         return 0;
 379 }
 380
 381 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host,
 382                                     struct mipi_dsi_device *dev)
 383 {
 384         struct tc358768_priv *priv = dsi_host_to_tc358768(host);
 385         struct drm_bridge *bridge;
 386         struct drm_panel *panel;
 387         struct device_node *ep;
 388         int ret;
 389
 390         if (dev->lanes > 4) {
 391                 dev_err(priv->dev, "unsupported number of data lanes(%u)\n",
 392                         dev->lanes);
 393                 return -EINVAL;
 394         }
 395
 396         /*
 397          * tc358768 supports both Video and Pulse mode, but the driver only
 398          * implements Video (event) mode currently
 399          */
 400         if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
 401                 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n");
 402                 return -ENOTSUPP;
 403         }
 404
 405         /*
 406          * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only
 407          * RGB888 is verified.
 408          */
 409         if (dev->format != MIPI_DSI_FMT_RGB888) {
 410                 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n");
 411                 return -ENOTSUPP;
 412         }
 413
 414         ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel,
 415                                           &bridge);
 416         if (ret)
 417                 return ret;
 418
 419         if (panel) {
 420                 bridge = drm_panel_bridge_add_typed(panel,
 421                                                     DRM_MODE_CONNECTOR_DSI);
 422                 if (IS_ERR(bridge))
 423                         return PTR_ERR(bridge);
 424         }
 425
 426         priv->output.dev = dev;
 427         priv->output.bridge = bridge;
 428         priv->output.panel = panel;
 429
 430         priv->dsi_lanes = dev->lanes;
 431         priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format);
 432
 433         /* get input ep (port0/endpoint0) */
 434         ret = -EINVAL;
 435         ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0);
 436         if (ep) {
 437                 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines);
 438
 439                 of_node_put(ep);
 440         }
 441
 442         if (ret)
 443                 priv->pd_lines = priv->dsi_bpp;
 444
 445         drm_bridge_add(&priv->bridge);
 446
 447         return 0;
 448 }
 449
 450 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host,
 451                                     struct mipi_dsi_device *dev)
 452 {
 453         struct tc358768_priv *priv = dsi_host_to_tc358768(host);
 454
 455         drm_bridge_remove(&priv->bridge);
 456         if (priv->output.panel)
 457                 drm_panel_bridge_remove(priv->output.bridge);
 458
 459         return 0;
 460 }
 461
 462 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host,
 463                                           const struct mipi_dsi_msg *msg)
 464 {
 465         struct tc358768_priv *priv = dsi_host_to_tc358768(host);
 466         struct mipi_dsi_packet packet;
 467         int ret;
 468
 469         if (!priv->enabled) {
 470                 dev_err(priv->dev, "Bridge is not enabled\n");
 471                 return -ENODEV;
 472         }
 473
 474         if (msg->rx_len) {
 475                 dev_warn(priv->dev, "MIPI rx is not supported\n");
 476                 return -ENOTSUPP;
 477         }
 478
 479         if (msg->tx_len > 8) {
 480                 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n");
 481                 return -ENOTSUPP;
 482         }
 483
 484         ret = mipi_dsi_create_packet(&packet, msg);
 485         if (ret)
 486                 return ret;
 487
 488         if (mipi_dsi_packet_format_is_short(msg->type)) {
 489                 tc358768_write(priv, TC358768_DSICMD_TYPE,
 490                                (0x10 << 8) | (packet.header[0] & 0x3f));
 491                 tc358768_write(priv, TC358768_DSICMD_WC, 0);
 492                 tc358768_write(priv, TC358768_DSICMD_WD0,
 493                                (packet.header[2] << 8) | packet.header[1]);
 494         } else {
 495                 int i;
 496
 497                 tc358768_write(priv, TC358768_DSICMD_TYPE,
 498                                (0x40 << 8) | (packet.header[0] & 0x3f));
 499                 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length);
 500                 for (i = 0; i < packet.payload_length; i += 2) {
 501                         u16 val = packet.payload[i];
 502
 503                         if (i + 1 < packet.payload_length)
 504                                 val |= packet.payload[i + 1] << 8;
 505
 506                         tc358768_write(priv, TC358768_DSICMD_WD0 + i, val);
 507                 }
 508         }
 509
 510         /* start transfer */
 511         tc358768_write(priv, TC358768_DSICMD_TX, 1);
 512
 513         ret = tc358768_clear_error(priv);
 514         if (ret)
 515                 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
 516         else
 517                 ret = packet.size;
 518
 519         return ret;
 520 }
 521
 522 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = {
 523         .attach = tc358768_dsi_host_attach,
 524         .detach = tc358768_dsi_host_detach,
 525         .transfer = tc358768_dsi_host_transfer,
 526 };
 527
 528 static int tc358768_bridge_attach(struct drm_bridge *bridge,
 529                                   enum drm_bridge_attach_flags flags)
 530 {
 531         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 532
 533         if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) {
 534                 dev_err(priv->dev, "needs atomic updates support\n");
 535                 return -ENOTSUPP;
 536         }
 537
 538         return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge,
 539                                  flags);
 540 }
 541
 542 static enum drm_mode_status
 543 tc358768_bridge_mode_valid(struct drm_bridge *bridge,
 544                            const struct drm_display_info *info,
 545                            const struct drm_display_mode *mode)
 546 {
 547         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 548
 549         if (tc358768_calc_pll(priv, mode, true))
 550                 return MODE_CLOCK_RANGE;
 551
 552         return MODE_OK;
 553 }
 554
 555 static void tc358768_bridge_disable(struct drm_bridge *bridge)
 556 {
 557         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 558         int ret;
 559
 560         /* set FrmStop */
 561         tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15));
 562
 563         /* wait at least for one frame */
 564         msleep(50);
 565
 566         /* clear PP_en */
 567         tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0);
 568
 569         /* set RstPtr */
 570         tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14));
 571
 572         ret = tc358768_clear_error(priv);
 573         if (ret)
 574                 dev_warn(priv->dev, "Software disable failed: %d\n", ret);
 575 }
 576
 577 static void tc358768_bridge_post_disable(struct drm_bridge *bridge)
 578 {
 579         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 580
 581         tc358768_hw_disable(priv);
 582 }
 583
 584 static int tc358768_setup_pll(struct tc358768_priv *priv,
 585                               const struct drm_display_mode *mode)
 586 {
 587         u32 fbd, prd, frs;
 588         int ret;
 589
 590         ret = tc358768_calc_pll(priv, mode, false);
 591         if (ret) {
 592                 dev_err(priv->dev, "PLL calculation failed: %d\n", ret);
 593                 return ret;
 594         }
 595
 596         fbd = priv->fbd;
 597         prd = priv->prd;
 598         frs = priv->frs;
 599
 600         dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
 601                 clk_get_rate(priv->refclk), fbd, prd, frs);
 602         dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, DSIByteClk %u\n",
 603                 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4);
 604         dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n",
 605                 tc358768_pll_to_pclk(priv, priv->dsiclk * 2),
 606                 mode->clock * 1000);
 607
 608         /* PRD[15:12] FBD[8:0] */
 609         tc358768_write(priv, TC358768_PLLCTL0, (prd << 12) | fbd);
 610
 611         /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */
 612         tc358768_write(priv, TC358768_PLLCTL1,
 613                        (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
 614
 615         /* wait for lock */
 616         usleep_range(1000, 2000);
 617
 618         /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */
 619         tc358768_write(priv, TC358768_PLLCTL1,
 620                        (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));
 621
 622         return tc358768_clear_error(priv);
 623 }
 624
 625 #define TC358768_PRECISION      1000
 626 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_nsk)
 627 {
 628         return (ns * TC358768_PRECISION + period_nsk) / period_nsk;
 629 }
 630
 631 static u32 tc358768_to_ns(u32 nsk)
 632 {
 633         return (nsk / TC358768_PRECISION);
 634 }
 635
 636 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge)
 637 {
 638         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 639         struct mipi_dsi_device *dsi_dev = priv->output.dev;
 640         unsigned long mode_flags = dsi_dev->mode_flags;
 641         u32 val, val2, lptxcnt, hact, data_type;
 642         s32 raw_val;
 643         const struct drm_display_mode *mode;
 644         u32 dsibclk_nsk, dsiclk_nsk, ui_nsk, phy_delay_nsk;
 645         u32 dsiclk, dsibclk;
 646         int ret, i;
 647
 648         if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
 649                 dev_warn_once(priv->dev, "Non-continuous mode unimplemented, falling back to continuous\n");
 650                 mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS;
 651         }
 652
 653         tc358768_hw_enable(priv);
 654
 655         ret = tc358768_sw_reset(priv);
 656         if (ret) {
 657                 dev_err(priv->dev, "Software reset failed: %d\n", ret);
 658                 tc358768_hw_disable(priv);
 659                 return;
 660         }
 661
 662         mode = &bridge->encoder->crtc->state->adjusted_mode;
 663         ret = tc358768_setup_pll(priv, mode);
 664         if (ret) {
 665                 dev_err(priv->dev, "PLL setup failed: %d\n", ret);
 666                 tc358768_hw_disable(priv);
 667                 return;
 668         }
 669
 670         dsiclk = priv->dsiclk;
 671         dsibclk = dsiclk / 4;
 672
 673         /* Data Format Control Register */
 674         val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */
 675         switch (dsi_dev->format) {
 676         case MIPI_DSI_FMT_RGB888:
 677                 val |= (0x3 << 4);
 678                 hact = mode->hdisplay * 3;
 679                 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
 680                 break;
 681         case MIPI_DSI_FMT_RGB666:
 682                 val |= (0x4 << 4);
 683                 hact = mode->hdisplay * 3;
 684                 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
 685                 break;
 686
 687         case MIPI_DSI_FMT_RGB666_PACKED:
 688                 val |= (0x4 << 4) | BIT(3);
 689                 hact = mode->hdisplay * 18 / 8;
 690                 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
 691                 break;
 692
 693         case MIPI_DSI_FMT_RGB565:
 694                 val |= (0x5 << 4);
 695                 hact = mode->hdisplay * 2;
 696                 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
 697                 break;
 698         default:
 699                 dev_err(priv->dev, "Invalid data format (%u)\n",
 700                         dsi_dev->format);
 701                 tc358768_hw_disable(priv);
 702                 return;
 703         }
 704
 705         /* VSDly[9:0] */
 706         tc358768_write(priv, TC358768_VSDLY, 1);
 707
 708         tc358768_write(priv, TC358768_DATAFMT, val);
 709         tc358768_write(priv, TC358768_DSITX_DT, data_type);
 710
 711         /* Enable D-PHY (HiZ->LP11) */
 712         tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000);
 713         /* Enable lanes */
 714         for (i = 0; i < dsi_dev->lanes; i++)
 715                 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000);
 716
 717         /* DSI Timings */
 718         dsibclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION,
 719                                   dsibclk);
 720         dsiclk_nsk = (u32)div_u64((u64)1000000000 * TC358768_PRECISION, dsiclk);
 721         ui_nsk = dsiclk_nsk / 2;
 722         phy_delay_nsk = dsibclk_nsk + 2 * dsiclk_nsk;
 723         dev_dbg(priv->dev, "dsiclk_nsk: %u\n", dsiclk_nsk);
 724         dev_dbg(priv->dev, "ui_nsk: %u\n", ui_nsk);
 725         dev_dbg(priv->dev, "dsibclk_nsk: %u\n", dsibclk_nsk);
 726         dev_dbg(priv->dev, "phy_delay_nsk: %u\n", phy_delay_nsk);
 727
 728         /* LP11 > 100us for D-PHY Rx Init */
 729         val = tc358768_ns_to_cnt(100 * 1000, dsibclk_nsk) - 1;
 730         dev_dbg(priv->dev, "LINEINITCNT: 0x%x\n", val);
 731         tc358768_write(priv, TC358768_LINEINITCNT, val);
 732
 733         /* LPTimeCnt > 50ns */
 734         val = tc358768_ns_to_cnt(50, dsibclk_nsk) - 1;
 735         lptxcnt = val;
 736         dev_dbg(priv->dev, "LPTXTIMECNT: 0x%x\n", val);
 737         tc358768_write(priv, TC358768_LPTXTIMECNT, val);
 738
 739         /* 38ns < TCLK_PREPARE < 95ns */
 740         val = tc358768_ns_to_cnt(65, dsibclk_nsk) - 1;
 741         /* TCLK_PREPARE + TCLK_ZERO > 300ns */
 742         val2 = tc358768_ns_to_cnt(300 - tc358768_to_ns(2 * ui_nsk),
 743                                   dsibclk_nsk) - 2;
 744         val |= val2 << 8;
 745         dev_dbg(priv->dev, "TCLK_HEADERCNT: 0x%x\n", val);
 746         tc358768_write(priv, TC358768_TCLK_HEADERCNT, val);
 747
 748         /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */
 749         raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(2 * ui_nsk), dsibclk_nsk) - 5;
 750         val = clamp(raw_val, 0, 127);
 751         dev_dbg(priv->dev, "TCLK_TRAILCNT: 0x%x\n", val);
 752         tc358768_write(priv, TC358768_TCLK_TRAILCNT, val);
 753
 754         /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */
 755         val = 50 + tc358768_to_ns(4 * ui_nsk);
 756         val = tc358768_ns_to_cnt(val, dsibclk_nsk) - 1;
 757         /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */
 758         raw_val = tc358768_ns_to_cnt(145 - tc358768_to_ns(3 * ui_nsk), dsibclk_nsk) - 10;
 759         val2 = clamp(raw_val, 0, 127);
 760         val |= val2 << 8;
 761         dev_dbg(priv->dev, "THS_HEADERCNT: 0x%x\n", val);
 762         tc358768_write(priv, TC358768_THS_HEADERCNT, val);
 763
 764         /* TWAKEUP > 1ms in lptxcnt steps */
 765         val = tc358768_ns_to_cnt(1020000, dsibclk_nsk);
 766         val = val / (lptxcnt + 1) - 1;
 767         dev_dbg(priv->dev, "TWAKEUP: 0x%x\n", val);
 768         tc358768_write(priv, TC358768_TWAKEUP, val);
 769
 770         /* TCLK_POSTCNT > 60ns + 52*UI */
 771         val = tc358768_ns_to_cnt(60 + tc358768_to_ns(52 * ui_nsk),
 772                                  dsibclk_nsk) - 3;
 773         dev_dbg(priv->dev, "TCLK_POSTCNT: 0x%x\n", val);
 774         tc358768_write(priv, TC358768_TCLK_POSTCNT, val);
 775
 776         /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */
 777         raw_val = tc358768_ns_to_cnt(60 + tc358768_to_ns(18 * ui_nsk),
 778                                      dsibclk_nsk) - 4;
 779         val = clamp(raw_val, 0, 15);
 780         dev_dbg(priv->dev, "THS_TRAILCNT: 0x%x\n", val);
 781         tc358768_write(priv, TC358768_THS_TRAILCNT, val);
 782
 783         val = BIT(0);
 784         for (i = 0; i < dsi_dev->lanes; i++)
 785                 val |= BIT(i + 1);
 786         tc358768_write(priv, TC358768_HSTXVREGEN, val);
 787
 788         tc358768_write(priv, TC358768_TXOPTIONCNTRL,
 789                        (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0));
 790
 791         /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */
 792         val = tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk * 4);
 793         val = tc358768_ns_to_cnt(val, dsibclk_nsk) / 4 - 1;
 794         val2 = tc358768_ns_to_cnt(tc358768_to_ns((lptxcnt + 1) * dsibclk_nsk),
 795                                   dsibclk_nsk) - 2;
 796         val |= val2 << 16;
 797         dev_dbg(priv->dev, "BTACNTRL1: 0x%x\n", val);
 798         tc358768_write(priv, TC358768_BTACNTRL1, val);
 799
 800         /* START[0] */
 801         tc358768_write(priv, TC358768_STARTCNTRL, 1);
 802
 803         /* Set event mode */
 804         tc358768_write(priv, TC358768_DSI_EVENT, 1);
 805
 806         /* vsw (+ vbp) */
 807         tc358768_write(priv, TC358768_DSI_VSW,
 808                        mode->vtotal - mode->vsync_start);
 809         /* vbp (not used in event mode) */
 810         tc358768_write(priv, TC358768_DSI_VBPR, 0);
 811         /* vact */
 812         tc358768_write(priv, TC358768_DSI_VACT, mode->vdisplay);
 813
 814         /* (hsw + hbp) * byteclk * ndl / pclk */
 815         val = (u32)div_u64((mode->htotal - mode->hsync_start) *
 816                            ((u64)priv->dsiclk / 4) * priv->dsi_lanes,
 817                            mode->clock * 1000);
 818         tc358768_write(priv, TC358768_DSI_HSW, val);
 819         /* hbp (not used in event mode) */
 820         tc358768_write(priv, TC358768_DSI_HBPR, 0);
 821         /* hact (bytes) */
 822         tc358768_write(priv, TC358768_DSI_HACT, hact);
 823
 824         /* VSYNC polarity */
 825         tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5),
 826                              (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0);
 827
 828         /* HSYNC polarity */
 829         tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0),
 830                              (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0);
 831
 832         /* Start DSI Tx */
 833         tc358768_write(priv, TC358768_DSI_START, 0x1);
 834
 835         /* Configure DSI_Control register */
 836         val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
 837         val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD |
 838                0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS;
 839         tc358768_write(priv, TC358768_DSI_CONFW, val);
 840
 841         val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
 842         val |= (dsi_dev->lanes - 1) << 1;
 843
 844         val |= TC358768_DSI_CONTROL_TXMD;
 845
 846         if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
 847                 val |= TC358768_DSI_CONTROL_HSCKMD;
 848
 849         if (dsi_dev->mode_flags & MIPI_DSI_MODE_EOT_PACKET)
 850                 val |= TC358768_DSI_CONTROL_EOTDIS;
 851
 852         tc358768_write(priv, TC358768_DSI_CONFW, val);
 853
 854         val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL;
 855         val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */
 856         tc358768_write(priv, TC358768_DSI_CONFW, val);
 857
 858         ret = tc358768_clear_error(priv);
 859         if (ret) {
 860                 dev_err(priv->dev, "Bridge pre_enable failed: %d\n", ret);
 861                 tc358768_bridge_disable(bridge);
 862                 tc358768_bridge_post_disable(bridge);
 863         }
 864 }
 865
 866 static void tc358768_bridge_enable(struct drm_bridge *bridge)
 867 {
 868         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 869         int ret;
 870
 871         if (!priv->enabled) {
 872                 dev_err(priv->dev, "Bridge is not enabled\n");
 873                 return;
 874         }
 875
 876         /* clear FrmStop and RstPtr */
 877         tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0);
 878
 879         /* set PP_en */
 880         tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6));
 881
 882         ret = tc358768_clear_error(priv);
 883         if (ret) {
 884                 dev_err(priv->dev, "Bridge enable failed: %d\n", ret);
 885                 tc358768_bridge_disable(bridge);
 886                 tc358768_bridge_post_disable(bridge);
 887         }
 888 }
 889
 890 #define MAX_INPUT_SEL_FORMATS   1
 891
 892 static u32 *
 893 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
 894                                    struct drm_bridge_state *bridge_state,
 895                                    struct drm_crtc_state *crtc_state,
 896                                    struct drm_connector_state *conn_state,
 897                                    u32 output_fmt,
 898                                    unsigned int *num_input_fmts)
 899 {
 900         struct tc358768_priv *priv = bridge_to_tc358768(bridge);
 901         u32 *input_fmts;
 902
 903         *num_input_fmts = 0;
 904
 905         input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts),
 906                              GFP_KERNEL);
 907         if (!input_fmts)
 908                 return NULL;
 909
 910         switch (priv->pd_lines) {
 911         case 16:
 912                 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16;
 913                 break;
 914         case 18:
 915                 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18;
 916                 break;
 917         default:
 918         case 24:
 919                 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
 920                 break;
 921         };
 922
 923         *num_input_fmts = MAX_INPUT_SEL_FORMATS;
 924
 925         return input_fmts;
 926 }
 927
 928 static const struct drm_bridge_funcs tc358768_bridge_funcs = {
 929         .attach = tc358768_bridge_attach,
 930         .mode_valid = tc358768_bridge_mode_valid,
 931         .pre_enable = tc358768_bridge_pre_enable,
 932         .enable = tc358768_bridge_enable,
 933         .disable = tc358768_bridge_disable,
 934         .post_disable = tc358768_bridge_post_disable,
 935
 936         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
 937         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
 938         .atomic_reset = drm_atomic_helper_bridge_reset,
 939         .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts,
 940 };
 941
 942 static const struct drm_bridge_timings default_tc358768_timings = {
 943         .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
 944                  | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE
 945                  | DRM_BUS_FLAG_DE_HIGH,
 946 };
 947
 948 static bool tc358768_is_reserved_reg(unsigned int reg)
 949 {
 950         switch (reg) {
 951         case 0x114 ... 0x13f:
 952         case 0x200:
 953         case 0x20c:
 954         case 0x400 ... 0x408:
 955         case 0x41c ... 0x42f:
 956                 return true;
 957         default:
 958                 return false;
 959         }
 960 }
 961
 962 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg)
 963 {
 964         if (tc358768_is_reserved_reg(reg))
 965                 return false;
 966
 967         switch (reg) {
 968         case TC358768_CHIPID:
 969         case TC358768_FIFOSTATUS:
 970         case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2):
 971         case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2):
 972         case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2):
 973                 return false;
 974         default:
 975                 return true;
 976         }
 977 }
 978
 979 static bool tc358768_readable_reg(struct device *dev, unsigned int reg)
 980 {
 981         if (tc358768_is_reserved_reg(reg))
 982                 return false;
 983
 984         switch (reg) {
 985         case TC358768_STARTCNTRL:
 986         case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2):
 987         case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2):
 988         case TC358768_DSI_START ... (TC358768_DSI_START + 2):
 989         case TC358768_DBG_DATA:
 990                 return false;
 991         default:
 992                 return true;
 993         }
 994 }
 995
 996 static const struct regmap_config tc358768_regmap_config = {
 997         .name = "tc358768",
 998         .reg_bits = 16,
 999         .val_bits = 16,
1000         .max_register = TC358768_DSI_HACT,
1001         .cache_type = REGCACHE_NONE,
1002         .writeable_reg = tc358768_writeable_reg,
1003         .readable_reg = tc358768_readable_reg,
1004         .reg_format_endian = REGMAP_ENDIAN_BIG,
1005         .val_format_endian = REGMAP_ENDIAN_BIG,
1006 };
1007
1008 static const struct i2c_device_id tc358768_i2c_ids[] = {
1009         { "tc358768", 0 },
1010         { "tc358778", 0 },
1011         { }
1012 };
1013 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids);
1014
1015 static const struct of_device_id tc358768_of_ids[] = {
1016         { .compatible = "toshiba,tc358768", },
1017         { .compatible = "toshiba,tc358778", },
1018         { }
1019 };
1020 MODULE_DEVICE_TABLE(of, tc358768_of_ids);
1021
1022 static int tc358768_get_regulators(struct tc358768_priv *priv)
1023 {
1024         int i, ret;
1025
1026         for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i)
1027                 priv->supplies[i].supply = tc358768_supplies[i];
1028
1029         ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies),
1030                                       priv->supplies);
1031         if (ret < 0)
1032                 dev_err(priv->dev, "failed to get regulators: %d\n", ret);
1033
1034         return ret;
1035 }
1036
1037 static int tc358768_i2c_probe(struct i2c_client *client,
1038                               const struct i2c_device_id *id)
1039 {
1040         struct tc358768_priv *priv;
1041         struct device *dev = &client->dev;
1042         struct device_node *np = dev->of_node;
1043         int ret;
1044
1045         if (!np)
1046                 return -ENODEV;
1047
1048         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1049         if (!priv)
1050                 return -ENOMEM;
1051
1052         dev_set_drvdata(dev, priv);
1053         priv->dev = dev;
1054
1055         ret = tc358768_get_regulators(priv);
1056         if (ret)
1057                 return ret;
1058
1059         priv->refclk = devm_clk_get(dev, "refclk");
1060         if (IS_ERR(priv->refclk))
1061                 return PTR_ERR(priv->refclk);
1062
1063         /*
1064          * RESX is low active, to disable tc358768 initially (keep in reset)
1065          * the gpio line must be LOW. This is the ASSERTED state of
1066          * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED).
1067          */
1068         priv->reset_gpio  = devm_gpiod_get_optional(dev, "reset",
1069                                                     GPIOD_OUT_HIGH);
1070         if (IS_ERR(priv->reset_gpio))
1071                 return PTR_ERR(priv->reset_gpio);
1072
1073         priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config);
1074         if (IS_ERR(priv->regmap)) {
1075                 dev_err(dev, "Failed to init regmap\n");
1076                 return PTR_ERR(priv->regmap);
1077         }
1078
1079         priv->dsi_host.dev = dev;
1080         priv->dsi_host.ops = &tc358768_dsi_host_ops;
1081
1082         priv->bridge.funcs = &tc358768_bridge_funcs;
1083         priv->bridge.timings = &default_tc358768_timings;
1084         priv->bridge.of_node = np;
1085
1086         i2c_set_clientdata(client, priv);
1087
1088         return mipi_dsi_host_register(&priv->dsi_host);
1089 }
1090
1091 static int tc358768_i2c_remove(struct i2c_client *client)
1092 {
1093         struct tc358768_priv *priv = i2c_get_clientdata(client);
1094
1095         mipi_dsi_host_unregister(&priv->dsi_host);
1096
1097         return 0;
1098 }
1099
1100 static struct i2c_driver tc358768_driver = {
1101         .driver = {
1102                 .name = "tc358768",
1103                 .of_match_table = tc358768_of_ids,
1104         },
1105         .id_table = tc358768_i2c_ids,
1106         .probe = tc358768_i2c_probe,
1107         .remove = tc358768_i2c_remove,
1108 };
1109 module_i2c_driver(tc358768_driver);
1110
1111 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
1112 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge");
1113 MODULE_LICENSE("GPL v2");