2 * tc358767 eDP bridge driver
4 * Copyright (C) 2016 CogentEmbedded Inc
5 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com>
7 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de>
9 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c
11 * Copyright (C) 2012 Texas Instruments
12 * Author: Rob Clark <robdclark@gmail.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
25 #include <linux/clk.h>
26 #include <linux/device.h>
27 #include <linux/gpio/consumer.h>
28 #include <linux/i2c.h>
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/regmap.h>
32 #include <linux/slab.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc_helper.h>
36 #include <drm/drm_dp_helper.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_of.h>
39 #include <drm/drm_panel.h>
43 /* Display Parallel Interface */
44 #define DPIPXLFMT 0x0440
45 #define VS_POL_ACTIVE_LOW (1 << 10)
46 #define HS_POL_ACTIVE_LOW (1 << 9)
47 #define DE_POL_ACTIVE_HIGH (0 << 8)
48 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */
49 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */
50 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */
51 #define DPI_BPP_RGB888 (0 << 0)
52 #define DPI_BPP_RGB666 (1 << 0)
53 #define DPI_BPP_RGB565 (2 << 0)
56 #define VPCTRL0 0x0450
57 #define OPXLFMT_RGB666 (0 << 8)
58 #define OPXLFMT_RGB888 (1 << 8)
59 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */
60 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */
61 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */
62 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */
68 #define VFUEN BIT(0) /* Video Frame Timing Upload */
71 #define TC_IDREG 0x0500
72 #define SYSCTRL 0x0510
73 #define DP0_AUDSRC_NO_INPUT (0 << 3)
74 #define DP0_AUDSRC_I2S_RX (1 << 3)
75 #define DP0_VIDSRC_NO_INPUT (0 << 0)
76 #define DP0_VIDSRC_DSI_RX (1 << 0)
77 #define DP0_VIDSRC_DPI_RX (2 << 0)
78 #define DP0_VIDSRC_COLOR_BAR (3 << 0)
82 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */
83 #define EF_EN BIT(5) /* Enable Enhanced Framing */
84 #define VID_EN BIT(1) /* Video transmission enable */
85 #define DP_EN BIT(0) /* Enable DPTX function */
88 #define DP0_VIDMNGEN0 0x0610
89 #define DP0_VIDMNGEN1 0x0614
90 #define DP0_VMNGENSTATUS 0x0618
93 #define DP0_SECSAMPLE 0x0640
94 #define DP0_VIDSYNCDELAY 0x0644
95 #define DP0_TOTALVAL 0x0648
96 #define DP0_STARTVAL 0x064c
97 #define DP0_ACTIVEVAL 0x0650
98 #define DP0_SYNCVAL 0x0654
99 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15)
100 #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31)
101 #define DP0_MISC 0x0658
102 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */
103 #define BPC_6 (0 << 5)
104 #define BPC_8 (1 << 5)
107 #define DP0_AUXCFG0 0x0660
108 #define DP0_AUXCFG1 0x0664
109 #define AUX_RX_FILTER_EN BIT(16)
111 #define DP0_AUXADDR 0x0668
112 #define DP0_AUXWDATA(i) (0x066c + (i) * 4)
113 #define DP0_AUXRDATA(i) (0x067c + (i) * 4)
114 #define DP0_AUXSTATUS 0x068c
115 #define AUX_STATUS_MASK 0xf0
116 #define AUX_STATUS_SHIFT 4
117 #define AUX_TIMEOUT BIT(1)
118 #define AUX_BUSY BIT(0)
119 #define DP0_AUXI2CADR 0x0698
122 #define DP0_SRCCTRL 0x06a0
123 #define DP0_SRCCTRL_SCRMBLDIS BIT(13)
124 #define DP0_SRCCTRL_EN810B BIT(12)
125 #define DP0_SRCCTRL_NOTP (0 << 8)
126 #define DP0_SRCCTRL_TP1 (1 << 8)
127 #define DP0_SRCCTRL_TP2 (2 << 8)
128 #define DP0_SRCCTRL_LANESKEW BIT(7)
129 #define DP0_SRCCTRL_SSCG BIT(3)
130 #define DP0_SRCCTRL_LANES_1 (0 << 2)
131 #define DP0_SRCCTRL_LANES_2 (1 << 2)
132 #define DP0_SRCCTRL_BW27 (1 << 1)
133 #define DP0_SRCCTRL_BW162 (0 << 1)
134 #define DP0_SRCCTRL_AUTOCORRECT BIT(0)
135 #define DP0_LTSTAT 0x06d0
136 #define LT_LOOPDONE BIT(13)
137 #define LT_STATUS_MASK (0x1f << 8)
138 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4)
139 #define LT_INTERLANE_ALIGN_DONE BIT(3)
140 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS)
141 #define DP0_SNKLTCHGREQ 0x06d4
142 #define DP0_LTLOOPCTRL 0x06d8
143 #define DP0_SNKLTCTRL 0x06e4
145 #define DP1_SRCCTRL 0x07a0
148 #define DP_PHY_CTRL 0x0800
149 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */
150 #define BGREN BIT(25) /* AUX PHY BGR Enable */
151 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */
152 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */
153 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */
154 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */
155 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */
156 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */
157 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */
160 #define DP0_PLLCTRL 0x0900
161 #define DP1_PLLCTRL 0x0904 /* not defined in DS */
162 #define PXL_PLLCTRL 0x0908
163 #define PLLUPDATE BIT(2)
164 #define PLLBYP BIT(1)
166 #define PXL_PLLPARAM 0x0914
167 #define IN_SEL_REFCLK (0 << 14)
168 #define SYS_PLLPARAM 0x0918
169 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */
170 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */
171 #define REF_FREQ_26M (2 << 8) /* 26 MHz */
172 #define REF_FREQ_13M (3 << 8) /* 13 MHz */
173 #define SYSCLK_SEL_LSCLK (0 << 4)
174 #define LSCLK_DIV_1 (0 << 0)
175 #define LSCLK_DIV_2 (1 << 0)
178 #define TSTCTL 0x0a00
179 #define PLL_DBG 0x0a04
181 static bool tc_test_pattern;
182 module_param_named(test, tc_test_pattern, bool, 0644);
185 struct drm_dp_link base;
196 struct regmap *regmap;
197 struct drm_dp_aux aux;
199 struct drm_bridge bridge;
200 struct drm_connector connector;
201 struct drm_panel *panel;
204 struct tc_edp_link link;
209 struct drm_display_mode *mode;
214 struct gpio_desc *sd_gpio;
215 struct gpio_desc *reset_gpio;
219 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a)
221 return container_of(a, struct tc_data, aux);
224 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
226 return container_of(b, struct tc_data, bridge);
229 static inline struct tc_data *connector_to_tc(struct drm_connector *c)
231 return container_of(c, struct tc_data, connector);
234 /* Simple macros to avoid repeated error checks */
235 #define tc_write(reg, var) \
237 ret = regmap_write(tc->regmap, reg, var); \
241 #define tc_read(reg, var) \
243 ret = regmap_read(tc->regmap, reg, var); \
248 static inline int tc_poll_timeout(struct regmap *map, unsigned int addr,
249 unsigned int cond_mask,
250 unsigned int cond_value,
251 unsigned long sleep_us, u64 timeout_us)
253 ktime_t timeout = ktime_add_us(ktime_get(), timeout_us);
258 ret = regmap_read(map, addr, &val);
261 if ((val & cond_mask) == cond_value)
263 if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) {
264 ret = regmap_read(map, addr, &val);
268 usleep_range((sleep_us >> 2) + 1, sleep_us);
270 return ret ?: (((val & cond_mask) == cond_value) ? 0 : -ETIMEDOUT);
273 static int tc_aux_wait_busy(struct tc_data *tc, unsigned int timeout_ms)
275 return tc_poll_timeout(tc->regmap, DP0_AUXSTATUS, AUX_BUSY, 0,
276 1000, 1000 * timeout_ms);
279 static int tc_aux_get_status(struct tc_data *tc, u8 *reply)
284 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &value);
287 if (value & AUX_BUSY) {
288 if (value & AUX_TIMEOUT) {
289 dev_err(tc->dev, "i2c access timeout!\n");
295 *reply = (value & AUX_STATUS_MASK) >> AUX_STATUS_SHIFT;
299 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux,
300 struct drm_dp_aux_msg *msg)
302 struct tc_data *tc = aux_to_tc(aux);
303 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size);
304 u8 request = msg->request & ~DP_AUX_I2C_MOT;
305 u8 *buf = msg->buffer;
313 ret = tc_aux_wait_busy(tc, 100);
317 if (request == DP_AUX_I2C_WRITE || request == DP_AUX_NATIVE_WRITE) {
320 if (request == DP_AUX_NATIVE_WRITE)
321 tmp = tmp | (buf[i] << (8 * (i & 0x3)));
323 tmp = (tmp << 8) | buf[i];
325 if (((i % 4) == 0) || (i == size)) {
326 tc_write(DP0_AUXWDATA((i - 1) >> 2), tmp);
330 } else if (request != DP_AUX_I2C_READ &&
331 request != DP_AUX_NATIVE_READ) {
336 tc_write(DP0_AUXADDR, msg->address);
338 tc_write(DP0_AUXCFG0, ((size - 1) << 8) | request);
340 ret = tc_aux_wait_busy(tc, 100);
344 ret = tc_aux_get_status(tc, &msg->reply);
348 if (request == DP_AUX_I2C_READ || request == DP_AUX_NATIVE_READ) {
352 tc_read(DP0_AUXRDATA(i >> 2), &tmp);
364 static const char * const training_pattern1_errors[] = {
368 "Max voltage reached error",
369 "Loop counter expired error",
373 static const char * const training_pattern2_errors[] = {
377 "Clock recovery failed error",
378 "Loop counter expired error",
382 static u32 tc_srcctrl(struct tc_data *tc)
385 * No training pattern, skew lane 1 data by two LSCLK cycles with
386 * respect to lane 0 data, AutoCorrect Mode = 0
388 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW;
390 if (tc->link.scrambler_dis)
391 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */
392 if (tc->link.coding8b10b)
393 /* Enable 8/10B Encoder (TxData[19:16] not used) */
394 reg |= DP0_SRCCTRL_EN810B;
396 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */
397 if (tc->link.base.num_lanes == 2)
398 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */
399 if (tc->link.base.rate != 162000)
400 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */
404 static void tc_wait_pll_lock(struct tc_data *tc)
406 /* Wait for PLL to lock: up to 2.09 ms, depending on refclk */
407 usleep_range(3000, 6000);
410 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
413 int i_pre, best_pre = 1;
414 int i_post, best_post = 1;
415 int div, best_div = 1;
416 int mul, best_mul = 1;
417 int delta, best_delta;
418 int ext_div[] = {1, 2, 3, 5, 7};
419 int best_pixelclock = 0;
422 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
424 best_delta = pixelclock;
425 /* Loop over all possible ext_divs, skipping invalid configurations */
426 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) {
428 * refclk / ext_pre_div should be in the 1 to 200 MHz range.
429 * We don't allow any refclk > 200 MHz, only check lower bounds.
431 if (refclk / ext_div[i_pre] < 1000000)
433 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) {
434 for (div = 1; div <= 16; div++) {
438 tmp = pixelclock * ext_div[i_pre] *
439 ext_div[i_post] * div;
444 if ((mul < 1) || (mul > 128))
447 clk = (refclk / ext_div[i_pre] / div) * mul;
449 * refclk * mul / (ext_pre_div * pre_div)
450 * should be in the 150 to 650 MHz range
452 if ((clk > 650000000) || (clk < 150000000))
455 clk = clk / ext_div[i_post];
456 delta = clk - pixelclock;
458 if (abs(delta) < abs(best_delta)) {
464 best_pixelclock = clk;
469 if (best_pixelclock == 0) {
470 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
475 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
477 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
478 ext_div[best_pre], best_div, best_mul, ext_div[best_post]);
480 /* if VCO >= 300 MHz */
481 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000)
489 /* Power up PLL and switch to bypass */
490 tc_write(PXL_PLLCTRL, PLLBYP | PLLEN);
492 tc_write(PXL_PLLPARAM,
493 (vco_hi << 24) | /* For PLL VCO >= 300 MHz = 1 */
494 (ext_div[best_pre] << 20) | /* External Pre-divider */
495 (ext_div[best_post] << 16) | /* External Post-divider */
496 IN_SEL_REFCLK | /* Use RefClk as PLL input */
497 (best_div << 8) | /* Divider for PLL RefClk */
498 (best_mul << 0)); /* Multiplier for PLL */
500 /* Force PLL parameter update and disable bypass */
501 tc_write(PXL_PLLCTRL, PLLUPDATE | PLLEN);
503 tc_wait_pll_lock(tc);
510 static int tc_pxl_pll_dis(struct tc_data *tc)
512 /* Enable PLL bypass, power down PLL */
513 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
516 static int tc_stream_clock_calc(struct tc_data *tc)
520 * If the Stream clock and Link Symbol clock are
521 * asynchronous with each other, the value of M changes over
522 * time. This way of generating link clock and stream
523 * clock is called Asynchronous Clock mode. The value M
524 * must change while the value N stays constant. The
525 * value of N in this Asynchronous Clock mode must be set
528 * LSCLK = 1/10 of high speed link clock
530 * f_STRMCLK = M/N * f_LSCLK
531 * M/N = f_STRMCLK / f_LSCLK
534 tc_write(DP0_VIDMNGEN1, 32768);
541 static int tc_aux_link_setup(struct tc_data *tc)
548 rate = clk_get_rate(tc->refclk);
551 value = REF_FREQ_38M4;
554 value = REF_FREQ_26M;
557 value = REF_FREQ_19M2;
560 value = REF_FREQ_13M;
563 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
567 /* Setup DP-PHY / PLL */
568 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
569 tc_write(SYS_PLLPARAM, value);
571 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN;
572 if (tc->link.base.num_lanes == 2)
573 dp_phy_ctrl |= PHY_2LANE;
574 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
577 * Initially PLLs are in bypass. Force PLL parameter update,
578 * disable PLL bypass, enable PLL
580 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
581 tc_wait_pll_lock(tc);
583 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
584 tc_wait_pll_lock(tc);
586 ret = tc_poll_timeout(tc->regmap, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 1,
588 if (ret == -ETIMEDOUT) {
589 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
595 tc_write(DP0_AUXCFG1, AUX_RX_FILTER_EN |
596 (0x06 << 8) | /* Aux Bit Period Calculator Threshold */
597 (0x3f << 0)); /* Aux Response Timeout Timer */
601 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
605 static int tc_get_display_props(struct tc_data *tc)
611 /* Read DP Rx Link Capability */
612 ret = drm_dp_link_probe(&tc->aux, &tc->link.base);
615 if (tc->link.base.rate != 162000 && tc->link.base.rate != 270000) {
616 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
617 tc->link.base.rate = 270000;
620 if (tc->link.base.num_lanes > 2) {
621 dev_dbg(tc->dev, "Falling to 2 lanes\n");
622 tc->link.base.num_lanes = 2;
625 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, tmp);
628 tc->link.spread = tmp[0] & BIT(0); /* 0.5% down spread */
630 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp);
633 tc->link.coding8b10b = tmp[0] & BIT(0);
634 tc->link.scrambler_dis = 0;
636 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp);
639 tc->link.assr = tmp[0] & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
641 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
642 tc->link.base.revision >> 4, tc->link.base.revision & 0x0f,
643 (tc->link.base.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
644 tc->link.base.num_lanes,
645 (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ?
646 "enhanced" : "non-enhanced");
647 dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b);
648 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
649 tc->link.assr, tc->assr);
654 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
658 static int tc_set_video_mode(struct tc_data *tc, struct drm_display_mode *mode)
664 int left_margin = mode->htotal - mode->hsync_end;
665 int right_margin = mode->hsync_start - mode->hdisplay;
666 int hsync_len = mode->hsync_end - mode->hsync_start;
667 int upper_margin = mode->vtotal - mode->vsync_end;
668 int lower_margin = mode->vsync_start - mode->vdisplay;
669 int vsync_len = mode->vsync_end - mode->vsync_start;
672 * Recommended maximum number of symbols transferred in a transfer unit:
673 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size,
674 * (output active video bandwidth in bytes))
675 * Must be less than tu_size.
677 max_tu_symbol = TU_SIZE_RECOMMENDED - 1;
679 dev_dbg(tc->dev, "set mode %dx%d\n",
680 mode->hdisplay, mode->vdisplay);
681 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
682 left_margin, right_margin, hsync_len);
683 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
684 upper_margin, lower_margin, vsync_len);
685 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
690 * datasheet is not clear of vsdelay in case of DPI
691 * assume we do not need any delay when DPI is a source of
694 tc_write(VPCTRL0, (0 << 20) /* VSDELAY */ |
695 OPXLFMT_RGB888 | FRMSYNC_DISABLED | MSF_DISABLED);
696 tc_write(HTIM01, (ALIGN(left_margin, 2) << 16) | /* H back porch */
697 (ALIGN(hsync_len, 2) << 0)); /* Hsync */
698 tc_write(HTIM02, (ALIGN(right_margin, 2) << 16) | /* H front porch */
699 (ALIGN(mode->hdisplay, 2) << 0)); /* width */
700 tc_write(VTIM01, (upper_margin << 16) | /* V back porch */
701 (vsync_len << 0)); /* Vsync */
702 tc_write(VTIM02, (lower_margin << 16) | /* V front porch */
703 (mode->vdisplay << 0)); /* height */
704 tc_write(VFUEN0, VFUEN); /* update settings */
706 /* Test pattern settings */
708 (120 << 24) | /* Red Color component value */
709 (20 << 16) | /* Green Color component value */
710 (99 << 8) | /* Blue Color component value */
711 (1 << 4) | /* Enable I2C Filter */
712 (2 << 0) | /* Color bar Mode */
715 /* DP Main Stream Attributes */
716 vid_sync_dly = hsync_len + left_margin + mode->hdisplay;
717 tc_write(DP0_VIDSYNCDELAY,
718 (max_tu_symbol << 16) | /* thresh_dly */
719 (vid_sync_dly << 0));
721 tc_write(DP0_TOTALVAL, (mode->vtotal << 16) | (mode->htotal));
723 tc_write(DP0_STARTVAL,
724 ((upper_margin + vsync_len) << 16) |
725 ((left_margin + hsync_len) << 0));
727 tc_write(DP0_ACTIVEVAL, (mode->vdisplay << 16) | (mode->hdisplay));
729 tc_write(DP0_SYNCVAL, (vsync_len << 16) | (hsync_len << 0) |
730 ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? SYNCVAL_HS_POL_ACTIVE_LOW : 0) |
731 ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? SYNCVAL_VS_POL_ACTIVE_LOW : 0));
733 tc_write(DPIPXLFMT, VS_POL_ACTIVE_LOW | HS_POL_ACTIVE_LOW |
734 DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888);
736 tc_write(DP0_MISC, (max_tu_symbol << 23) | (TU_SIZE_RECOMMENDED << 16) |
744 static int tc_link_training(struct tc_data *tc, int pattern)
746 const char * const *errors;
747 u32 srcctrl = tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
748 DP0_SRCCTRL_AUTOCORRECT;
754 if (pattern == DP_TRAINING_PATTERN_1) {
755 srcctrl |= DP0_SRCCTRL_TP1;
756 errors = training_pattern1_errors;
758 srcctrl |= DP0_SRCCTRL_TP2;
759 errors = training_pattern2_errors;
762 /* Set DPCD 0x102 for Training Part 1 or 2 */
763 tc_write(DP0_SNKLTCTRL, DP_LINK_SCRAMBLING_DISABLE | pattern);
765 tc_write(DP0_LTLOOPCTRL,
766 (0x0f << 28) | /* Defer Iteration Count */
767 (0x0f << 24) | /* Loop Iteration Count */
768 (0x0d << 0)); /* Loop Timer Delay */
772 /* Set DP0 Training Pattern */
773 tc_write(DP0_SRCCTRL, srcctrl);
775 /* Enable DP0 to start Link Training */
776 tc_write(DP0CTL, DP_EN);
781 tc_read(DP0_LTSTAT, &value);
783 } while ((!(value & LT_LOOPDONE)) && (--timeout));
785 dev_err(tc->dev, "Link training timeout!\n");
787 int pattern = (value >> 11) & 0x3;
788 int error = (value >> 8) & 0x7;
791 "Link training phase %d done after %d uS: %s\n",
792 pattern, 1000 - timeout, errors[error]);
793 if (pattern == DP_TRAINING_PATTERN_1 && error == 0)
795 if (pattern == DP_TRAINING_PATTERN_2) {
796 value &= LT_CHANNEL1_EQ_BITS |
797 LT_INTERLANE_ALIGN_DONE |
799 /* in case of two lanes */
800 if ((tc->link.base.num_lanes == 2) &&
801 (value == (LT_CHANNEL1_EQ_BITS |
802 LT_INTERLANE_ALIGN_DONE |
803 LT_CHANNEL0_EQ_BITS)))
805 /* in case of one line */
806 if ((tc->link.base.num_lanes == 1) &&
807 (value == (LT_INTERLANE_ALIGN_DONE |
808 LT_CHANNEL0_EQ_BITS)))
814 usleep_range(10, 20);
817 dev_err(tc->dev, "Failed to finish training phase %d\n",
826 static int tc_main_link_setup(struct tc_data *tc)
828 struct drm_dp_aux *aux = &tc->aux;
829 struct device *dev = tc->dev;
837 /* display mode should be set at this point */
841 tc_write(DP0_SRCCTRL, tc_srcctrl(tc));
842 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */
843 tc_write(DP1_SRCCTRL,
844 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
845 ((tc->link.base.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
847 rate = clk_get_rate(tc->refclk);
850 value = REF_FREQ_38M4;
853 value = REF_FREQ_26M;
856 value = REF_FREQ_19M2;
859 value = REF_FREQ_13M;
864 value |= SYSCLK_SEL_LSCLK | LSCLK_DIV_2;
865 tc_write(SYS_PLLPARAM, value);
867 /* Setup Main Link */
868 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN;
869 if (tc->link.base.num_lanes == 2)
870 dp_phy_ctrl |= PHY_2LANE;
871 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
875 tc_write(DP0_PLLCTRL, PLLUPDATE | PLLEN);
876 tc_wait_pll_lock(tc);
878 tc_write(DP1_PLLCTRL, PLLUPDATE | PLLEN);
879 tc_wait_pll_lock(tc);
882 if (tc_test_pattern) {
883 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
884 1000 * tc->mode->clock);
889 /* Reset/Enable Main Links */
890 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST;
891 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
892 usleep_range(100, 200);
893 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST);
894 tc_write(DP_PHY_CTRL, dp_phy_ctrl);
898 tc_read(DP_PHY_CTRL, &value);
900 } while ((!(value & PHY_RDY)) && (--timeout));
903 dev_err(dev, "timeout waiting for phy become ready");
907 /* Set misc: 8 bits per color */
908 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
914 * on TC358767 side ASSR configured through strap pin
915 * seems there is no way to change this setting from SW
917 * check is tc configured for same mode
919 if (tc->assr != tc->link.assr) {
920 dev_dbg(dev, "Trying to set display to ASSR: %d\n",
922 /* try to set ASSR on display side */
924 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]);
928 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp);
932 if (tmp[0] != tc->assr) {
933 dev_warn(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n",
935 /* trying with disabled scrambler */
936 tc->link.scrambler_dis = 1;
940 /* Setup Link & DPRx Config for Training */
941 ret = drm_dp_link_configure(aux, &tc->link.base);
945 /* DOWNSPREAD_CTRL */
946 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
947 /* MAIN_LINK_CHANNEL_CODING_SET */
948 tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00;
949 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2);
953 ret = tc_link_training(tc, DP_TRAINING_PATTERN_1);
957 ret = tc_link_training(tc, DP_TRAINING_PATTERN_2);
961 /* Clear DPCD 0x102 */
962 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */
963 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
964 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]);
968 /* Clear Training Pattern, set AutoCorrect Mode = 1 */
969 tc_write(DP0_SRCCTRL, tc_srcctrl(tc) | DP0_SRCCTRL_AUTOCORRECT);
975 /* Read DPCD 0x202-0x207 */
976 ret = drm_dp_dpcd_read_link_status(aux, tmp + 2);
979 } while ((--timeout) &&
980 !(drm_dp_channel_eq_ok(tmp + 2, tc->link.base.num_lanes)));
983 /* Read DPCD 0x200-0x201 */
984 ret = drm_dp_dpcd_read(aux, DP_SINK_COUNT, tmp, 2);
987 dev_err(dev, "channel(s) EQ not ok\n");
988 dev_info(dev, "0x0200 SINK_COUNT: 0x%02x\n", tmp[0]);
989 dev_info(dev, "0x0201 DEVICE_SERVICE_IRQ_VECTOR: 0x%02x\n",
991 dev_info(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[2]);
992 dev_info(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n",
994 dev_info(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[5]);
995 dev_info(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n",
1001 ret = tc_set_video_mode(tc, tc->mode);
1006 ret = tc_stream_clock_calc(tc);
1012 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1015 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1020 static int tc_main_link_stream(struct tc_data *tc, int state)
1025 dev_dbg(tc->dev, "stream: %d\n", state);
1028 value = VID_MN_GEN | DP_EN;
1029 if (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1031 tc_write(DP0CTL, value);
1033 * VID_EN assertion should be delayed by at least N * LSCLK
1034 * cycles from the time VID_MN_GEN is enabled in order to
1035 * generate stable values for VID_M. LSCLK is 270 MHz or
1036 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(),
1037 * so a delay of at least 203 us should suffice.
1039 usleep_range(500, 1000);
1041 tc_write(DP0CTL, value);
1042 /* Set input interface */
1043 value = DP0_AUDSRC_NO_INPUT;
1044 if (tc_test_pattern)
1045 value |= DP0_VIDSRC_COLOR_BAR;
1047 value |= DP0_VIDSRC_DPI_RX;
1048 tc_write(SYSCTRL, value);
1050 tc_write(DP0CTL, 0);
1058 static enum drm_connector_status
1059 tc_connector_detect(struct drm_connector *connector, bool force)
1061 return connector_status_connected;
1064 static void tc_bridge_pre_enable(struct drm_bridge *bridge)
1066 struct tc_data *tc = bridge_to_tc(bridge);
1068 drm_panel_prepare(tc->panel);
1071 static void tc_bridge_enable(struct drm_bridge *bridge)
1073 struct tc_data *tc = bridge_to_tc(bridge);
1076 ret = tc_main_link_setup(tc);
1078 dev_err(tc->dev, "main link setup error: %d\n", ret);
1082 ret = tc_main_link_stream(tc, 1);
1084 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1088 drm_panel_enable(tc->panel);
1091 static void tc_bridge_disable(struct drm_bridge *bridge)
1093 struct tc_data *tc = bridge_to_tc(bridge);
1096 drm_panel_disable(tc->panel);
1098 ret = tc_main_link_stream(tc, 0);
1100 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1103 static void tc_bridge_post_disable(struct drm_bridge *bridge)
1105 struct tc_data *tc = bridge_to_tc(bridge);
1107 drm_panel_unprepare(tc->panel);
1110 static bool tc_bridge_mode_fixup(struct drm_bridge *bridge,
1111 const struct drm_display_mode *mode,
1112 struct drm_display_mode *adj)
1114 /* Fixup sync polarities, both hsync and vsync are active low */
1115 adj->flags = mode->flags;
1116 adj->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
1117 adj->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
1122 static int tc_connector_mode_valid(struct drm_connector *connector,
1123 struct drm_display_mode *mode)
1125 struct tc_data *tc = connector_to_tc(connector);
1127 u32 bits_per_pixel = 24;
1129 /* DPI interface clock limitation: upto 154 MHz */
1130 if (mode->clock > 154000)
1131 return MODE_CLOCK_HIGH;
1133 req = mode->clock * bits_per_pixel / 8;
1134 avail = tc->link.base.num_lanes * tc->link.base.rate;
1142 static void tc_bridge_mode_set(struct drm_bridge *bridge,
1143 struct drm_display_mode *mode,
1144 struct drm_display_mode *adj)
1146 struct tc_data *tc = bridge_to_tc(bridge);
1151 static int tc_connector_get_modes(struct drm_connector *connector)
1153 struct tc_data *tc = connector_to_tc(connector);
1158 ret = tc_get_display_props(tc);
1160 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1164 if (tc->panel && tc->panel->funcs && tc->panel->funcs->get_modes) {
1165 count = tc->panel->funcs->get_modes(tc->panel);
1170 edid = drm_get_edid(connector, &tc->aux.ddc);
1177 drm_mode_connector_update_edid_property(connector, edid);
1178 count = drm_add_edid_modes(connector, edid);
1183 static void tc_connector_set_polling(struct tc_data *tc,
1184 struct drm_connector *connector)
1186 /* TODO: add support for HPD */
1187 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1188 DRM_CONNECTOR_POLL_DISCONNECT;
1191 static struct drm_encoder *
1192 tc_connector_best_encoder(struct drm_connector *connector)
1194 struct tc_data *tc = connector_to_tc(connector);
1196 return tc->bridge.encoder;
1199 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = {
1200 .get_modes = tc_connector_get_modes,
1201 .mode_valid = tc_connector_mode_valid,
1202 .best_encoder = tc_connector_best_encoder,
1205 static const struct drm_connector_funcs tc_connector_funcs = {
1206 .dpms = drm_atomic_helper_connector_dpms,
1207 .fill_modes = drm_helper_probe_single_connector_modes,
1208 .detect = tc_connector_detect,
1209 .destroy = drm_connector_cleanup,
1210 .reset = drm_atomic_helper_connector_reset,
1211 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1212 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1215 static int tc_bridge_attach(struct drm_bridge *bridge)
1217 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
1218 struct tc_data *tc = bridge_to_tc(bridge);
1219 struct drm_device *drm = bridge->dev;
1222 /* Create eDP connector */
1223 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1224 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs,
1225 DRM_MODE_CONNECTOR_eDP);
1230 drm_panel_attach(tc->panel, &tc->connector);
1232 drm_display_info_set_bus_formats(&tc->connector.display_info,
1234 drm_mode_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1239 static const struct drm_bridge_funcs tc_bridge_funcs = {
1240 .attach = tc_bridge_attach,
1241 .mode_set = tc_bridge_mode_set,
1242 .pre_enable = tc_bridge_pre_enable,
1243 .enable = tc_bridge_enable,
1244 .disable = tc_bridge_disable,
1245 .post_disable = tc_bridge_post_disable,
1246 .mode_fixup = tc_bridge_mode_fixup,
1249 static bool tc_readable_reg(struct device *dev, unsigned int reg)
1251 return reg != SYSCTRL;
1254 static const struct regmap_range tc_volatile_ranges[] = {
1255 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS),
1256 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ),
1257 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL),
1258 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL),
1259 regmap_reg_range(VFUEN0, VFUEN0),
1262 static const struct regmap_access_table tc_volatile_table = {
1263 .yes_ranges = tc_volatile_ranges,
1264 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges),
1267 static bool tc_writeable_reg(struct device *dev, unsigned int reg)
1269 return (reg != TC_IDREG) &&
1270 (reg != DP0_LTSTAT) &&
1271 (reg != DP0_SNKLTCHGREQ);
1274 static const struct regmap_config tc_regmap_config = {
1279 .max_register = PLL_DBG,
1280 .cache_type = REGCACHE_RBTREE,
1281 .readable_reg = tc_readable_reg,
1282 .volatile_table = &tc_volatile_table,
1283 .writeable_reg = tc_writeable_reg,
1284 .reg_format_endian = REGMAP_ENDIAN_BIG,
1285 .val_format_endian = REGMAP_ENDIAN_LITTLE,
1288 static int tc_probe(struct i2c_client *client, const struct i2c_device_id *id)
1290 struct device *dev = &client->dev;
1291 struct device_node *ep;
1295 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
1301 /* port@2 is the output port */
1302 ep = of_graph_get_endpoint_by_regs(dev->of_node, 2, -1);
1304 struct device_node *remote;
1306 remote = of_graph_get_remote_port_parent(ep);
1308 dev_warn(dev, "endpoint %s not connected\n",
1314 tc->panel = of_drm_find_panel(remote);
1316 dev_dbg(dev, "found panel %s\n", remote->full_name);
1318 dev_dbg(dev, "waiting for panel %s\n",
1320 of_node_put(remote);
1321 return -EPROBE_DEFER;
1323 of_node_put(remote);
1326 /* Shut down GPIO is optional */
1327 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
1328 if (IS_ERR(tc->sd_gpio))
1329 return PTR_ERR(tc->sd_gpio);
1332 gpiod_set_value_cansleep(tc->sd_gpio, 0);
1333 usleep_range(5000, 10000);
1336 /* Reset GPIO is optional */
1337 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1338 if (IS_ERR(tc->reset_gpio))
1339 return PTR_ERR(tc->reset_gpio);
1341 if (tc->reset_gpio) {
1342 gpiod_set_value_cansleep(tc->reset_gpio, 1);
1343 usleep_range(5000, 10000);
1346 tc->refclk = devm_clk_get(dev, "ref");
1347 if (IS_ERR(tc->refclk)) {
1348 ret = PTR_ERR(tc->refclk);
1349 dev_err(dev, "Failed to get refclk: %d\n", ret);
1353 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
1354 if (IS_ERR(tc->regmap)) {
1355 ret = PTR_ERR(tc->regmap);
1356 dev_err(dev, "Failed to initialize regmap: %d\n", ret);
1360 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
1362 dev_err(tc->dev, "can not read device ID: %d\n", ret);
1366 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
1367 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
1371 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
1373 ret = tc_aux_link_setup(tc);
1377 /* Register DP AUX channel */
1378 tc->aux.name = "TC358767 AUX i2c adapter";
1379 tc->aux.dev = tc->dev;
1380 tc->aux.transfer = tc_aux_transfer;
1381 ret = drm_dp_aux_register(&tc->aux);
1385 ret = tc_get_display_props(tc);
1387 goto err_unregister_aux;
1389 tc_connector_set_polling(tc, &tc->connector);
1391 tc->bridge.funcs = &tc_bridge_funcs;
1392 tc->bridge.of_node = dev->of_node;
1393 ret = drm_bridge_add(&tc->bridge);
1395 dev_err(dev, "Failed to add drm_bridge: %d\n", ret);
1396 goto err_unregister_aux;
1399 i2c_set_clientdata(client, tc);
1403 drm_dp_aux_unregister(&tc->aux);
1407 static int tc_remove(struct i2c_client *client)
1409 struct tc_data *tc = i2c_get_clientdata(client);
1411 drm_bridge_remove(&tc->bridge);
1412 drm_dp_aux_unregister(&tc->aux);
1419 static const struct i2c_device_id tc358767_i2c_ids[] = {
1423 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids);
1425 static const struct of_device_id tc358767_of_ids[] = {
1426 { .compatible = "toshiba,tc358767", },
1429 MODULE_DEVICE_TABLE(of, tc358767_of_ids);
1431 static struct i2c_driver tc358767_driver = {
1434 .of_match_table = tc358767_of_ids,
1436 .id_table = tc358767_i2c_ids,
1438 .remove = tc_remove,
1440 module_i2c_driver(tc358767_driver);
1442 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>");
1443 MODULE_DESCRIPTION("tc358767 eDP encoder driver");
1444 MODULE_LICENSE("GPL");