2 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
3 * Copyright (C) STMicroelectronics SA 2017
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * Modified by Philippe Cornu <philippe.cornu@st.com>
11 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
12 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
15 #include <linux/clk.h>
16 #include <linux/component.h>
17 #include <linux/iopoll.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/reset.h>
23 #include <drm/drm_atomic_helper.h>
24 #include <drm/drm_bridge.h>
25 #include <drm/drm_crtc.h>
26 #include <drm/drm_crtc_helper.h>
27 #include <drm/drm_mipi_dsi.h>
28 #include <drm/drm_of.h>
29 #include <drm/bridge/dw_mipi_dsi.h>
30 #include <video/mipi_display.h>
32 #define DSI_VERSION 0x00
33 #define DSI_PWR_UP 0x04
35 #define POWERUP BIT(0)
37 #define DSI_CLKMGR_CFG 0x08
38 #define TO_CLK_DIVIDSION(div) (((div) & 0xff) << 8)
39 #define TX_ESC_CLK_DIVIDSION(div) (((div) & 0xff) << 0)
41 #define DSI_DPI_VCID 0x0c
42 #define DPI_VID(vid) (((vid) & 0x3) << 0)
44 #define DSI_DPI_COLOR_CODING 0x10
45 #define EN18_LOOSELY BIT(8)
46 #define DPI_COLOR_CODING_16BIT_1 0x0
47 #define DPI_COLOR_CODING_16BIT_2 0x1
48 #define DPI_COLOR_CODING_16BIT_3 0x2
49 #define DPI_COLOR_CODING_18BIT_1 0x3
50 #define DPI_COLOR_CODING_18BIT_2 0x4
51 #define DPI_COLOR_CODING_24BIT 0x5
53 #define DSI_DPI_CFG_POL 0x14
54 #define COLORM_ACTIVE_LOW BIT(4)
55 #define SHUTD_ACTIVE_LOW BIT(3)
56 #define HSYNC_ACTIVE_LOW BIT(2)
57 #define VSYNC_ACTIVE_LOW BIT(1)
58 #define DATAEN_ACTIVE_LOW BIT(0)
60 #define DSI_DPI_LP_CMD_TIM 0x18
61 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
62 #define INVACT_LPCMD_TIME(p) ((p) & 0xff)
64 #define DSI_DBI_CFG 0x20
65 #define DSI_DBI_CMDSIZE 0x28
67 #define DSI_PCKHDL_CFG 0x2c
68 #define EN_CRC_RX BIT(4)
69 #define EN_ECC_RX BIT(3)
71 #define EN_EOTP_RX BIT(1)
72 #define EN_EOTP_TX BIT(0)
74 #define DSI_MODE_CFG 0x34
75 #define ENABLE_VIDEO_MODE 0
76 #define ENABLE_CMD_MODE BIT(0)
78 #define DSI_VID_MODE_CFG 0x38
79 #define FRAME_BTA_ACK BIT(14)
80 #define ENABLE_LOW_POWER (0x3f << 8)
81 #define ENABLE_LOW_POWER_MASK (0x3f << 8)
82 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
83 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
84 #define VID_MODE_TYPE_BURST 0x2
85 #define VID_MODE_TYPE_MASK 0x3
87 #define DSI_VID_PKT_SIZE 0x3c
88 #define VID_PKT_SIZE(p) (((p) & 0x3fff) << 0)
89 #define VID_PKT_MAX_SIZE 0x3fff
91 #define DSI_VID_HSA_TIME 0x48
92 #define DSI_VID_HBP_TIME 0x4c
93 #define DSI_VID_HLINE_TIME 0x50
94 #define DSI_VID_VSA_LINES 0x54
95 #define DSI_VID_VBP_LINES 0x58
96 #define DSI_VID_VFP_LINES 0x5c
97 #define DSI_VID_VACTIVE_LINES 0x60
98 #define DSI_CMD_MODE_CFG 0x68
99 #define MAX_RD_PKT_SIZE_LP BIT(24)
100 #define DCS_LW_TX_LP BIT(19)
101 #define DCS_SR_0P_TX_LP BIT(18)
102 #define DCS_SW_1P_TX_LP BIT(17)
103 #define DCS_SW_0P_TX_LP BIT(16)
104 #define GEN_LW_TX_LP BIT(14)
105 #define GEN_SR_2P_TX_LP BIT(13)
106 #define GEN_SR_1P_TX_LP BIT(12)
107 #define GEN_SR_0P_TX_LP BIT(11)
108 #define GEN_SW_2P_TX_LP BIT(10)
109 #define GEN_SW_1P_TX_LP BIT(9)
110 #define GEN_SW_0P_TX_LP BIT(8)
111 #define EN_ACK_RQST BIT(1)
112 #define EN_TEAR_FX BIT(0)
114 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
127 #define DSI_GEN_HDR 0x6c
128 #define GEN_HDATA(data) (((data) & 0xffff) << 8)
129 #define GEN_HDATA_MASK (0xffff << 8)
130 #define GEN_HTYPE(type) (((type) & 0xff) << 0)
131 #define GEN_HTYPE_MASK 0xff
133 #define DSI_GEN_PLD_DATA 0x70
135 #define DSI_CMD_PKT_STATUS 0x74
136 #define GEN_CMD_EMPTY BIT(0)
137 #define GEN_CMD_FULL BIT(1)
138 #define GEN_PLD_W_EMPTY BIT(2)
139 #define GEN_PLD_W_FULL BIT(3)
140 #define GEN_PLD_R_EMPTY BIT(4)
141 #define GEN_PLD_R_FULL BIT(5)
142 #define GEN_RD_CMD_BUSY BIT(6)
144 #define DSI_TO_CNT_CFG 0x78
145 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
146 #define LPRX_TO_CNT(p) ((p) & 0xffff)
148 #define DSI_BTA_TO_CNT 0x8c
149 #define DSI_LPCLK_CTRL 0x94
150 #define AUTO_CLKLANE_CTRL BIT(1)
151 #define PHY_TXREQUESTCLKHS BIT(0)
153 #define DSI_PHY_TMR_LPCLK_CFG 0x98
154 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
155 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
157 #define DSI_PHY_TMR_CFG 0x9c
158 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
159 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
160 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
162 #define DSI_PHY_RSTZ 0xa0
163 #define PHY_DISFORCEPLL 0
164 #define PHY_ENFORCEPLL BIT(3)
165 #define PHY_DISABLECLK 0
166 #define PHY_ENABLECLK BIT(2)
168 #define PHY_UNRSTZ BIT(1)
169 #define PHY_SHUTDOWNZ 0
170 #define PHY_UNSHUTDOWNZ BIT(0)
172 #define DSI_PHY_IF_CFG 0xa4
173 #define N_LANES(n) ((((n) - 1) & 0x3) << 0)
174 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
176 #define DSI_PHY_STATUS 0xb0
178 #define STOP_STATE_CLK_LANE BIT(2)
180 #define DSI_PHY_TST_CTRL0 0xb4
181 #define PHY_TESTCLK BIT(1)
182 #define PHY_UNTESTCLK 0
183 #define PHY_TESTCLR BIT(0)
184 #define PHY_UNTESTCLR 0
186 #define DSI_PHY_TST_CTRL1 0xb8
187 #define PHY_TESTEN BIT(16)
188 #define PHY_UNTESTEN 0
189 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
190 #define PHY_TESTDIN(n) (((n) & 0xff) << 0)
192 #define DSI_INT_ST0 0xbc
193 #define DSI_INT_ST1 0xc0
194 #define DSI_INT_MSK0 0xc4
195 #define DSI_INT_MSK1 0xc8
197 #define PHY_STATUS_TIMEOUT_US 10000
198 #define CMD_PKT_STATUS_TIMEOUT_US 20000
201 struct drm_bridge bridge;
202 struct mipi_dsi_host dsi_host;
203 struct drm_bridge *panel_bridge;
204 bool is_panel_bridge;
210 unsigned int lane_mbps; /* per lane */
214 unsigned long mode_flags;
216 const struct dw_mipi_dsi_plat_data *plat_data;
220 * The controller should generate 2 frames before
221 * preparing the peripheral.
223 static void dw_mipi_dsi_wait_for_two_frames(struct drm_display_mode *mode)
225 int refresh, two_frames;
227 refresh = drm_mode_vrefresh(mode);
228 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
232 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host)
234 return container_of(host, struct dw_mipi_dsi, dsi_host);
237 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
239 return container_of(bridge, struct dw_mipi_dsi, bridge);
242 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
244 writel(val, dsi->base + reg);
247 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
249 return readl(dsi->base + reg);
252 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
253 struct mipi_dsi_device *device)
255 struct dw_mipi_dsi *dsi = host_to_dsi(host);
256 struct drm_bridge *bridge;
257 struct drm_panel *panel;
260 if (device->lanes > dsi->plat_data->max_data_lanes) {
261 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
266 dsi->lanes = device->lanes;
267 dsi->channel = device->channel;
268 dsi->format = device->format;
269 dsi->mode_flags = device->mode_flags;
271 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0,
277 bridge = drm_panel_bridge_add(panel, DRM_MODE_CONNECTOR_DSI);
279 return PTR_ERR(bridge);
280 dsi->is_panel_bridge = true;
283 dsi->panel_bridge = bridge;
285 drm_bridge_add(&dsi->bridge);
290 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
291 struct mipi_dsi_device *device)
293 struct dw_mipi_dsi *dsi = host_to_dsi(host);
295 if (dsi->is_panel_bridge)
296 drm_panel_bridge_remove(dsi->panel_bridge);
298 drm_bridge_remove(&dsi->bridge);
303 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
304 const struct mipi_dsi_msg *msg)
306 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
309 if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
312 val |= CMD_MODE_ALL_LP;
314 dsi_write(dsi, DSI_CMD_MODE_CFG, val);
317 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
322 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
323 val, !(val & GEN_CMD_FULL), 1000,
324 CMD_PKT_STATUS_TIMEOUT_US);
326 dev_err(dsi->dev, "failed to get available command FIFO\n");
330 dsi_write(dsi, DSI_GEN_HDR, hdr_val);
332 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
333 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
334 val, (val & mask) == mask,
335 1000, CMD_PKT_STATUS_TIMEOUT_US);
337 dev_err(dsi->dev, "failed to write command FIFO\n");
344 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi,
345 const struct mipi_dsi_msg *msg)
347 const u8 *tx_buf = msg->tx_buf;
354 data |= tx_buf[1] << 8;
356 if (msg->tx_len > 2) {
357 dev_err(dsi->dev, "too long tx buf length %zu for short write\n",
362 val = GEN_HDATA(data) | GEN_HTYPE(msg->type);
363 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
366 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
367 const struct mipi_dsi_msg *msg)
369 const u8 *tx_buf = msg->tx_buf;
370 int len = msg->tx_len, pld_data_bytes = sizeof(u32), ret;
371 u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
375 if (msg->tx_len < 3) {
376 dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
381 while (DIV_ROUND_UP(len, pld_data_bytes)) {
382 if (len < pld_data_bytes) {
384 memcpy(&remainder, tx_buf, len);
385 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
388 memcpy(&remainder, tx_buf, pld_data_bytes);
389 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder);
390 tx_buf += pld_data_bytes;
391 len -= pld_data_bytes;
394 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
395 val, !(val & GEN_PLD_W_FULL), 1000,
396 CMD_PKT_STATUS_TIMEOUT_US);
399 "failed to get available write payload FIFO\n");
404 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
407 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
408 const struct mipi_dsi_msg *msg)
410 struct dw_mipi_dsi *dsi = host_to_dsi(host);
414 * TODO dw drv improvements
415 * use mipi_dsi_create_packet() instead of all following
416 * functions and code (no switch cases, no
417 * dw_mipi_dsi_dcs_short_write(), only the loop in long_write...)
418 * and use packet.header...
420 dw_mipi_message_config(dsi, msg);
423 case MIPI_DSI_DCS_SHORT_WRITE:
424 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
425 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
426 ret = dw_mipi_dsi_dcs_short_write(dsi, msg);
428 case MIPI_DSI_DCS_LONG_WRITE:
429 ret = dw_mipi_dsi_dcs_long_write(dsi, msg);
432 dev_err(dsi->dev, "unsupported message type 0x%02x\n",
440 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
441 .attach = dw_mipi_dsi_host_attach,
442 .detach = dw_mipi_dsi_host_detach,
443 .transfer = dw_mipi_dsi_host_transfer,
446 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
451 * TODO dw drv improvements
452 * enabling low power is panel-dependent, we should use the
453 * panel configuration here...
455 val = ENABLE_LOW_POWER;
457 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
458 val |= VID_MODE_TYPE_BURST;
459 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
460 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
462 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
464 dsi_write(dsi, DSI_VID_MODE_CFG, val);
467 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
468 unsigned long mode_flags)
472 dsi_write(dsi, DSI_PWR_UP, RESET);
474 if (mode_flags & MIPI_DSI_MODE_VIDEO) {
475 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
476 dw_mipi_dsi_video_mode_config(dsi);
478 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
481 val = PHY_TXREQUESTCLKHS;
482 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
483 val |= AUTO_CLKLANE_CTRL;
484 dsi_write(dsi, DSI_LPCLK_CTRL, val);
486 dsi_write(dsi, DSI_PWR_UP, POWERUP);
489 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
491 dsi_write(dsi, DSI_PWR_UP, RESET);
492 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
495 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
498 * The maximum permitted escape clock is 20MHz and it is derived from
499 * lanebyteclk, which is running at "lane_mbps / 8". Thus we want:
501 * (lane_mbps >> 3) / esc_clk_division < 20
503 * (lane_mbps >> 3) / 20 > esc_clk_division
505 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
507 dsi_write(dsi, DSI_PWR_UP, RESET);
510 * TODO dw drv improvements
511 * timeout clock division should be computed with the
512 * high speed transmission counter timeout and byte lane...
514 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) |
515 TX_ESC_CLK_DIVIDSION(esc_clk_division));
518 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
519 struct drm_display_mode *mode)
521 u32 val = 0, color = 0;
523 switch (dsi->format) {
524 case MIPI_DSI_FMT_RGB888:
525 color = DPI_COLOR_CODING_24BIT;
527 case MIPI_DSI_FMT_RGB666:
528 color = DPI_COLOR_CODING_18BIT_2 | EN18_LOOSELY;
530 case MIPI_DSI_FMT_RGB666_PACKED:
531 color = DPI_COLOR_CODING_18BIT_1;
533 case MIPI_DSI_FMT_RGB565:
534 color = DPI_COLOR_CODING_16BIT_1;
538 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
539 val |= VSYNC_ACTIVE_LOW;
540 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
541 val |= HSYNC_ACTIVE_LOW;
543 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel));
544 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
545 dsi_write(dsi, DSI_DPI_CFG_POL, val);
547 * TODO dw drv improvements
548 * largest packet sizes during hfp or during vsa/vpb/vfp
549 * should be computed according to byte lane, lane number and only
550 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
552 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
553 | INVACT_LPCMD_TIME(4));
556 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
558 dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA);
561 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
562 struct drm_display_mode *mode)
565 * TODO dw drv improvements
566 * only burst mode is supported here. For non-burst video modes,
567 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC &
568 * DSI_VNPCR.NPSIZE... especially because this driver supports
569 * non-burst video modes, see dw_mipi_dsi_video_mode_config()...
571 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay));
574 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
577 * TODO dw drv improvements
578 * compute high speed transmission counter timeout according
579 * to the timeout clock division (TO_CLK_DIVIDSION) and byte lane...
581 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
583 * TODO dw drv improvements
584 * the Bus-Turn-Around Timeout Counter should be computed
585 * according to byte lane...
587 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
588 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
591 /* Get lane byte clock cycles. */
592 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
593 struct drm_display_mode *mode,
598 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
600 frac = lbcc % mode->clock;
601 lbcc = lbcc / mode->clock;
608 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
609 struct drm_display_mode *mode)
611 u32 htotal, hsa, hbp, lbcc;
613 htotal = mode->htotal;
614 hsa = mode->hsync_end - mode->hsync_start;
615 hbp = mode->htotal - mode->hsync_end;
618 * TODO dw drv improvements
619 * computations below may be improved...
621 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
622 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
624 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
625 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
627 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
628 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
631 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
632 struct drm_display_mode *mode)
634 u32 vactive, vsa, vfp, vbp;
636 vactive = mode->vdisplay;
637 vsa = mode->vsync_end - mode->vsync_start;
638 vfp = mode->vsync_start - mode->vdisplay;
639 vbp = mode->vtotal - mode->vsync_end;
641 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
642 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
643 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
644 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
647 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
650 * TODO dw drv improvements
651 * data & clock lane timers should be computed according to panel
652 * blankings and to the automatic clock lane control mode...
653 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
654 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
656 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
657 | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
659 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
660 | PHY_CLKLP2HS_TIME(0x40));
663 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
666 * TODO dw drv improvements
667 * stop wait time should be the maximum between host dsi
668 * and panel stop wait times
670 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
671 N_LANES(dsi->lanes));
674 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
676 /* Clear PHY state */
677 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
678 | PHY_RSTZ | PHY_SHUTDOWNZ);
679 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
680 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
681 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
684 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
689 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
690 PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
692 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
693 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
695 DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
697 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
698 val, val & STOP_STATE_CLK_LANE, 1000,
699 PHY_STATUS_TIMEOUT_US);
701 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
704 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
706 dsi_read(dsi, DSI_INT_ST0);
707 dsi_read(dsi, DSI_INT_ST1);
708 dsi_write(dsi, DSI_INT_MSK0, 0);
709 dsi_write(dsi, DSI_INT_MSK1, 0);
712 static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
714 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
717 * Switch to command mode before panel-bridge post_disable &
719 * Note: panel-bridge disable & panel disable has been called
720 * before by the drm framework.
722 dw_mipi_dsi_set_mode(dsi, 0);
725 * TODO Only way found to call panel-bridge post_disable &
726 * panel unprepare before the dsi "final" disable...
727 * This needs to be fixed in the drm_bridge framework and the API
728 * needs to be updated to manage our own call chains...
730 dsi->panel_bridge->funcs->post_disable(dsi->panel_bridge);
732 dw_mipi_dsi_disable(dsi);
733 clk_disable_unprepare(dsi->pclk);
734 pm_runtime_put(dsi->dev);
737 void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge,
738 struct drm_display_mode *mode,
739 struct drm_display_mode *adjusted_mode)
741 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
742 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
743 void *priv_data = dsi->plat_data->priv_data;
746 clk_prepare_enable(dsi->pclk);
748 ret = phy_ops->get_lane_mbps(priv_data, mode, dsi->mode_flags,
749 dsi->lanes, dsi->format, &dsi->lane_mbps);
751 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n");
753 pm_runtime_get_sync(dsi->dev);
754 dw_mipi_dsi_init(dsi);
755 dw_mipi_dsi_dpi_config(dsi, mode);
756 dw_mipi_dsi_packet_handler_config(dsi);
757 dw_mipi_dsi_video_mode_config(dsi);
758 dw_mipi_dsi_video_packet_config(dsi, mode);
759 dw_mipi_dsi_command_mode_config(dsi);
760 dw_mipi_dsi_line_timer_config(dsi, mode);
761 dw_mipi_dsi_vertical_timing_config(dsi, mode);
763 dw_mipi_dsi_dphy_init(dsi);
764 dw_mipi_dsi_dphy_timing_config(dsi);
765 dw_mipi_dsi_dphy_interface_config(dsi);
767 dw_mipi_dsi_clear_err(dsi);
769 ret = phy_ops->init(priv_data);
771 DRM_DEBUG_DRIVER("Phy init() failed\n");
773 dw_mipi_dsi_dphy_enable(dsi);
775 dw_mipi_dsi_wait_for_two_frames(mode);
777 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */
778 dw_mipi_dsi_set_mode(dsi, 0);
781 static void dw_mipi_dsi_bridge_enable(struct drm_bridge *bridge)
783 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
785 /* Switch to video mode for panel-bridge enable & panel enable */
786 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
789 static enum drm_mode_status
790 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
791 const struct drm_display_mode *mode)
793 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
794 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
795 enum drm_mode_status mode_status = MODE_OK;
797 if (pdata->mode_valid)
798 mode_status = pdata->mode_valid(pdata->priv_data, mode);
803 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge)
805 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
807 if (!bridge->encoder) {
808 DRM_ERROR("Parent encoder object not found\n");
812 /* Set the encoder type as caller does not know it */
813 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI;
815 /* Attach the panel-bridge to the dsi bridge */
816 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge);
819 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = {
820 .mode_set = dw_mipi_dsi_bridge_mode_set,
821 .enable = dw_mipi_dsi_bridge_enable,
822 .post_disable = dw_mipi_dsi_bridge_post_disable,
823 .mode_valid = dw_mipi_dsi_bridge_mode_valid,
824 .attach = dw_mipi_dsi_bridge_attach,
827 static struct dw_mipi_dsi *
828 __dw_mipi_dsi_probe(struct platform_device *pdev,
829 const struct dw_mipi_dsi_plat_data *plat_data)
831 struct device *dev = &pdev->dev;
832 struct reset_control *apb_rst;
833 struct dw_mipi_dsi *dsi;
834 struct resource *res;
837 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
839 return ERR_PTR(-ENOMEM);
842 dsi->plat_data = plat_data;
844 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps) {
845 DRM_ERROR("Phy not properly configured\n");
846 return ERR_PTR(-ENODEV);
849 if (!plat_data->base) {
850 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
852 return ERR_PTR(-ENODEV);
854 dsi->base = devm_ioremap_resource(dev, res);
855 if (IS_ERR(dsi->base))
856 return ERR_PTR(-ENODEV);
859 dsi->base = plat_data->base;
862 dsi->pclk = devm_clk_get(dev, "pclk");
863 if (IS_ERR(dsi->pclk)) {
864 ret = PTR_ERR(dsi->pclk);
865 dev_err(dev, "Unable to get pclk: %d\n", ret);
870 * Note that the reset was not defined in the initial device tree, so
871 * we have to be prepared for it not being found.
873 apb_rst = devm_reset_control_get(dev, "apb");
874 if (IS_ERR(apb_rst)) {
875 ret = PTR_ERR(apb_rst);
876 if (ret == -ENOENT) {
879 dev_err(dev, "Unable to get reset control: %d\n", ret);
885 ret = clk_prepare_enable(dsi->pclk);
887 dev_err(dev, "%s: Failed to enable pclk\n", __func__);
891 reset_control_assert(apb_rst);
892 usleep_range(10, 20);
893 reset_control_deassert(apb_rst);
895 clk_disable_unprepare(dsi->pclk);
898 pm_runtime_enable(dev);
900 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
901 dsi->dsi_host.dev = dev;
902 ret = mipi_dsi_host_register(&dsi->dsi_host);
904 dev_err(dev, "Failed to register MIPI host: %d\n", ret);
908 dsi->bridge.driver_private = dsi;
909 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
911 dsi->bridge.of_node = pdev->dev.of_node;
914 dev_set_drvdata(dev, dsi);
919 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
921 pm_runtime_disable(dsi->dev);
925 * Probe/remove API, used from platforms based on the DRM bridge API.
927 int dw_mipi_dsi_probe(struct platform_device *pdev,
928 const struct dw_mipi_dsi_plat_data *plat_data)
930 struct dw_mipi_dsi *dsi;
932 dsi = __dw_mipi_dsi_probe(pdev, plat_data);
938 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe);
940 void dw_mipi_dsi_remove(struct platform_device *pdev)
942 struct dw_mipi_dsi *dsi = platform_get_drvdata(pdev);
944 mipi_dsi_host_unregister(&dsi->dsi_host);
946 __dw_mipi_dsi_remove(dsi);
948 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove);
951 * Bind/unbind API, used from platforms based on the component framework.
953 int dw_mipi_dsi_bind(struct platform_device *pdev, struct drm_encoder *encoder,
954 const struct dw_mipi_dsi_plat_data *plat_data)
956 struct dw_mipi_dsi *dsi;
959 dsi = __dw_mipi_dsi_probe(pdev, plat_data);
963 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL);
965 dw_mipi_dsi_remove(pdev);
966 DRM_ERROR("Failed to initialize bridge with drm\n");
972 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind);
974 void dw_mipi_dsi_unbind(struct device *dev)
976 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev);
978 __dw_mipi_dsi_remove(dsi);
980 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind);
982 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
983 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
984 MODULE_DESCRIPTION("DW MIPI DSI host controller driver");
985 MODULE_LICENSE("GPL");
986 MODULE_ALIAS("platform:dw-mipi-dsi");